150120Swpaul/* $NetBSD: nsphyreg.h,v 1.1 1998/08/10 23:58:39 thorpej Exp $ */ 250120Swpaul 350120Swpaul/*- 450120Swpaul * Copyright (c) 1998 The NetBSD Foundation, Inc. 550120Swpaul * All rights reserved. 650120Swpaul * 750120Swpaul * This code is derived from software contributed to The NetBSD Foundation 850120Swpaul * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 950120Swpaul * NASA Ames Research Center. 1050120Swpaul * 1150120Swpaul * Redistribution and use in source and binary forms, with or without 1250120Swpaul * modification, are permitted provided that the following conditions 1350120Swpaul * are met: 1450120Swpaul * 1. Redistributions of source code must retain the above copyright 1550120Swpaul * notice, this list of conditions and the following disclaimer. 1650120Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1750120Swpaul * notice, this list of conditions and the following disclaimer in the 1850120Swpaul * documentation and/or other materials provided with the distribution. 1950120Swpaul * 2050120Swpaul * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2150120Swpaul * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2250120Swpaul * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2350120Swpaul * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2450120Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550120Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650120Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750120Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850120Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950120Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3050120Swpaul * POSSIBILITY OF SUCH DAMAGE. 3150120Swpaul * 3250477Speter * $FreeBSD$ 3350120Swpaul */ 3450120Swpaul 3550120Swpaul#ifndef _DEV_MII_NSPHYREG_H_ 3650120Swpaul#define _DEV_MII_NSPHYREG_H_ 3750120Swpaul 3850120Swpaul/* 3950120Swpaul * DP83840 registers. 4050120Swpaul */ 4150120Swpaul 4250120Swpaul#define MII_NSPHY_DCR 0x12 /* Disconnect counter */ 4350120Swpaul 4450120Swpaul#define MII_NSPHY_FCSCR 0x13 /* False carrier sense counter */ 4550120Swpaul 4650120Swpaul#define MII_NSPHY_RECR 0x15 /* Receive error counter */ 4750120Swpaul 4850120Swpaul#define MII_NSPHY_SRR 0x16 /* Silicon revision */ 4950120Swpaul 5050120Swpaul#define MII_NSPHY_PCR 0x17 /* PCS sub-layer configuration */ 5150120Swpaul#define PCR_NRZI 0x8000 /* NRZI encoding enabled for 100TX */ 5250120Swpaul#define PCR_DESCRTOSEL 0x4000 /* descrambler t/o select (2ms) */ 5350120Swpaul#define PCR_DESCRTODIS 0x2000 /* descrambler t/o disable */ 5450120Swpaul#define PCR_REPEATER 0x1000 /* repeater mode */ 5550120Swpaul#define PCR_ENCSEL 0x0800 /* encoder mode select */ 5650120Swpaul#define PCR_CLK25MDIS 0x0080 /* CLK25M disable */ 5750120Swpaul#define PCR_FLINK100 0x0040 /* force good link in 100mbps */ 5850120Swpaul#define PCR_CIMDIS 0x0020 /* carrier integrity monitor disable */ 5950120Swpaul#define PCR_TXOFF 0x0010 /* force transmit off */ 6050120Swpaul#define PCR_LED1MODE 0x0004 /* LED1 mode: see below */ 6150120Swpaul#define PCR_LED4MODE 0x0002 /* LED4 mode: see below */ 6250120Swpaul 6350120Swpaul/* 6450120Swpaul * LED1 Mode: 6550120Swpaul * 6650120Swpaul * 1 LED1 output configured to PAR's CON_STATUS, useful for 6750120Swpaul * network management in 100baseTX mode. 6850120Swpaul * 6950120Swpaul * 0 Normal LED1 operation - 10baseTX and 100baseTX transmission 7050120Swpaul * activity. 7150120Swpaul * 7250120Swpaul * LED4 Mode: 7350120Swpaul * 7450120Swpaul * 1 LED4 output configured to indicate full-duplex in both 7550120Swpaul * 10baseT and 100baseTX modes. 7650120Swpaul * 7750120Swpaul * 0 LED4 output configured to indicate polarity in 10baseT 7850120Swpaul * mode and full-duplex in 100baseTX mode. 7950120Swpaul */ 8050120Swpaul 8150120Swpaul#define MII_NSPHY_LBREMR 0x18 /* Loopback, bypass, error mask */ 8250120Swpaul#define LBREMR_BADSSDEN 0x8000 /* enable bad SSD detection */ 8350120Swpaul#define LBREMR_BP4B5B 0x4000 /* bypass 4b/5b encoding */ 8450120Swpaul#define LBREMR_BPSCR 0x2000 /* bypass scrambler */ 8550120Swpaul#define LBREMR_BPALIGN 0x1000 /* bypass alignment function */ 8650120Swpaul#define LBREMR_10LOOP 0x0800 /* 10baseT loopback */ 8750120Swpaul#define LBREMR_LB1 0x0200 /* loopback ctl 1 */ 8850120Swpaul#define LBREMR_LB0 0x0100 /* loopback ctl 0 */ 8950120Swpaul#define LBREMR_ALTCRS 0x0040 /* alt crs operation */ 9050120Swpaul#define LBREMR_LOOPXMTDIS 0x0020 /* disable transmit in 100TX loopbk */ 9150120Swpaul#define LBREMR_CODEERR 0x0010 /* code errors */ 9250120Swpaul#define LBREMR_PEERR 0x0008 /* premature end errors */ 9350120Swpaul#define LBREMR_LINKERR 0x0004 /* link errors */ 9450120Swpaul#define LBREMR_PKTERR 0x0002 /* packet errors */ 9550120Swpaul 9650120Swpaul#define MII_NSPHY_PAR 0x19 /* Physical address and status */ 9750120Swpaul#define PAR_DISCRSJAB 0x0800 /* disable car sense during jab */ 9850120Swpaul#define PAR_ANENSTAT 0x0400 /* autoneg mode status */ 9950120Swpaul#define PAR_FEFIEN 0x0100 /* far end fault enable */ 10050120Swpaul#define PAR_FDX 0x0080 /* full duplex status */ 10150120Swpaul#define PAR_10 0x0040 /* 10mbps mode */ 10250120Swpaul#define PAR_CON 0x0020 /* connect status */ 10350120Swpaul#define PAR_AMASK 0x001f /* PHY address bits */ 10450120Swpaul 10550120Swpaul#define MII_NSPHY_10BTSR 0x1b /* 10baseT status */ 10650120Swpaul#define MII_NSPHY_10BTCR 0x1c /* 10baseT configuration */ 10750120Swpaul 10850120Swpaul#endif /* _DEV_MII_NSPHYREG_H_ */ 109