mfireg.h revision 250496
1/*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26/*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53#ifndef _MFIREG_H 54#define _MFIREG_H 55 56#include <sys/cdefs.h> 57__FBSDID("$FreeBSD: stable/9/sys/dev/mfi/mfireg.h 250496 2013-05-11 02:42:59Z smh $"); 58 59/* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67#define MEGAMFI_FRAME_SIZE 64 68/* 69 * Start with the register set. All registers are 32 bits wide. 70 * The usual Intel IOP style setup. 71 */ 72#define MFI_IMSG0 0x10 /* Inbound message 0 */ 73#define MFI_IMSG1 0x14 /* Inbound message 1 */ 74#define MFI_OMSG0 0x18 /* Outbound message 0 */ 75#define MFI_OMSG1 0x1c /* Outbound message 1 */ 76#define MFI_IDB 0x20 /* Inbound doorbell */ 77#define MFI_ISTS 0x24 /* Inbound interrupt status */ 78#define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79#define MFI_ODB 0x2c /* Outbound doorbell */ 80#define MFI_OSTS 0x30 /* Outbound interrupt status */ 81#define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82#define MFI_IQP 0x40 /* Inbound queue port */ 83#define MFI_OQP 0x44 /* Outbound queue port */ 84 85/* 86* ThunderBolt specific Register 87*/ 88 89#define MFI_RFPI 0x48 /* reply_free_post_host_index */ 90#define MFI_RPI 0x6c /* reply_post_host_index */ 91#define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 92#define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 93 94/* 95 * 1078 specific related register 96 */ 97#define MFI_ODR0 0x9c /* outbound doorbell register0 */ 98#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 99#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 100#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 101#define MFI_RMI 0x2 /* reply message interrupt */ 102#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 103#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 104 105/* OCR registers */ 106#define MFI_WSR 0x004 /* write sequence register */ 107#define MFI_HDR 0x008 /* host diagnostic register */ 108#define MFI_RSR 0x3c3 /* Reset Status Register */ 109 110/* 111 * GEN2 specific changes 112 */ 113#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 114#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 115 116/* 117 * skinny specific changes 118 */ 119#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 120#define MFI_IQPL 0x000000c0 121#define MFI_IQPH 0x000000c4 122#define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 123 124/* Bits for MFI_OSTS */ 125#define MFI_OSTS_INTR_VALID 0x00000002 126 127/* OCR specific flags */ 128#define MFI_FIRMWARE_STATE_CHANGE 0x00000002 129#define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 130 131/* 132 * Firmware state values. Found in OMSG0 during initialization. 133 */ 134#define MFI_FWSTATE_MASK 0xf0000000 135#define MFI_FWSTATE_UNDEFINED 0x00000000 136#define MFI_FWSTATE_BB_INIT 0x10000000 137#define MFI_FWSTATE_FW_INIT 0x40000000 138#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 139#define MFI_FWSTATE_FW_INIT_2 0x70000000 140#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 141#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 142#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 143#define MFI_FWSTATE_READY 0xb0000000 144#define MFI_FWSTATE_OPERATIONAL 0xc0000000 145#define MFI_FWSTATE_FAULT 0xf0000000 146#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 147#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 148#define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 149#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 150#define MFI_RESET_REQUIRED 0x00000001 151 152/* ThunderBolt Support */ 153#define MFI_FWSTATE_TB_MASK 0xf0000000 154#define MFI_FWSTATE_TB_RESET 0x00000000 155#define MFI_FWSTATE_TB_READY 0x10000000 156#define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 157#define MFI_FWSTATE_TB_FAULT 0x40000000 158 159/* 160 * Control bits to drive the card to ready state. These go into the IDB 161 * register. 162 */ 163#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 164#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 165#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 166#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 167#define MFI_FWINIT_HOTPLUG 0x00000010 168 169/* ADP reset flags */ 170#define MFI_STOP_ADP 0x00000020 171#define MFI_ADP_RESET 0x00000040 172#define DIAG_WRITE_ENABLE 0x00000080 173#define DIAG_RESET_ADAPTER 0x00000004 174 175/* MFI Commands */ 176typedef enum { 177 MFI_CMD_INIT = 0x00, 178 MFI_CMD_LD_READ, 179 MFI_CMD_LD_WRITE, 180 MFI_CMD_LD_SCSI_IO, 181 MFI_CMD_PD_SCSI_IO, 182 MFI_CMD_DCMD, 183 MFI_CMD_ABORT, 184 MFI_CMD_SMP, 185 MFI_CMD_STP 186} mfi_cmd_t; 187 188/* Direct commands */ 189typedef enum { 190 MFI_DCMD_CTRL_GETINFO = 0x01010000, 191 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 192 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 193 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 194 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 195 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 196 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 197 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 198 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 199 MFI_DCMD_PR_GET_STATUS = 0x01070100, 200 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 201 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 202 MFI_DCMD_PR_START = 0x01070400, 203 MFI_DCMD_PR_STOP = 0x01070500, 204 MFI_DCMD_TIME_SECS_GET = 0x01080201, 205 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 206 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 207 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 208 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 209 MFI_DCMD_PD_GET_LIST = 0x02010000, 210 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 211 MFI_DCMD_PD_GET_INFO = 0x02020000, 212 MFI_DCMD_PD_STATE_SET = 0x02030100, 213 MFI_DCMD_PD_REBUILD_START = 0x02040100, 214 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 215 MFI_DCMD_PD_CLEAR_START = 0x02050100, 216 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 217 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 218 MFI_DCMD_PD_LOCATE_START = 0x02070100, 219 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 220 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 221 MFI_DCMD_LD_SYNC = 0x0300e102, 222 MFI_DCMD_LD_GET_LIST = 0x03010000, 223 MFI_DCMD_LD_GET_INFO = 0x03020000, 224 MFI_DCMD_LD_GET_PROP = 0x03030000, 225 MFI_DCMD_LD_SET_PROP = 0x03040000, 226 MFI_DCMD_LD_INIT_START = 0x03060100, 227 MFI_DCMD_LD_DELETE = 0x03090000, 228 MFI_DCMD_CFG_READ = 0x04010000, 229 MFI_DCMD_CFG_ADD = 0x04020000, 230 MFI_DCMD_CFG_CLEAR = 0x04030000, 231 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 232 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 233 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 234 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 235 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 236 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 237 MFI_DCMD_BBU_START_LEARN = 0x05040000, 238 MFI_DCMD_BBU_GET_PROP = 0x05050100, 239 MFI_DCMD_BBU_SET_PROP = 0x05050200, 240 MFI_DCMD_CLUSTER = 0x08000000, 241 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 242 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 243} mfi_dcmd_t; 244 245/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 246#define MFI_FLUSHCACHE_CTRL 0x01 247#define MFI_FLUSHCACHE_DISK 0x02 248 249/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 250#define MFI_SHUTDOWN_SPINDOWN 0x01 251 252/* 253 * MFI Frame flags 254 */ 255#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 256#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 257#define MFI_FRAME_SGL32 0x0000 258#define MFI_FRAME_SGL64 0x0002 259#define MFI_FRAME_SENSE32 0x0000 260#define MFI_FRAME_SENSE64 0x0004 261#define MFI_FRAME_DIR_NONE 0x0000 262#define MFI_FRAME_DIR_WRITE 0x0008 263#define MFI_FRAME_DIR_READ 0x0010 264#define MFI_FRAME_DIR_BOTH 0x0018 265#define MFI_FRAME_IEEE_SGL 0x0020 266#define MFI_FRAME_FMT "\20" \ 267 "\1NOPOST" \ 268 "\2SGL64" \ 269 "\3SENSE64" \ 270 "\4WRITE" \ 271 "\5READ" \ 272 "\6IEEESGL" 273 274/* ThunderBolt Specific */ 275 276/* 277 * Pre-TB command size and TB command size. 278 * We will be checking it at the load time for the time being 279 */ 280#define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 281 282#define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 283/* 284 * We are defining only 128 byte message to reduce memory move over head 285 * and also it will reduce the SRB extension size by 128byte compared with 286 * 256 message size 287 */ 288#define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 289#define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 290#define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 291#define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 292#define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 293#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 294 295#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 296#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 297 298#define MR_INTERNAL_MFI_FRAMES_SMID 1 299#define MR_CTRL_EVENT_WAIT_SMID 2 300#define MR_INTERNAL_DRIVER_RESET_SMID 3 301 302 303/* MFI Status codes */ 304typedef enum { 305 MFI_STAT_OK = 0x00, 306 MFI_STAT_INVALID_CMD, 307 MFI_STAT_INVALID_DCMD, 308 MFI_STAT_INVALID_PARAMETER, 309 MFI_STAT_INVALID_SEQUENCE_NUMBER, 310 MFI_STAT_ABORT_NOT_POSSIBLE, 311 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 312 MFI_STAT_APP_IN_USE, 313 MFI_STAT_APP_NOT_INITIALIZED, 314 MFI_STAT_ARRAY_INDEX_INVALID, 315 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 316 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 317 MFI_STAT_DEVICE_NOT_FOUND, 318 MFI_STAT_DRIVE_TOO_SMALL, 319 MFI_STAT_FLASH_ALLOC_FAIL, 320 MFI_STAT_FLASH_BUSY, 321 MFI_STAT_FLASH_ERROR = 0x10, 322 MFI_STAT_FLASH_IMAGE_BAD, 323 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 324 MFI_STAT_FLASH_NOT_OPEN, 325 MFI_STAT_FLASH_NOT_STARTED, 326 MFI_STAT_FLUSH_FAILED, 327 MFI_STAT_HOST_CODE_NOT_FOUNT, 328 MFI_STAT_LD_CC_IN_PROGRESS, 329 MFI_STAT_LD_INIT_IN_PROGRESS, 330 MFI_STAT_LD_LBA_OUT_OF_RANGE, 331 MFI_STAT_LD_MAX_CONFIGURED, 332 MFI_STAT_LD_NOT_OPTIMAL, 333 MFI_STAT_LD_RBLD_IN_PROGRESS, 334 MFI_STAT_LD_RECON_IN_PROGRESS, 335 MFI_STAT_LD_WRONG_RAID_LEVEL, 336 MFI_STAT_MAX_SPARES_EXCEEDED, 337 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 338 MFI_STAT_MFC_HW_ERROR, 339 MFI_STAT_NO_HW_PRESENT, 340 MFI_STAT_NOT_FOUND, 341 MFI_STAT_NOT_IN_ENCL, 342 MFI_STAT_PD_CLEAR_IN_PROGRESS, 343 MFI_STAT_PD_TYPE_WRONG, 344 MFI_STAT_PR_DISABLED, 345 MFI_STAT_ROW_INDEX_INVALID, 346 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 347 MFI_STAT_SAS_CONFIG_INVALID_DATA, 348 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 349 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 350 MFI_STAT_SCSI_DONE_WITH_ERROR, 351 MFI_STAT_SCSI_IO_FAILED, 352 MFI_STAT_SCSI_RESERVATION_CONFLICT, 353 MFI_STAT_SHUTDOWN_FAILED = 0x30, 354 MFI_STAT_TIME_NOT_SET, 355 MFI_STAT_WRONG_STATE, 356 MFI_STAT_LD_OFFLINE, 357 MFI_STAT_PEER_NOTIFICATION_REJECTED, 358 MFI_STAT_PEER_NOTIFICATION_FAILED, 359 MFI_STAT_RESERVATION_IN_PROGRESS, 360 MFI_STAT_I2C_ERRORS_DETECTED, 361 MFI_STAT_PCI_ERRORS_DETECTED, 362 MFI_STAT_DIAG_FAILED, 363 MFI_STAT_BOOT_MSG_PENDING, 364 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 365 MFI_STAT_INVALID_STATUS = 0xFF 366} mfi_status_t; 367 368typedef enum { 369 MFI_EVT_CLASS_DEBUG = -2, 370 MFI_EVT_CLASS_PROGRESS = -1, 371 MFI_EVT_CLASS_INFO = 0, 372 MFI_EVT_CLASS_WARNING = 1, 373 MFI_EVT_CLASS_CRITICAL = 2, 374 MFI_EVT_CLASS_FATAL = 3, 375 MFI_EVT_CLASS_DEAD = 4 376} mfi_evt_class_t; 377 378typedef enum { 379 MFI_EVT_LOCALE_LD = 0x0001, 380 MFI_EVT_LOCALE_PD = 0x0002, 381 MFI_EVT_LOCALE_ENCL = 0x0004, 382 MFI_EVT_LOCALE_BBU = 0x0008, 383 MFI_EVT_LOCALE_SAS = 0x0010, 384 MFI_EVT_LOCALE_CTRL = 0x0020, 385 MFI_EVT_LOCALE_CONFIG = 0x0040, 386 MFI_EVT_LOCALE_CLUSTER = 0x0080, 387 MFI_EVT_LOCALE_ALL = 0xffff 388} mfi_evt_locale_t; 389 390typedef enum { 391 MR_EVT_ARGS_NONE = 0x00, 392 MR_EVT_ARGS_CDB_SENSE, 393 MR_EVT_ARGS_LD, 394 MR_EVT_ARGS_LD_COUNT, 395 MR_EVT_ARGS_LD_LBA, 396 MR_EVT_ARGS_LD_OWNER, 397 MR_EVT_ARGS_LD_LBA_PD_LBA, 398 MR_EVT_ARGS_LD_PROG, 399 MR_EVT_ARGS_LD_STATE, 400 MR_EVT_ARGS_LD_STRIP, 401 MR_EVT_ARGS_PD, 402 MR_EVT_ARGS_PD_ERR, 403 MR_EVT_ARGS_PD_LBA, 404 MR_EVT_ARGS_PD_LBA_LD, 405 MR_EVT_ARGS_PD_PROG, 406 MR_EVT_ARGS_PD_STATE, 407 MR_EVT_ARGS_PCI, 408 MR_EVT_ARGS_RATE, 409 MR_EVT_ARGS_STR, 410 MR_EVT_ARGS_TIME, 411 MR_EVT_ARGS_ECC 412} mfi_evt_args; 413 414#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 415#define MR_EVT_PD_REMOVED 0x0070 416#define MR_EVT_PD_INSERTED 0x005b 417#define MR_EVT_LD_CHANGE 0x0051 418 419typedef enum { 420 MR_LD_CACHE_WRITE_BACK = 0x01, 421 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 422 MR_LD_CACHE_READ_AHEAD = 0x04, 423 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 424 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 425 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 426 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 427} mfi_ld_cache; 428#define MR_LD_CACHE_MASK 0x7f 429 430#define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 431#define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 432#define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 433 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 434#define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 435#define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 436#define MR_LD_CACHE_POLICY_IO_CACHED \ 437 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 438#define MR_LD_CACHE_POLICY_IO_DIRECT 0 439 440typedef enum { 441 MR_PD_CACHE_UNCHANGED = 0, 442 MR_PD_CACHE_ENABLE = 1, 443 MR_PD_CACHE_DISABLE = 2 444} mfi_pd_cache; 445 446typedef enum { 447 MR_PD_QUERY_TYPE_ALL = 0, 448 MR_PD_QUERY_TYPE_STATE = 1, 449 MR_PD_QUERY_TYPE_POWER_STATE = 2, 450 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 451 MR_PD_QUERY_TYPE_SPEED = 4, 452 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 453} mfi_pd_query_type; 454 455/* 456 * Other propertities and definitions 457 */ 458#define MFI_MAX_PD_CHANNELS 2 459#define MFI_MAX_LD_CHANNELS 2 460#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 461#define MFI_MAX_CHANNEL_DEVS 128 462#define MFI_DEFAULT_ID -1 463#define MFI_MAX_LUN 8 464#define MFI_MAX_LD 64 465#define MFI_MAX_PD 256 466 467#define MFI_FRAME_SIZE 64 468#define MFI_MBOX_SIZE 12 469 470/* Firmware flashing can take 50+ seconds */ 471#define MFI_POLL_TIMEOUT_SECS 60 472 473/* Allow for speedier math calculations */ 474#define MFI_SECTOR_LEN 512 475 476/* Scatter Gather elements */ 477struct mfi_sg32 { 478 uint32_t addr; 479 uint32_t len; 480} __packed; 481 482struct mfi_sg64 { 483 uint64_t addr; 484 uint32_t len; 485} __packed; 486 487struct mfi_sg_skinny { 488 uint64_t addr; 489 uint32_t len; 490 uint32_t flag; 491} __packed; 492 493union mfi_sgl { 494 struct mfi_sg32 sg32[1]; 495 struct mfi_sg64 sg64[1]; 496 struct mfi_sg_skinny sg_skinny[1]; 497} __packed; 498 499/* Message frames. All messages have a common header */ 500struct mfi_frame_header { 501 uint8_t cmd; 502 uint8_t sense_len; 503 uint8_t cmd_status; 504 uint8_t scsi_status; 505 uint8_t target_id; 506 uint8_t lun_id; 507 uint8_t cdb_len; 508 uint8_t sg_count; 509 uint32_t context; 510 /* 511 * pad0 is MSI Specific. Not used by Driver. Zero the value before 512 * sending the command to f/w. 513 */ 514 uint32_t pad0; 515 uint16_t flags; 516#define MFI_FRAME_DATAOUT 0x08 517#define MFI_FRAME_DATAIN 0x10 518 uint16_t timeout; 519 uint32_t data_len; 520} __packed; 521 522struct mfi_init_frame { 523 struct mfi_frame_header header; 524 uint32_t qinfo_new_addr_lo; 525 uint32_t qinfo_new_addr_hi; 526 uint32_t qinfo_old_addr_lo; 527 uint32_t qinfo_old_addr_hi; 528 // Start LSIP200113393 529 uint32_t driver_ver_lo; /*28h */ 530 uint32_t driver_ver_hi; /*2Ch */ 531 532 uint32_t reserved[4]; 533 // End LSIP200113393 534} __packed; 535 536/* 537 * Define MFI Address Context union. 538 */ 539#ifdef MFI_ADDRESS_IS_uint64_t 540 typedef uint64_t MFI_ADDRESS; 541#else 542 typedef union _MFI_ADDRESS { 543 struct { 544 uint32_t addressLow; 545 uint32_t addressHigh; 546 } u; 547 uint64_t address; 548 } MFI_ADDRESS, *PMFI_ADDRESS; 549#endif 550 551#define MFI_IO_FRAME_SIZE 40 552struct mfi_io_frame { 553 struct mfi_frame_header header; 554 uint32_t sense_addr_lo; 555 uint32_t sense_addr_hi; 556 uint32_t lba_lo; 557 uint32_t lba_hi; 558 union mfi_sgl sgl; 559} __packed; 560 561#define MFI_PASS_FRAME_SIZE 48 562struct mfi_pass_frame { 563 struct mfi_frame_header header; 564 uint32_t sense_addr_lo; 565 uint32_t sense_addr_hi; 566 uint8_t cdb[16]; 567 union mfi_sgl sgl; 568} __packed; 569 570#define MFI_DCMD_FRAME_SIZE 40 571struct mfi_dcmd_frame { 572 struct mfi_frame_header header; 573 uint32_t opcode; 574 uint8_t mbox[MFI_MBOX_SIZE]; 575 union mfi_sgl sgl; 576} __packed; 577 578struct mfi_abort_frame { 579 struct mfi_frame_header header; 580 uint32_t abort_context; 581 /* pad is changed to reserved.*/ 582 uint32_t reserved0; 583 uint32_t abort_mfi_addr_lo; 584 uint32_t abort_mfi_addr_hi; 585 uint32_t reserved1[6]; 586} __packed; 587 588struct mfi_smp_frame { 589 struct mfi_frame_header header; 590 uint64_t sas_addr; 591 union { 592 struct mfi_sg32 sg32[2]; 593 struct mfi_sg64 sg64[2]; 594 } sgl; 595} __packed; 596 597struct mfi_stp_frame { 598 struct mfi_frame_header header; 599 uint16_t fis[10]; 600 uint32_t stp_flags; 601 union { 602 struct mfi_sg32 sg32[2]; 603 struct mfi_sg64 sg64[2]; 604 } sgl; 605} __packed; 606 607union mfi_frame { 608 struct mfi_frame_header header; 609 struct mfi_init_frame init; 610 /* ThunderBolt Initialization */ 611 struct mfi_io_frame io; 612 struct mfi_pass_frame pass; 613 struct mfi_dcmd_frame dcmd; 614 struct mfi_abort_frame abort; 615 struct mfi_smp_frame smp; 616 struct mfi_stp_frame stp; 617 uint8_t bytes[MFI_FRAME_SIZE]; 618}; 619 620#define MFI_SENSE_LEN 128 621struct mfi_sense { 622 uint8_t data[MFI_SENSE_LEN]; 623}; 624 625/* The queue init structure that is passed with the init message */ 626struct mfi_init_qinfo { 627 uint32_t flags; 628 uint32_t rq_entries; 629 uint32_t rq_addr_lo; 630 uint32_t rq_addr_hi; 631 uint32_t pi_addr_lo; 632 uint32_t pi_addr_hi; 633 uint32_t ci_addr_lo; 634 uint32_t ci_addr_hi; 635} __packed; 636 637/* SAS (?) controller properties, part of mfi_ctrl_info */ 638struct mfi_ctrl_props { 639 uint16_t seq_num; 640 uint16_t pred_fail_poll_interval; 641 uint16_t intr_throttle_cnt; 642 uint16_t intr_throttle_timeout; 643 uint8_t rebuild_rate; 644 uint8_t patrol_read_rate; 645 uint8_t bgi_rate; 646 uint8_t cc_rate; 647 uint8_t recon_rate; 648 uint8_t cache_flush_interval; 649 uint8_t spinup_drv_cnt; 650 uint8_t spinup_delay; 651 uint8_t cluster_enable; 652 uint8_t coercion_mode; 653 uint8_t alarm_enable; 654 uint8_t disable_auto_rebuild; 655 uint8_t disable_battery_warn; 656 uint8_t ecc_bucket_size; 657 uint16_t ecc_bucket_leak_rate; 658 uint8_t restore_hotspare_on_insertion; 659 uint8_t expose_encl_devices; 660 uint8_t maintainPdFailHistory; 661 uint8_t disallowHostRequestReordering; 662 /* set TRUE to abort CC on detecting an inconsistency */ 663 uint8_t abortCCOnError; 664 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 665 uint8_t loadBalanceMode; 666 /* 667 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 668 * h/w mechansim like GPIO pins 669 * 1 - disable auto detect SGPIO, 670 * 2 - disable i2c SEP auto detect 671 * 3 - disable both auto detect 672 */ 673 uint8_t disableAutoDetectBackplane; 674 /* 675 * % of source LD to be reserved for a VDs snapshot in snapshot 676 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 677 */ 678 uint8_t snapVDSpace; 679 680 /* 681 * Add properties that can be controlled by a bit in the following 682 * structure. 683 */ 684 struct { 685 /* set TRUE to disable copyBack (0=copback enabled) */ 686 uint32_t copyBackDisabled :1; 687 uint32_t SMARTerEnabled :1; 688 uint32_t prCorrectUnconfiguredAreas :1; 689 uint32_t useFdeOnly :1; 690 uint32_t disableNCQ :1; 691 uint32_t SSDSMARTerEnabled :1; 692 uint32_t SSDPatrolReadEnabled :1; 693 uint32_t enableSpinDownUnconfigured :1; 694 uint32_t autoEnhancedImport :1; 695 uint32_t enableSecretKeyControl :1; 696 uint32_t disableOnlineCtrlReset :1; 697 uint32_t allowBootWithPinnedCache :1; 698 uint32_t disableSpinDownHS :1; 699 uint32_t enableJBOD :1; 700 uint32_t reserved :18; 701 } OnOffProperties; 702 /* 703 * % of source LD to be reserved for auto snapshot in snapshot 704 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 705 */ 706 uint8_t autoSnapVDSpace; 707 /* 708 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 709 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 710 */ 711 uint8_t viewSpace; 712 /* # of idle minutes before device is spun down (0=use FW defaults) */ 713 uint16_t spinDownTime; 714 uint8_t reserved[24]; 715} __packed; 716 717/* PCI information about the card. */ 718struct mfi_info_pci { 719 uint16_t vendor; 720 uint16_t device; 721 uint16_t subvendor; 722 uint16_t subdevice; 723 uint8_t reserved[24]; 724} __packed; 725 726/* Host (front end) interface information */ 727struct mfi_info_host { 728 uint8_t type; 729#define MFI_INFO_HOST_PCIX 0x01 730#define MFI_INFO_HOST_PCIE 0x02 731#define MFI_INFO_HOST_ISCSI 0x04 732#define MFI_INFO_HOST_SAS3G 0x08 733 uint8_t reserved[6]; 734 uint8_t port_count; 735 uint64_t port_addr[8]; 736} __packed; 737 738/* Device (back end) interface information */ 739struct mfi_info_device { 740 uint8_t type; 741#define MFI_INFO_DEV_SPI 0x01 742#define MFI_INFO_DEV_SAS3G 0x02 743#define MFI_INFO_DEV_SATA1 0x04 744#define MFI_INFO_DEV_SATA3G 0x08 745 uint8_t reserved[6]; 746 uint8_t port_count; 747 uint64_t port_addr[8]; 748} __packed; 749 750/* Firmware component information */ 751struct mfi_info_component { 752 char name[8]; 753 char version[32]; 754 char build_date[16]; 755 char build_time[16]; 756} __packed; 757 758/* Controller default settings */ 759struct mfi_defaults { 760 uint64_t sas_addr; 761 uint8_t phy_polarity; 762 uint8_t background_rate; 763 uint8_t stripe_size; 764 uint8_t flush_time; 765 uint8_t write_back; 766 uint8_t read_ahead; 767 uint8_t cache_when_bbu_bad; 768 uint8_t cached_io; 769 uint8_t smart_mode; 770 uint8_t alarm_disable; 771 uint8_t coercion; 772 uint8_t zrc_config; 773 uint8_t dirty_led_shows_drive_activity; 774 uint8_t bios_continue_on_error; 775 uint8_t spindown_mode; 776 uint8_t allowed_device_types; 777 uint8_t allow_mix_in_enclosure; 778 uint8_t allow_mix_in_ld; 779 uint8_t allow_sata_in_cluster; 780 uint8_t max_chained_enclosures; 781 uint8_t disable_ctrl_r; 782 uint8_t enabel_web_bios; 783 uint8_t phy_polarity_split; 784 uint8_t direct_pd_mapping; 785 uint8_t bios_enumerate_lds; 786 uint8_t restored_hot_spare_on_insertion; 787 uint8_t expose_enclosure_devices; 788 uint8_t maintain_pd_fail_history; 789 uint8_t resv[28]; 790} __packed; 791 792/* Controller default settings */ 793struct mfi_bios_data { 794 uint16_t boot_target_id; 795 uint8_t do_not_int_13; 796 uint8_t continue_on_error; 797 uint8_t verbose; 798 uint8_t geometry; 799 uint8_t expose_all_drives; 800 uint8_t reserved[56]; 801 uint8_t check_sum; 802} __packed; 803 804/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 805struct mfi_ctrl_info { 806 struct mfi_info_pci pci; 807 struct mfi_info_host host; 808 struct mfi_info_device device; 809 810 /* Firmware components that are present and active. */ 811 uint32_t image_check_word; 812 uint32_t image_component_count; 813 struct mfi_info_component image_component[8]; 814 815 /* Firmware components that have been flashed but are inactive */ 816 uint32_t pending_image_component_count; 817 struct mfi_info_component pending_image_component[8]; 818 819 uint8_t max_arms; 820 uint8_t max_spans; 821 uint8_t max_arrays; 822 uint8_t max_lds; 823 char product_name[80]; 824 char serial_number[32]; 825 uint32_t hw_present; 826#define MFI_INFO_HW_BBU 0x01 827#define MFI_INFO_HW_ALARM 0x02 828#define MFI_INFO_HW_NVRAM 0x04 829#define MFI_INFO_HW_UART 0x08 830 uint32_t current_fw_time; 831 uint16_t max_cmds; 832 uint16_t max_sg_elements; 833 uint32_t max_request_size; 834 uint16_t lds_present; 835 uint16_t lds_degraded; 836 uint16_t lds_offline; 837 uint16_t pd_present; 838 uint16_t pd_disks_present; 839 uint16_t pd_disks_pred_failure; 840 uint16_t pd_disks_failed; 841 uint16_t nvram_size; 842 uint16_t memory_size; 843 uint16_t flash_size; 844 uint16_t ram_correctable_errors; 845 uint16_t ram_uncorrectable_errors; 846 uint8_t cluster_allowed; 847 uint8_t cluster_active; 848 uint16_t max_strips_per_io; 849 850 uint32_t raid_levels; 851#define MFI_INFO_RAID_0 0x01 852#define MFI_INFO_RAID_1 0x02 853#define MFI_INFO_RAID_5 0x04 854#define MFI_INFO_RAID_1E 0x08 855#define MFI_INFO_RAID_6 0x10 856 857 uint32_t adapter_ops; 858#define MFI_INFO_AOPS_RBLD_RATE 0x0001 859#define MFI_INFO_AOPS_CC_RATE 0x0002 860#define MFI_INFO_AOPS_BGI_RATE 0x0004 861#define MFI_INFO_AOPS_RECON_RATE 0x0008 862#define MFI_INFO_AOPS_PATROL_RATE 0x0010 863#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 864#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 865#define MFI_INFO_AOPS_BBU 0x0080 866#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 867#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 868#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 869#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 870#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 871#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 872#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 873 874 uint32_t ld_ops; 875#define MFI_INFO_LDOPS_READ_POLICY 0x01 876#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 877#define MFI_INFO_LDOPS_IO_POLICY 0x04 878#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 879#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 880 881 struct { 882 uint8_t min; 883 uint8_t max; 884 uint8_t reserved[2]; 885 } __packed stripe_sz_ops; 886 887 uint32_t pd_ops; 888#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 889#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 890#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 891 892 uint32_t pd_mix_support; 893#define MFI_INFO_PDMIX_SAS 0x01 894#define MFI_INFO_PDMIX_SATA 0x02 895#define MFI_INFO_PDMIX_ENCL 0x04 896#define MFI_INFO_PDMIX_LD 0x08 897#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 898 899 uint8_t ecc_bucket_count; 900 uint8_t reserved2[11]; 901 struct mfi_ctrl_props properties; 902 char package_version[0x60]; 903 uint8_t pad[0x800 - 0x6a0]; 904} __packed; 905 906/* keep track of an event. */ 907union mfi_evt { 908 struct { 909 uint16_t locale; 910 uint8_t reserved; 911 int8_t evt_class; 912 } members; 913 uint32_t word; 914} __packed; 915 916/* event log state. */ 917struct mfi_evt_log_state { 918 uint32_t newest_seq_num; 919 uint32_t oldest_seq_num; 920 uint32_t clear_seq_num; 921 uint32_t shutdown_seq_num; 922 uint32_t boot_seq_num; 923} __packed; 924 925struct mfi_progress { 926 uint16_t progress; 927 uint16_t elapsed_seconds; 928} __packed; 929 930struct mfi_evt_ld { 931 uint16_t target_id; 932 uint8_t ld_index; 933 uint8_t reserved; 934} __packed; 935 936struct mfi_evt_pd { 937 uint16_t device_id; 938 uint8_t enclosure_index; 939 uint8_t slot_number; 940} __packed; 941 942/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 943struct mfi_evt_detail { 944 uint32_t seq; 945 uint32_t time; 946 uint32_t code; 947 union mfi_evt evt_class; 948 uint8_t arg_type; 949 uint8_t reserved1[15]; 950 951 union { 952 struct { 953 struct mfi_evt_pd pd; 954 uint8_t cdb_len; 955 uint8_t sense_len; 956 uint8_t reserved[2]; 957 uint8_t cdb[16]; 958 uint8_t sense[64]; 959 } cdb_sense; 960 961 struct mfi_evt_ld ld; 962 963 struct { 964 struct mfi_evt_ld ld; 965 uint64_t count; 966 } ld_count; 967 968 struct { 969 uint64_t lba; 970 struct mfi_evt_ld ld; 971 } ld_lba; 972 973 struct { 974 struct mfi_evt_ld ld; 975 uint32_t pre_owner; 976 uint32_t new_owner; 977 } ld_owner; 978 979 struct { 980 uint64_t ld_lba; 981 uint64_t pd_lba; 982 struct mfi_evt_ld ld; 983 struct mfi_evt_pd pd; 984 } ld_lba_pd_lba; 985 986 struct { 987 struct mfi_evt_ld ld; 988 struct mfi_progress prog; 989 } ld_prog; 990 991 struct { 992 struct mfi_evt_ld ld; 993 uint32_t prev_state; 994 uint32_t new_state; 995 } ld_state; 996 997 struct { 998 uint64_t strip; 999 struct mfi_evt_ld ld; 1000 } ld_strip; 1001 1002 struct mfi_evt_pd pd; 1003 1004 struct { 1005 struct mfi_evt_pd pd; 1006 uint32_t err; 1007 } pd_err; 1008 1009 struct { 1010 uint64_t lba; 1011 struct mfi_evt_pd pd; 1012 } pd_lba; 1013 1014 struct { 1015 uint64_t lba; 1016 struct mfi_evt_pd pd; 1017 struct mfi_evt_ld ld; 1018 } pd_lba_ld; 1019 1020 struct { 1021 struct mfi_evt_pd pd; 1022 struct mfi_progress prog; 1023 } pd_prog; 1024 1025 struct { 1026 struct mfi_evt_pd ld; 1027 uint32_t prev_state; 1028 uint32_t new_state; 1029 } pd_state; 1030 1031 struct { 1032 uint16_t venderId; 1033 uint16_t deviceId; 1034 uint16_t subVenderId; 1035 uint16_t subDeviceId; 1036 } pci; 1037 1038 uint32_t rate; 1039 1040 char str[96]; 1041 1042 struct { 1043 uint32_t rtc; 1044 uint16_t elapsedSeconds; 1045 } time; 1046 1047 struct { 1048 uint32_t ecar; 1049 uint32_t elog; 1050 char str[64]; 1051 } ecc; 1052 1053 uint8_t b[96]; 1054 uint16_t s[48]; 1055 uint32_t w[24]; 1056 uint64_t d[12]; 1057 } args; 1058 1059 char description[128]; 1060} __packed; 1061 1062struct mfi_evt_list { 1063 uint32_t count; 1064 uint32_t reserved; 1065 struct mfi_evt_detail event[1]; 1066} __packed; 1067 1068union mfi_pd_ref { 1069 struct { 1070 uint16_t device_id; 1071 uint16_t seq_num; 1072 } v; 1073 uint32_t ref; 1074} __packed; 1075 1076union mfi_pd_ddf_type { 1077 struct { 1078 union { 1079 struct { 1080 uint16_t forced_pd_guid : 1; 1081 uint16_t in_vd : 1; 1082 uint16_t is_global_spare : 1; 1083 uint16_t is_spare : 1; 1084 uint16_t is_foreign : 1; 1085 uint16_t reserved : 7; 1086 uint16_t intf : 4; 1087 } pd_type; 1088 uint16_t type; 1089 } v; 1090 uint16_t reserved; 1091 } ddf; 1092 struct { 1093 uint32_t reserved; 1094 } non_disk; 1095 uint32_t type; 1096} __packed; 1097 1098struct mfi_pd_progress { 1099 uint32_t active; 1100#define MFI_PD_PROGRESS_REBUILD (1<<0) 1101#define MFI_PD_PROGRESS_PATROL (1<<1) 1102#define MFI_PD_PROGRESS_CLEAR (1<<2) 1103 struct mfi_progress rbld; 1104 struct mfi_progress patrol; 1105 struct mfi_progress clear; 1106 struct mfi_progress reserved[4]; 1107} __packed; 1108 1109struct mfi_pd_info { 1110 union mfi_pd_ref ref; 1111 uint8_t inquiry_data[96]; 1112 uint8_t vpd_page83[64]; 1113 uint8_t not_supported; 1114 uint8_t scsi_dev_type; 1115 uint8_t connected_port_bitmap; 1116 uint8_t device_speed; 1117 uint32_t media_err_count; 1118 uint32_t other_err_count; 1119 uint32_t pred_fail_count; 1120 uint32_t last_pred_fail_event_seq_num; 1121 uint16_t fw_state; /* MFI_PD_STATE_* */ 1122 uint8_t disabled_for_removal; 1123 uint8_t link_speed; 1124 union mfi_pd_ddf_type state; 1125 struct { 1126 uint8_t count; 1127 uint8_t is_path_broken; 1128 uint8_t reserved[6]; 1129 uint64_t sas_addr[4]; 1130 } path_info; 1131 uint64_t raw_size; 1132 uint64_t non_coerced_size; 1133 uint64_t coerced_size; 1134 uint16_t encl_device_id; 1135 uint8_t encl_index; 1136 uint8_t slot_number; 1137 struct mfi_pd_progress prog_info; 1138 uint8_t bad_block_table_full; 1139 uint8_t unusable_in_current_config; 1140 uint8_t vpd_page83_ext[64]; 1141 uint8_t reserved[512-358]; 1142} __packed; 1143 1144struct mfi_pd_address { 1145 uint16_t device_id; 1146 uint16_t encl_device_id; 1147 uint8_t encl_index; 1148 uint8_t slot_number; 1149 uint8_t scsi_dev_type; /* 0 = disk */ 1150 uint8_t connect_port_bitmap; 1151 uint64_t sas_addr[2]; 1152} __packed; 1153 1154#define MAX_SYS_PDS 240 1155struct mfi_pd_list { 1156 uint32_t size; 1157 uint32_t count; 1158 struct mfi_pd_address addr[MAX_SYS_PDS]; 1159} __packed; 1160 1161enum mfi_pd_state { 1162 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1163 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1164 MFI_PD_STATE_HOT_SPARE = 0x02, 1165 MFI_PD_STATE_OFFLINE = 0x10, 1166 MFI_PD_STATE_FAILED = 0x11, 1167 MFI_PD_STATE_REBUILD = 0x14, 1168 MFI_PD_STATE_ONLINE = 0x18, 1169 MFI_PD_STATE_COPYBACK = 0x20, 1170 MFI_PD_STATE_SYSTEM = 0x40 1171}; 1172 1173/* 1174 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1175 * Adding a #define to denote this. 1176 */ 1177#define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1178 1179union mfi_ld_ref { 1180 struct { 1181 uint8_t target_id; 1182 uint8_t reserved; 1183 uint16_t seq; 1184 } v; 1185 uint32_t ref; 1186} __packed; 1187 1188struct mfi_ld_list { 1189 uint32_t ld_count; 1190 uint32_t reserved1; 1191 struct { 1192 union mfi_ld_ref ld; 1193 uint8_t state; 1194 uint8_t reserved2[3]; 1195 uint64_t size; 1196 } ld_list[MFI_MAX_LD]; 1197} __packed; 1198 1199enum mfi_ld_access { 1200 MFI_LD_ACCESS_RW = 0, 1201 MFI_LD_ACCSSS_RO = 2, 1202 MFI_LD_ACCESS_BLOCKED = 3, 1203}; 1204#define MFI_LD_ACCESS_MASK 3 1205 1206enum mfi_ld_state { 1207 MFI_LD_STATE_OFFLINE = 0, 1208 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1209 MFI_LD_STATE_DEGRADED = 2, 1210 MFI_LD_STATE_OPTIMAL = 3 1211}; 1212 1213struct mfi_ld_props { 1214 union mfi_ld_ref ld; 1215 char name[16]; 1216 uint8_t default_cache_policy; 1217 uint8_t access_policy; 1218 uint8_t disk_cache_policy; 1219 uint8_t current_cache_policy; 1220 uint8_t no_bgi; 1221 uint8_t reserved[7]; 1222} __packed; 1223 1224struct mfi_ld_params { 1225 uint8_t primary_raid_level; 1226 uint8_t raid_level_qualifier; 1227 uint8_t secondary_raid_level; 1228 uint8_t stripe_size; 1229 uint8_t num_drives; 1230 uint8_t span_depth; 1231 uint8_t state; 1232 uint8_t init_state; 1233#define MFI_LD_PARAMS_INIT_NO 0 1234#define MFI_LD_PARAMS_INIT_QUICK 1 1235#define MFI_LD_PARAMS_INIT_FULL 2 1236 uint8_t is_consistent; 1237 uint8_t reserved1[6]; 1238 uint8_t isSSCD; 1239 uint8_t reserved2[16]; 1240} __packed; 1241 1242struct mfi_ld_progress { 1243 uint32_t active; 1244#define MFI_LD_PROGRESS_CC (1<<0) 1245#define MFI_LD_PROGRESS_BGI (1<<1) 1246#define MFI_LD_PROGRESS_FGI (1<<2) 1247#define MFI_LD_PROGRESS_RECON (1<<3) 1248 struct mfi_progress cc; 1249 struct mfi_progress bgi; 1250 struct mfi_progress fgi; 1251 struct mfi_progress recon; 1252 struct mfi_progress reserved[4]; 1253} __packed; 1254 1255struct mfi_span { 1256 uint64_t start_block; 1257 uint64_t num_blocks; 1258 uint16_t array_ref; 1259 uint8_t reserved[6]; 1260} __packed; 1261 1262#define MFI_MAX_SPAN_DEPTH 8 1263struct mfi_ld_config { 1264 struct mfi_ld_props properties; 1265 struct mfi_ld_params params; 1266 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1267} __packed; 1268 1269struct mfi_ld_info { 1270 struct mfi_ld_config ld_config; 1271 uint64_t size; 1272 struct mfi_ld_progress progress; 1273 uint16_t cluster_owner; 1274 uint8_t reconstruct_active; 1275 uint8_t reserved1[1]; 1276 uint8_t vpd_page83[64]; 1277 uint8_t reserved2[16]; 1278} __packed; 1279 1280#define MFI_MAX_ARRAYS 16 1281struct mfi_spare { 1282 union mfi_pd_ref ref; 1283 uint8_t spare_type; 1284#define MFI_SPARE_DEDICATED (1 << 0) 1285#define MFI_SPARE_REVERTIBLE (1 << 1) 1286#define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1287 uint8_t reserved[2]; 1288 uint8_t array_count; 1289 uint16_t array_ref[MFI_MAX_ARRAYS]; 1290} __packed; 1291 1292#define MFI_MAX_ROW_SIZE 32 1293struct mfi_array { 1294 uint64_t size; 1295 uint8_t num_drives; 1296 uint8_t reserved; 1297 uint16_t array_ref; 1298 uint8_t pad[20]; 1299 struct { 1300 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1301 uint16_t fw_state; /* MFI_PD_STATE_* */ 1302 struct { 1303 uint8_t pd; 1304 uint8_t slot; 1305 } encl; 1306 } pd[MFI_MAX_ROW_SIZE]; 1307} __packed; 1308 1309struct mfi_config_data { 1310 uint32_t size; 1311 uint16_t array_count; 1312 uint16_t array_size; 1313 uint16_t log_drv_count; 1314 uint16_t log_drv_size; 1315 uint16_t spares_count; 1316 uint16_t spares_size; 1317 uint8_t reserved[16]; 1318 struct mfi_array array[0]; 1319 struct mfi_ld_config ld[0]; 1320 struct mfi_spare spare[0]; 1321} __packed; 1322 1323struct mfi_bbu_capacity_info { 1324 uint16_t relative_charge; 1325 uint16_t absolute_charge; 1326 uint16_t remaining_capacity; 1327 uint16_t full_charge_capacity; 1328 uint16_t run_time_to_empty; 1329 uint16_t average_time_to_empty; 1330 uint16_t average_time_to_full; 1331 uint16_t cycle_count; 1332 uint16_t max_error; 1333 uint16_t remaining_capacity_alarm; 1334 uint16_t remaining_time_alarm; 1335 uint8_t reserved[26]; 1336} __packed; 1337 1338struct mfi_bbu_design_info { 1339 uint32_t mfg_date; 1340 uint16_t design_capacity; 1341 uint16_t design_voltage; 1342 uint16_t spec_info; 1343 uint16_t serial_number; 1344 uint16_t pack_stat_config; 1345 uint8_t mfg_name[12]; 1346 uint8_t device_name[8]; 1347 uint8_t device_chemistry[8]; 1348 uint8_t mfg_data[8]; 1349 uint8_t reserved[17]; 1350} __packed; 1351 1352struct mfi_ibbu_state { 1353 uint16_t gas_guage_status; 1354 uint16_t relative_charge; 1355 uint16_t charger_system_state; 1356 uint16_t charger_system_ctrl; 1357 uint16_t charging_current; 1358 uint16_t absolute_charge; 1359 uint16_t max_error; 1360 uint8_t reserved[18]; 1361} __packed; 1362 1363struct mfi_bbu_state { 1364 uint16_t gas_guage_status; 1365 uint16_t relative_charge; 1366 uint16_t charger_status; 1367 uint16_t remaining_capacity; 1368 uint16_t full_charge_capacity; 1369 uint8_t is_SOH_good; 1370 uint8_t reserved[21]; 1371} __packed; 1372 1373struct mfi_bbu_properties { 1374 uint32_t auto_learn_period; 1375 uint32_t next_learn_time; 1376 uint8_t learn_delay_interval; 1377 uint8_t auto_learn_mode; 1378 uint8_t bbu_mode; 1379 uint8_t reserved[21]; 1380} __packed; 1381 1382union mfi_bbu_status_detail { 1383 struct mfi_ibbu_state ibbu; 1384 struct mfi_bbu_state bbu; 1385}; 1386 1387struct mfi_bbu_status { 1388 uint8_t battery_type; 1389#define MFI_BBU_TYPE_NONE 0 1390#define MFI_BBU_TYPE_IBBU 1 1391#define MFI_BBU_TYPE_BBU 2 1392 uint8_t reserved; 1393 uint16_t voltage; 1394 int16_t current; 1395 uint16_t temperature; 1396 uint32_t fw_status; 1397#define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1398#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1399#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1400#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1401#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1402#define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1403#define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1404#define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1405#define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1406#define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1407 uint8_t pad[20]; 1408 union mfi_bbu_status_detail detail; 1409} __packed; 1410 1411enum mfi_pr_state { 1412 MFI_PR_STATE_STOPPED = 0, 1413 MFI_PR_STATE_READY = 1, 1414 MFI_PR_STATE_ACTIVE = 2, 1415 MFI_PR_STATE_ABORTED = 0xff 1416}; 1417 1418struct mfi_pr_status { 1419 uint32_t num_iteration; 1420 uint8_t state; 1421 uint8_t num_pd_done; 1422 uint8_t reserved[10]; 1423}; 1424 1425enum mfi_pr_opmode { 1426 MFI_PR_OPMODE_AUTO = 0, 1427 MFI_PR_OPMODE_MANUAL = 1, 1428 MFI_PR_OPMODE_DISABLED = 2 1429}; 1430 1431struct mfi_pr_properties { 1432 uint8_t op_mode; 1433 uint8_t max_pd; 1434 uint8_t reserved; 1435 uint8_t exclude_ld_count; 1436 uint16_t excluded_ld[MFI_MAX_LD]; 1437 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1438 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1439 uint32_t next_exec; 1440 uint32_t exec_freq; 1441 uint32_t clear_freq; 1442}; 1443 1444/* ThunderBolt support */ 1445 1446/* 1447 * Raid Context structure which describes MegaRAID specific IO Paramenters 1448 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1449 */ 1450typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1451 uint16_t resvd0; /* 0x00 - 0x01 */ 1452 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1453 uint8_t regLockFlags; 1454 uint8_t armId; 1455 uint16_t TargetID; /* 0x06 - 0x07 */ 1456 1457 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1458 1459 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1460 1461 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1462 uint8_t exStatus; /* 0x16 */ 1463 uint8_t Status; /* 0x17 status */ 1464 1465 uint8_t RAIDFlags; /* 0x18 */ 1466 uint8_t numSGE; /* 0x19 numSge */ 1467 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1468 uint8_t spanArm; /* 0x1C */ 1469 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1470} MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1471 1472/***************************************************************************** 1473* 1474* Message Functions 1475* 1476*****************************************************************************/ 1477 1478#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1479#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1480#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1481#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1482#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1483#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1484#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1485#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1486#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1487#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1488#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1489#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1490#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1491#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1492#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1493#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1494#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1495#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1496#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1497#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1498#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1499#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1500#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1501#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1502#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1503#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1504#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1505#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1506#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1507#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1508 1509/* Doorbell functions */ 1510#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1511#define MPI2_FUNCTION_HANDSHAKE (0x42) 1512 1513/***************************************************************************** 1514* 1515* MPI Version Definitions 1516* 1517*****************************************************************************/ 1518 1519#define MPI2_VERSION_MAJOR (0x02) 1520#define MPI2_VERSION_MINOR (0x00) 1521#define MPI2_VERSION_MAJOR_MASK (0xFF00) 1522#define MPI2_VERSION_MAJOR_SHIFT (8) 1523#define MPI2_VERSION_MINOR_MASK (0x00FF) 1524#define MPI2_VERSION_MINOR_SHIFT (0) 1525#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1526 MPI2_VERSION_MINOR) 1527 1528#define MPI2_VERSION_02_00 (0x0200) 1529 1530/* versioning for this MPI header set */ 1531#define MPI2_HEADER_VERSION_UNIT (0x10) 1532#define MPI2_HEADER_VERSION_DEV (0x00) 1533#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1534#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1535#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1536#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1537#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1538 MPI2_HEADER_VERSION_DEV) 1539 1540 1541/* IOCInit Request message */ 1542struct MPI2_IOC_INIT_REQUEST { 1543 uint8_t WhoInit; /* 0x00 */ 1544 uint8_t Reserved1; /* 0x01 */ 1545 uint8_t ChainOffset; /* 0x02 */ 1546 uint8_t Function; /* 0x03 */ 1547 uint16_t Reserved2; /* 0x04 */ 1548 uint8_t Reserved3; /* 0x06 */ 1549 uint8_t MsgFlags; /* 0x07 */ 1550 uint8_t VP_ID; /* 0x08 */ 1551 uint8_t VF_ID; /* 0x09 */ 1552 uint16_t Reserved4; /* 0x0A */ 1553 uint16_t MsgVersion; /* 0x0C */ 1554 uint16_t HeaderVersion; /* 0x0E */ 1555 uint32_t Reserved5; /* 0x10 */ 1556 uint16_t Reserved6; /* 0x14 */ 1557 uint8_t Reserved7; /* 0x16 */ 1558 uint8_t HostMSIxVectors; /* 0x17 */ 1559 uint16_t Reserved8; /* 0x18 */ 1560 uint16_t SystemRequestFrameSize; /* 0x1A */ 1561 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1562 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1563 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1564 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1565 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1566 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1567 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1568 uint64_t TimeStamp; /* 0x40 */ 1569}; 1570 1571/* WhoInit values */ 1572#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1573#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1574#define MPI2_WHOINIT_ROM_BIOS (0x02) 1575#define MPI2_WHOINIT_PCI_PEER (0x03) 1576#define MPI2_WHOINIT_HOST_DRIVER (0x04) 1577#define MPI2_WHOINIT_MANUFACTURER (0x05) 1578 1579struct MPI2_SGE_CHAIN_UNION { 1580 uint16_t Length; 1581 uint8_t NextChainOffset; 1582 uint8_t Flags; 1583 union { 1584 uint32_t Address32; 1585 uint64_t Address64; 1586 } u; 1587}; 1588 1589struct MPI2_IEEE_SGE_SIMPLE32 { 1590 uint32_t Address; 1591 uint32_t FlagsLength; 1592}; 1593 1594struct MPI2_IEEE_SGE_SIMPLE64 { 1595 uint64_t Address; 1596 uint32_t Length; 1597 uint16_t Reserved1; 1598 uint8_t Reserved2; 1599 uint8_t Flags; 1600}; 1601 1602typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1603 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1604 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1605} MPI2_IEEE_SGE_SIMPLE_UNION; 1606 1607typedef struct _MPI2_SGE_SIMPLE_UNION { 1608 uint32_t FlagsLength; 1609 union { 1610 uint32_t Address32; 1611 uint64_t Address64; 1612 } u; 1613} MPI2_SGE_SIMPLE_UNION; 1614 1615/**************************************************************************** 1616* IEEE SGE field definitions and masks 1617****************************************************************************/ 1618 1619/* Flags field bit definitions */ 1620 1621#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1622 1623#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1624 1625#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1626 1627/* Element Type */ 1628 1629#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1630#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1631 1632/* Data Location Address Space */ 1633 1634#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1635#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1636#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1637#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1638#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1639 1640/* Address Size */ 1641 1642#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1643#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1644 1645/*******************/ 1646/* SCSI IO Control bits */ 1647#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1648#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1649 1650#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1651#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1652#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1653#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1654#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1655 1656#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1657#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1658 1659#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1660#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1661#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1662#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1663#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1664 1665#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1666#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1667#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1668#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1669 1670/*******************/ 1671 1672typedef struct { 1673 uint8_t CDB[20]; /* 0x00 */ 1674 uint32_t PrimaryReferenceTag; /* 0x14 */ 1675 uint16_t PrimaryApplicationTag; /* 0x18 */ 1676 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1677 uint32_t TransferLength; /* 0x1C */ 1678} MPI2_SCSI_IO_CDB_EEDP32; 1679 1680 1681typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1682 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1683 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1684} MPI2_IEEE_SGE_CHAIN_UNION; 1685 1686typedef union _MPI2_SIMPLE_SGE_UNION { 1687 MPI2_SGE_SIMPLE_UNION MpiSimple; 1688 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1689} MPI2_SIMPLE_SGE_UNION; 1690 1691typedef union _MPI2_SGE_IO_UNION { 1692 MPI2_SGE_SIMPLE_UNION MpiSimple; 1693 struct MPI2_SGE_CHAIN_UNION MpiChain; 1694 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1695 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1696} MPI2_SGE_IO_UNION; 1697 1698typedef union { 1699 uint8_t CDB32[32]; 1700 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1701 MPI2_SGE_SIMPLE_UNION SGE; 1702} MPI2_SCSI_IO_CDB_UNION; 1703 1704 1705/* MPI 2.5 SGLs */ 1706 1707#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1708 1709typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1710 uint64_t Address; 1711 uint32_t Length; 1712 uint16_t Reserved1; 1713 uint8_t NextChainOffset; 1714 uint8_t Flags; 1715} MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1716 1717/* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1718 1719 1720/********/ 1721 1722/* 1723 * RAID SCSI IO Request Message 1724 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1725 */ 1726struct mfi_mpi2_request_raid_scsi_io { 1727 uint16_t DevHandle; /* 0x00 */ 1728 uint8_t ChainOffset; /* 0x02 */ 1729 uint8_t Function; /* 0x03 */ 1730 uint16_t Reserved1; /* 0x04 */ 1731 uint8_t Reserved2; /* 0x06 */ 1732 uint8_t MsgFlags; /* 0x07 */ 1733 uint8_t VP_ID; /* 0x08 */ 1734 uint8_t VF_ID; /* 0x09 */ 1735 uint16_t Reserved3; /* 0x0A */ 1736 uint32_t SenseBufferLowAddress; /* 0x0C */ 1737 uint16_t SGLFlags; /* 0x10 */ 1738 uint8_t SenseBufferLength; /* 0x12 */ 1739 uint8_t Reserved4; /* 0x13 */ 1740 uint8_t SGLOffset0; /* 0x14 */ 1741 uint8_t SGLOffset1; /* 0x15 */ 1742 uint8_t SGLOffset2; /* 0x16 */ 1743 uint8_t SGLOffset3; /* 0x17 */ 1744 uint32_t SkipCount; /* 0x18 */ 1745 uint32_t DataLength; /* 0x1C */ 1746 uint32_t BidirectionalDataLength; /* 0x20 */ 1747 uint16_t IoFlags; /* 0x24 */ 1748 uint16_t EEDPFlags; /* 0x26 */ 1749 uint32_t EEDPBlockSize; /* 0x28 */ 1750 uint32_t SecondaryReferenceTag; /* 0x2C */ 1751 uint16_t SecondaryApplicationTag; /* 0x30 */ 1752 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1753 uint8_t LUN[8]; /* 0x34 */ 1754 uint32_t Control; /* 0x3C */ 1755 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1756 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1757 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1758} __packed; 1759 1760/* 1761 * MPT RAID MFA IO Descriptor. 1762 */ 1763typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1764 uint32_t RequestFlags : 8; 1765 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1766 uint32_t MessageAddress2; /* bits 61:32 */ 1767} MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1768 1769struct mfi_mpi2_request_header { 1770 uint8_t RequestFlags; /* 0x00 */ 1771 uint8_t MSIxIndex; /* 0x01 */ 1772 uint16_t SMID; /* 0x02 */ 1773 uint16_t LMID; /* 0x04 */ 1774}; 1775 1776/* defines for the RequestFlags field */ 1777#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1778#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1779#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1780#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1781#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1782#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1783 1784#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1785 1786struct mfi_mpi2_request_high_priority { 1787 struct mfi_mpi2_request_header header; 1788 uint16_t reserved; 1789}; 1790 1791struct mfi_mpi2_request_scsi_io { 1792 struct mfi_mpi2_request_header header; 1793 uint16_t scsi_io_dev_handle; 1794}; 1795 1796struct mfi_mpi2_request_scsi_target { 1797 struct mfi_mpi2_request_header header; 1798 uint16_t scsi_target_io_index; 1799}; 1800 1801/* Request Descriptors */ 1802union mfi_mpi2_request_descriptor { 1803 struct mfi_mpi2_request_header header; 1804 struct mfi_mpi2_request_high_priority high_priority; 1805 struct mfi_mpi2_request_scsi_io scsi_io; 1806 struct mfi_mpi2_request_scsi_target scsi_target; 1807 uint64_t words; 1808}; 1809 1810 1811struct mfi_mpi2_reply_header { 1812 uint8_t ReplyFlags; /* 0x00 */ 1813 uint8_t MSIxIndex; /* 0x01 */ 1814 uint16_t SMID; /* 0x02 */ 1815}; 1816 1817/* defines for the ReplyFlags field */ 1818#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1819#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1820#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1821#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1822#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1823#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1824#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1825 1826/* values for marking a reply descriptor as unused */ 1827#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1828#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1829 1830struct mfi_mpi2_reply_default { 1831 struct mfi_mpi2_reply_header header; 1832 uint32_t DescriptorTypeDependent2; 1833}; 1834 1835struct mfi_mpi2_reply_address { 1836 struct mfi_mpi2_reply_header header; 1837 uint32_t ReplyFrameAddress; 1838}; 1839 1840struct mfi_mpi2_reply_scsi_io { 1841 struct mfi_mpi2_reply_header header; 1842 uint16_t TaskTag; /* 0x04 */ 1843 uint16_t Reserved1; /* 0x06 */ 1844}; 1845 1846struct mfi_mpi2_reply_target_assist { 1847 struct mfi_mpi2_reply_header header; 1848 uint8_t SequenceNumber; /* 0x04 */ 1849 uint8_t Reserved1; /* 0x04 */ 1850 uint16_t IoIndex; /* 0x06 */ 1851}; 1852 1853struct mfi_mpi2_reply_target_cmd_buffer { 1854 struct mfi_mpi2_reply_header header; 1855 uint8_t SequenceNumber; /* 0x04 */ 1856 uint8_t Flags; /* 0x04 */ 1857 uint16_t InitiatorDevHandle; /* 0x06 */ 1858 uint16_t IoIndex; /* 0x06 */ 1859}; 1860 1861struct mfi_mpi2_reply_raid_accel { 1862 struct mfi_mpi2_reply_header header; 1863 uint8_t SequenceNumber; /* 0x04 */ 1864 uint32_t Reserved; /* 0x04 */ 1865}; 1866 1867/* union of Reply Descriptors */ 1868union mfi_mpi2_reply_descriptor { 1869 struct mfi_mpi2_reply_header header; 1870 struct mfi_mpi2_reply_scsi_io scsi_io; 1871 struct mfi_mpi2_reply_target_assist target_assist; 1872 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1873 struct mfi_mpi2_reply_raid_accel raid_accel; 1874 struct mfi_mpi2_reply_default reply_default; 1875 uint64_t words; 1876}; 1877 1878struct IO_REQUEST_INFO { 1879 uint64_t ldStartBlock; 1880 uint32_t numBlocks; 1881 uint16_t ldTgtId; 1882 uint8_t isRead; 1883 uint16_t devHandle; 1884 uint64_t pdBlock; 1885 uint8_t fpOkForIo; 1886}; 1887 1888#define MFI_SCSI_MAX_TARGETS 128 1889#define MFI_SCSI_MAX_LUNS 8 1890#define MFI_SCSI_INITIATOR_ID 255 1891#define MFI_SCSI_MAX_CMDS 8 1892#define MFI_SCSI_MAX_CDB_LEN 16 1893 1894#endif /* _MFIREG_H */ 1895