mfireg.h revision 250482
1/*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26/*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53#ifndef _MFIREG_H 54#define _MFIREG_H 55 56#include <sys/cdefs.h> 57__FBSDID("$FreeBSD: stable/9/sys/dev/mfi/mfireg.h 250482 2013-05-10 21:08:53Z markj $"); 58 59/* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67#define MEGAMFI_FRAME_SIZE 64 68/* 69 * Start with the register set. All registers are 32 bits wide. 70 * The usual Intel IOP style setup. 71 */ 72#define MFI_IMSG0 0x10 /* Inbound message 0 */ 73#define MFI_IMSG1 0x14 /* Inbound message 1 */ 74#define MFI_OMSG0 0x18 /* Outbound message 0 */ 75#define MFI_OMSG1 0x1c /* Outbound message 1 */ 76#define MFI_IDB 0x20 /* Inbound doorbell */ 77#define MFI_ISTS 0x24 /* Inbound interrupt status */ 78#define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79#define MFI_ODB 0x2c /* Outbound doorbell */ 80#define MFI_OSTS 0x30 /* Outbound interrupt status */ 81#define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82#define MFI_IQP 0x40 /* Inbound queue port */ 83#define MFI_OQP 0x44 /* Outbound queue port */ 84 85/* 86* ThunderBolt specific Register 87*/ 88 89#define MFI_RPI 0x6c /* reply_post_host_index */ 90#define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 91#define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 92 93/* 94 * 1078 specific related register 95 */ 96#define MFI_ODR0 0x9c /* outbound doorbell register0 */ 97#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 98#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 99#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 100#define MFI_RMI 0x2 /* reply message interrupt */ 101#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 102#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 103 104/* OCR registers */ 105#define MFI_WSR 0x004 /* write sequence register */ 106#define MFI_HDR 0x008 /* host diagnostic register */ 107#define MFI_RSR 0x3c3 /* Reset Status Register */ 108 109/* 110 * GEN2 specific changes 111 */ 112#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 113#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 114 115/* 116 * skinny specific changes 117 */ 118#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 119#define MFI_IQPL 0x000000c0 120#define MFI_IQPH 0x000000c4 121#define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 122 123/* Bits for MFI_OSTS */ 124#define MFI_OSTS_INTR_VALID 0x00000002 125 126/* OCR specific flags */ 127#define MFI_FIRMWARE_STATE_CHANGE 0x00000002 128#define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 129 130/* 131 * Firmware state values. Found in OMSG0 during initialization. 132 */ 133#define MFI_FWSTATE_MASK 0xf0000000 134#define MFI_FWSTATE_UNDEFINED 0x00000000 135#define MFI_FWSTATE_BB_INIT 0x10000000 136#define MFI_FWSTATE_FW_INIT 0x40000000 137#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 138#define MFI_FWSTATE_FW_INIT_2 0x70000000 139#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 140#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 141#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 142#define MFI_FWSTATE_READY 0xb0000000 143#define MFI_FWSTATE_OPERATIONAL 0xc0000000 144#define MFI_FWSTATE_FAULT 0xf0000000 145#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 146#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 147#define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 148#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 149#define MFI_RESET_REQUIRED 0x00000001 150 151/* ThunderBolt Support */ 152#define MFI_FWSTATE_TB_MASK 0xf0000000 153#define MFI_FWSTATE_TB_RESET 0x00000000 154#define MFI_FWSTATE_TB_READY 0x10000000 155#define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 156#define MFI_FWSTATE_TB_FAULT 0x40000000 157 158/* 159 * Control bits to drive the card to ready state. These go into the IDB 160 * register. 161 */ 162#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 163#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 164#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 165#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 166#define MFI_FWINIT_HOTPLUG 0x00000010 167 168/* ADP reset flags */ 169#define MFI_STOP_ADP 0x00000020 170#define MFI_ADP_RESET 0x00000040 171#define DIAG_WRITE_ENABLE 0x00000080 172#define DIAG_RESET_ADAPTER 0x00000004 173 174/* MFI Commands */ 175typedef enum { 176 MFI_CMD_INIT = 0x00, 177 MFI_CMD_LD_READ, 178 MFI_CMD_LD_WRITE, 179 MFI_CMD_LD_SCSI_IO, 180 MFI_CMD_PD_SCSI_IO, 181 MFI_CMD_DCMD, 182 MFI_CMD_ABORT, 183 MFI_CMD_SMP, 184 MFI_CMD_STP 185} mfi_cmd_t; 186 187/* Direct commands */ 188typedef enum { 189 MFI_DCMD_CTRL_GETINFO = 0x01010000, 190 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 191 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 192 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 193 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 194 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 195 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 196 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 197 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 198 MFI_DCMD_PR_GET_STATUS = 0x01070100, 199 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 200 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 201 MFI_DCMD_PR_START = 0x01070400, 202 MFI_DCMD_PR_STOP = 0x01070500, 203 MFI_DCMD_TIME_SECS_GET = 0x01080201, 204 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 205 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 206 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 207 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 208 MFI_DCMD_PD_GET_LIST = 0x02010000, 209 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 210 MFI_DCMD_PD_GET_INFO = 0x02020000, 211 MFI_DCMD_PD_STATE_SET = 0x02030100, 212 MFI_DCMD_PD_REBUILD_START = 0x02040100, 213 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 214 MFI_DCMD_PD_CLEAR_START = 0x02050100, 215 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 216 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 217 MFI_DCMD_PD_LOCATE_START = 0x02070100, 218 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 219 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 220 MFI_DCMD_LD_SYNC = 0x0300e102, 221 MFI_DCMD_LD_GET_LIST = 0x03010000, 222 MFI_DCMD_LD_GET_INFO = 0x03020000, 223 MFI_DCMD_LD_GET_PROP = 0x03030000, 224 MFI_DCMD_LD_SET_PROP = 0x03040000, 225 MFI_DCMD_LD_INIT_START = 0x03060100, 226 MFI_DCMD_LD_DELETE = 0x03090000, 227 MFI_DCMD_CFG_READ = 0x04010000, 228 MFI_DCMD_CFG_ADD = 0x04020000, 229 MFI_DCMD_CFG_CLEAR = 0x04030000, 230 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 231 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 232 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 233 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 234 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 235 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 236 MFI_DCMD_BBU_START_LEARN = 0x05040000, 237 MFI_DCMD_BBU_GET_PROP = 0x05050100, 238 MFI_DCMD_BBU_SET_PROP = 0x05050200, 239 MFI_DCMD_CLUSTER = 0x08000000, 240 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 241 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 242} mfi_dcmd_t; 243 244/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 245#define MFI_FLUSHCACHE_CTRL 0x01 246#define MFI_FLUSHCACHE_DISK 0x02 247 248/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 249#define MFI_SHUTDOWN_SPINDOWN 0x01 250 251/* 252 * MFI Frame flags 253 */ 254#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 255#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 256#define MFI_FRAME_SGL32 0x0000 257#define MFI_FRAME_SGL64 0x0002 258#define MFI_FRAME_SENSE32 0x0000 259#define MFI_FRAME_SENSE64 0x0004 260#define MFI_FRAME_DIR_NONE 0x0000 261#define MFI_FRAME_DIR_WRITE 0x0008 262#define MFI_FRAME_DIR_READ 0x0010 263#define MFI_FRAME_DIR_BOTH 0x0018 264#define MFI_FRAME_IEEE_SGL 0x0020 265 266/* ThunderBolt Specific */ 267 268/* 269 * Pre-TB command size and TB command size. 270 * We will be checking it at the load time for the time being 271 */ 272#define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 273 274#define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 275/* 276 * We are defining only 128 byte message to reduce memory move over head 277 * and also it will reduce the SRB extension size by 128byte compared with 278 * 256 message size 279 */ 280#define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 281#define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 282#define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 283#define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 284#define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 285#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 286 287#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 288#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 289 290#define MR_INTERNAL_MFI_FRAMES_SMID 1 291#define MR_CTRL_EVENT_WAIT_SMID 2 292#define MR_INTERNAL_DRIVER_RESET_SMID 3 293 294 295/* MFI Status codes */ 296typedef enum { 297 MFI_STAT_OK = 0x00, 298 MFI_STAT_INVALID_CMD, 299 MFI_STAT_INVALID_DCMD, 300 MFI_STAT_INVALID_PARAMETER, 301 MFI_STAT_INVALID_SEQUENCE_NUMBER, 302 MFI_STAT_ABORT_NOT_POSSIBLE, 303 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 304 MFI_STAT_APP_IN_USE, 305 MFI_STAT_APP_NOT_INITIALIZED, 306 MFI_STAT_ARRAY_INDEX_INVALID, 307 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 308 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 309 MFI_STAT_DEVICE_NOT_FOUND, 310 MFI_STAT_DRIVE_TOO_SMALL, 311 MFI_STAT_FLASH_ALLOC_FAIL, 312 MFI_STAT_FLASH_BUSY, 313 MFI_STAT_FLASH_ERROR = 0x10, 314 MFI_STAT_FLASH_IMAGE_BAD, 315 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 316 MFI_STAT_FLASH_NOT_OPEN, 317 MFI_STAT_FLASH_NOT_STARTED, 318 MFI_STAT_FLUSH_FAILED, 319 MFI_STAT_HOST_CODE_NOT_FOUNT, 320 MFI_STAT_LD_CC_IN_PROGRESS, 321 MFI_STAT_LD_INIT_IN_PROGRESS, 322 MFI_STAT_LD_LBA_OUT_OF_RANGE, 323 MFI_STAT_LD_MAX_CONFIGURED, 324 MFI_STAT_LD_NOT_OPTIMAL, 325 MFI_STAT_LD_RBLD_IN_PROGRESS, 326 MFI_STAT_LD_RECON_IN_PROGRESS, 327 MFI_STAT_LD_WRONG_RAID_LEVEL, 328 MFI_STAT_MAX_SPARES_EXCEEDED, 329 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 330 MFI_STAT_MFC_HW_ERROR, 331 MFI_STAT_NO_HW_PRESENT, 332 MFI_STAT_NOT_FOUND, 333 MFI_STAT_NOT_IN_ENCL, 334 MFI_STAT_PD_CLEAR_IN_PROGRESS, 335 MFI_STAT_PD_TYPE_WRONG, 336 MFI_STAT_PR_DISABLED, 337 MFI_STAT_ROW_INDEX_INVALID, 338 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 339 MFI_STAT_SAS_CONFIG_INVALID_DATA, 340 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 341 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 342 MFI_STAT_SCSI_DONE_WITH_ERROR, 343 MFI_STAT_SCSI_IO_FAILED, 344 MFI_STAT_SCSI_RESERVATION_CONFLICT, 345 MFI_STAT_SHUTDOWN_FAILED = 0x30, 346 MFI_STAT_TIME_NOT_SET, 347 MFI_STAT_WRONG_STATE, 348 MFI_STAT_LD_OFFLINE, 349 MFI_STAT_PEER_NOTIFICATION_REJECTED, 350 MFI_STAT_PEER_NOTIFICATION_FAILED, 351 MFI_STAT_RESERVATION_IN_PROGRESS, 352 MFI_STAT_I2C_ERRORS_DETECTED, 353 MFI_STAT_PCI_ERRORS_DETECTED, 354 MFI_STAT_DIAG_FAILED, 355 MFI_STAT_BOOT_MSG_PENDING, 356 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 357 MFI_STAT_INVALID_STATUS = 0xFF 358} mfi_status_t; 359 360typedef enum { 361 MFI_EVT_CLASS_DEBUG = -2, 362 MFI_EVT_CLASS_PROGRESS = -1, 363 MFI_EVT_CLASS_INFO = 0, 364 MFI_EVT_CLASS_WARNING = 1, 365 MFI_EVT_CLASS_CRITICAL = 2, 366 MFI_EVT_CLASS_FATAL = 3, 367 MFI_EVT_CLASS_DEAD = 4 368} mfi_evt_class_t; 369 370typedef enum { 371 MFI_EVT_LOCALE_LD = 0x0001, 372 MFI_EVT_LOCALE_PD = 0x0002, 373 MFI_EVT_LOCALE_ENCL = 0x0004, 374 MFI_EVT_LOCALE_BBU = 0x0008, 375 MFI_EVT_LOCALE_SAS = 0x0010, 376 MFI_EVT_LOCALE_CTRL = 0x0020, 377 MFI_EVT_LOCALE_CONFIG = 0x0040, 378 MFI_EVT_LOCALE_CLUSTER = 0x0080, 379 MFI_EVT_LOCALE_ALL = 0xffff 380} mfi_evt_locale_t; 381 382typedef enum { 383 MR_EVT_ARGS_NONE = 0x00, 384 MR_EVT_ARGS_CDB_SENSE, 385 MR_EVT_ARGS_LD, 386 MR_EVT_ARGS_LD_COUNT, 387 MR_EVT_ARGS_LD_LBA, 388 MR_EVT_ARGS_LD_OWNER, 389 MR_EVT_ARGS_LD_LBA_PD_LBA, 390 MR_EVT_ARGS_LD_PROG, 391 MR_EVT_ARGS_LD_STATE, 392 MR_EVT_ARGS_LD_STRIP, 393 MR_EVT_ARGS_PD, 394 MR_EVT_ARGS_PD_ERR, 395 MR_EVT_ARGS_PD_LBA, 396 MR_EVT_ARGS_PD_LBA_LD, 397 MR_EVT_ARGS_PD_PROG, 398 MR_EVT_ARGS_PD_STATE, 399 MR_EVT_ARGS_PCI, 400 MR_EVT_ARGS_RATE, 401 MR_EVT_ARGS_STR, 402 MR_EVT_ARGS_TIME, 403 MR_EVT_ARGS_ECC 404} mfi_evt_args; 405 406#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 407#define MR_EVT_PD_REMOVED 0x0070 408#define MR_EVT_PD_INSERTED 0x005b 409#define MR_EVT_LD_CHANGE 0x0051 410 411typedef enum { 412 MR_LD_CACHE_WRITE_BACK = 0x01, 413 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 414 MR_LD_CACHE_READ_AHEAD = 0x04, 415 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 416 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 417 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 418 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 419} mfi_ld_cache; 420#define MR_LD_CACHE_MASK 0x7f 421 422#define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 423#define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 424#define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 425 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 426#define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 427#define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 428#define MR_LD_CACHE_POLICY_IO_CACHED \ 429 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 430#define MR_LD_CACHE_POLICY_IO_DIRECT 0 431 432typedef enum { 433 MR_PD_CACHE_UNCHANGED = 0, 434 MR_PD_CACHE_ENABLE = 1, 435 MR_PD_CACHE_DISABLE = 2 436} mfi_pd_cache; 437 438typedef enum { 439 MR_PD_QUERY_TYPE_ALL = 0, 440 MR_PD_QUERY_TYPE_STATE = 1, 441 MR_PD_QUERY_TYPE_POWER_STATE = 2, 442 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 443 MR_PD_QUERY_TYPE_SPEED = 4, 444 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 445} mfi_pd_query_type; 446 447/* 448 * Other propertities and definitions 449 */ 450#define MFI_MAX_PD_CHANNELS 2 451#define MFI_MAX_LD_CHANNELS 2 452#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 453#define MFI_MAX_CHANNEL_DEVS 128 454#define MFI_DEFAULT_ID -1 455#define MFI_MAX_LUN 8 456#define MFI_MAX_LD 64 457#define MFI_MAX_PD 256 458 459#define MFI_FRAME_SIZE 64 460#define MFI_MBOX_SIZE 12 461 462/* Firmware flashing can take 40s */ 463#define MFI_POLL_TIMEOUT_SECS 50 464 465/* Allow for speedier math calculations */ 466#define MFI_SECTOR_LEN 512 467 468/* Scatter Gather elements */ 469struct mfi_sg32 { 470 uint32_t addr; 471 uint32_t len; 472} __packed; 473 474struct mfi_sg64 { 475 uint64_t addr; 476 uint32_t len; 477} __packed; 478 479struct mfi_sg_skinny { 480 uint64_t addr; 481 uint32_t len; 482 uint32_t flag; 483} __packed; 484 485union mfi_sgl { 486 struct mfi_sg32 sg32[1]; 487 struct mfi_sg64 sg64[1]; 488 struct mfi_sg_skinny sg_skinny[1]; 489} __packed; 490 491/* Message frames. All messages have a common header */ 492struct mfi_frame_header { 493 uint8_t cmd; 494 uint8_t sense_len; 495 uint8_t cmd_status; 496 uint8_t scsi_status; 497 uint8_t target_id; 498 uint8_t lun_id; 499 uint8_t cdb_len; 500 uint8_t sg_count; 501 uint32_t context; 502 /* 503 * pad0 is MSI Specific. Not used by Driver. Zero the value before 504 * sending the command to f/w. 505 */ 506 uint32_t pad0; 507 uint16_t flags; 508#define MFI_FRAME_DATAOUT 0x08 509#define MFI_FRAME_DATAIN 0x10 510 uint16_t timeout; 511 uint32_t data_len; 512} __packed; 513 514struct mfi_init_frame { 515 struct mfi_frame_header header; 516 uint32_t qinfo_new_addr_lo; 517 uint32_t qinfo_new_addr_hi; 518 uint32_t qinfo_old_addr_lo; 519 uint32_t qinfo_old_addr_hi; 520 // Start LSIP200113393 521 uint32_t driver_ver_lo; /*28h */ 522 uint32_t driver_ver_hi; /*2Ch */ 523 524 uint32_t reserved[4]; 525 // End LSIP200113393 526} __packed; 527 528/* 529 * Define MFI Address Context union. 530 */ 531#ifdef MFI_ADDRESS_IS_uint64_t 532 typedef uint64_t MFI_ADDRESS; 533#else 534 typedef union _MFI_ADDRESS { 535 struct { 536 uint32_t addressLow; 537 uint32_t addressHigh; 538 } u; 539 uint64_t address; 540 } MFI_ADDRESS, *PMFI_ADDRESS; 541#endif 542 543#define MFI_IO_FRAME_SIZE 40 544struct mfi_io_frame { 545 struct mfi_frame_header header; 546 uint32_t sense_addr_lo; 547 uint32_t sense_addr_hi; 548 uint32_t lba_lo; 549 uint32_t lba_hi; 550 union mfi_sgl sgl; 551} __packed; 552 553#define MFI_PASS_FRAME_SIZE 48 554struct mfi_pass_frame { 555 struct mfi_frame_header header; 556 uint32_t sense_addr_lo; 557 uint32_t sense_addr_hi; 558 uint8_t cdb[16]; 559 union mfi_sgl sgl; 560} __packed; 561 562#define MFI_DCMD_FRAME_SIZE 40 563struct mfi_dcmd_frame { 564 struct mfi_frame_header header; 565 uint32_t opcode; 566 uint8_t mbox[MFI_MBOX_SIZE]; 567 union mfi_sgl sgl; 568} __packed; 569 570struct mfi_abort_frame { 571 struct mfi_frame_header header; 572 uint32_t abort_context; 573 /* pad is changed to reserved.*/ 574 uint32_t reserved0; 575 uint32_t abort_mfi_addr_lo; 576 uint32_t abort_mfi_addr_hi; 577 uint32_t reserved1[6]; 578} __packed; 579 580struct mfi_smp_frame { 581 struct mfi_frame_header header; 582 uint64_t sas_addr; 583 union { 584 struct mfi_sg32 sg32[2]; 585 struct mfi_sg64 sg64[2]; 586 } sgl; 587} __packed; 588 589struct mfi_stp_frame { 590 struct mfi_frame_header header; 591 uint16_t fis[10]; 592 uint32_t stp_flags; 593 union { 594 struct mfi_sg32 sg32[2]; 595 struct mfi_sg64 sg64[2]; 596 } sgl; 597} __packed; 598 599union mfi_frame { 600 struct mfi_frame_header header; 601 struct mfi_init_frame init; 602 /* ThunderBolt Initialization */ 603 struct mfi_io_frame io; 604 struct mfi_pass_frame pass; 605 struct mfi_dcmd_frame dcmd; 606 struct mfi_abort_frame abort; 607 struct mfi_smp_frame smp; 608 struct mfi_stp_frame stp; 609 uint8_t bytes[MFI_FRAME_SIZE]; 610}; 611 612#define MFI_SENSE_LEN 128 613struct mfi_sense { 614 uint8_t data[MFI_SENSE_LEN]; 615}; 616 617/* The queue init structure that is passed with the init message */ 618struct mfi_init_qinfo { 619 uint32_t flags; 620 uint32_t rq_entries; 621 uint32_t rq_addr_lo; 622 uint32_t rq_addr_hi; 623 uint32_t pi_addr_lo; 624 uint32_t pi_addr_hi; 625 uint32_t ci_addr_lo; 626 uint32_t ci_addr_hi; 627} __packed; 628 629/* SAS (?) controller properties, part of mfi_ctrl_info */ 630struct mfi_ctrl_props { 631 uint16_t seq_num; 632 uint16_t pred_fail_poll_interval; 633 uint16_t intr_throttle_cnt; 634 uint16_t intr_throttle_timeout; 635 uint8_t rebuild_rate; 636 uint8_t patrol_read_rate; 637 uint8_t bgi_rate; 638 uint8_t cc_rate; 639 uint8_t recon_rate; 640 uint8_t cache_flush_interval; 641 uint8_t spinup_drv_cnt; 642 uint8_t spinup_delay; 643 uint8_t cluster_enable; 644 uint8_t coercion_mode; 645 uint8_t alarm_enable; 646 uint8_t disable_auto_rebuild; 647 uint8_t disable_battery_warn; 648 uint8_t ecc_bucket_size; 649 uint16_t ecc_bucket_leak_rate; 650 uint8_t restore_hotspare_on_insertion; 651 uint8_t expose_encl_devices; 652 uint8_t maintainPdFailHistory; 653 uint8_t disallowHostRequestReordering; 654 /* set TRUE to abort CC on detecting an inconsistency */ 655 uint8_t abortCCOnError; 656 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 657 uint8_t loadBalanceMode; 658 /* 659 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 660 * h/w mechansim like GPIO pins 661 * 1 - disable auto detect SGPIO, 662 * 2 - disable i2c SEP auto detect 663 * 3 - disable both auto detect 664 */ 665 uint8_t disableAutoDetectBackplane; 666 /* 667 * % of source LD to be reserved for a VDs snapshot in snapshot 668 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 669 */ 670 uint8_t snapVDSpace; 671 672 /* 673 * Add properties that can be controlled by a bit in the following 674 * structure. 675 */ 676 struct { 677 /* set TRUE to disable copyBack (0=copback enabled) */ 678 uint32_t copyBackDisabled :1; 679 uint32_t SMARTerEnabled :1; 680 uint32_t prCorrectUnconfiguredAreas :1; 681 uint32_t useFdeOnly :1; 682 uint32_t disableNCQ :1; 683 uint32_t SSDSMARTerEnabled :1; 684 uint32_t SSDPatrolReadEnabled :1; 685 uint32_t enableSpinDownUnconfigured :1; 686 uint32_t autoEnhancedImport :1; 687 uint32_t enableSecretKeyControl :1; 688 uint32_t disableOnlineCtrlReset :1; 689 uint32_t allowBootWithPinnedCache :1; 690 uint32_t disableSpinDownHS :1; 691 uint32_t enableJBOD :1; 692 uint32_t reserved :18; 693 } OnOffProperties; 694 /* 695 * % of source LD to be reserved for auto snapshot in snapshot 696 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 697 */ 698 uint8_t autoSnapVDSpace; 699 /* 700 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 701 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 702 */ 703 uint8_t viewSpace; 704 /* # of idle minutes before device is spun down (0=use FW defaults) */ 705 uint16_t spinDownTime; 706 uint8_t reserved[24]; 707} __packed; 708 709/* PCI information about the card. */ 710struct mfi_info_pci { 711 uint16_t vendor; 712 uint16_t device; 713 uint16_t subvendor; 714 uint16_t subdevice; 715 uint8_t reserved[24]; 716} __packed; 717 718/* Host (front end) interface information */ 719struct mfi_info_host { 720 uint8_t type; 721#define MFI_INFO_HOST_PCIX 0x01 722#define MFI_INFO_HOST_PCIE 0x02 723#define MFI_INFO_HOST_ISCSI 0x04 724#define MFI_INFO_HOST_SAS3G 0x08 725 uint8_t reserved[6]; 726 uint8_t port_count; 727 uint64_t port_addr[8]; 728} __packed; 729 730/* Device (back end) interface information */ 731struct mfi_info_device { 732 uint8_t type; 733#define MFI_INFO_DEV_SPI 0x01 734#define MFI_INFO_DEV_SAS3G 0x02 735#define MFI_INFO_DEV_SATA1 0x04 736#define MFI_INFO_DEV_SATA3G 0x08 737 uint8_t reserved[6]; 738 uint8_t port_count; 739 uint64_t port_addr[8]; 740} __packed; 741 742/* Firmware component information */ 743struct mfi_info_component { 744 char name[8]; 745 char version[32]; 746 char build_date[16]; 747 char build_time[16]; 748} __packed; 749 750/* Controller default settings */ 751struct mfi_defaults { 752 uint64_t sas_addr; 753 uint8_t phy_polarity; 754 uint8_t background_rate; 755 uint8_t stripe_size; 756 uint8_t flush_time; 757 uint8_t write_back; 758 uint8_t read_ahead; 759 uint8_t cache_when_bbu_bad; 760 uint8_t cached_io; 761 uint8_t smart_mode; 762 uint8_t alarm_disable; 763 uint8_t coercion; 764 uint8_t zrc_config; 765 uint8_t dirty_led_shows_drive_activity; 766 uint8_t bios_continue_on_error; 767 uint8_t spindown_mode; 768 uint8_t allowed_device_types; 769 uint8_t allow_mix_in_enclosure; 770 uint8_t allow_mix_in_ld; 771 uint8_t allow_sata_in_cluster; 772 uint8_t max_chained_enclosures; 773 uint8_t disable_ctrl_r; 774 uint8_t enabel_web_bios; 775 uint8_t phy_polarity_split; 776 uint8_t direct_pd_mapping; 777 uint8_t bios_enumerate_lds; 778 uint8_t restored_hot_spare_on_insertion; 779 uint8_t expose_enclosure_devices; 780 uint8_t maintain_pd_fail_history; 781 uint8_t resv[28]; 782} __packed; 783 784/* Controller default settings */ 785struct mfi_bios_data { 786 uint16_t boot_target_id; 787 uint8_t do_not_int_13; 788 uint8_t continue_on_error; 789 uint8_t verbose; 790 uint8_t geometry; 791 uint8_t expose_all_drives; 792 uint8_t reserved[56]; 793 uint8_t check_sum; 794} __packed; 795 796/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 797struct mfi_ctrl_info { 798 struct mfi_info_pci pci; 799 struct mfi_info_host host; 800 struct mfi_info_device device; 801 802 /* Firmware components that are present and active. */ 803 uint32_t image_check_word; 804 uint32_t image_component_count; 805 struct mfi_info_component image_component[8]; 806 807 /* Firmware components that have been flashed but are inactive */ 808 uint32_t pending_image_component_count; 809 struct mfi_info_component pending_image_component[8]; 810 811 uint8_t max_arms; 812 uint8_t max_spans; 813 uint8_t max_arrays; 814 uint8_t max_lds; 815 char product_name[80]; 816 char serial_number[32]; 817 uint32_t hw_present; 818#define MFI_INFO_HW_BBU 0x01 819#define MFI_INFO_HW_ALARM 0x02 820#define MFI_INFO_HW_NVRAM 0x04 821#define MFI_INFO_HW_UART 0x08 822 uint32_t current_fw_time; 823 uint16_t max_cmds; 824 uint16_t max_sg_elements; 825 uint32_t max_request_size; 826 uint16_t lds_present; 827 uint16_t lds_degraded; 828 uint16_t lds_offline; 829 uint16_t pd_present; 830 uint16_t pd_disks_present; 831 uint16_t pd_disks_pred_failure; 832 uint16_t pd_disks_failed; 833 uint16_t nvram_size; 834 uint16_t memory_size; 835 uint16_t flash_size; 836 uint16_t ram_correctable_errors; 837 uint16_t ram_uncorrectable_errors; 838 uint8_t cluster_allowed; 839 uint8_t cluster_active; 840 uint16_t max_strips_per_io; 841 842 uint32_t raid_levels; 843#define MFI_INFO_RAID_0 0x01 844#define MFI_INFO_RAID_1 0x02 845#define MFI_INFO_RAID_5 0x04 846#define MFI_INFO_RAID_1E 0x08 847#define MFI_INFO_RAID_6 0x10 848 849 uint32_t adapter_ops; 850#define MFI_INFO_AOPS_RBLD_RATE 0x0001 851#define MFI_INFO_AOPS_CC_RATE 0x0002 852#define MFI_INFO_AOPS_BGI_RATE 0x0004 853#define MFI_INFO_AOPS_RECON_RATE 0x0008 854#define MFI_INFO_AOPS_PATROL_RATE 0x0010 855#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 856#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 857#define MFI_INFO_AOPS_BBU 0x0080 858#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 859#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 860#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 861#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 862#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 863#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 864#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 865 866 uint32_t ld_ops; 867#define MFI_INFO_LDOPS_READ_POLICY 0x01 868#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 869#define MFI_INFO_LDOPS_IO_POLICY 0x04 870#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 871#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 872 873 struct { 874 uint8_t min; 875 uint8_t max; 876 uint8_t reserved[2]; 877 } __packed stripe_sz_ops; 878 879 uint32_t pd_ops; 880#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 881#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 882#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 883 884 uint32_t pd_mix_support; 885#define MFI_INFO_PDMIX_SAS 0x01 886#define MFI_INFO_PDMIX_SATA 0x02 887#define MFI_INFO_PDMIX_ENCL 0x04 888#define MFI_INFO_PDMIX_LD 0x08 889#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 890 891 uint8_t ecc_bucket_count; 892 uint8_t reserved2[11]; 893 struct mfi_ctrl_props properties; 894 char package_version[0x60]; 895 uint8_t pad[0x800 - 0x6a0]; 896} __packed; 897 898/* keep track of an event. */ 899union mfi_evt { 900 struct { 901 uint16_t locale; 902 uint8_t reserved; 903 int8_t evt_class; 904 } members; 905 uint32_t word; 906} __packed; 907 908/* event log state. */ 909struct mfi_evt_log_state { 910 uint32_t newest_seq_num; 911 uint32_t oldest_seq_num; 912 uint32_t clear_seq_num; 913 uint32_t shutdown_seq_num; 914 uint32_t boot_seq_num; 915} __packed; 916 917struct mfi_progress { 918 uint16_t progress; 919 uint16_t elapsed_seconds; 920} __packed; 921 922struct mfi_evt_ld { 923 uint16_t target_id; 924 uint8_t ld_index; 925 uint8_t reserved; 926} __packed; 927 928struct mfi_evt_pd { 929 uint16_t device_id; 930 uint8_t enclosure_index; 931 uint8_t slot_number; 932} __packed; 933 934/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 935struct mfi_evt_detail { 936 uint32_t seq; 937 uint32_t time; 938 uint32_t code; 939 union mfi_evt evt_class; 940 uint8_t arg_type; 941 uint8_t reserved1[15]; 942 943 union { 944 struct { 945 struct mfi_evt_pd pd; 946 uint8_t cdb_len; 947 uint8_t sense_len; 948 uint8_t reserved[2]; 949 uint8_t cdb[16]; 950 uint8_t sense[64]; 951 } cdb_sense; 952 953 struct mfi_evt_ld ld; 954 955 struct { 956 struct mfi_evt_ld ld; 957 uint64_t count; 958 } ld_count; 959 960 struct { 961 uint64_t lba; 962 struct mfi_evt_ld ld; 963 } ld_lba; 964 965 struct { 966 struct mfi_evt_ld ld; 967 uint32_t pre_owner; 968 uint32_t new_owner; 969 } ld_owner; 970 971 struct { 972 uint64_t ld_lba; 973 uint64_t pd_lba; 974 struct mfi_evt_ld ld; 975 struct mfi_evt_pd pd; 976 } ld_lba_pd_lba; 977 978 struct { 979 struct mfi_evt_ld ld; 980 struct mfi_progress prog; 981 } ld_prog; 982 983 struct { 984 struct mfi_evt_ld ld; 985 uint32_t prev_state; 986 uint32_t new_state; 987 } ld_state; 988 989 struct { 990 uint64_t strip; 991 struct mfi_evt_ld ld; 992 } ld_strip; 993 994 struct mfi_evt_pd pd; 995 996 struct { 997 struct mfi_evt_pd pd; 998 uint32_t err; 999 } pd_err; 1000 1001 struct { 1002 uint64_t lba; 1003 struct mfi_evt_pd pd; 1004 } pd_lba; 1005 1006 struct { 1007 uint64_t lba; 1008 struct mfi_evt_pd pd; 1009 struct mfi_evt_ld ld; 1010 } pd_lba_ld; 1011 1012 struct { 1013 struct mfi_evt_pd pd; 1014 struct mfi_progress prog; 1015 } pd_prog; 1016 1017 struct { 1018 struct mfi_evt_pd ld; 1019 uint32_t prev_state; 1020 uint32_t new_state; 1021 } pd_state; 1022 1023 struct { 1024 uint16_t venderId; 1025 uint16_t deviceId; 1026 uint16_t subVenderId; 1027 uint16_t subDeviceId; 1028 } pci; 1029 1030 uint32_t rate; 1031 1032 char str[96]; 1033 1034 struct { 1035 uint32_t rtc; 1036 uint16_t elapsedSeconds; 1037 } time; 1038 1039 struct { 1040 uint32_t ecar; 1041 uint32_t elog; 1042 char str[64]; 1043 } ecc; 1044 1045 uint8_t b[96]; 1046 uint16_t s[48]; 1047 uint32_t w[24]; 1048 uint64_t d[12]; 1049 } args; 1050 1051 char description[128]; 1052} __packed; 1053 1054struct mfi_evt_list { 1055 uint32_t count; 1056 uint32_t reserved; 1057 struct mfi_evt_detail event[1]; 1058} __packed; 1059 1060union mfi_pd_ref { 1061 struct { 1062 uint16_t device_id; 1063 uint16_t seq_num; 1064 } v; 1065 uint32_t ref; 1066} __packed; 1067 1068union mfi_pd_ddf_type { 1069 struct { 1070 union { 1071 struct { 1072 uint16_t forced_pd_guid : 1; 1073 uint16_t in_vd : 1; 1074 uint16_t is_global_spare : 1; 1075 uint16_t is_spare : 1; 1076 uint16_t is_foreign : 1; 1077 uint16_t reserved : 7; 1078 uint16_t intf : 4; 1079 } pd_type; 1080 uint16_t type; 1081 } v; 1082 uint16_t reserved; 1083 } ddf; 1084 struct { 1085 uint32_t reserved; 1086 } non_disk; 1087 uint32_t type; 1088} __packed; 1089 1090struct mfi_pd_progress { 1091 uint32_t active; 1092#define MFI_PD_PROGRESS_REBUILD (1<<0) 1093#define MFI_PD_PROGRESS_PATROL (1<<1) 1094#define MFI_PD_PROGRESS_CLEAR (1<<2) 1095 struct mfi_progress rbld; 1096 struct mfi_progress patrol; 1097 struct mfi_progress clear; 1098 struct mfi_progress reserved[4]; 1099} __packed; 1100 1101struct mfi_pd_info { 1102 union mfi_pd_ref ref; 1103 uint8_t inquiry_data[96]; 1104 uint8_t vpd_page83[64]; 1105 uint8_t not_supported; 1106 uint8_t scsi_dev_type; 1107 uint8_t connected_port_bitmap; 1108 uint8_t device_speed; 1109 uint32_t media_err_count; 1110 uint32_t other_err_count; 1111 uint32_t pred_fail_count; 1112 uint32_t last_pred_fail_event_seq_num; 1113 uint16_t fw_state; /* MFI_PD_STATE_* */ 1114 uint8_t disabled_for_removal; 1115 uint8_t link_speed; 1116 union mfi_pd_ddf_type state; 1117 struct { 1118 uint8_t count; 1119 uint8_t is_path_broken; 1120 uint8_t reserved[6]; 1121 uint64_t sas_addr[4]; 1122 } path_info; 1123 uint64_t raw_size; 1124 uint64_t non_coerced_size; 1125 uint64_t coerced_size; 1126 uint16_t encl_device_id; 1127 uint8_t encl_index; 1128 uint8_t slot_number; 1129 struct mfi_pd_progress prog_info; 1130 uint8_t bad_block_table_full; 1131 uint8_t unusable_in_current_config; 1132 uint8_t vpd_page83_ext[64]; 1133 uint8_t reserved[512-358]; 1134} __packed; 1135 1136struct mfi_pd_address { 1137 uint16_t device_id; 1138 uint16_t encl_device_id; 1139 uint8_t encl_index; 1140 uint8_t slot_number; 1141 uint8_t scsi_dev_type; /* 0 = disk */ 1142 uint8_t connect_port_bitmap; 1143 uint64_t sas_addr[2]; 1144} __packed; 1145 1146#define MAX_SYS_PDS 240 1147struct mfi_pd_list { 1148 uint32_t size; 1149 uint32_t count; 1150 struct mfi_pd_address addr[MAX_SYS_PDS]; 1151} __packed; 1152 1153enum mfi_pd_state { 1154 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1155 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1156 MFI_PD_STATE_HOT_SPARE = 0x02, 1157 MFI_PD_STATE_OFFLINE = 0x10, 1158 MFI_PD_STATE_FAILED = 0x11, 1159 MFI_PD_STATE_REBUILD = 0x14, 1160 MFI_PD_STATE_ONLINE = 0x18, 1161 MFI_PD_STATE_COPYBACK = 0x20, 1162 MFI_PD_STATE_SYSTEM = 0x40 1163}; 1164 1165/* 1166 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1167 * Adding a #define to denote this. 1168 */ 1169#define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1170 1171union mfi_ld_ref { 1172 struct { 1173 uint8_t target_id; 1174 uint8_t reserved; 1175 uint16_t seq; 1176 } v; 1177 uint32_t ref; 1178} __packed; 1179 1180struct mfi_ld_list { 1181 uint32_t ld_count; 1182 uint32_t reserved1; 1183 struct { 1184 union mfi_ld_ref ld; 1185 uint8_t state; 1186 uint8_t reserved2[3]; 1187 uint64_t size; 1188 } ld_list[MFI_MAX_LD]; 1189} __packed; 1190 1191enum mfi_ld_access { 1192 MFI_LD_ACCESS_RW = 0, 1193 MFI_LD_ACCSSS_RO = 2, 1194 MFI_LD_ACCESS_BLOCKED = 3, 1195}; 1196#define MFI_LD_ACCESS_MASK 3 1197 1198enum mfi_ld_state { 1199 MFI_LD_STATE_OFFLINE = 0, 1200 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1201 MFI_LD_STATE_DEGRADED = 2, 1202 MFI_LD_STATE_OPTIMAL = 3 1203}; 1204 1205struct mfi_ld_props { 1206 union mfi_ld_ref ld; 1207 char name[16]; 1208 uint8_t default_cache_policy; 1209 uint8_t access_policy; 1210 uint8_t disk_cache_policy; 1211 uint8_t current_cache_policy; 1212 uint8_t no_bgi; 1213 uint8_t reserved[7]; 1214} __packed; 1215 1216struct mfi_ld_params { 1217 uint8_t primary_raid_level; 1218 uint8_t raid_level_qualifier; 1219 uint8_t secondary_raid_level; 1220 uint8_t stripe_size; 1221 uint8_t num_drives; 1222 uint8_t span_depth; 1223 uint8_t state; 1224 uint8_t init_state; 1225#define MFI_LD_PARAMS_INIT_NO 0 1226#define MFI_LD_PARAMS_INIT_QUICK 1 1227#define MFI_LD_PARAMS_INIT_FULL 2 1228 uint8_t is_consistent; 1229 uint8_t reserved1[6]; 1230 uint8_t isSSCD; 1231 uint8_t reserved2[16]; 1232} __packed; 1233 1234struct mfi_ld_progress { 1235 uint32_t active; 1236#define MFI_LD_PROGRESS_CC (1<<0) 1237#define MFI_LD_PROGRESS_BGI (1<<1) 1238#define MFI_LD_PROGRESS_FGI (1<<2) 1239#define MFI_LD_PROGRESS_RECON (1<<3) 1240 struct mfi_progress cc; 1241 struct mfi_progress bgi; 1242 struct mfi_progress fgi; 1243 struct mfi_progress recon; 1244 struct mfi_progress reserved[4]; 1245} __packed; 1246 1247struct mfi_span { 1248 uint64_t start_block; 1249 uint64_t num_blocks; 1250 uint16_t array_ref; 1251 uint8_t reserved[6]; 1252} __packed; 1253 1254#define MFI_MAX_SPAN_DEPTH 8 1255struct mfi_ld_config { 1256 struct mfi_ld_props properties; 1257 struct mfi_ld_params params; 1258 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1259} __packed; 1260 1261struct mfi_ld_info { 1262 struct mfi_ld_config ld_config; 1263 uint64_t size; 1264 struct mfi_ld_progress progress; 1265 uint16_t cluster_owner; 1266 uint8_t reconstruct_active; 1267 uint8_t reserved1[1]; 1268 uint8_t vpd_page83[64]; 1269 uint8_t reserved2[16]; 1270} __packed; 1271 1272#define MFI_MAX_ARRAYS 16 1273struct mfi_spare { 1274 union mfi_pd_ref ref; 1275 uint8_t spare_type; 1276#define MFI_SPARE_DEDICATED (1 << 0) 1277#define MFI_SPARE_REVERTIBLE (1 << 1) 1278#define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1279 uint8_t reserved[2]; 1280 uint8_t array_count; 1281 uint16_t array_ref[MFI_MAX_ARRAYS]; 1282} __packed; 1283 1284#define MFI_MAX_ROW_SIZE 32 1285struct mfi_array { 1286 uint64_t size; 1287 uint8_t num_drives; 1288 uint8_t reserved; 1289 uint16_t array_ref; 1290 uint8_t pad[20]; 1291 struct { 1292 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1293 uint16_t fw_state; /* MFI_PD_STATE_* */ 1294 struct { 1295 uint8_t pd; 1296 uint8_t slot; 1297 } encl; 1298 } pd[MFI_MAX_ROW_SIZE]; 1299} __packed; 1300 1301struct mfi_config_data { 1302 uint32_t size; 1303 uint16_t array_count; 1304 uint16_t array_size; 1305 uint16_t log_drv_count; 1306 uint16_t log_drv_size; 1307 uint16_t spares_count; 1308 uint16_t spares_size; 1309 uint8_t reserved[16]; 1310 struct mfi_array array[0]; 1311 struct mfi_ld_config ld[0]; 1312 struct mfi_spare spare[0]; 1313} __packed; 1314 1315struct mfi_bbu_capacity_info { 1316 uint16_t relative_charge; 1317 uint16_t absolute_charge; 1318 uint16_t remaining_capacity; 1319 uint16_t full_charge_capacity; 1320 uint16_t run_time_to_empty; 1321 uint16_t average_time_to_empty; 1322 uint16_t average_time_to_full; 1323 uint16_t cycle_count; 1324 uint16_t max_error; 1325 uint16_t remaining_capacity_alarm; 1326 uint16_t remaining_time_alarm; 1327 uint8_t reserved[26]; 1328} __packed; 1329 1330struct mfi_bbu_design_info { 1331 uint32_t mfg_date; 1332 uint16_t design_capacity; 1333 uint16_t design_voltage; 1334 uint16_t spec_info; 1335 uint16_t serial_number; 1336 uint16_t pack_stat_config; 1337 uint8_t mfg_name[12]; 1338 uint8_t device_name[8]; 1339 uint8_t device_chemistry[8]; 1340 uint8_t mfg_data[8]; 1341 uint8_t reserved[17]; 1342} __packed; 1343 1344struct mfi_ibbu_state { 1345 uint16_t gas_guage_status; 1346 uint16_t relative_charge; 1347 uint16_t charger_system_state; 1348 uint16_t charger_system_ctrl; 1349 uint16_t charging_current; 1350 uint16_t absolute_charge; 1351 uint16_t max_error; 1352 uint8_t reserved[18]; 1353} __packed; 1354 1355struct mfi_bbu_state { 1356 uint16_t gas_guage_status; 1357 uint16_t relative_charge; 1358 uint16_t charger_status; 1359 uint16_t remaining_capacity; 1360 uint16_t full_charge_capacity; 1361 uint8_t is_SOH_good; 1362 uint8_t reserved[21]; 1363} __packed; 1364 1365struct mfi_bbu_properties { 1366 uint32_t auto_learn_period; 1367 uint32_t next_learn_time; 1368 uint8_t learn_delay_interval; 1369 uint8_t auto_learn_mode; 1370 uint8_t bbu_mode; 1371 uint8_t reserved[21]; 1372} __packed; 1373 1374union mfi_bbu_status_detail { 1375 struct mfi_ibbu_state ibbu; 1376 struct mfi_bbu_state bbu; 1377}; 1378 1379struct mfi_bbu_status { 1380 uint8_t battery_type; 1381#define MFI_BBU_TYPE_NONE 0 1382#define MFI_BBU_TYPE_IBBU 1 1383#define MFI_BBU_TYPE_BBU 2 1384 uint8_t reserved; 1385 uint16_t voltage; 1386 int16_t current; 1387 uint16_t temperature; 1388 uint32_t fw_status; 1389#define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1390#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1391#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1392#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1393#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1394#define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1395#define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1396#define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1397#define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1398#define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1399 uint8_t pad[20]; 1400 union mfi_bbu_status_detail detail; 1401} __packed; 1402 1403enum mfi_pr_state { 1404 MFI_PR_STATE_STOPPED = 0, 1405 MFI_PR_STATE_READY = 1, 1406 MFI_PR_STATE_ACTIVE = 2, 1407 MFI_PR_STATE_ABORTED = 0xff 1408}; 1409 1410struct mfi_pr_status { 1411 uint32_t num_iteration; 1412 uint8_t state; 1413 uint8_t num_pd_done; 1414 uint8_t reserved[10]; 1415}; 1416 1417enum mfi_pr_opmode { 1418 MFI_PR_OPMODE_AUTO = 0, 1419 MFI_PR_OPMODE_MANUAL = 1, 1420 MFI_PR_OPMODE_DISABLED = 2 1421}; 1422 1423struct mfi_pr_properties { 1424 uint8_t op_mode; 1425 uint8_t max_pd; 1426 uint8_t reserved; 1427 uint8_t exclude_ld_count; 1428 uint16_t excluded_ld[MFI_MAX_LD]; 1429 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1430 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1431 uint32_t next_exec; 1432 uint32_t exec_freq; 1433 uint32_t clear_freq; 1434}; 1435 1436/* ThunderBolt support */ 1437 1438/* 1439 * Raid Context structure which describes MegaRAID specific IO Paramenters 1440 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1441 */ 1442typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1443 uint16_t resvd0; /* 0x00 - 0x01 */ 1444 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1445 uint8_t regLockFlags; 1446 uint8_t armId; 1447 uint16_t TargetID; /* 0x06 - 0x07 */ 1448 1449 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1450 1451 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1452 1453 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1454 uint8_t exStatus; /* 0x16 */ 1455 uint8_t Status; /* 0x17 status */ 1456 1457 uint8_t RAIDFlags; /* 0x18 */ 1458 uint8_t numSGE; /* 0x19 numSge */ 1459 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1460 uint8_t spanArm; /* 0x1C */ 1461 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1462} MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1463 1464/***************************************************************************** 1465* 1466* Message Functions 1467* 1468*****************************************************************************/ 1469 1470#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1471#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1472#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1473#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1474#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1475#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1476#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1477#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1478#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1479#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1480#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1481#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1482#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1483#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1484#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1485#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1486#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1487#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1488#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1489#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1490#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1491#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1492#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1493#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1494#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1495#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1496#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1497#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1498#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1499#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1500 1501/* Doorbell functions */ 1502#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1503#define MPI2_FUNCTION_HANDSHAKE (0x42) 1504 1505/***************************************************************************** 1506* 1507* MPI Version Definitions 1508* 1509*****************************************************************************/ 1510 1511#define MPI2_VERSION_MAJOR (0x02) 1512#define MPI2_VERSION_MINOR (0x00) 1513#define MPI2_VERSION_MAJOR_MASK (0xFF00) 1514#define MPI2_VERSION_MAJOR_SHIFT (8) 1515#define MPI2_VERSION_MINOR_MASK (0x00FF) 1516#define MPI2_VERSION_MINOR_SHIFT (0) 1517#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1518 MPI2_VERSION_MINOR) 1519 1520#define MPI2_VERSION_02_00 (0x0200) 1521 1522/* versioning for this MPI header set */ 1523#define MPI2_HEADER_VERSION_UNIT (0x10) 1524#define MPI2_HEADER_VERSION_DEV (0x00) 1525#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1526#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1527#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1528#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1529#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1530 MPI2_HEADER_VERSION_DEV) 1531 1532 1533/* IOCInit Request message */ 1534struct MPI2_IOC_INIT_REQUEST { 1535 uint8_t WhoInit; /* 0x00 */ 1536 uint8_t Reserved1; /* 0x01 */ 1537 uint8_t ChainOffset; /* 0x02 */ 1538 uint8_t Function; /* 0x03 */ 1539 uint16_t Reserved2; /* 0x04 */ 1540 uint8_t Reserved3; /* 0x06 */ 1541 uint8_t MsgFlags; /* 0x07 */ 1542 uint8_t VP_ID; /* 0x08 */ 1543 uint8_t VF_ID; /* 0x09 */ 1544 uint16_t Reserved4; /* 0x0A */ 1545 uint16_t MsgVersion; /* 0x0C */ 1546 uint16_t HeaderVersion; /* 0x0E */ 1547 uint32_t Reserved5; /* 0x10 */ 1548 uint16_t Reserved6; /* 0x14 */ 1549 uint8_t Reserved7; /* 0x16 */ 1550 uint8_t HostMSIxVectors; /* 0x17 */ 1551 uint16_t Reserved8; /* 0x18 */ 1552 uint16_t SystemRequestFrameSize; /* 0x1A */ 1553 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1554 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1555 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1556 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1557 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1558 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1559 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1560 uint64_t TimeStamp; /* 0x40 */ 1561}; 1562 1563/* WhoInit values */ 1564#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1565#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1566#define MPI2_WHOINIT_ROM_BIOS (0x02) 1567#define MPI2_WHOINIT_PCI_PEER (0x03) 1568#define MPI2_WHOINIT_HOST_DRIVER (0x04) 1569#define MPI2_WHOINIT_MANUFACTURER (0x05) 1570 1571struct MPI2_SGE_CHAIN_UNION { 1572 uint16_t Length; 1573 uint8_t NextChainOffset; 1574 uint8_t Flags; 1575 union { 1576 uint32_t Address32; 1577 uint64_t Address64; 1578 } u; 1579}; 1580 1581struct MPI2_IEEE_SGE_SIMPLE32 { 1582 uint32_t Address; 1583 uint32_t FlagsLength; 1584}; 1585 1586struct MPI2_IEEE_SGE_SIMPLE64 { 1587 uint64_t Address; 1588 uint32_t Length; 1589 uint16_t Reserved1; 1590 uint8_t Reserved2; 1591 uint8_t Flags; 1592}; 1593 1594typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1595 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1596 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1597} MPI2_IEEE_SGE_SIMPLE_UNION; 1598 1599typedef struct _MPI2_SGE_SIMPLE_UNION { 1600 uint32_t FlagsLength; 1601 union { 1602 uint32_t Address32; 1603 uint64_t Address64; 1604 } u; 1605} MPI2_SGE_SIMPLE_UNION; 1606 1607/**************************************************************************** 1608* IEEE SGE field definitions and masks 1609****************************************************************************/ 1610 1611/* Flags field bit definitions */ 1612 1613#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1614 1615#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1616 1617#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1618 1619/* Element Type */ 1620 1621#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1622#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1623 1624/* Data Location Address Space */ 1625 1626#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1627#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1628#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1629#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1630#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1631 1632/* Address Size */ 1633 1634#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1635#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1636 1637/*******************/ 1638/* SCSI IO Control bits */ 1639#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1640#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1641 1642#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1643#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1644#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1645#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1646#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1647 1648#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1649#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1650 1651#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1652#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1653#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1654#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1655#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1656 1657#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1658#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1659#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1660#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1661 1662/*******************/ 1663 1664typedef struct { 1665 uint8_t CDB[20]; /* 0x00 */ 1666 uint32_t PrimaryReferenceTag; /* 0x14 */ 1667 uint16_t PrimaryApplicationTag; /* 0x18 */ 1668 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1669 uint32_t TransferLength; /* 0x1C */ 1670} MPI2_SCSI_IO_CDB_EEDP32; 1671 1672 1673typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1674 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1675 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1676} MPI2_IEEE_SGE_CHAIN_UNION; 1677 1678typedef union _MPI2_SIMPLE_SGE_UNION { 1679 MPI2_SGE_SIMPLE_UNION MpiSimple; 1680 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1681} MPI2_SIMPLE_SGE_UNION; 1682 1683typedef union _MPI2_SGE_IO_UNION { 1684 MPI2_SGE_SIMPLE_UNION MpiSimple; 1685 struct MPI2_SGE_CHAIN_UNION MpiChain; 1686 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1687 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1688} MPI2_SGE_IO_UNION; 1689 1690typedef union { 1691 uint8_t CDB32[32]; 1692 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1693 MPI2_SGE_SIMPLE_UNION SGE; 1694} MPI2_SCSI_IO_CDB_UNION; 1695 1696 1697/* MPI 2.5 SGLs */ 1698 1699#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1700 1701typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1702 uint64_t Address; 1703 uint32_t Length; 1704 uint16_t Reserved1; 1705 uint8_t NextChainOffset; 1706 uint8_t Flags; 1707} MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1708 1709/* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1710 1711 1712/********/ 1713 1714/* 1715 * RAID SCSI IO Request Message 1716 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1717 */ 1718struct mfi_mpi2_request_raid_scsi_io { 1719 uint16_t DevHandle; /* 0x00 */ 1720 uint8_t ChainOffset; /* 0x02 */ 1721 uint8_t Function; /* 0x03 */ 1722 uint16_t Reserved1; /* 0x04 */ 1723 uint8_t Reserved2; /* 0x06 */ 1724 uint8_t MsgFlags; /* 0x07 */ 1725 uint8_t VP_ID; /* 0x08 */ 1726 uint8_t VF_ID; /* 0x09 */ 1727 uint16_t Reserved3; /* 0x0A */ 1728 uint32_t SenseBufferLowAddress; /* 0x0C */ 1729 uint16_t SGLFlags; /* 0x10 */ 1730 uint8_t SenseBufferLength; /* 0x12 */ 1731 uint8_t Reserved4; /* 0x13 */ 1732 uint8_t SGLOffset0; /* 0x14 */ 1733 uint8_t SGLOffset1; /* 0x15 */ 1734 uint8_t SGLOffset2; /* 0x16 */ 1735 uint8_t SGLOffset3; /* 0x17 */ 1736 uint32_t SkipCount; /* 0x18 */ 1737 uint32_t DataLength; /* 0x1C */ 1738 uint32_t BidirectionalDataLength; /* 0x20 */ 1739 uint16_t IoFlags; /* 0x24 */ 1740 uint16_t EEDPFlags; /* 0x26 */ 1741 uint32_t EEDPBlockSize; /* 0x28 */ 1742 uint32_t SecondaryReferenceTag; /* 0x2C */ 1743 uint16_t SecondaryApplicationTag; /* 0x30 */ 1744 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1745 uint8_t LUN[8]; /* 0x34 */ 1746 uint32_t Control; /* 0x3C */ 1747 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1748 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1749 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1750} __packed; 1751 1752/* 1753 * MPT RAID MFA IO Descriptor. 1754 */ 1755typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1756 uint32_t RequestFlags : 8; 1757 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1758 uint32_t MessageAddress2; /* bits 61:32 */ 1759} MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1760 1761struct mfi_mpi2_request_header { 1762 uint8_t RequestFlags; /* 0x00 */ 1763 uint8_t MSIxIndex; /* 0x01 */ 1764 uint16_t SMID; /* 0x02 */ 1765 uint16_t LMID; /* 0x04 */ 1766}; 1767 1768/* defines for the RequestFlags field */ 1769#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1770#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1771#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1772#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1773#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1774#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1775 1776#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1777 1778struct mfi_mpi2_request_high_priority { 1779 struct mfi_mpi2_request_header header; 1780 uint16_t reserved; 1781}; 1782 1783struct mfi_mpi2_request_scsi_io { 1784 struct mfi_mpi2_request_header header; 1785 uint16_t scsi_io_dev_handle; 1786}; 1787 1788struct mfi_mpi2_request_scsi_target { 1789 struct mfi_mpi2_request_header header; 1790 uint16_t scsi_target_io_index; 1791}; 1792 1793/* Request Descriptors */ 1794union mfi_mpi2_request_descriptor { 1795 struct mfi_mpi2_request_header header; 1796 struct mfi_mpi2_request_high_priority high_priority; 1797 struct mfi_mpi2_request_scsi_io scsi_io; 1798 struct mfi_mpi2_request_scsi_target scsi_target; 1799 uint64_t words; 1800}; 1801 1802 1803struct mfi_mpi2_reply_header { 1804 uint8_t ReplyFlags; /* 0x00 */ 1805 uint8_t MSIxIndex; /* 0x01 */ 1806 uint16_t SMID; /* 0x02 */ 1807}; 1808 1809/* defines for the ReplyFlags field */ 1810#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1811#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1812#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1813#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1814#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1815#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1816#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1817 1818/* values for marking a reply descriptor as unused */ 1819#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1820#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1821 1822struct mfi_mpi2_reply_default { 1823 struct mfi_mpi2_reply_header header; 1824 uint32_t DescriptorTypeDependent2; 1825}; 1826 1827struct mfi_mpi2_reply_address { 1828 struct mfi_mpi2_reply_header header; 1829 uint32_t ReplyFrameAddress; 1830}; 1831 1832struct mfi_mpi2_reply_scsi_io { 1833 struct mfi_mpi2_reply_header header; 1834 uint16_t TaskTag; /* 0x04 */ 1835 uint16_t Reserved1; /* 0x06 */ 1836}; 1837 1838struct mfi_mpi2_reply_target_assist { 1839 struct mfi_mpi2_reply_header header; 1840 uint8_t SequenceNumber; /* 0x04 */ 1841 uint8_t Reserved1; /* 0x04 */ 1842 uint16_t IoIndex; /* 0x06 */ 1843}; 1844 1845struct mfi_mpi2_reply_target_cmd_buffer { 1846 struct mfi_mpi2_reply_header header; 1847 uint8_t SequenceNumber; /* 0x04 */ 1848 uint8_t Flags; /* 0x04 */ 1849 uint16_t InitiatorDevHandle; /* 0x06 */ 1850 uint16_t IoIndex; /* 0x06 */ 1851}; 1852 1853struct mfi_mpi2_reply_raid_accel { 1854 struct mfi_mpi2_reply_header header; 1855 uint8_t SequenceNumber; /* 0x04 */ 1856 uint32_t Reserved; /* 0x04 */ 1857}; 1858 1859/* union of Reply Descriptors */ 1860union mfi_mpi2_reply_descriptor { 1861 struct mfi_mpi2_reply_header header; 1862 struct mfi_mpi2_reply_scsi_io scsi_io; 1863 struct mfi_mpi2_reply_target_assist target_assist; 1864 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1865 struct mfi_mpi2_reply_raid_accel raid_accel; 1866 struct mfi_mpi2_reply_default reply_default; 1867 uint64_t words; 1868}; 1869 1870struct IO_REQUEST_INFO { 1871 uint64_t ldStartBlock; 1872 uint32_t numBlocks; 1873 uint16_t ldTgtId; 1874 uint8_t isRead; 1875 uint16_t devHandle; 1876 uint64_t pdBlock; 1877 uint8_t fpOkForIo; 1878}; 1879 1880#define MFI_SCSI_MAX_TARGETS 128 1881#define MFI_SCSI_MAX_LUNS 8 1882#define MFI_SCSI_INITIATOR_ID 255 1883#define MFI_SCSI_MAX_CMDS 8 1884#define MFI_SCSI_MAX_CDB_LEN 16 1885 1886#endif /* _MFIREG_H */ 1887