mfireg.h revision 235738
1/*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26/*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53#ifndef _MFIREG_H 54#define _MFIREG_H 55 56#include <sys/cdefs.h> 57__FBSDID("$FreeBSD: stable/9/sys/dev/mfi/mfireg.h 235738 2012-05-21 19:58:40Z sbruno $"); 58 59/* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67#define MEGAMFI_FRAME_SIZE 64 68/* 69 * Start with the register set. All registers are 32 bits wide. 70 * The usual Intel IOP style setup. 71 */ 72#define MFI_IMSG0 0x10 /* Inbound message 0 */ 73#define MFI_IMSG1 0x14 /* Inbound message 1 */ 74#define MFI_OMSG0 0x18 /* Outbound message 0 */ 75#define MFI_OMSG1 0x1c /* Outbound message 1 */ 76#define MFI_IDB 0x20 /* Inbound doorbell */ 77#define MFI_ISTS 0x24 /* Inbound interrupt status */ 78#define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79#define MFI_ODB 0x2c /* Outbound doorbell */ 80#define MFI_OSTS 0x30 /* Outbound interrupt status */ 81#define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82#define MFI_IQP 0x40 /* Inbound queue port */ 83#define MFI_OQP 0x44 /* Outbound queue port */ 84 85/* 86* ThunderBolt specific Register 87*/ 88 89#define MFI_RPI 0x6c /* reply_post_host_index */ 90#define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 91#define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 92 93/* 94 * 1078 specific related register 95 */ 96#define MFI_ODR0 0x9c /* outbound doorbell register0 */ 97#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 98#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 99#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 100#define MFI_RMI 0x2 /* reply message interrupt */ 101#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 102#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 103 104/* OCR registers */ 105#define MFI_WSR 0x004 /* write sequence register */ 106#define MFI_HDR 0x008 /* host diagnostic register */ 107#define MFI_RSR 0x3c3 /* Reset Status Register */ 108 109/* 110 * GEN2 specific changes 111 */ 112#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 113#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 114 115/* 116 * skinny specific changes 117 */ 118#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 119#define MFI_IQPL 0x000000c0 120#define MFI_IQPH 0x000000c4 121#define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 122 123/* Bits for MFI_OSTS */ 124#define MFI_OSTS_INTR_VALID 0x00000002 125 126/* OCR specific flags */ 127#define MFI_FIRMWARE_STATE_CHANGE 0x00000002 128#define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 129 130/* 131 * Firmware state values. Found in OMSG0 during initialization. 132 */ 133#define MFI_FWSTATE_MASK 0xf0000000 134#define MFI_FWSTATE_UNDEFINED 0x00000000 135#define MFI_FWSTATE_BB_INIT 0x10000000 136#define MFI_FWSTATE_FW_INIT 0x40000000 137#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 138#define MFI_FWSTATE_FW_INIT_2 0x70000000 139#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 140#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 141#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 142#define MFI_FWSTATE_READY 0xb0000000 143#define MFI_FWSTATE_OPERATIONAL 0xc0000000 144#define MFI_FWSTATE_FAULT 0xf0000000 145#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 146#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 147#define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 148#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 149#define MFI_RESET_REQUIRED 0x00000001 150 151/* ThunderBolt Support */ 152#define MFI_FWSTATE_TB_MASK 0xf0000000 153#define MFI_FWSTATE_TB_RESET 0x00000000 154#define MFI_FWSTATE_TB_READY 0x10000000 155#define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 156#define MFI_FWSTATE_TB_FAULT 0x40000000 157 158/* 159 * Control bits to drive the card to ready state. These go into the IDB 160 * register. 161 */ 162#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 163#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 164#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 165#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 166#define MFI_FWINIT_HOTPLUG 0x00000010 167 168/* ADP reset flags */ 169#define MFI_STOP_ADP 0x00000020 170#define MFI_ADP_RESET 0x00000040 171#define DIAG_WRITE_ENABLE 0x00000080 172#define DIAG_RESET_ADAPTER 0x00000004 173 174/* MFI Commands */ 175typedef enum { 176 MFI_CMD_INIT = 0x00, 177 MFI_CMD_LD_READ, 178 MFI_CMD_LD_WRITE, 179 MFI_CMD_LD_SCSI_IO, 180 MFI_CMD_PD_SCSI_IO, 181 MFI_CMD_DCMD, 182 MFI_CMD_ABORT, 183 MFI_CMD_SMP, 184 MFI_CMD_STP 185} mfi_cmd_t; 186 187/* Direct commands */ 188typedef enum { 189 MFI_DCMD_CTRL_GETINFO = 0x01010000, 190 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 191 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 192 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 193 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 194 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 195 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 196 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 197 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 198 MFI_DCMD_PR_GET_STATUS = 0x01070100, 199 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 200 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 201 MFI_DCMD_PR_START = 0x01070400, 202 MFI_DCMD_PR_STOP = 0x01070500, 203 MFI_DCMD_TIME_SECS_GET = 0x01080201, 204 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 205 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 206 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 207 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 208 MFI_DCMD_PD_GET_LIST = 0x02010000, 209 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 210 MFI_DCMD_PD_GET_INFO = 0x02020000, 211 MFI_DCMD_PD_STATE_SET = 0x02030100, 212 MFI_DCMD_PD_REBUILD_START = 0x02040100, 213 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 214 MFI_DCMD_PD_CLEAR_START = 0x02050100, 215 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 216 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 217 MFI_DCMD_PD_LOCATE_START = 0x02070100, 218 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 219 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 220 MFI_DCMD_LD_SYNC = 0x0300e102, 221 MFI_DCMD_LD_GET_LIST = 0x03010000, 222 MFI_DCMD_LD_GET_INFO = 0x03020000, 223 MFI_DCMD_LD_GET_PROP = 0x03030000, 224 MFI_DCMD_LD_SET_PROP = 0x03040000, 225 MFI_DCMD_LD_INIT_START = 0x03060100, 226 MFI_DCMD_LD_DELETE = 0x03090000, 227 MFI_DCMD_CFG_READ = 0x04010000, 228 MFI_DCMD_CFG_ADD = 0x04020000, 229 MFI_DCMD_CFG_CLEAR = 0x04030000, 230 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 231 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 232 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 233 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 234 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 235 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 236 MFI_DCMD_CLUSTER = 0x08000000, 237 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 238 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 239} mfi_dcmd_t; 240 241/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 242#define MFI_FLUSHCACHE_CTRL 0x01 243#define MFI_FLUSHCACHE_DISK 0x02 244 245/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 246#define MFI_SHUTDOWN_SPINDOWN 0x01 247 248/* 249 * MFI Frame flags 250 */ 251#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 252#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 253#define MFI_FRAME_SGL32 0x0000 254#define MFI_FRAME_SGL64 0x0002 255#define MFI_FRAME_SENSE32 0x0000 256#define MFI_FRAME_SENSE64 0x0004 257#define MFI_FRAME_DIR_NONE 0x0000 258#define MFI_FRAME_DIR_WRITE 0x0008 259#define MFI_FRAME_DIR_READ 0x0010 260#define MFI_FRAME_DIR_BOTH 0x0018 261#define MFI_FRAME_IEEE_SGL 0x0020 262 263/* ThunderBolt Specific */ 264 265/* 266 * Pre-TB command size and TB command size. 267 * We will be checking it at the load time for the time being 268 */ 269#define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 270 271#define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 272/* 273 * We are defining only 128 byte message to reduce memory move over head 274 * and also it will reduce the SRB extension size by 128byte compared with 275 * 256 message size 276 */ 277#define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 278#define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 279#define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 280#define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 281#define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 282#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 283 284#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 285#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 286 287#define MR_INTERNAL_MFI_FRAMES_SMID 1 288#define MR_CTRL_EVENT_WAIT_SMID 2 289#define MR_INTERNAL_DRIVER_RESET_SMID 3 290 291 292/* MFI Status codes */ 293typedef enum { 294 MFI_STAT_OK = 0x00, 295 MFI_STAT_INVALID_CMD, 296 MFI_STAT_INVALID_DCMD, 297 MFI_STAT_INVALID_PARAMETER, 298 MFI_STAT_INVALID_SEQUENCE_NUMBER, 299 MFI_STAT_ABORT_NOT_POSSIBLE, 300 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 301 MFI_STAT_APP_IN_USE, 302 MFI_STAT_APP_NOT_INITIALIZED, 303 MFI_STAT_ARRAY_INDEX_INVALID, 304 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 305 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 306 MFI_STAT_DEVICE_NOT_FOUND, 307 MFI_STAT_DRIVE_TOO_SMALL, 308 MFI_STAT_FLASH_ALLOC_FAIL, 309 MFI_STAT_FLASH_BUSY, 310 MFI_STAT_FLASH_ERROR = 0x10, 311 MFI_STAT_FLASH_IMAGE_BAD, 312 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 313 MFI_STAT_FLASH_NOT_OPEN, 314 MFI_STAT_FLASH_NOT_STARTED, 315 MFI_STAT_FLUSH_FAILED, 316 MFI_STAT_HOST_CODE_NOT_FOUNT, 317 MFI_STAT_LD_CC_IN_PROGRESS, 318 MFI_STAT_LD_INIT_IN_PROGRESS, 319 MFI_STAT_LD_LBA_OUT_OF_RANGE, 320 MFI_STAT_LD_MAX_CONFIGURED, 321 MFI_STAT_LD_NOT_OPTIMAL, 322 MFI_STAT_LD_RBLD_IN_PROGRESS, 323 MFI_STAT_LD_RECON_IN_PROGRESS, 324 MFI_STAT_LD_WRONG_RAID_LEVEL, 325 MFI_STAT_MAX_SPARES_EXCEEDED, 326 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 327 MFI_STAT_MFC_HW_ERROR, 328 MFI_STAT_NO_HW_PRESENT, 329 MFI_STAT_NOT_FOUND, 330 MFI_STAT_NOT_IN_ENCL, 331 MFI_STAT_PD_CLEAR_IN_PROGRESS, 332 MFI_STAT_PD_TYPE_WRONG, 333 MFI_STAT_PR_DISABLED, 334 MFI_STAT_ROW_INDEX_INVALID, 335 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 336 MFI_STAT_SAS_CONFIG_INVALID_DATA, 337 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 338 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 339 MFI_STAT_SCSI_DONE_WITH_ERROR, 340 MFI_STAT_SCSI_IO_FAILED, 341 MFI_STAT_SCSI_RESERVATION_CONFLICT, 342 MFI_STAT_SHUTDOWN_FAILED = 0x30, 343 MFI_STAT_TIME_NOT_SET, 344 MFI_STAT_WRONG_STATE, 345 MFI_STAT_LD_OFFLINE, 346 MFI_STAT_PEER_NOTIFICATION_REJECTED, 347 MFI_STAT_PEER_NOTIFICATION_FAILED, 348 MFI_STAT_RESERVATION_IN_PROGRESS, 349 MFI_STAT_I2C_ERRORS_DETECTED, 350 MFI_STAT_PCI_ERRORS_DETECTED, 351 MFI_STAT_DIAG_FAILED, 352 MFI_STAT_BOOT_MSG_PENDING, 353 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 354 MFI_STAT_INVALID_STATUS = 0xFF 355} mfi_status_t; 356 357typedef enum { 358 MFI_EVT_CLASS_DEBUG = -2, 359 MFI_EVT_CLASS_PROGRESS = -1, 360 MFI_EVT_CLASS_INFO = 0, 361 MFI_EVT_CLASS_WARNING = 1, 362 MFI_EVT_CLASS_CRITICAL = 2, 363 MFI_EVT_CLASS_FATAL = 3, 364 MFI_EVT_CLASS_DEAD = 4 365} mfi_evt_class_t; 366 367typedef enum { 368 MFI_EVT_LOCALE_LD = 0x0001, 369 MFI_EVT_LOCALE_PD = 0x0002, 370 MFI_EVT_LOCALE_ENCL = 0x0004, 371 MFI_EVT_LOCALE_BBU = 0x0008, 372 MFI_EVT_LOCALE_SAS = 0x0010, 373 MFI_EVT_LOCALE_CTRL = 0x0020, 374 MFI_EVT_LOCALE_CONFIG = 0x0040, 375 MFI_EVT_LOCALE_CLUSTER = 0x0080, 376 MFI_EVT_LOCALE_ALL = 0xffff 377} mfi_evt_locale_t; 378 379typedef enum { 380 MR_EVT_ARGS_NONE = 0x00, 381 MR_EVT_ARGS_CDB_SENSE, 382 MR_EVT_ARGS_LD, 383 MR_EVT_ARGS_LD_COUNT, 384 MR_EVT_ARGS_LD_LBA, 385 MR_EVT_ARGS_LD_OWNER, 386 MR_EVT_ARGS_LD_LBA_PD_LBA, 387 MR_EVT_ARGS_LD_PROG, 388 MR_EVT_ARGS_LD_STATE, 389 MR_EVT_ARGS_LD_STRIP, 390 MR_EVT_ARGS_PD, 391 MR_EVT_ARGS_PD_ERR, 392 MR_EVT_ARGS_PD_LBA, 393 MR_EVT_ARGS_PD_LBA_LD, 394 MR_EVT_ARGS_PD_PROG, 395 MR_EVT_ARGS_PD_STATE, 396 MR_EVT_ARGS_PCI, 397 MR_EVT_ARGS_RATE, 398 MR_EVT_ARGS_STR, 399 MR_EVT_ARGS_TIME, 400 MR_EVT_ARGS_ECC 401} mfi_evt_args; 402 403#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 404#define MR_EVT_PD_REMOVED 0x0070 405#define MR_EVT_PD_INSERTED 0x005b 406#define MR_EVT_LD_CHANGE 0x0051 407 408typedef enum { 409 MR_LD_CACHE_WRITE_BACK = 0x01, 410 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 411 MR_LD_CACHE_READ_AHEAD = 0x04, 412 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 413 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 414 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 415 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 416} mfi_ld_cache; 417#define MR_LD_CACHE_MASK 0x7f 418 419#define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 420#define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 421#define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 422 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 423#define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 424#define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 425#define MR_LD_CACHE_POLICY_IO_CACHED \ 426 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 427#define MR_LD_CACHE_POLICY_IO_DIRECT 0 428 429typedef enum { 430 MR_PD_CACHE_UNCHANGED = 0, 431 MR_PD_CACHE_ENABLE = 1, 432 MR_PD_CACHE_DISABLE = 2 433} mfi_pd_cache; 434 435typedef enum { 436 MR_PD_QUERY_TYPE_ALL = 0, 437 MR_PD_QUERY_TYPE_STATE = 1, 438 MR_PD_QUERY_TYPE_POWER_STATE = 2, 439 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 440 MR_PD_QUERY_TYPE_SPEED = 4, 441 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 442} mfi_pd_query_type; 443 444/* 445 * Other propertities and definitions 446 */ 447#define MFI_MAX_PD_CHANNELS 2 448#define MFI_MAX_LD_CHANNELS 2 449#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 450#define MFI_MAX_CHANNEL_DEVS 128 451#define MFI_DEFAULT_ID -1 452#define MFI_MAX_LUN 8 453#define MFI_MAX_LD 64 454#define MFI_MAX_PD 256 455 456#define MFI_FRAME_SIZE 64 457#define MFI_MBOX_SIZE 12 458 459/* Firmware flashing can take 40s */ 460#define MFI_POLL_TIMEOUT_SECS 50 461 462/* Allow for speedier math calculations */ 463#define MFI_SECTOR_LEN 512 464 465/* Scatter Gather elements */ 466struct mfi_sg32 { 467 uint32_t addr; 468 uint32_t len; 469} __packed; 470 471struct mfi_sg64 { 472 uint64_t addr; 473 uint32_t len; 474} __packed; 475 476struct mfi_sg_skinny { 477 uint64_t addr; 478 uint32_t len; 479 uint32_t flag; 480} __packed; 481 482union mfi_sgl { 483 struct mfi_sg32 sg32[1]; 484 struct mfi_sg64 sg64[1]; 485 struct mfi_sg_skinny sg_skinny[1]; 486} __packed; 487 488/* Message frames. All messages have a common header */ 489struct mfi_frame_header { 490 uint8_t cmd; 491 uint8_t sense_len; 492 uint8_t cmd_status; 493 uint8_t scsi_status; 494 uint8_t target_id; 495 uint8_t lun_id; 496 uint8_t cdb_len; 497 uint8_t sg_count; 498 uint32_t context; 499 /* 500 * pad0 is MSI Specific. Not used by Driver. Zero the value before 501 * sending the command to f/w. 502 */ 503 uint32_t pad0; 504 uint16_t flags; 505#define MFI_FRAME_DATAOUT 0x08 506#define MFI_FRAME_DATAIN 0x10 507 uint16_t timeout; 508 uint32_t data_len; 509} __packed; 510 511struct mfi_init_frame { 512 struct mfi_frame_header header; 513 uint32_t qinfo_new_addr_lo; 514 uint32_t qinfo_new_addr_hi; 515 uint32_t qinfo_old_addr_lo; 516 uint32_t qinfo_old_addr_hi; 517 // Start LSIP200113393 518 uint32_t driver_ver_lo; /*28h */ 519 uint32_t driver_ver_hi; /*2Ch */ 520 521 uint32_t reserved[4]; 522 // End LSIP200113393 523} __packed; 524 525/* 526 * Define MFI Address Context union. 527 */ 528#ifdef MFI_ADDRESS_IS_uint64_t 529 typedef uint64_t MFI_ADDRESS; 530#else 531 typedef union _MFI_ADDRESS { 532 struct { 533 uint32_t addressLow; 534 uint32_t addressHigh; 535 } u; 536 uint64_t address; 537 } MFI_ADDRESS, *PMFI_ADDRESS; 538#endif 539 540#define MFI_IO_FRAME_SIZE 40 541struct mfi_io_frame { 542 struct mfi_frame_header header; 543 uint32_t sense_addr_lo; 544 uint32_t sense_addr_hi; 545 uint32_t lba_lo; 546 uint32_t lba_hi; 547 union mfi_sgl sgl; 548} __packed; 549 550#define MFI_PASS_FRAME_SIZE 48 551struct mfi_pass_frame { 552 struct mfi_frame_header header; 553 uint32_t sense_addr_lo; 554 uint32_t sense_addr_hi; 555 uint8_t cdb[16]; 556 union mfi_sgl sgl; 557} __packed; 558 559#define MFI_DCMD_FRAME_SIZE 40 560struct mfi_dcmd_frame { 561 struct mfi_frame_header header; 562 uint32_t opcode; 563 uint8_t mbox[MFI_MBOX_SIZE]; 564 union mfi_sgl sgl; 565} __packed; 566 567struct mfi_abort_frame { 568 struct mfi_frame_header header; 569 uint32_t abort_context; 570 /* pad is changed to reserved.*/ 571 uint32_t reserved0; 572 uint32_t abort_mfi_addr_lo; 573 uint32_t abort_mfi_addr_hi; 574 uint32_t reserved1[6]; 575} __packed; 576 577struct mfi_smp_frame { 578 struct mfi_frame_header header; 579 uint64_t sas_addr; 580 union { 581 struct mfi_sg32 sg32[2]; 582 struct mfi_sg64 sg64[2]; 583 } sgl; 584} __packed; 585 586struct mfi_stp_frame { 587 struct mfi_frame_header header; 588 uint16_t fis[10]; 589 uint32_t stp_flags; 590 union { 591 struct mfi_sg32 sg32[2]; 592 struct mfi_sg64 sg64[2]; 593 } sgl; 594} __packed; 595 596union mfi_frame { 597 struct mfi_frame_header header; 598 struct mfi_init_frame init; 599 /* ThunderBolt Initialization */ 600 struct mfi_io_frame io; 601 struct mfi_pass_frame pass; 602 struct mfi_dcmd_frame dcmd; 603 struct mfi_abort_frame abort; 604 struct mfi_smp_frame smp; 605 struct mfi_stp_frame stp; 606 uint8_t bytes[MFI_FRAME_SIZE]; 607}; 608 609#define MFI_SENSE_LEN 128 610struct mfi_sense { 611 uint8_t data[MFI_SENSE_LEN]; 612}; 613 614/* The queue init structure that is passed with the init message */ 615struct mfi_init_qinfo { 616 uint32_t flags; 617 uint32_t rq_entries; 618 uint32_t rq_addr_lo; 619 uint32_t rq_addr_hi; 620 uint32_t pi_addr_lo; 621 uint32_t pi_addr_hi; 622 uint32_t ci_addr_lo; 623 uint32_t ci_addr_hi; 624} __packed; 625 626/* SAS (?) controller properties, part of mfi_ctrl_info */ 627struct mfi_ctrl_props { 628 uint16_t seq_num; 629 uint16_t pred_fail_poll_interval; 630 uint16_t intr_throttle_cnt; 631 uint16_t intr_throttle_timeout; 632 uint8_t rebuild_rate; 633 uint8_t patrol_read_rate; 634 uint8_t bgi_rate; 635 uint8_t cc_rate; 636 uint8_t recon_rate; 637 uint8_t cache_flush_interval; 638 uint8_t spinup_drv_cnt; 639 uint8_t spinup_delay; 640 uint8_t cluster_enable; 641 uint8_t coercion_mode; 642 uint8_t alarm_enable; 643 uint8_t disable_auto_rebuild; 644 uint8_t disable_battery_warn; 645 uint8_t ecc_bucket_size; 646 uint16_t ecc_bucket_leak_rate; 647 uint8_t restore_hotspare_on_insertion; 648 uint8_t expose_encl_devices; 649 uint8_t maintainPdFailHistory; 650 uint8_t disallowHostRequestReordering; 651 /* set TRUE to abort CC on detecting an inconsistency */ 652 uint8_t abortCCOnError; 653 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 654 uint8_t loadBalanceMode; 655 /* 656 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 657 * h/w mechansim like GPIO pins 658 * 1 - disable auto detect SGPIO, 659 * 2 - disable i2c SEP auto detect 660 * 3 - disable both auto detect 661 */ 662 uint8_t disableAutoDetectBackplane; 663 /* 664 * % of source LD to be reserved for a VDs snapshot in snapshot 665 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 666 */ 667 uint8_t snapVDSpace; 668 669 /* 670 * Add properties that can be controlled by a bit in the following 671 * structure. 672 */ 673 struct { 674 /* set TRUE to disable copyBack (0=copback enabled) */ 675 uint32_t copyBackDisabled :1; 676 uint32_t SMARTerEnabled :1; 677 uint32_t prCorrectUnconfiguredAreas :1; 678 uint32_t useFdeOnly :1; 679 uint32_t disableNCQ :1; 680 uint32_t SSDSMARTerEnabled :1; 681 uint32_t SSDPatrolReadEnabled :1; 682 uint32_t enableSpinDownUnconfigured :1; 683 uint32_t autoEnhancedImport :1; 684 uint32_t enableSecretKeyControl :1; 685 uint32_t disableOnlineCtrlReset :1; 686 uint32_t allowBootWithPinnedCache :1; 687 uint32_t disableSpinDownHS :1; 688 uint32_t enableJBOD :1; 689 uint32_t reserved :18; 690 } OnOffProperties; 691 /* 692 * % of source LD to be reserved for auto snapshot in snapshot 693 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 694 */ 695 uint8_t autoSnapVDSpace; 696 /* 697 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 698 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 699 */ 700 uint8_t viewSpace; 701 /* # of idle minutes before device is spun down (0=use FW defaults) */ 702 uint16_t spinDownTime; 703 uint8_t reserved[24]; 704} __packed; 705 706/* PCI information about the card. */ 707struct mfi_info_pci { 708 uint16_t vendor; 709 uint16_t device; 710 uint16_t subvendor; 711 uint16_t subdevice; 712 uint8_t reserved[24]; 713} __packed; 714 715/* Host (front end) interface information */ 716struct mfi_info_host { 717 uint8_t type; 718#define MFI_INFO_HOST_PCIX 0x01 719#define MFI_INFO_HOST_PCIE 0x02 720#define MFI_INFO_HOST_ISCSI 0x04 721#define MFI_INFO_HOST_SAS3G 0x08 722 uint8_t reserved[6]; 723 uint8_t port_count; 724 uint64_t port_addr[8]; 725} __packed; 726 727/* Device (back end) interface information */ 728struct mfi_info_device { 729 uint8_t type; 730#define MFI_INFO_DEV_SPI 0x01 731#define MFI_INFO_DEV_SAS3G 0x02 732#define MFI_INFO_DEV_SATA1 0x04 733#define MFI_INFO_DEV_SATA3G 0x08 734 uint8_t reserved[6]; 735 uint8_t port_count; 736 uint64_t port_addr[8]; 737} __packed; 738 739/* Firmware component information */ 740struct mfi_info_component { 741 char name[8]; 742 char version[32]; 743 char build_date[16]; 744 char build_time[16]; 745} __packed; 746 747/* Controller default settings */ 748struct mfi_defaults { 749 uint64_t sas_addr; 750 uint8_t phy_polarity; 751 uint8_t background_rate; 752 uint8_t stripe_size; 753 uint8_t flush_time; 754 uint8_t write_back; 755 uint8_t read_ahead; 756 uint8_t cache_when_bbu_bad; 757 uint8_t cached_io; 758 uint8_t smart_mode; 759 uint8_t alarm_disable; 760 uint8_t coercion; 761 uint8_t zrc_config; 762 uint8_t dirty_led_shows_drive_activity; 763 uint8_t bios_continue_on_error; 764 uint8_t spindown_mode; 765 uint8_t allowed_device_types; 766 uint8_t allow_mix_in_enclosure; 767 uint8_t allow_mix_in_ld; 768 uint8_t allow_sata_in_cluster; 769 uint8_t max_chained_enclosures; 770 uint8_t disable_ctrl_r; 771 uint8_t enabel_web_bios; 772 uint8_t phy_polarity_split; 773 uint8_t direct_pd_mapping; 774 uint8_t bios_enumerate_lds; 775 uint8_t restored_hot_spare_on_insertion; 776 uint8_t expose_enclosure_devices; 777 uint8_t maintain_pd_fail_history; 778 uint8_t resv[28]; 779} __packed; 780 781/* Controller default settings */ 782struct mfi_bios_data { 783 uint16_t boot_target_id; 784 uint8_t do_not_int_13; 785 uint8_t continue_on_error; 786 uint8_t verbose; 787 uint8_t geometry; 788 uint8_t expose_all_drives; 789 uint8_t reserved[56]; 790 uint8_t check_sum; 791} __packed; 792 793/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 794struct mfi_ctrl_info { 795 struct mfi_info_pci pci; 796 struct mfi_info_host host; 797 struct mfi_info_device device; 798 799 /* Firmware components that are present and active. */ 800 uint32_t image_check_word; 801 uint32_t image_component_count; 802 struct mfi_info_component image_component[8]; 803 804 /* Firmware components that have been flashed but are inactive */ 805 uint32_t pending_image_component_count; 806 struct mfi_info_component pending_image_component[8]; 807 808 uint8_t max_arms; 809 uint8_t max_spans; 810 uint8_t max_arrays; 811 uint8_t max_lds; 812 char product_name[80]; 813 char serial_number[32]; 814 uint32_t hw_present; 815#define MFI_INFO_HW_BBU 0x01 816#define MFI_INFO_HW_ALARM 0x02 817#define MFI_INFO_HW_NVRAM 0x04 818#define MFI_INFO_HW_UART 0x08 819 uint32_t current_fw_time; 820 uint16_t max_cmds; 821 uint16_t max_sg_elements; 822 uint32_t max_request_size; 823 uint16_t lds_present; 824 uint16_t lds_degraded; 825 uint16_t lds_offline; 826 uint16_t pd_present; 827 uint16_t pd_disks_present; 828 uint16_t pd_disks_pred_failure; 829 uint16_t pd_disks_failed; 830 uint16_t nvram_size; 831 uint16_t memory_size; 832 uint16_t flash_size; 833 uint16_t ram_correctable_errors; 834 uint16_t ram_uncorrectable_errors; 835 uint8_t cluster_allowed; 836 uint8_t cluster_active; 837 uint16_t max_strips_per_io; 838 839 uint32_t raid_levels; 840#define MFI_INFO_RAID_0 0x01 841#define MFI_INFO_RAID_1 0x02 842#define MFI_INFO_RAID_5 0x04 843#define MFI_INFO_RAID_1E 0x08 844#define MFI_INFO_RAID_6 0x10 845 846 uint32_t adapter_ops; 847#define MFI_INFO_AOPS_RBLD_RATE 0x0001 848#define MFI_INFO_AOPS_CC_RATE 0x0002 849#define MFI_INFO_AOPS_BGI_RATE 0x0004 850#define MFI_INFO_AOPS_RECON_RATE 0x0008 851#define MFI_INFO_AOPS_PATROL_RATE 0x0010 852#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 853#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 854#define MFI_INFO_AOPS_BBU 0x0080 855#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 856#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 857#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 858#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 859#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 860#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 861#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 862 863 uint32_t ld_ops; 864#define MFI_INFO_LDOPS_READ_POLICY 0x01 865#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 866#define MFI_INFO_LDOPS_IO_POLICY 0x04 867#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 868#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 869 870 struct { 871 uint8_t min; 872 uint8_t max; 873 uint8_t reserved[2]; 874 } __packed stripe_sz_ops; 875 876 uint32_t pd_ops; 877#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 878#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 879#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 880 881 uint32_t pd_mix_support; 882#define MFI_INFO_PDMIX_SAS 0x01 883#define MFI_INFO_PDMIX_SATA 0x02 884#define MFI_INFO_PDMIX_ENCL 0x04 885#define MFI_INFO_PDMIX_LD 0x08 886#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 887 888 uint8_t ecc_bucket_count; 889 uint8_t reserved2[11]; 890 struct mfi_ctrl_props properties; 891 char package_version[0x60]; 892 uint8_t pad[0x800 - 0x6a0]; 893} __packed; 894 895/* keep track of an event. */ 896union mfi_evt { 897 struct { 898 uint16_t locale; 899 uint8_t reserved; 900 int8_t evt_class; 901 } members; 902 uint32_t word; 903} __packed; 904 905/* event log state. */ 906struct mfi_evt_log_state { 907 uint32_t newest_seq_num; 908 uint32_t oldest_seq_num; 909 uint32_t clear_seq_num; 910 uint32_t shutdown_seq_num; 911 uint32_t boot_seq_num; 912} __packed; 913 914struct mfi_progress { 915 uint16_t progress; 916 uint16_t elapsed_seconds; 917} __packed; 918 919struct mfi_evt_ld { 920 uint16_t target_id; 921 uint8_t ld_index; 922 uint8_t reserved; 923} __packed; 924 925struct mfi_evt_pd { 926 uint16_t device_id; 927 uint8_t enclosure_index; 928 uint8_t slot_number; 929} __packed; 930 931/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 932struct mfi_evt_detail { 933 uint32_t seq; 934 uint32_t time; 935 uint32_t code; 936 union mfi_evt evt_class; 937 uint8_t arg_type; 938 uint8_t reserved1[15]; 939 940 union { 941 struct { 942 struct mfi_evt_pd pd; 943 uint8_t cdb_len; 944 uint8_t sense_len; 945 uint8_t reserved[2]; 946 uint8_t cdb[16]; 947 uint8_t sense[64]; 948 } cdb_sense; 949 950 struct mfi_evt_ld ld; 951 952 struct { 953 struct mfi_evt_ld ld; 954 uint64_t count; 955 } ld_count; 956 957 struct { 958 uint64_t lba; 959 struct mfi_evt_ld ld; 960 } ld_lba; 961 962 struct { 963 struct mfi_evt_ld ld; 964 uint32_t pre_owner; 965 uint32_t new_owner; 966 } ld_owner; 967 968 struct { 969 uint64_t ld_lba; 970 uint64_t pd_lba; 971 struct mfi_evt_ld ld; 972 struct mfi_evt_pd pd; 973 } ld_lba_pd_lba; 974 975 struct { 976 struct mfi_evt_ld ld; 977 struct mfi_progress prog; 978 } ld_prog; 979 980 struct { 981 struct mfi_evt_ld ld; 982 uint32_t prev_state; 983 uint32_t new_state; 984 } ld_state; 985 986 struct { 987 uint64_t strip; 988 struct mfi_evt_ld ld; 989 } ld_strip; 990 991 struct mfi_evt_pd pd; 992 993 struct { 994 struct mfi_evt_pd pd; 995 uint32_t err; 996 } pd_err; 997 998 struct { 999 uint64_t lba; 1000 struct mfi_evt_pd pd; 1001 } pd_lba; 1002 1003 struct { 1004 uint64_t lba; 1005 struct mfi_evt_pd pd; 1006 struct mfi_evt_ld ld; 1007 } pd_lba_ld; 1008 1009 struct { 1010 struct mfi_evt_pd pd; 1011 struct mfi_progress prog; 1012 } pd_prog; 1013 1014 struct { 1015 struct mfi_evt_pd ld; 1016 uint32_t prev_state; 1017 uint32_t new_state; 1018 } pd_state; 1019 1020 struct { 1021 uint16_t venderId; 1022 uint16_t deviceId; 1023 uint16_t subVenderId; 1024 uint16_t subDeviceId; 1025 } pci; 1026 1027 uint32_t rate; 1028 1029 char str[96]; 1030 1031 struct { 1032 uint32_t rtc; 1033 uint16_t elapsedSeconds; 1034 } time; 1035 1036 struct { 1037 uint32_t ecar; 1038 uint32_t elog; 1039 char str[64]; 1040 } ecc; 1041 1042 uint8_t b[96]; 1043 uint16_t s[48]; 1044 uint32_t w[24]; 1045 uint64_t d[12]; 1046 } args; 1047 1048 char description[128]; 1049} __packed; 1050 1051struct mfi_evt_list { 1052 uint32_t count; 1053 uint32_t reserved; 1054 struct mfi_evt_detail event[1]; 1055} __packed; 1056 1057union mfi_pd_ref { 1058 struct { 1059 uint16_t device_id; 1060 uint16_t seq_num; 1061 } v; 1062 uint32_t ref; 1063} __packed; 1064 1065union mfi_pd_ddf_type { 1066 struct { 1067 union { 1068 struct { 1069 uint16_t forced_pd_guid : 1; 1070 uint16_t in_vd : 1; 1071 uint16_t is_global_spare : 1; 1072 uint16_t is_spare : 1; 1073 uint16_t is_foreign : 1; 1074 uint16_t reserved : 7; 1075 uint16_t intf : 4; 1076 } pd_type; 1077 uint16_t type; 1078 } v; 1079 uint16_t reserved; 1080 } ddf; 1081 struct { 1082 uint32_t reserved; 1083 } non_disk; 1084 uint32_t type; 1085} __packed; 1086 1087struct mfi_pd_progress { 1088 uint32_t active; 1089#define MFI_PD_PROGRESS_REBUILD (1<<0) 1090#define MFI_PD_PROGRESS_PATROL (1<<1) 1091#define MFI_PD_PROGRESS_CLEAR (1<<2) 1092 struct mfi_progress rbld; 1093 struct mfi_progress patrol; 1094 struct mfi_progress clear; 1095 struct mfi_progress reserved[4]; 1096} __packed; 1097 1098struct mfi_pd_info { 1099 union mfi_pd_ref ref; 1100 uint8_t inquiry_data[96]; 1101 uint8_t vpd_page83[64]; 1102 uint8_t not_supported; 1103 uint8_t scsi_dev_type; 1104 uint8_t connected_port_bitmap; 1105 uint8_t device_speed; 1106 uint32_t media_err_count; 1107 uint32_t other_err_count; 1108 uint32_t pred_fail_count; 1109 uint32_t last_pred_fail_event_seq_num; 1110 uint16_t fw_state; /* MFI_PD_STATE_* */ 1111 uint8_t disabled_for_removal; 1112 uint8_t link_speed; 1113 union mfi_pd_ddf_type state; 1114 struct { 1115 uint8_t count; 1116 uint8_t is_path_broken; 1117 uint8_t reserved[6]; 1118 uint64_t sas_addr[4]; 1119 } path_info; 1120 uint64_t raw_size; 1121 uint64_t non_coerced_size; 1122 uint64_t coerced_size; 1123 uint16_t encl_device_id; 1124 uint8_t encl_index; 1125 uint8_t slot_number; 1126 struct mfi_pd_progress prog_info; 1127 uint8_t bad_block_table_full; 1128 uint8_t unusable_in_current_config; 1129 uint8_t vpd_page83_ext[64]; 1130 uint8_t reserved[512-358]; 1131} __packed; 1132 1133struct mfi_pd_address { 1134 uint16_t device_id; 1135 uint16_t encl_device_id; 1136 uint8_t encl_index; 1137 uint8_t slot_number; 1138 uint8_t scsi_dev_type; /* 0 = disk */ 1139 uint8_t connect_port_bitmap; 1140 uint64_t sas_addr[2]; 1141} __packed; 1142 1143#define MAX_SYS_PDS 240 1144struct mfi_pd_list { 1145 uint32_t size; 1146 uint32_t count; 1147 struct mfi_pd_address addr[MAX_SYS_PDS]; 1148} __packed; 1149 1150enum mfi_pd_state { 1151 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1152 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1153 MFI_PD_STATE_HOT_SPARE = 0x02, 1154 MFI_PD_STATE_OFFLINE = 0x10, 1155 MFI_PD_STATE_FAILED = 0x11, 1156 MFI_PD_STATE_REBUILD = 0x14, 1157 MFI_PD_STATE_ONLINE = 0x18, 1158 MFI_PD_STATE_COPYBACK = 0x20, 1159 MFI_PD_STATE_SYSTEM = 0x40 1160}; 1161 1162/* 1163 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1164 * Adding a #define to denote this. 1165 */ 1166#define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1167 1168union mfi_ld_ref { 1169 struct { 1170 uint8_t target_id; 1171 uint8_t reserved; 1172 uint16_t seq; 1173 } v; 1174 uint32_t ref; 1175} __packed; 1176 1177struct mfi_ld_list { 1178 uint32_t ld_count; 1179 uint32_t reserved1; 1180 struct { 1181 union mfi_ld_ref ld; 1182 uint8_t state; 1183 uint8_t reserved2[3]; 1184 uint64_t size; 1185 } ld_list[MFI_MAX_LD]; 1186} __packed; 1187 1188enum mfi_ld_access { 1189 MFI_LD_ACCESS_RW = 0, 1190 MFI_LD_ACCSSS_RO = 2, 1191 MFI_LD_ACCESS_BLOCKED = 3, 1192}; 1193#define MFI_LD_ACCESS_MASK 3 1194 1195enum mfi_ld_state { 1196 MFI_LD_STATE_OFFLINE = 0, 1197 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1198 MFI_LD_STATE_DEGRADED = 2, 1199 MFI_LD_STATE_OPTIMAL = 3 1200}; 1201 1202struct mfi_ld_props { 1203 union mfi_ld_ref ld; 1204 char name[16]; 1205 uint8_t default_cache_policy; 1206 uint8_t access_policy; 1207 uint8_t disk_cache_policy; 1208 uint8_t current_cache_policy; 1209 uint8_t no_bgi; 1210 uint8_t reserved[7]; 1211} __packed; 1212 1213struct mfi_ld_params { 1214 uint8_t primary_raid_level; 1215 uint8_t raid_level_qualifier; 1216 uint8_t secondary_raid_level; 1217 uint8_t stripe_size; 1218 uint8_t num_drives; 1219 uint8_t span_depth; 1220 uint8_t state; 1221 uint8_t init_state; 1222#define MFI_LD_PARAMS_INIT_NO 0 1223#define MFI_LD_PARAMS_INIT_QUICK 1 1224#define MFI_LD_PARAMS_INIT_FULL 2 1225 uint8_t is_consistent; 1226 uint8_t reserved1[6]; 1227 uint8_t isSSCD; 1228 uint8_t reserved2[16]; 1229} __packed; 1230 1231struct mfi_ld_progress { 1232 uint32_t active; 1233#define MFI_LD_PROGRESS_CC (1<<0) 1234#define MFI_LD_PROGRESS_BGI (1<<1) 1235#define MFI_LD_PROGRESS_FGI (1<<2) 1236#define MFI_LD_PROGRESS_RECON (1<<3) 1237 struct mfi_progress cc; 1238 struct mfi_progress bgi; 1239 struct mfi_progress fgi; 1240 struct mfi_progress recon; 1241 struct mfi_progress reserved[4]; 1242} __packed; 1243 1244struct mfi_span { 1245 uint64_t start_block; 1246 uint64_t num_blocks; 1247 uint16_t array_ref; 1248 uint8_t reserved[6]; 1249} __packed; 1250 1251#define MFI_MAX_SPAN_DEPTH 8 1252struct mfi_ld_config { 1253 struct mfi_ld_props properties; 1254 struct mfi_ld_params params; 1255 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1256} __packed; 1257 1258struct mfi_ld_info { 1259 struct mfi_ld_config ld_config; 1260 uint64_t size; 1261 struct mfi_ld_progress progress; 1262 uint16_t cluster_owner; 1263 uint8_t reconstruct_active; 1264 uint8_t reserved1[1]; 1265 uint8_t vpd_page83[64]; 1266 uint8_t reserved2[16]; 1267} __packed; 1268 1269#define MFI_MAX_ARRAYS 16 1270struct mfi_spare { 1271 union mfi_pd_ref ref; 1272 uint8_t spare_type; 1273#define MFI_SPARE_DEDICATED (1 << 0) 1274#define MFI_SPARE_REVERTIBLE (1 << 1) 1275#define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1276 uint8_t reserved[2]; 1277 uint8_t array_count; 1278 uint16_t array_ref[MFI_MAX_ARRAYS]; 1279} __packed; 1280 1281#define MFI_MAX_ROW_SIZE 32 1282struct mfi_array { 1283 uint64_t size; 1284 uint8_t num_drives; 1285 uint8_t reserved; 1286 uint16_t array_ref; 1287 uint8_t pad[20]; 1288 struct { 1289 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1290 uint16_t fw_state; /* MFI_PD_STATE_* */ 1291 struct { 1292 uint8_t pd; 1293 uint8_t slot; 1294 } encl; 1295 } pd[MFI_MAX_ROW_SIZE]; 1296} __packed; 1297 1298struct mfi_config_data { 1299 uint32_t size; 1300 uint16_t array_count; 1301 uint16_t array_size; 1302 uint16_t log_drv_count; 1303 uint16_t log_drv_size; 1304 uint16_t spares_count; 1305 uint16_t spares_size; 1306 uint8_t reserved[16]; 1307 struct mfi_array array[0]; 1308 struct mfi_ld_config ld[0]; 1309 struct mfi_spare spare[0]; 1310} __packed; 1311 1312struct mfi_bbu_capacity_info { 1313 uint16_t relative_charge; 1314 uint16_t absolute_charge; 1315 uint16_t remaining_capacity; 1316 uint16_t full_charge_capacity; 1317 uint16_t run_time_to_empty; 1318 uint16_t average_time_to_empty; 1319 uint16_t average_time_to_full; 1320 uint16_t cycle_count; 1321 uint16_t max_error; 1322 uint16_t remaining_capacity_alarm; 1323 uint16_t remaining_time_alarm; 1324 uint8_t reserved[26]; 1325} __packed; 1326 1327struct mfi_bbu_design_info { 1328 uint32_t mfg_date; 1329 uint16_t design_capacity; 1330 uint16_t design_voltage; 1331 uint16_t spec_info; 1332 uint16_t serial_number; 1333 uint16_t pack_stat_config; 1334 uint8_t mfg_name[12]; 1335 uint8_t device_name[8]; 1336 uint8_t device_chemistry[8]; 1337 uint8_t mfg_data[8]; 1338 uint8_t reserved[17]; 1339} __packed; 1340 1341struct mfi_ibbu_state { 1342 uint16_t gas_guage_status; 1343 uint16_t relative_charge; 1344 uint16_t charger_system_state; 1345 uint16_t charger_system_ctrl; 1346 uint16_t charging_current; 1347 uint16_t absolute_charge; 1348 uint16_t max_error; 1349 uint8_t reserved[18]; 1350} __packed; 1351 1352struct mfi_bbu_state { 1353 uint16_t gas_guage_status; 1354 uint16_t relative_charge; 1355 uint16_t charger_status; 1356 uint16_t remaining_capacity; 1357 uint16_t full_charge_capacity; 1358 uint8_t is_SOH_good; 1359 uint8_t reserved[21]; 1360} __packed; 1361 1362union mfi_bbu_status_detail { 1363 struct mfi_ibbu_state ibbu; 1364 struct mfi_bbu_state bbu; 1365}; 1366 1367struct mfi_bbu_status { 1368 uint8_t battery_type; 1369#define MFI_BBU_TYPE_NONE 0 1370#define MFI_BBU_TYPE_IBBU 1 1371#define MFI_BBU_TYPE_BBU 2 1372 uint8_t reserved; 1373 uint16_t voltage; 1374 int16_t current; 1375 uint16_t temperature; 1376 uint32_t fw_status; 1377#define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1378#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1379#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1380#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1381#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1382#define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1383#define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1384#define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1385#define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1386#define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1387 uint8_t pad[20]; 1388 union mfi_bbu_status_detail detail; 1389} __packed; 1390 1391enum mfi_pr_state { 1392 MFI_PR_STATE_STOPPED = 0, 1393 MFI_PR_STATE_READY = 1, 1394 MFI_PR_STATE_ACTIVE = 2, 1395 MFI_PR_STATE_ABORTED = 0xff 1396}; 1397 1398struct mfi_pr_status { 1399 uint32_t num_iteration; 1400 uint8_t state; 1401 uint8_t num_pd_done; 1402 uint8_t reserved[10]; 1403}; 1404 1405enum mfi_pr_opmode { 1406 MFI_PR_OPMODE_AUTO = 0, 1407 MFI_PR_OPMODE_MANUAL = 1, 1408 MFI_PR_OPMODE_DISABLED = 2 1409}; 1410 1411struct mfi_pr_properties { 1412 uint8_t op_mode; 1413 uint8_t max_pd; 1414 uint8_t reserved; 1415 uint8_t exclude_ld_count; 1416 uint16_t excluded_ld[MFI_MAX_LD]; 1417 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1418 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1419 uint32_t next_exec; 1420 uint32_t exec_freq; 1421 uint32_t clear_freq; 1422}; 1423 1424/* ThunderBolt support */ 1425 1426/* 1427 * Raid Context structure which describes MegaRAID specific IO Paramenters 1428 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1429 */ 1430typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1431 uint16_t resvd0; /* 0x00 - 0x01 */ 1432 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1433 uint8_t regLockFlags; 1434 uint8_t armId; 1435 uint16_t TargetID; /* 0x06 - 0x07 */ 1436 1437 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1438 1439 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1440 1441 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1442 uint8_t exStatus; /* 0x16 */ 1443 uint8_t Status; /* 0x17 status */ 1444 1445 uint8_t RAIDFlags; /* 0x18 */ 1446 uint8_t numSGE; /* 0x19 numSge */ 1447 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1448 uint8_t spanArm; /* 0x1C */ 1449 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1450} MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1451 1452/***************************************************************************** 1453* 1454* Message Functions 1455* 1456*****************************************************************************/ 1457 1458#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1459#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1460#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1461#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1462#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1463#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1464#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1465#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1466#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1467#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1468#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1469#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1470#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1471#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1472#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1473#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1474#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1475#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1476#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1477#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1478#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1479#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1480#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1481#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1482#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1483#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1484#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1485#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1486#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1487#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1488 1489/* Doorbell functions */ 1490#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1491#define MPI2_FUNCTION_HANDSHAKE (0x42) 1492 1493/***************************************************************************** 1494* 1495* MPI Version Definitions 1496* 1497*****************************************************************************/ 1498 1499#define MPI2_VERSION_MAJOR (0x02) 1500#define MPI2_VERSION_MINOR (0x00) 1501#define MPI2_VERSION_MAJOR_MASK (0xFF00) 1502#define MPI2_VERSION_MAJOR_SHIFT (8) 1503#define MPI2_VERSION_MINOR_MASK (0x00FF) 1504#define MPI2_VERSION_MINOR_SHIFT (0) 1505#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1506 MPI2_VERSION_MINOR) 1507 1508#define MPI2_VERSION_02_00 (0x0200) 1509 1510/* versioning for this MPI header set */ 1511#define MPI2_HEADER_VERSION_UNIT (0x10) 1512#define MPI2_HEADER_VERSION_DEV (0x00) 1513#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1514#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1515#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1516#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1517#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1518 MPI2_HEADER_VERSION_DEV) 1519 1520 1521/* IOCInit Request message */ 1522struct MPI2_IOC_INIT_REQUEST { 1523 uint8_t WhoInit; /* 0x00 */ 1524 uint8_t Reserved1; /* 0x01 */ 1525 uint8_t ChainOffset; /* 0x02 */ 1526 uint8_t Function; /* 0x03 */ 1527 uint16_t Reserved2; /* 0x04 */ 1528 uint8_t Reserved3; /* 0x06 */ 1529 uint8_t MsgFlags; /* 0x07 */ 1530 uint8_t VP_ID; /* 0x08 */ 1531 uint8_t VF_ID; /* 0x09 */ 1532 uint16_t Reserved4; /* 0x0A */ 1533 uint16_t MsgVersion; /* 0x0C */ 1534 uint16_t HeaderVersion; /* 0x0E */ 1535 uint32_t Reserved5; /* 0x10 */ 1536 uint16_t Reserved6; /* 0x14 */ 1537 uint8_t Reserved7; /* 0x16 */ 1538 uint8_t HostMSIxVectors; /* 0x17 */ 1539 uint16_t Reserved8; /* 0x18 */ 1540 uint16_t SystemRequestFrameSize; /* 0x1A */ 1541 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1542 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1543 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1544 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1545 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1546 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1547 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1548 uint64_t TimeStamp; /* 0x40 */ 1549}; 1550 1551/* WhoInit values */ 1552#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1553#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1554#define MPI2_WHOINIT_ROM_BIOS (0x02) 1555#define MPI2_WHOINIT_PCI_PEER (0x03) 1556#define MPI2_WHOINIT_HOST_DRIVER (0x04) 1557#define MPI2_WHOINIT_MANUFACTURER (0x05) 1558 1559struct MPI2_SGE_CHAIN_UNION { 1560 uint16_t Length; 1561 uint8_t NextChainOffset; 1562 uint8_t Flags; 1563 union { 1564 uint32_t Address32; 1565 uint64_t Address64; 1566 } u; 1567}; 1568 1569struct MPI2_IEEE_SGE_SIMPLE32 { 1570 uint32_t Address; 1571 uint32_t FlagsLength; 1572}; 1573 1574struct MPI2_IEEE_SGE_SIMPLE64 { 1575 uint64_t Address; 1576 uint32_t Length; 1577 uint16_t Reserved1; 1578 uint8_t Reserved2; 1579 uint8_t Flags; 1580}; 1581 1582typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1583 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1584 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1585} MPI2_IEEE_SGE_SIMPLE_UNION; 1586 1587typedef struct _MPI2_SGE_SIMPLE_UNION { 1588 uint32_t FlagsLength; 1589 union { 1590 uint32_t Address32; 1591 uint64_t Address64; 1592 } u; 1593} MPI2_SGE_SIMPLE_UNION; 1594 1595/**************************************************************************** 1596* IEEE SGE field definitions and masks 1597****************************************************************************/ 1598 1599/* Flags field bit definitions */ 1600 1601#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1602 1603#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1604 1605#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1606 1607/* Element Type */ 1608 1609#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1610#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1611 1612/* Data Location Address Space */ 1613 1614#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1615#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1616#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1617#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1618#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1619 1620/* Address Size */ 1621 1622#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1623#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1624 1625/*******************/ 1626/* SCSI IO Control bits */ 1627#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1628#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1629 1630#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1631#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1632#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1633#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1634#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1635 1636#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1637#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1638 1639#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1640#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1641#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1642#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1643#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1644 1645#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1646#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1647#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1648#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1649 1650/*******************/ 1651 1652typedef struct { 1653 uint8_t CDB[20]; /* 0x00 */ 1654 uint32_t PrimaryReferenceTag; /* 0x14 */ 1655 uint16_t PrimaryApplicationTag; /* 0x18 */ 1656 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1657 uint32_t TransferLength; /* 0x1C */ 1658} MPI2_SCSI_IO_CDB_EEDP32; 1659 1660 1661typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1662 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1663 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1664} MPI2_IEEE_SGE_CHAIN_UNION; 1665 1666typedef union _MPI2_SIMPLE_SGE_UNION { 1667 MPI2_SGE_SIMPLE_UNION MpiSimple; 1668 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1669} MPI2_SIMPLE_SGE_UNION; 1670 1671typedef union _MPI2_SGE_IO_UNION { 1672 MPI2_SGE_SIMPLE_UNION MpiSimple; 1673 struct MPI2_SGE_CHAIN_UNION MpiChain; 1674 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1675 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1676} MPI2_SGE_IO_UNION; 1677 1678typedef union { 1679 uint8_t CDB32[32]; 1680 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1681 MPI2_SGE_SIMPLE_UNION SGE; 1682} MPI2_SCSI_IO_CDB_UNION; 1683 1684 1685/* MPI 2.5 SGLs */ 1686 1687#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1688 1689typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1690 uint64_t Address; 1691 uint32_t Length; 1692 uint16_t Reserved1; 1693 uint8_t NextChainOffset; 1694 uint8_t Flags; 1695} MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1696 1697/* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1698 1699 1700/********/ 1701 1702/* 1703 * RAID SCSI IO Request Message 1704 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1705 */ 1706struct mfi_mpi2_request_raid_scsi_io { 1707 uint16_t DevHandle; /* 0x00 */ 1708 uint8_t ChainOffset; /* 0x02 */ 1709 uint8_t Function; /* 0x03 */ 1710 uint16_t Reserved1; /* 0x04 */ 1711 uint8_t Reserved2; /* 0x06 */ 1712 uint8_t MsgFlags; /* 0x07 */ 1713 uint8_t VP_ID; /* 0x08 */ 1714 uint8_t VF_ID; /* 0x09 */ 1715 uint16_t Reserved3; /* 0x0A */ 1716 uint32_t SenseBufferLowAddress; /* 0x0C */ 1717 uint16_t SGLFlags; /* 0x10 */ 1718 uint8_t SenseBufferLength; /* 0x12 */ 1719 uint8_t Reserved4; /* 0x13 */ 1720 uint8_t SGLOffset0; /* 0x14 */ 1721 uint8_t SGLOffset1; /* 0x15 */ 1722 uint8_t SGLOffset2; /* 0x16 */ 1723 uint8_t SGLOffset3; /* 0x17 */ 1724 uint32_t SkipCount; /* 0x18 */ 1725 uint32_t DataLength; /* 0x1C */ 1726 uint32_t BidirectionalDataLength; /* 0x20 */ 1727 uint16_t IoFlags; /* 0x24 */ 1728 uint16_t EEDPFlags; /* 0x26 */ 1729 uint32_t EEDPBlockSize; /* 0x28 */ 1730 uint32_t SecondaryReferenceTag; /* 0x2C */ 1731 uint16_t SecondaryApplicationTag; /* 0x30 */ 1732 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1733 uint8_t LUN[8]; /* 0x34 */ 1734 uint32_t Control; /* 0x3C */ 1735 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1736 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1737 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1738} __packed; 1739 1740/* 1741 * MPT RAID MFA IO Descriptor. 1742 */ 1743typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1744 uint32_t RequestFlags : 8; 1745 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1746 uint32_t MessageAddress2; /* bits 61:32 */ 1747} MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1748 1749struct mfi_mpi2_request_header { 1750 uint8_t RequestFlags; /* 0x00 */ 1751 uint8_t MSIxIndex; /* 0x01 */ 1752 uint16_t SMID; /* 0x02 */ 1753 uint16_t LMID; /* 0x04 */ 1754}; 1755 1756/* defines for the RequestFlags field */ 1757#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1758#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1759#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1760#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1761#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1762#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1763 1764#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1765 1766struct mfi_mpi2_request_high_priority { 1767 struct mfi_mpi2_request_header header; 1768 uint16_t reserved; 1769}; 1770 1771struct mfi_mpi2_request_scsi_io { 1772 struct mfi_mpi2_request_header header; 1773 uint16_t scsi_io_dev_handle; 1774}; 1775 1776struct mfi_mpi2_request_scsi_target { 1777 struct mfi_mpi2_request_header header; 1778 uint16_t scsi_target_io_index; 1779}; 1780 1781/* Request Descriptors */ 1782union mfi_mpi2_request_descriptor { 1783 struct mfi_mpi2_request_header header; 1784 struct mfi_mpi2_request_high_priority high_priority; 1785 struct mfi_mpi2_request_scsi_io scsi_io; 1786 struct mfi_mpi2_request_scsi_target scsi_target; 1787 uint64_t words; 1788}; 1789 1790 1791struct mfi_mpi2_reply_header { 1792 uint8_t ReplyFlags; /* 0x00 */ 1793 uint8_t MSIxIndex; /* 0x01 */ 1794 uint16_t SMID; /* 0x02 */ 1795}; 1796 1797/* defines for the ReplyFlags field */ 1798#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1799#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1800#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1801#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1802#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1803#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1804#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1805 1806/* values for marking a reply descriptor as unused */ 1807#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1808#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1809 1810struct mfi_mpi2_reply_default { 1811 struct mfi_mpi2_reply_header header; 1812 uint32_t DescriptorTypeDependent2; 1813}; 1814 1815struct mfi_mpi2_reply_address { 1816 struct mfi_mpi2_reply_header header; 1817 uint32_t ReplyFrameAddress; 1818}; 1819 1820struct mfi_mpi2_reply_scsi_io { 1821 struct mfi_mpi2_reply_header header; 1822 uint16_t TaskTag; /* 0x04 */ 1823 uint16_t Reserved1; /* 0x06 */ 1824}; 1825 1826struct mfi_mpi2_reply_target_assist { 1827 struct mfi_mpi2_reply_header header; 1828 uint8_t SequenceNumber; /* 0x04 */ 1829 uint8_t Reserved1; /* 0x04 */ 1830 uint16_t IoIndex; /* 0x06 */ 1831}; 1832 1833struct mfi_mpi2_reply_target_cmd_buffer { 1834 struct mfi_mpi2_reply_header header; 1835 uint8_t SequenceNumber; /* 0x04 */ 1836 uint8_t Flags; /* 0x04 */ 1837 uint16_t InitiatorDevHandle; /* 0x06 */ 1838 uint16_t IoIndex; /* 0x06 */ 1839}; 1840 1841struct mfi_mpi2_reply_raid_accel { 1842 struct mfi_mpi2_reply_header header; 1843 uint8_t SequenceNumber; /* 0x04 */ 1844 uint32_t Reserved; /* 0x04 */ 1845}; 1846 1847/* union of Reply Descriptors */ 1848union mfi_mpi2_reply_descriptor { 1849 struct mfi_mpi2_reply_header header; 1850 struct mfi_mpi2_reply_scsi_io scsi_io; 1851 struct mfi_mpi2_reply_target_assist target_assist; 1852 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1853 struct mfi_mpi2_reply_raid_accel raid_accel; 1854 struct mfi_mpi2_reply_default reply_default; 1855 uint64_t words; 1856}; 1857 1858struct IO_REQUEST_INFO { 1859 uint64_t ldStartBlock; 1860 uint32_t numBlocks; 1861 uint16_t ldTgtId; 1862 uint8_t isRead; 1863 uint16_t devHandle; 1864 uint64_t pdBlock; 1865 uint8_t fpOkForIo; 1866}; 1867 1868#define MFI_SCSI_MAX_TARGETS 128 1869#define MFI_SCSI_MAX_LUNS 8 1870#define MFI_SCSI_INITIATOR_ID 255 1871#define MFI_SCSI_MAX_CMDS 8 1872#define MFI_SCSI_MAX_CDB_LEN 16 1873 1874#endif /* _MFIREG_H */ 1875