mfireg.h revision 158737
1/*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#ifndef _MFIREG_H 28#define _MFIREG_H 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/mfi/mfireg.h 158737 2006-05-18 23:30:48Z ambrisko $"); 32 33/* 34 * MegaRAID SAS MFI firmware definitions 35 * 36 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 37 * new firmware interface from the old AMI MegaRAID one, and there is no 38 * reason why this interface should be limited to just SAS. In any case, LSI 39 * seems to also call this interface 'MFI', so that will be used here. 40 */ 41 42/* 43 * Start with the register set. All registers are 32 bits wide. 44 * The usual Intel IOP style setup. 45 */ 46#define MFI_IMSG0 0x10 /* Inbound message 0 */ 47#define MFI_IMSG1 0x14 /* Inbound message 1 */ 48#define MFI_OMSG0 0x18 /* Outbound message 0 */ 49#define MFI_OMSG1 0x1c /* Outbound message 1 */ 50#define MFI_IDB 0x20 /* Inbound doorbell */ 51#define MFI_ISTS 0x24 /* Inbound interrupt status */ 52#define MFI_IMSK 0x28 /* Inbound interrupt mask */ 53#define MFI_ODB 0x2c /* Outbound doorbell */ 54#define MFI_OSTS 0x30 /* Outbound interrupt status */ 55#define MFI_OMSK 0x34 /* Outbound interrupt mask */ 56#define MFI_IQP 0x40 /* Inbound queue port */ 57#define MFI_OQP 0x44 /* Outbound queue port */ 58 59/* Bits for MFI_OSTS */ 60#define MFI_OSTS_INTR_VALID 0x00000002 61 62/* 63 * Firmware state values. Found in OMSG0 during initialization. 64 */ 65#define MFI_FWSTATE_MASK 0xf0000000 66#define MFI_FWSTATE_UNDEFINED 0x00000000 67#define MFI_FWSTATE_BB_INIT 0x10000000 68#define MFI_FWSTATE_FW_INIT 0x40000000 69#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 70#define MFI_FWSTATE_FW_INIT_2 0x70000000 71#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 72#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 73#define MFI_FWSTATE_READY 0xb0000000 74#define MFI_FWSTATE_OPERATIONAL 0xc0000000 75#define MFI_FWSTATE_FAULT 0xf0000000 76#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 77#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 78 79/* 80 * Control bits to drive the card to ready state. These go into the IDB 81 * register. 82 */ 83#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 84#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 85#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 86#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 87 88/* MFI Commands */ 89typedef enum { 90 MFI_CMD_INIT = 0x00, 91 MFI_CMD_LD_READ, 92 MFI_CMD_LD_WRITE, 93 MFI_CMD_LD_SCSI_IO, 94 MFI_CMD_PD_SCSI_IO, 95 MFI_CMD_DCMD, 96 MFI_CMD_ABORT, 97 MFI_CMD_SMP, 98 MFI_CMD_STP 99} mfi_cmd_t; 100 101/* Direct commands */ 102typedef enum { 103 MFI_DCMD_CTRL_GETINFO = 0x01010000, 104 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 105 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 106 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 107 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 108 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 109 MFI_DCMD_LD_GET_PROP = 0x03030000, 110 MFI_DCMD_CLUSTER = 0x08000000, 111 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 112 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 113} mfi_dcmd_t; 114 115/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 116#define MFI_FLUSHCACHE_CTRL 0x01 117#define MFI_FLUSHCACHE_DISK 0x02 118 119/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 120#define MFI_SHUTDOWN_SPINDOWN 0x01 121 122/* 123 * MFI Frame flags 124 */ 125#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 126#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 127#define MFI_FRAME_SGL32 0x0000 128#define MFI_FRAME_SGL64 0x0002 129#define MFI_FRAME_SENSE32 0x0000 130#define MFI_FRAME_SENSE64 0x0004 131#define MFI_FRAME_DIR_NONE 0x0000 132#define MFI_FRAME_DIR_WRITE 0x0008 133#define MFI_FRAME_DIR_READ 0x0010 134#define MFI_FRAME_DIR_BOTH 0x0018 135 136/* MFI Status codes */ 137typedef enum { 138 MFI_STAT_OK = 0x00, 139 MFI_STAT_INVALID_CMD, 140 MFI_STAT_INVALID_DCMD, 141 MFI_STAT_INVALID_PARAMETER, 142 MFI_STAT_INVALID_SEQUENCE_NUMBER, 143 MFI_STAT_ABORT_NOT_POSSIBLE, 144 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 145 MFI_STAT_APP_IN_USE, 146 MFI_STAT_APP_NOT_INITIALIZED, 147 MFI_STAT_ARRAY_INDEX_INVALID, 148 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 149 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 150 MFI_STAT_DEVICE_NOT_FOUND, 151 MFI_STAT_DRIVE_TOO_SMALL, 152 MFI_STAT_FLASH_ALLOC_FAIL, 153 MFI_STAT_FLASH_BUSY, 154 MFI_STAT_FLASH_ERROR = 0x10, 155 MFI_STAT_FLASH_IMAGE_BAD, 156 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 157 MFI_STAT_FLASH_NOT_OPEN, 158 MFI_STAT_FLASH_NOT_STARTED, 159 MFI_STAT_FLUSH_FAILED, 160 MFI_STAT_HOST_CODE_NOT_FOUNT, 161 MFI_STAT_LD_CC_IN_PROGRESS, 162 MFI_STAT_LD_INIT_IN_PROGRESS, 163 MFI_STAT_LD_LBA_OUT_OF_RANGE, 164 MFI_STAT_LD_MAX_CONFIGURED, 165 MFI_STAT_LD_NOT_OPTIMAL, 166 MFI_STAT_LD_RBLD_IN_PROGRESS, 167 MFI_STAT_LD_RECON_IN_PROGRESS, 168 MFI_STAT_LD_WRONG_RAID_LEVEL, 169 MFI_STAT_MAX_SPARES_EXCEEDED, 170 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 171 MFI_STAT_MFC_HW_ERROR, 172 MFI_STAT_NO_HW_PRESENT, 173 MFI_STAT_NOT_FOUND, 174 MFI_STAT_NOT_IN_ENCL, 175 MFI_STAT_PD_CLEAR_IN_PROGRESS, 176 MFI_STAT_PD_TYPE_WRONG, 177 MFI_STAT_PR_DISABLED, 178 MFI_STAT_ROW_INDEX_INVALID, 179 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 180 MFI_STAT_SAS_CONFIG_INVALID_DATA, 181 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 182 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 183 MFI_STAT_SCSI_DONE_WITH_ERROR, 184 MFI_STAT_SCSI_IO_FAILED, 185 MFI_STAT_SCSI_RESERVATION_CONFLICT, 186 MFI_STAT_SHUTDOWN_FAILED = 0x30, 187 MFI_STAT_TIME_NOT_SET, 188 MFI_STAT_WRONG_STATE, 189 MFI_STAT_LD_OFFLINE, 190 MFI_STAT_PEER_NOTIFICATION_REJECTED, 191 MFI_STAT_PEER_NOTIFICATION_FAILED, 192 MFI_STAT_RESERVATION_IN_PROGRESS, 193 MFI_STAT_I2C_ERRORS_DETECTED, 194 MFI_STAT_PCI_ERRORS_DETECTED, 195 MFI_STAT_INVALID_STATUS = 0xFF 196} mfi_status_t; 197 198typedef enum { 199 MFI_EVT_CLASS_DEBUG = -2, 200 MFI_EVT_CLASS_PROGRESS = -1, 201 MFI_EVT_CLASS_INFO = 0, 202 MFI_EVT_CLASS_WARNING = 1, 203 MFI_EVT_CLASS_CRITICAL = 2, 204 MFI_EVT_CLASS_FATAL = 3, 205 MFI_EVT_CLASS_DEAD = 4 206} mfi_evt_class_t; 207 208typedef enum { 209 MFI_EVT_LOCALE_LD = 0x0001, 210 MFI_EVT_LOCALE_PD = 0x0002, 211 MFI_EVT_LOCALE_ENCL = 0x0004, 212 MFI_EVT_LOCALE_BBU = 0x0008, 213 MFI_EVT_LOCALE_SAS = 0x0010, 214 MFI_EVT_LOCALE_CTRL = 0x0020, 215 MFI_EVT_LOCALE_CONFIG = 0x0040, 216 MFI_EVT_LOCALE_CLUSTER = 0x0080, 217 MFI_EVT_LOCALE_ALL = 0xffff 218} mfi_evt_locale_t; 219 220typedef enum { 221 MR_EVT_ARGS_NONE = 0x00, 222 MR_EVT_ARGS_CDB_SENSE, 223 MR_EVT_ARGS_LD, 224 MR_EVT_ARGS_LD_COUNT, 225 MR_EVT_ARGS_LD_LBA, 226 MR_EVT_ARGS_LD_OWNER, 227 MR_EVT_ARGS_LD_LBA_PD_LBA, 228 MR_EVT_ARGS_LD_PROG, 229 MR_EVT_ARGS_LD_STATE, 230 MR_EVT_ARGS_LD_STRIP, 231 MR_EVT_ARGS_PD, 232 MR_EVT_ARGS_PD_ERR, 233 MR_EVT_ARGS_PD_LBA, 234 MR_EVT_ARGS_PD_LBA_LD, 235 MR_EVT_ARGS_PD_PROG, 236 MR_EVT_ARGS_PD_STATE, 237 MR_EVT_ARGS_PCI, 238 MR_EVT_ARGS_RATE, 239 MR_EVT_ARGS_STR, 240 MR_EVT_ARGS_TIME, 241 MR_EVT_ARGS_ECC 242} mfi_evt_args; 243 244/* 245 * Other propertities and definitions 246 */ 247#define MFI_MAX_PD_CHANNELS 2 248#define MFI_MAX_LD_CHANNELS 2 249#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 250#define MFI_MAX_CHANNEL_DEVS 128 251#define MFI_DEFAULT_ID -1 252#define MFI_MAX_LUN 8 253#define MFI_MAX_LD 64 254 255#define MFI_FRAME_SIZE 64 256#define MFI_MBOX_SIZE 12 257 258#define MFI_POLL_TIMEOUT_SECS 10 259 260/* Allow for speedier math calculations */ 261#define MFI_SECTOR_LEN 512 262 263/* Scatter Gather elements */ 264struct mfi_sg32 { 265 uint32_t addr; 266 uint32_t len; 267} __packed; 268 269struct mfi_sg64 { 270 uint64_t addr; 271 uint32_t len; 272} __packed; 273 274union mfi_sgl { 275 struct mfi_sg32 sg32[1]; 276 struct mfi_sg64 sg64[1]; 277} __packed; 278 279/* Message frames. All messages have a common header */ 280struct mfi_frame_header { 281 uint8_t cmd; 282 uint8_t sense_len; 283 uint8_t cmd_status; 284 uint8_t scsi_status; 285 uint8_t target_id; 286 uint8_t lun_id; 287 uint8_t cdb_len; 288 uint8_t sg_count; 289 uint32_t context; 290 uint32_t pad0; 291 uint16_t flags; 292 uint16_t timeout; 293 uint32_t data_len; 294} __packed; 295 296struct mfi_init_frame { 297 struct mfi_frame_header header; 298 uint32_t qinfo_new_addr_lo; 299 uint32_t qinfo_new_addr_hi; 300 uint32_t qinfo_old_addr_lo; 301 uint32_t qinfo_old_addr_hi; 302 uint32_t reserved[6]; 303} __packed; 304 305#define MFI_IO_FRAME_SIZE 40 306struct mfi_io_frame { 307 struct mfi_frame_header header; 308 uint32_t sense_addr_lo; 309 uint32_t sense_addr_hi; 310 uint32_t lba_lo; 311 uint32_t lba_hi; 312 union mfi_sgl sgl; 313} __packed; 314 315#define MFI_PASS_FRAME_SIZE 48 316struct mfi_pass_frame { 317 struct mfi_frame_header header; 318 uint32_t sense_addr_lo; 319 uint32_t sense_addr_hi; 320 uint8_t cdb[16]; 321 union mfi_sgl sgl; 322} __packed; 323 324#define MFI_DCMD_FRAME_SIZE 40 325struct mfi_dcmd_frame { 326 struct mfi_frame_header header; 327 uint32_t opcode; 328 uint8_t mbox[MFI_MBOX_SIZE]; 329 union mfi_sgl sgl; 330} __packed; 331 332struct mfi_abort_frame { 333 struct mfi_frame_header header; 334 uint32_t abort_context; 335 uint32_t pad; 336 uint32_t abort_mfi_addr_lo; 337 uint32_t abort_mfi_addr_hi; 338 uint32_t reserved[6]; 339} __packed; 340 341struct mfi_smp_frame { 342 struct mfi_frame_header header; 343 uint64_t sas_addr; 344 union { 345 struct mfi_sg32 sg32[2]; 346 struct mfi_sg64 sg64[2]; 347 } sgl; 348} __packed; 349 350struct mfi_stp_frame { 351 struct mfi_frame_header header; 352 uint16_t fis[10]; 353 uint32_t stp_flags; 354 union { 355 struct mfi_sg32 sg32[2]; 356 struct mfi_sg64 sg64[2]; 357 } sgl; 358} __packed; 359 360union mfi_frame { 361 struct mfi_frame_header header; 362 struct mfi_init_frame init; 363 struct mfi_io_frame io; 364 struct mfi_pass_frame pass; 365 struct mfi_dcmd_frame dcmd; 366 struct mfi_abort_frame abort; 367 struct mfi_smp_frame smp; 368 struct mfi_stp_frame stp; 369 uint8_t bytes[MFI_FRAME_SIZE]; 370}; 371 372#define MFI_SENSE_LEN 128 373struct mfi_sense { 374 uint8_t data[MFI_SENSE_LEN]; 375}; 376 377/* The queue init structure that is passed with the init message */ 378struct mfi_init_qinfo { 379 uint32_t flags; 380 uint32_t rq_entries; 381 uint32_t rq_addr_lo; 382 uint32_t rq_addr_hi; 383 uint32_t pi_addr_lo; 384 uint32_t pi_addr_hi; 385 uint32_t ci_addr_lo; 386 uint32_t ci_addr_hi; 387} __packed; 388 389/* SAS (?) controller properties, part of mfi_ctrl_info */ 390struct mfi_ctrl_props { 391 uint16_t seq_num; 392 uint16_t pred_fail_poll_interval; 393 uint16_t intr_throttle_cnt; 394 uint16_t intr_throttle_timeout; 395 uint8_t rebuild_rate; 396 uint8_t patrol_read_rate; 397 uint8_t bgi_rate; 398 uint8_t cc_rate; 399 uint8_t recon_rate; 400 uint8_t cache_flush_interval; 401 uint8_t spinup_drv_cnt; 402 uint8_t spinup_delay; 403 uint8_t cluster_enable; 404 uint8_t coercion_mode; 405 uint8_t alarm_enable; 406 uint8_t disable_auto_rebuild; 407 uint8_t disable_battery_warn; 408 uint8_t ecc_bucket_size; 409 uint16_t ecc_bucket_leak_rate; 410 uint8_t restore_hotspare_on_insertion; 411 uint8_t expose_encl_devices; 412 uint8_t reserved[38]; 413} __packed; 414 415/* PCI information about the card. */ 416struct mfi_info_pci { 417 uint16_t vendor; 418 uint16_t device; 419 uint16_t subvendor; 420 uint16_t subdevice; 421 uint8_t reserved[24]; 422} __packed; 423 424/* Host (front end) interface information */ 425struct mfi_info_host { 426 uint8_t type; 427#define MFI_INFO_HOST_PCIX 0x01 428#define MFI_INFO_HOST_PCIE 0x02 429#define MFI_INFO_HOST_ISCSI 0x04 430#define MFI_INFO_HOST_SAS3G 0x08 431 uint8_t reserved[6]; 432 uint8_t port_count; 433 uint64_t port_addr[8]; 434} __packed; 435 436/* Device (back end) interface information */ 437struct mfi_info_device { 438 uint8_t type; 439#define MFI_INFO_DEV_SPI 0x01 440#define MFI_INFO_DEV_SAS3G 0x02 441#define MFI_INFO_DEV_SATA1 0x04 442#define MFI_INFO_DEV_SATA3G 0x08 443 uint8_t reserved[6]; 444 uint8_t port_count; 445 uint64_t port_addr[8]; 446} __packed; 447 448/* Firmware component information */ 449struct mfi_info_component { 450 char name[8]; 451 char version[32]; 452 char build_date[16]; 453 char build_time[16]; 454} __packed; 455 456 457/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 458struct mfi_ctrl_info { 459 struct mfi_info_pci pci; 460 struct mfi_info_host host; 461 struct mfi_info_device device; 462 463 /* Firmware components that are present and active. */ 464 uint32_t image_check_word; 465 uint32_t image_component_count; 466 struct mfi_info_component image_component[8]; 467 468 /* Firmware components that have been flashed but are inactive */ 469 uint32_t pending_image_component_count; 470 struct mfi_info_component pending_image_component[8]; 471 472 uint8_t max_arms; 473 uint8_t max_spans; 474 uint8_t max_arrays; 475 uint8_t max_lds; 476 char product_name[80]; 477 char serial_number[32]; 478 uint32_t hw_present; 479#define MFI_INFO_HW_BBU 0x01 480#define MFI_INFO_HW_ALARM 0x02 481#define MFI_INFO_HW_NVRAM 0x04 482#define MFI_INFO_HW_UART 0x08 483 uint32_t current_fw_time; 484 uint16_t max_cmds; 485 uint16_t max_sg_elements; 486 uint32_t max_request_size; 487 uint16_t lds_present; 488 uint16_t lds_degraded; 489 uint16_t lds_offline; 490 uint16_t pd_present; 491 uint16_t pd_disks_present; 492 uint16_t pd_disks_pred_failure; 493 uint16_t pd_disks_failed; 494 uint16_t nvram_size; 495 uint16_t memory_size; 496 uint16_t flash_size; 497 uint16_t ram_correctable_errors; 498 uint16_t ram_uncorrectable_errors; 499 uint8_t cluster_allowed; 500 uint8_t cluster_active; 501 uint16_t max_strips_per_io; 502 503 uint32_t raid_levels; 504#define MFI_INFO_RAID_0 0x01 505#define MFI_INFO_RAID_1 0x02 506#define MFI_INFO_RAID_5 0x04 507#define MFI_INFO_RAID_1E 0x08 508#define MFI_INFO_RAID_6 0x10 509 510 uint32_t adapter_ops; 511#define MFI_INFO_AOPS_RBLD_RATE 0x0001 512#define MFI_INFO_AOPS_CC_RATE 0x0002 513#define MFI_INFO_AOPS_BGI_RATE 0x0004 514#define MFI_INFO_AOPS_RECON_RATE 0x0008 515#define MFI_INFO_AOPS_PATROL_RATE 0x0010 516#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 517#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 518#define MFI_INFO_AOPS_BBU 0x0080 519#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 520#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 521#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 522#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 523#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 524#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 525#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 526 527 uint32_t ld_ops; 528#define MFI_INFO_LDOPS_READ_POLICY 0x01 529#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 530#define MFI_INFO_LDOPS_IO_POLICY 0x04 531#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 532#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 533 534 struct { 535 uint8_t min; 536 uint8_t max; 537 uint8_t reserved[2]; 538 } __packed stripe_sz_ops; 539 540 uint32_t pd_ops; 541#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 542#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 543#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 544 545 uint32_t pd_mix_support; 546#define MFI_INFO_PDMIX_SAS 0x01 547#define MFI_INFO_PDMIX_SATA 0x02 548#define MFI_INFO_PDMIX_ENCL 0x04 549#define MFI_INFO_PDMIX_LD 0x08 550#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 551 552 uint8_t ecc_bucket_count; 553 uint8_t reserved2[11]; 554 struct mfi_ctrl_props properties; 555 char package_version[0x60]; 556 uint8_t pad[0x800 - 0x6a0]; 557} __packed; 558 559/* keep track of an event. */ 560union mfi_evt { 561 struct { 562 uint16_t locale; 563 uint8_t reserved; 564 uint8_t class; 565 } members; 566 uint32_t word; 567} __packed; 568 569/* event log state. */ 570struct mfi_evt_log_state { 571 uint32_t newest_seq_num; 572 uint32_t oldest_seq_num; 573 uint32_t clear_seq_num; 574 uint32_t shutdown_seq_num; 575 uint32_t boot_seq_num; 576} __packed; 577 578struct mfi_progress { 579 uint16_t progress; 580 uint16_t elapsed_seconds; 581} __packed; 582 583struct mfi_evt_ld { 584 uint16_t target_id; 585 uint8_t ld_index; 586 uint8_t reserved; 587} __packed; 588 589struct mfi_evt_pd { 590 uint16_t device_id; 591 uint8_t enclosure_index; 592 uint8_t slot_number; 593} __packed; 594 595/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 596struct mfi_evt_detail { 597 uint32_t seq; 598 uint32_t time; 599 uint32_t code; 600 union mfi_evt class; 601 uint8_t arg_type; 602 uint8_t reserved1[15]; 603 604 union { 605 struct { 606 struct mfi_evt_pd pd; 607 uint8_t cdb_len; 608 uint8_t sense_len; 609 uint8_t reserved[2]; 610 uint8_t cdb[16]; 611 uint8_t sense[64]; 612 } cdb_sense; 613 614 struct mfi_evt_ld ld; 615 616 struct { 617 struct mfi_evt_ld ld; 618 uint64_t count; 619 } ld_count; 620 621 struct { 622 uint64_t lba; 623 struct mfi_evt_ld ld; 624 } ld_lba; 625 626 struct { 627 struct mfi_evt_ld ld; 628 uint32_t pre_owner; 629 uint32_t new_owner; 630 } ld_owner; 631 632 struct { 633 uint64_t ld_lba; 634 uint64_t pd_lba; 635 struct mfi_evt_ld ld; 636 struct mfi_evt_pd pd; 637 } ld_lba_pd_lba; 638 639 struct { 640 struct mfi_evt_ld ld; 641 struct mfi_progress prog; 642 } ld_prog; 643 644 struct { 645 struct mfi_evt_ld ld; 646 uint32_t prev_state; 647 uint32_t new_state; 648 } ld_state; 649 650 struct { 651 uint64_t strip; 652 struct mfi_evt_ld ld; 653 } ld_strip; 654 655 struct mfi_evt_pd pd; 656 657 struct { 658 struct mfi_evt_pd pd; 659 uint32_t err; 660 } pd_err; 661 662 struct { 663 uint64_t lba; 664 struct mfi_evt_pd pd; 665 } pd_lba; 666 667 struct { 668 uint64_t lba; 669 struct mfi_evt_pd pd; 670 struct mfi_evt_ld ld; 671 } pd_lba_ld; 672 673 struct { 674 struct mfi_evt_pd pd; 675 struct mfi_progress prog; 676 } pd_prog; 677 678 struct { 679 struct mfi_evt_pd ld; 680 uint32_t prev_state; 681 uint32_t new_state; 682 } pd_state; 683 684 struct { 685 uint16_t venderId; 686 uint16_t deviceId; 687 uint16_t subVenderId; 688 uint16_t subDeviceId; 689 } pci; 690 691 uint32_t rate; 692 693 char str[96]; 694 695 struct { 696 uint32_t rtc; 697 uint16_t elapsedSeconds; 698 } time; 699 700 struct { 701 uint32_t ecar; 702 uint32_t elog; 703 char str[64]; 704 } ecc; 705 706 uint8_t b[96]; 707 uint16_t s[48]; 708 uint32_t w[24]; 709 uint64_t d[12]; 710 } args; 711 712 char description[128]; 713} __packed; 714 715/* SAS log detail guessed at */ 716struct mfi_log_detail { 717 uint32_t something1; 718 uint32_t something2; 719 uint32_t seq; 720 uint32_t something3; 721 uint32_t arg_type; 722 uint8_t reserved1[15]; 723 724 union { 725 uint8_t b[96]; 726 } args; 727 char description[128]; 728} __packed; 729 730#endif /* _MFIREG_H */ 731