mfireg.h revision 171821
1/*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#ifndef _MFIREG_H 28#define _MFIREG_H 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/mfi/mfireg.h 171821 2007-08-13 19:29:17Z jhb $"); 32 33/* 34 * MegaRAID SAS MFI firmware definitions 35 * 36 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 37 * new firmware interface from the old AMI MegaRAID one, and there is no 38 * reason why this interface should be limited to just SAS. In any case, LSI 39 * seems to also call this interface 'MFI', so that will be used here. 40 */ 41 42/* 43 * Start with the register set. All registers are 32 bits wide. 44 * The usual Intel IOP style setup. 45 */ 46#define MFI_IMSG0 0x10 /* Inbound message 0 */ 47#define MFI_IMSG1 0x14 /* Inbound message 1 */ 48#define MFI_OMSG0 0x18 /* Outbound message 0 */ 49#define MFI_OMSG1 0x1c /* Outbound message 1 */ 50#define MFI_IDB 0x20 /* Inbound doorbell */ 51#define MFI_ISTS 0x24 /* Inbound interrupt status */ 52#define MFI_IMSK 0x28 /* Inbound interrupt mask */ 53#define MFI_ODB 0x2c /* Outbound doorbell */ 54#define MFI_OSTS 0x30 /* Outbound interrupt status */ 55#define MFI_OMSK 0x34 /* Outbound interrupt mask */ 56#define MFI_IQP 0x40 /* Inbound queue port */ 57#define MFI_OQP 0x44 /* Outbound queue port */ 58 59/* Bits for MFI_OSTS */ 60#define MFI_OSTS_INTR_VALID 0x00000002 61 62/* 63 * Firmware state values. Found in OMSG0 during initialization. 64 */ 65#define MFI_FWSTATE_MASK 0xf0000000 66#define MFI_FWSTATE_UNDEFINED 0x00000000 67#define MFI_FWSTATE_BB_INIT 0x10000000 68#define MFI_FWSTATE_FW_INIT 0x40000000 69#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 70#define MFI_FWSTATE_FW_INIT_2 0x70000000 71#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 72#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 73#define MFI_FWSTATE_READY 0xb0000000 74#define MFI_FWSTATE_OPERATIONAL 0xc0000000 75#define MFI_FWSTATE_FAULT 0xf0000000 76#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 77#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 78 79/* 80 * Control bits to drive the card to ready state. These go into the IDB 81 * register. 82 */ 83#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 84#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 85#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 86#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 87 88/* MFI Commands */ 89typedef enum { 90 MFI_CMD_INIT = 0x00, 91 MFI_CMD_LD_READ, 92 MFI_CMD_LD_WRITE, 93 MFI_CMD_LD_SCSI_IO, 94 MFI_CMD_PD_SCSI_IO, 95 MFI_CMD_DCMD, 96 MFI_CMD_ABORT, 97 MFI_CMD_SMP, 98 MFI_CMD_STP 99} mfi_cmd_t; 100 101/* Direct commands */ 102typedef enum { 103 MFI_DCMD_CTRL_GETINFO = 0x01010000, 104 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 105 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 106 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 107 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 108 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 109 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 110 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 111 MFI_DCMD_LD_GET_LIST = 0x03010000, 112 MFI_DCMD_LD_GET_INFO = 0x03020000, 113 MFI_DCMD_LD_GET_PROP = 0x03030000, 114 MFI_DCMD_LD_SET_PROP = 0x03040000, 115 MFI_DCMD_LD_DELETE = 0x03090000, 116 MFI_DCMD_CFG_READ = 0x04010000, 117 MFI_DCMD_CFG_ADD = 0x04020000, 118 MFI_DCMD_CFG_CLEAR = 0x04030000, 119 MFI_DCMD_CLUSTER = 0x08000000, 120 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 121 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 122} mfi_dcmd_t; 123 124/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 125#define MFI_FLUSHCACHE_CTRL 0x01 126#define MFI_FLUSHCACHE_DISK 0x02 127 128/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 129#define MFI_SHUTDOWN_SPINDOWN 0x01 130 131/* 132 * MFI Frame flags 133 */ 134#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 135#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 136#define MFI_FRAME_SGL32 0x0000 137#define MFI_FRAME_SGL64 0x0002 138#define MFI_FRAME_SENSE32 0x0000 139#define MFI_FRAME_SENSE64 0x0004 140#define MFI_FRAME_DIR_NONE 0x0000 141#define MFI_FRAME_DIR_WRITE 0x0008 142#define MFI_FRAME_DIR_READ 0x0010 143#define MFI_FRAME_DIR_BOTH 0x0018 144 145/* MFI Status codes */ 146typedef enum { 147 MFI_STAT_OK = 0x00, 148 MFI_STAT_INVALID_CMD, 149 MFI_STAT_INVALID_DCMD, 150 MFI_STAT_INVALID_PARAMETER, 151 MFI_STAT_INVALID_SEQUENCE_NUMBER, 152 MFI_STAT_ABORT_NOT_POSSIBLE, 153 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 154 MFI_STAT_APP_IN_USE, 155 MFI_STAT_APP_NOT_INITIALIZED, 156 MFI_STAT_ARRAY_INDEX_INVALID, 157 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 158 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 159 MFI_STAT_DEVICE_NOT_FOUND, 160 MFI_STAT_DRIVE_TOO_SMALL, 161 MFI_STAT_FLASH_ALLOC_FAIL, 162 MFI_STAT_FLASH_BUSY, 163 MFI_STAT_FLASH_ERROR = 0x10, 164 MFI_STAT_FLASH_IMAGE_BAD, 165 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 166 MFI_STAT_FLASH_NOT_OPEN, 167 MFI_STAT_FLASH_NOT_STARTED, 168 MFI_STAT_FLUSH_FAILED, 169 MFI_STAT_HOST_CODE_NOT_FOUNT, 170 MFI_STAT_LD_CC_IN_PROGRESS, 171 MFI_STAT_LD_INIT_IN_PROGRESS, 172 MFI_STAT_LD_LBA_OUT_OF_RANGE, 173 MFI_STAT_LD_MAX_CONFIGURED, 174 MFI_STAT_LD_NOT_OPTIMAL, 175 MFI_STAT_LD_RBLD_IN_PROGRESS, 176 MFI_STAT_LD_RECON_IN_PROGRESS, 177 MFI_STAT_LD_WRONG_RAID_LEVEL, 178 MFI_STAT_MAX_SPARES_EXCEEDED, 179 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 180 MFI_STAT_MFC_HW_ERROR, 181 MFI_STAT_NO_HW_PRESENT, 182 MFI_STAT_NOT_FOUND, 183 MFI_STAT_NOT_IN_ENCL, 184 MFI_STAT_PD_CLEAR_IN_PROGRESS, 185 MFI_STAT_PD_TYPE_WRONG, 186 MFI_STAT_PR_DISABLED, 187 MFI_STAT_ROW_INDEX_INVALID, 188 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 189 MFI_STAT_SAS_CONFIG_INVALID_DATA, 190 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 191 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 192 MFI_STAT_SCSI_DONE_WITH_ERROR, 193 MFI_STAT_SCSI_IO_FAILED, 194 MFI_STAT_SCSI_RESERVATION_CONFLICT, 195 MFI_STAT_SHUTDOWN_FAILED = 0x30, 196 MFI_STAT_TIME_NOT_SET, 197 MFI_STAT_WRONG_STATE, 198 MFI_STAT_LD_OFFLINE, 199 MFI_STAT_PEER_NOTIFICATION_REJECTED, 200 MFI_STAT_PEER_NOTIFICATION_FAILED, 201 MFI_STAT_RESERVATION_IN_PROGRESS, 202 MFI_STAT_I2C_ERRORS_DETECTED, 203 MFI_STAT_PCI_ERRORS_DETECTED, 204 MFI_STAT_INVALID_STATUS = 0xFF 205} mfi_status_t; 206 207typedef enum { 208 MFI_EVT_CLASS_DEBUG = -2, 209 MFI_EVT_CLASS_PROGRESS = -1, 210 MFI_EVT_CLASS_INFO = 0, 211 MFI_EVT_CLASS_WARNING = 1, 212 MFI_EVT_CLASS_CRITICAL = 2, 213 MFI_EVT_CLASS_FATAL = 3, 214 MFI_EVT_CLASS_DEAD = 4 215} mfi_evt_class_t; 216 217typedef enum { 218 MFI_EVT_LOCALE_LD = 0x0001, 219 MFI_EVT_LOCALE_PD = 0x0002, 220 MFI_EVT_LOCALE_ENCL = 0x0004, 221 MFI_EVT_LOCALE_BBU = 0x0008, 222 MFI_EVT_LOCALE_SAS = 0x0010, 223 MFI_EVT_LOCALE_CTRL = 0x0020, 224 MFI_EVT_LOCALE_CONFIG = 0x0040, 225 MFI_EVT_LOCALE_CLUSTER = 0x0080, 226 MFI_EVT_LOCALE_ALL = 0xffff 227} mfi_evt_locale_t; 228 229typedef enum { 230 MR_EVT_ARGS_NONE = 0x00, 231 MR_EVT_ARGS_CDB_SENSE, 232 MR_EVT_ARGS_LD, 233 MR_EVT_ARGS_LD_COUNT, 234 MR_EVT_ARGS_LD_LBA, 235 MR_EVT_ARGS_LD_OWNER, 236 MR_EVT_ARGS_LD_LBA_PD_LBA, 237 MR_EVT_ARGS_LD_PROG, 238 MR_EVT_ARGS_LD_STATE, 239 MR_EVT_ARGS_LD_STRIP, 240 MR_EVT_ARGS_PD, 241 MR_EVT_ARGS_PD_ERR, 242 MR_EVT_ARGS_PD_LBA, 243 MR_EVT_ARGS_PD_LBA_LD, 244 MR_EVT_ARGS_PD_PROG, 245 MR_EVT_ARGS_PD_STATE, 246 MR_EVT_ARGS_PCI, 247 MR_EVT_ARGS_RATE, 248 MR_EVT_ARGS_STR, 249 MR_EVT_ARGS_TIME, 250 MR_EVT_ARGS_ECC 251} mfi_evt_args; 252 253typedef enum { 254 MR_LD_CACHE_WRITE_BACK = 0x01, 255 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 256 MR_LD_CACHE_READ_AHEAD = 0x04, 257 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 258 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 259 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 260 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 261} mfi_ld_cache; 262 263typedef enum { 264 MR_PD_CACHE_UNCHANGED = 0, 265 MR_PD_CACHE_ENABLE = 1, 266 MR_PD_CACHE_DISABLE = 2 267} mfi_pd_cache; 268 269/* 270 * Other propertities and definitions 271 */ 272#define MFI_MAX_PD_CHANNELS 2 273#define MFI_MAX_LD_CHANNELS 2 274#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 275#define MFI_MAX_CHANNEL_DEVS 128 276#define MFI_DEFAULT_ID -1 277#define MFI_MAX_LUN 8 278#define MFI_MAX_LD 64 279 280#define MFI_FRAME_SIZE 64 281#define MFI_MBOX_SIZE 12 282 283/* Firmware flashing can take 40s */ 284#define MFI_POLL_TIMEOUT_SECS 50 285 286/* Allow for speedier math calculations */ 287#define MFI_SECTOR_LEN 512 288 289/* Scatter Gather elements */ 290struct mfi_sg32 { 291 uint32_t addr; 292 uint32_t len; 293} __packed; 294 295struct mfi_sg64 { 296 uint64_t addr; 297 uint32_t len; 298} __packed; 299 300union mfi_sgl { 301 struct mfi_sg32 sg32[1]; 302 struct mfi_sg64 sg64[1]; 303} __packed; 304 305/* Message frames. All messages have a common header */ 306struct mfi_frame_header { 307 uint8_t cmd; 308 uint8_t sense_len; 309 uint8_t cmd_status; 310 uint8_t scsi_status; 311 uint8_t target_id; 312 uint8_t lun_id; 313 uint8_t cdb_len; 314 uint8_t sg_count; 315 uint32_t context; 316 uint32_t pad0; 317 uint16_t flags; 318 uint16_t timeout; 319 uint32_t data_len; 320} __packed; 321 322struct mfi_init_frame { 323 struct mfi_frame_header header; 324 uint32_t qinfo_new_addr_lo; 325 uint32_t qinfo_new_addr_hi; 326 uint32_t qinfo_old_addr_lo; 327 uint32_t qinfo_old_addr_hi; 328 uint32_t reserved[6]; 329} __packed; 330 331#define MFI_IO_FRAME_SIZE 40 332struct mfi_io_frame { 333 struct mfi_frame_header header; 334 uint32_t sense_addr_lo; 335 uint32_t sense_addr_hi; 336 uint32_t lba_lo; 337 uint32_t lba_hi; 338 union mfi_sgl sgl; 339} __packed; 340 341#define MFI_PASS_FRAME_SIZE 48 342struct mfi_pass_frame { 343 struct mfi_frame_header header; 344 uint32_t sense_addr_lo; 345 uint32_t sense_addr_hi; 346 uint8_t cdb[16]; 347 union mfi_sgl sgl; 348} __packed; 349 350#define MFI_DCMD_FRAME_SIZE 40 351struct mfi_dcmd_frame { 352 struct mfi_frame_header header; 353 uint32_t opcode; 354 uint8_t mbox[MFI_MBOX_SIZE]; 355 union mfi_sgl sgl; 356} __packed; 357 358struct mfi_abort_frame { 359 struct mfi_frame_header header; 360 uint32_t abort_context; 361 uint32_t pad; 362 uint32_t abort_mfi_addr_lo; 363 uint32_t abort_mfi_addr_hi; 364 uint32_t reserved[6]; 365} __packed; 366 367struct mfi_smp_frame { 368 struct mfi_frame_header header; 369 uint64_t sas_addr; 370 union { 371 struct mfi_sg32 sg32[2]; 372 struct mfi_sg64 sg64[2]; 373 } sgl; 374} __packed; 375 376struct mfi_stp_frame { 377 struct mfi_frame_header header; 378 uint16_t fis[10]; 379 uint32_t stp_flags; 380 union { 381 struct mfi_sg32 sg32[2]; 382 struct mfi_sg64 sg64[2]; 383 } sgl; 384} __packed; 385 386union mfi_frame { 387 struct mfi_frame_header header; 388 struct mfi_init_frame init; 389 struct mfi_io_frame io; 390 struct mfi_pass_frame pass; 391 struct mfi_dcmd_frame dcmd; 392 struct mfi_abort_frame abort; 393 struct mfi_smp_frame smp; 394 struct mfi_stp_frame stp; 395 uint8_t bytes[MFI_FRAME_SIZE]; 396}; 397 398#define MFI_SENSE_LEN 128 399struct mfi_sense { 400 uint8_t data[MFI_SENSE_LEN]; 401}; 402 403/* The queue init structure that is passed with the init message */ 404struct mfi_init_qinfo { 405 uint32_t flags; 406 uint32_t rq_entries; 407 uint32_t rq_addr_lo; 408 uint32_t rq_addr_hi; 409 uint32_t pi_addr_lo; 410 uint32_t pi_addr_hi; 411 uint32_t ci_addr_lo; 412 uint32_t ci_addr_hi; 413} __packed; 414 415/* SAS (?) controller properties, part of mfi_ctrl_info */ 416struct mfi_ctrl_props { 417 uint16_t seq_num; 418 uint16_t pred_fail_poll_interval; 419 uint16_t intr_throttle_cnt; 420 uint16_t intr_throttle_timeout; 421 uint8_t rebuild_rate; 422 uint8_t patrol_read_rate; 423 uint8_t bgi_rate; 424 uint8_t cc_rate; 425 uint8_t recon_rate; 426 uint8_t cache_flush_interval; 427 uint8_t spinup_drv_cnt; 428 uint8_t spinup_delay; 429 uint8_t cluster_enable; 430 uint8_t coercion_mode; 431 uint8_t alarm_enable; 432 uint8_t disable_auto_rebuild; 433 uint8_t disable_battery_warn; 434 uint8_t ecc_bucket_size; 435 uint16_t ecc_bucket_leak_rate; 436 uint8_t restore_hotspare_on_insertion; 437 uint8_t expose_encl_devices; 438 uint8_t reserved[38]; 439} __packed; 440 441/* PCI information about the card. */ 442struct mfi_info_pci { 443 uint16_t vendor; 444 uint16_t device; 445 uint16_t subvendor; 446 uint16_t subdevice; 447 uint8_t reserved[24]; 448} __packed; 449 450/* Host (front end) interface information */ 451struct mfi_info_host { 452 uint8_t type; 453#define MFI_INFO_HOST_PCIX 0x01 454#define MFI_INFO_HOST_PCIE 0x02 455#define MFI_INFO_HOST_ISCSI 0x04 456#define MFI_INFO_HOST_SAS3G 0x08 457 uint8_t reserved[6]; 458 uint8_t port_count; 459 uint64_t port_addr[8]; 460} __packed; 461 462/* Device (back end) interface information */ 463struct mfi_info_device { 464 uint8_t type; 465#define MFI_INFO_DEV_SPI 0x01 466#define MFI_INFO_DEV_SAS3G 0x02 467#define MFI_INFO_DEV_SATA1 0x04 468#define MFI_INFO_DEV_SATA3G 0x08 469 uint8_t reserved[6]; 470 uint8_t port_count; 471 uint64_t port_addr[8]; 472} __packed; 473 474/* Firmware component information */ 475struct mfi_info_component { 476 char name[8]; 477 char version[32]; 478 char build_date[16]; 479 char build_time[16]; 480} __packed; 481 482/* Controller default settings */ 483struct mfi_defaults { 484 uint64_t sas_addr; 485 uint8_t phy_polarity; 486 uint8_t background_rate; 487 uint8_t stripe_size; 488 uint8_t flush_time; 489 uint8_t write_back; 490 uint8_t read_ahead; 491 uint8_t cache_when_bbu_bad; 492 uint8_t cached_io; 493 uint8_t smart_mode; 494 uint8_t alarm_disable; 495 uint8_t coercion; 496 uint8_t zrc_config; 497 uint8_t dirty_led_shows_drive_activity; 498 uint8_t bios_continue_on_error; 499 uint8_t spindown_mode; 500 uint8_t allowed_device_types; 501 uint8_t allow_mix_in_enclosure; 502 uint8_t allow_mix_in_ld; 503 uint8_t allow_sata_in_cluster; 504 uint8_t max_chained_enclosures; 505 uint8_t disable_ctrl_r; 506 uint8_t enabel_web_bios; 507 uint8_t phy_polarity_split; 508 uint8_t direct_pd_mapping; 509 uint8_t bios_enumerate_lds; 510 uint8_t restored_hot_spare_on_insertion; 511 uint8_t expose_enclosure_devices; 512 uint8_t maintain_pd_fail_history; 513 uint8_t resv[28]; 514} __packed; 515 516/* Controller default settings */ 517struct mfi_bios_data { 518 uint16_t boot_target_id; 519 uint8_t do_not_int_13; 520 uint8_t continue_on_error; 521 uint8_t verbose; 522 uint8_t geometry; 523 uint8_t expose_all_drives; 524 uint8_t reserved[56]; 525 uint8_t check_sum; 526} __packed; 527 528/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 529struct mfi_ctrl_info { 530 struct mfi_info_pci pci; 531 struct mfi_info_host host; 532 struct mfi_info_device device; 533 534 /* Firmware components that are present and active. */ 535 uint32_t image_check_word; 536 uint32_t image_component_count; 537 struct mfi_info_component image_component[8]; 538 539 /* Firmware components that have been flashed but are inactive */ 540 uint32_t pending_image_component_count; 541 struct mfi_info_component pending_image_component[8]; 542 543 uint8_t max_arms; 544 uint8_t max_spans; 545 uint8_t max_arrays; 546 uint8_t max_lds; 547 char product_name[80]; 548 char serial_number[32]; 549 uint32_t hw_present; 550#define MFI_INFO_HW_BBU 0x01 551#define MFI_INFO_HW_ALARM 0x02 552#define MFI_INFO_HW_NVRAM 0x04 553#define MFI_INFO_HW_UART 0x08 554 uint32_t current_fw_time; 555 uint16_t max_cmds; 556 uint16_t max_sg_elements; 557 uint32_t max_request_size; 558 uint16_t lds_present; 559 uint16_t lds_degraded; 560 uint16_t lds_offline; 561 uint16_t pd_present; 562 uint16_t pd_disks_present; 563 uint16_t pd_disks_pred_failure; 564 uint16_t pd_disks_failed; 565 uint16_t nvram_size; 566 uint16_t memory_size; 567 uint16_t flash_size; 568 uint16_t ram_correctable_errors; 569 uint16_t ram_uncorrectable_errors; 570 uint8_t cluster_allowed; 571 uint8_t cluster_active; 572 uint16_t max_strips_per_io; 573 574 uint32_t raid_levels; 575#define MFI_INFO_RAID_0 0x01 576#define MFI_INFO_RAID_1 0x02 577#define MFI_INFO_RAID_5 0x04 578#define MFI_INFO_RAID_1E 0x08 579#define MFI_INFO_RAID_6 0x10 580 581 uint32_t adapter_ops; 582#define MFI_INFO_AOPS_RBLD_RATE 0x0001 583#define MFI_INFO_AOPS_CC_RATE 0x0002 584#define MFI_INFO_AOPS_BGI_RATE 0x0004 585#define MFI_INFO_AOPS_RECON_RATE 0x0008 586#define MFI_INFO_AOPS_PATROL_RATE 0x0010 587#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 588#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 589#define MFI_INFO_AOPS_BBU 0x0080 590#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 591#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 592#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 593#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 594#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 595#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 596#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 597 598 uint32_t ld_ops; 599#define MFI_INFO_LDOPS_READ_POLICY 0x01 600#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 601#define MFI_INFO_LDOPS_IO_POLICY 0x04 602#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 603#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 604 605 struct { 606 uint8_t min; 607 uint8_t max; 608 uint8_t reserved[2]; 609 } __packed stripe_sz_ops; 610 611 uint32_t pd_ops; 612#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 613#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 614#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 615 616 uint32_t pd_mix_support; 617#define MFI_INFO_PDMIX_SAS 0x01 618#define MFI_INFO_PDMIX_SATA 0x02 619#define MFI_INFO_PDMIX_ENCL 0x04 620#define MFI_INFO_PDMIX_LD 0x08 621#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 622 623 uint8_t ecc_bucket_count; 624 uint8_t reserved2[11]; 625 struct mfi_ctrl_props properties; 626 char package_version[0x60]; 627 uint8_t pad[0x800 - 0x6a0]; 628} __packed; 629 630/* keep track of an event. */ 631union mfi_evt { 632 struct { 633 uint16_t locale; 634 uint8_t reserved; 635 int8_t class; 636 } members; 637 uint32_t word; 638} __packed; 639 640/* event log state. */ 641struct mfi_evt_log_state { 642 uint32_t newest_seq_num; 643 uint32_t oldest_seq_num; 644 uint32_t clear_seq_num; 645 uint32_t shutdown_seq_num; 646 uint32_t boot_seq_num; 647} __packed; 648 649struct mfi_progress { 650 uint16_t progress; 651 uint16_t elapsed_seconds; 652} __packed; 653 654struct mfi_evt_ld { 655 uint16_t target_id; 656 uint8_t ld_index; 657 uint8_t reserved; 658} __packed; 659 660struct mfi_evt_pd { 661 uint16_t device_id; 662 uint8_t enclosure_index; 663 uint8_t slot_number; 664} __packed; 665 666/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 667struct mfi_evt_detail { 668 uint32_t seq; 669 uint32_t time; 670 uint32_t code; 671 union mfi_evt class; 672 uint8_t arg_type; 673 uint8_t reserved1[15]; 674 675 union { 676 struct { 677 struct mfi_evt_pd pd; 678 uint8_t cdb_len; 679 uint8_t sense_len; 680 uint8_t reserved[2]; 681 uint8_t cdb[16]; 682 uint8_t sense[64]; 683 } cdb_sense; 684 685 struct mfi_evt_ld ld; 686 687 struct { 688 struct mfi_evt_ld ld; 689 uint64_t count; 690 } ld_count; 691 692 struct { 693 uint64_t lba; 694 struct mfi_evt_ld ld; 695 } ld_lba; 696 697 struct { 698 struct mfi_evt_ld ld; 699 uint32_t pre_owner; 700 uint32_t new_owner; 701 } ld_owner; 702 703 struct { 704 uint64_t ld_lba; 705 uint64_t pd_lba; 706 struct mfi_evt_ld ld; 707 struct mfi_evt_pd pd; 708 } ld_lba_pd_lba; 709 710 struct { 711 struct mfi_evt_ld ld; 712 struct mfi_progress prog; 713 } ld_prog; 714 715 struct { 716 struct mfi_evt_ld ld; 717 uint32_t prev_state; 718 uint32_t new_state; 719 } ld_state; 720 721 struct { 722 uint64_t strip; 723 struct mfi_evt_ld ld; 724 } ld_strip; 725 726 struct mfi_evt_pd pd; 727 728 struct { 729 struct mfi_evt_pd pd; 730 uint32_t err; 731 } pd_err; 732 733 struct { 734 uint64_t lba; 735 struct mfi_evt_pd pd; 736 } pd_lba; 737 738 struct { 739 uint64_t lba; 740 struct mfi_evt_pd pd; 741 struct mfi_evt_ld ld; 742 } pd_lba_ld; 743 744 struct { 745 struct mfi_evt_pd pd; 746 struct mfi_progress prog; 747 } pd_prog; 748 749 struct { 750 struct mfi_evt_pd ld; 751 uint32_t prev_state; 752 uint32_t new_state; 753 } pd_state; 754 755 struct { 756 uint16_t venderId; 757 uint16_t deviceId; 758 uint16_t subVenderId; 759 uint16_t subDeviceId; 760 } pci; 761 762 uint32_t rate; 763 764 char str[96]; 765 766 struct { 767 uint32_t rtc; 768 uint16_t elapsedSeconds; 769 } time; 770 771 struct { 772 uint32_t ecar; 773 uint32_t elog; 774 char str[64]; 775 } ecc; 776 777 uint8_t b[96]; 778 uint16_t s[48]; 779 uint32_t w[24]; 780 uint64_t d[12]; 781 } args; 782 783 char description[128]; 784} __packed; 785 786struct mfi_evt_list { 787 uint32_t count; 788 uint32_t reserved; 789 struct mfi_evt_detail event[1]; 790} __packed; 791 792union mfi_pd_ref { 793 struct { 794 uint16_t device_id; 795 uint16_t seq_num; 796 } v; 797 uint32_t ref; 798} __packed; 799 800union mfi_pd_ddf_type { 801 struct { 802 union { 803 struct { 804 uint16_t forced_pd_guid : 1; 805 uint16_t in_vd : 1; 806 uint16_t is_global_spare : 1; 807 uint16_t is_spare : 1; 808 uint16_t is_foreign : 1; 809 uint16_t reserved : 7; 810 uint16_t intf : 4; 811 } pd_type; 812 uint16_t type; 813 } v; 814 uint16_t reserved; 815 } ddf; 816 struct { 817 uint32_t reserved; 818 } non_disk; 819 uint32_t type; 820} __packed; 821 822struct mfi_pd_progress { 823 struct { 824 uint32_t rbld : 1; 825 uint32_t patrol : 1; 826 uint32_t clear : 1; 827 uint32_t reserved: 29; 828 } active; 829 struct mfi_progress rbld; 830 struct mfi_progress patrol; 831 struct mfi_progress clear; 832 struct mfi_progress reserved[4]; 833} __packed; 834 835struct mfi_pd_info { 836 union mfi_pd_ref ref; 837 uint8_t inquiry_data[96]; 838 uint8_t vpd_page83[64]; 839 uint8_t not_supported; 840 uint8_t scsi_dev_type; 841 uint8_t connected_port_bitmap; 842 uint8_t device_speed; 843 uint32_t media_err_count; 844 uint32_t other_err_count; 845 uint32_t pred_fail_count; 846 uint32_t last_pred_fail_event_seq_num; 847 uint16_t fw_state; 848 uint8_t disable_for_removal; 849 uint8_t link_speed; 850 union mfi_pd_ddf_type state; 851 struct { 852 uint8_t count; 853 uint8_t is_path_broken; 854 uint8_t reserved[6]; 855 uint64_t sas_addr[4]; 856 } path_info; 857 uint64_t raw_size; 858 uint64_t non_coerced_size; 859 uint64_t coerced_size; 860 uint16_t encl_device_id; 861 uint8_t encl_index; 862 uint8_t slot_number; 863 struct mfi_pd_progress prog_info; 864 uint8_t bad_block_table_full; 865 uint8_t unusable_in_current_config; 866 uint8_t vpd_page83_ext[64]; 867 uint8_t reserved[512-358]; 868} __packed; 869 870struct mfi_pd_address { 871 uint16_t device_id; 872 uint16_t encl_device_id; 873 uint8_t encl_index; 874 uint8_t slot_number; 875 uint8_t scsi_dev_type; 876 uint8_t connect_port_bitmap; 877 uint64_t sas_addr[2]; 878} __packed; 879 880struct mfi_pd_list { 881 uint32_t size; 882 uint32_t count; 883 uint8_t data; 884 /* 885 struct mfi_pd_address addr[]; 886 */ 887} __packed; 888 889union mfi_ld_ref { 890 struct { 891 uint8_t target_id; 892 uint8_t reserved; 893 uint16_t seq; 894 } v; 895 uint32_t ref; 896} __packed; 897 898struct mfi_ld_list { 899 uint32_t ld_count; 900 uint32_t reserved1; 901 struct { 902 union mfi_ld_ref ld; 903 uint8_t state; 904 uint8_t reserved2[3]; 905 uint64_t size; 906 } ld_list[MFI_MAX_LD]; 907} __packed; 908 909enum mfi_ld_access { 910 MFI_LD_ACCESS_RW = 0, 911 MFI_LD_ACCSSS_RO = 2, 912 MFI_LD_ACCESS_BLOCKED = 3, 913}; 914#define MFI_LD_ACCESS_MASK 3 915 916enum mfi_ld_state { 917 MFI_LD_STATE_OFFLINE = 0, 918 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 919 MFI_LD_STATE_DEGRADED = 2, 920 MFI_LD_STATE_OPTIMAL = 3 921}; 922 923struct mfi_ld_props { 924 union mfi_ld_ref ld; 925 char name[16]; 926 uint8_t default_cache_policy; 927 uint8_t access_policy; 928 uint8_t disk_cache_policy; 929 uint8_t current_cache_policy; 930 uint8_t no_bgi; 931 uint8_t reserved[7]; 932} __packed; 933 934struct mfi_ld_params { 935 uint8_t primary_raid_level; 936 uint8_t raid_level_qualifier; 937 uint8_t secondary_raid_level; 938 uint8_t stripe_size; 939 uint8_t num_drives; 940 uint8_t span_depth; 941 uint8_t state; 942 uint8_t init_state; 943 uint8_t is_consistent; 944 uint8_t reserved[23]; 945} __packed; 946 947struct mfi_ld_progress { 948 uint32_t active; 949#define MFI_LD_PROGRESS_CC (1<<0) 950#define MFI_LD_PROGRESS_BGI (1<<1) 951#define MFI_LD_PROGRESS_FGI (1<<2) 952#define MFI_LD_PORGRESS_RECON (1<<3) 953 struct mfi_progress cc; 954 struct mfi_progress bgi; 955 struct mfi_progress fgi; 956 struct mfi_progress recon; 957 struct mfi_progress reserved[4]; 958} __packed; 959 960struct mfi_span { 961 uint64_t start_block; 962 uint64_t num_blocks; 963 uint16_t array_ref; 964 uint8_t reserved[6]; 965} __packed; 966 967#define MFI_MAX_SPAN_DEPTH 8 968struct mfi_ld_config { 969 struct mfi_ld_props properties; 970 struct mfi_ld_params params; 971 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 972} __packed; 973 974struct mfi_ld_info { 975 struct mfi_ld_config ld_config; 976 uint64_t size; 977 struct mfi_ld_progress progress; 978 uint16_t cluster_owner; 979 uint8_t reconstruct_active; 980 uint8_t reserved1[1]; 981 uint8_t vpd_page83[64]; 982 uint8_t reserved2[16]; 983} __packed; 984 985union mfi_spare_type { 986 struct { 987 uint8_t is_dedicate :1; 988 uint8_t is_revertable :1; 989 uint8_t is_encl_affinity :1; 990 uint8_t reserved :5; 991 } v; 992 uint8_t type; 993} __packed; 994 995#define MAX_ARRAYS 16 996struct mfi_spare { 997 union mfi_pd_ref ref; 998 union mfi_spare_type spare_type; 999 uint8_t reserved[2]; 1000 uint8_t array_count; 1001 uint16_t array_refd[MAX_ARRAYS]; 1002} __packed; 1003 1004#define MAX_ROW_SIZE 32 1005struct mfi_array { 1006 uint64_t size; 1007 uint8_t num_drives; 1008 uint8_t reserved; 1009 uint16_t array_ref; 1010 uint8_t pad[20]; 1011 struct { 1012 union mfi_pd_ref ref; 1013 uint16_t fw_state; 1014 struct { 1015 uint8_t pd; 1016 uint8_t slot; 1017 } encl; 1018 } pd[MAX_ROW_SIZE]; 1019} __packed; 1020 1021struct mfi_config_data { 1022 uint32_t size; 1023 uint16_t array_count; 1024 uint16_t array_size; 1025 uint16_t log_drv_count; 1026 uint16_t log_drv_size; 1027 uint16_t spares_count; 1028 uint16_t spares_size; 1029 uint8_t reserved[16]; 1030 uint8_t data; 1031 /* 1032 struct mfi_array array[]; 1033 struct mfi_ld_config ld[]; 1034 struct mfi_spare spare[]; 1035 */ 1036} __packed; 1037 1038#define MFI_SCSI_MAX_TARGETS 128 1039#define MFI_SCSI_MAX_LUNS 8 1040#define MFI_SCSI_INITIATOR_ID 255 1041#define MFI_SCSI_MAX_CMDS 8 1042#define MFI_SCSI_MAX_CDB_LEN 16 1043 1044#endif /* _MFIREG_H */ 1045