1157114Sscottl/*- 2157114Sscottl * Copyright (c) 2006 IronPort Systems 3157114Sscottl * All rights reserved. 4157114Sscottl * 5157114Sscottl * Redistribution and use in source and binary forms, with or without 6157114Sscottl * modification, are permitted provided that the following conditions 7157114Sscottl * are met: 8157114Sscottl * 1. Redistributions of source code must retain the above copyright 9157114Sscottl * notice, this list of conditions and the following disclaimer. 10157114Sscottl * 2. Redistributions in binary form must reproduce the above copyright 11157114Sscottl * notice, this list of conditions and the following disclaimer in the 12157114Sscottl * documentation and/or other materials provided with the distribution. 13157114Sscottl * 14157114Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15157114Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16157114Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17157114Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18157114Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19157114Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20157114Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21157114Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22157114Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23157114Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24157114Sscottl * SUCH DAMAGE. 25157114Sscottl */ 26171980Sscottl/*- 27171980Sscottl * Copyright (c) 2007 LSI Corp. 28171980Sscottl * Copyright (c) 2007 Rajesh Prabhakaran. 29171980Sscottl * All rights reserved. 30171980Sscottl * 31171980Sscottl * Redistribution and use in source and binary forms, with or without 32171980Sscottl * modification, are permitted provided that the following conditions 33171980Sscottl * are met: 34171980Sscottl * 1. Redistributions of source code must retain the above copyright 35171980Sscottl * notice, this list of conditions and the following disclaimer. 36171980Sscottl * 2. Redistributions in binary form must reproduce the above copyright 37171980Sscottl * notice, this list of conditions and the following disclaimer in the 38171980Sscottl * documentation and/or other materials provided with the distribution. 39171980Sscottl * 40171980Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41171980Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42171980Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43171980Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44171980Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45171980Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46171980Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47171980Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48171980Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49171980Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50171980Sscottl * SUCH DAMAGE. 51171980Sscottl */ 52157114Sscottl 53157114Sscottl#ifndef _MFIREG_H 54157114Sscottl#define _MFIREG_H 55157114Sscottl 56157114Sscottl#include <sys/cdefs.h> 57157114Sscottl__FBSDID("$FreeBSD$"); 58157114Sscottl 59157114Sscottl/* 60157114Sscottl * MegaRAID SAS MFI firmware definitions 61157114Sscottl * 62157114Sscottl * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63157114Sscottl * new firmware interface from the old AMI MegaRAID one, and there is no 64157114Sscottl * reason why this interface should be limited to just SAS. In any case, LSI 65157114Sscottl * seems to also call this interface 'MFI', so that will be used here. 66157114Sscottl */ 67234429Sambrisko#define MEGAMFI_FRAME_SIZE 64 68157114Sscottl/* 69157114Sscottl * Start with the register set. All registers are 32 bits wide. 70157114Sscottl * The usual Intel IOP style setup. 71157114Sscottl */ 72157114Sscottl#define MFI_IMSG0 0x10 /* Inbound message 0 */ 73157114Sscottl#define MFI_IMSG1 0x14 /* Inbound message 1 */ 74157114Sscottl#define MFI_OMSG0 0x18 /* Outbound message 0 */ 75157114Sscottl#define MFI_OMSG1 0x1c /* Outbound message 1 */ 76157114Sscottl#define MFI_IDB 0x20 /* Inbound doorbell */ 77157114Sscottl#define MFI_ISTS 0x24 /* Inbound interrupt status */ 78157114Sscottl#define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79157114Sscottl#define MFI_ODB 0x2c /* Outbound doorbell */ 80157114Sscottl#define MFI_OSTS 0x30 /* Outbound interrupt status */ 81157114Sscottl#define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82157114Sscottl#define MFI_IQP 0x40 /* Inbound queue port */ 83157114Sscottl#define MFI_OQP 0x44 /* Outbound queue port */ 84157114Sscottl 85171980Sscottl/* 86234429Sambrisko* ThunderBolt specific Register 87234429Sambrisko*/ 88234429Sambrisko 89250496Ssmh#define MFI_RFPI 0x48 /* reply_free_post_host_index */ 90234429Sambrisko#define MFI_RPI 0x6c /* reply_post_host_index */ 91234429Sambrisko#define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 92234429Sambrisko#define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 93234429Sambrisko 94234429Sambrisko/* 95171980Sscottl * 1078 specific related register 96171980Sscottl */ 97171980Sscottl#define MFI_ODR0 0x9c /* outbound doorbell register0 */ 98171980Sscottl#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 99171980Sscottl#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 100171980Sscottl#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 101234429Sambrisko#define MFI_RMI 0x2 /* reply message interrupt */ 102171980Sscottl#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 103171980Sscottl#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 104171980Sscottl 105234429Sambrisko/* OCR registers */ 106234429Sambrisko#define MFI_WSR 0x004 /* write sequence register */ 107234429Sambrisko#define MFI_HDR 0x008 /* host diagnostic register */ 108234429Sambrisko#define MFI_RSR 0x3c3 /* Reset Status Register */ 109234429Sambrisko 110184897Sambrisko/* 111184897Sambrisko * GEN2 specific changes 112184897Sambrisko */ 113184897Sambrisko#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 114184897Sambrisko#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 115184897Sambrisko 116234429Sambrisko/* 117234429Sambrisko * skinny specific changes 118234429Sambrisko */ 119234429Sambrisko#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 120234429Sambrisko#define MFI_IQPL 0x000000c0 121234429Sambrisko#define MFI_IQPH 0x000000c4 122234429Sambrisko#define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 123234429Sambrisko 124157114Sscottl/* Bits for MFI_OSTS */ 125157114Sscottl#define MFI_OSTS_INTR_VALID 0x00000002 126157114Sscottl 127234429Sambrisko/* OCR specific flags */ 128234429Sambrisko#define MFI_FIRMWARE_STATE_CHANGE 0x00000002 129234429Sambrisko#define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 130234429Sambrisko 131157114Sscottl/* 132157114Sscottl * Firmware state values. Found in OMSG0 during initialization. 133157114Sscottl */ 134157114Sscottl#define MFI_FWSTATE_MASK 0xf0000000 135157114Sscottl#define MFI_FWSTATE_UNDEFINED 0x00000000 136157114Sscottl#define MFI_FWSTATE_BB_INIT 0x10000000 137157114Sscottl#define MFI_FWSTATE_FW_INIT 0x40000000 138157114Sscottl#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 139157114Sscottl#define MFI_FWSTATE_FW_INIT_2 0x70000000 140157114Sscottl#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 141224041Sjhb#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 142157114Sscottl#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 143157114Sscottl#define MFI_FWSTATE_READY 0xb0000000 144157114Sscottl#define MFI_FWSTATE_OPERATIONAL 0xc0000000 145157114Sscottl#define MFI_FWSTATE_FAULT 0xf0000000 146157114Sscottl#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 147157114Sscottl#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 148234429Sambrisko#define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 149234429Sambrisko#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 150234429Sambrisko#define MFI_RESET_REQUIRED 0x00000001 151157114Sscottl 152234429Sambrisko/* ThunderBolt Support */ 153234429Sambrisko#define MFI_FWSTATE_TB_MASK 0xf0000000 154234429Sambrisko#define MFI_FWSTATE_TB_RESET 0x00000000 155234429Sambrisko#define MFI_FWSTATE_TB_READY 0x10000000 156234429Sambrisko#define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 157234429Sambrisko#define MFI_FWSTATE_TB_FAULT 0x40000000 158234429Sambrisko 159157114Sscottl/* 160157114Sscottl * Control bits to drive the card to ready state. These go into the IDB 161157114Sscottl * register. 162157114Sscottl */ 163157114Sscottl#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 164157114Sscottl#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 165157114Sscottl#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 166157114Sscottl#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 167224041Sjhb#define MFI_FWINIT_HOTPLUG 0x00000010 168157114Sscottl 169234429Sambrisko/* ADP reset flags */ 170234429Sambrisko#define MFI_STOP_ADP 0x00000020 171234429Sambrisko#define MFI_ADP_RESET 0x00000040 172234429Sambrisko#define DIAG_WRITE_ENABLE 0x00000080 173234429Sambrisko#define DIAG_RESET_ADAPTER 0x00000004 174234429Sambrisko 175157114Sscottl/* MFI Commands */ 176157114Sscottltypedef enum { 177157114Sscottl MFI_CMD_INIT = 0x00, 178157114Sscottl MFI_CMD_LD_READ, 179157114Sscottl MFI_CMD_LD_WRITE, 180157114Sscottl MFI_CMD_LD_SCSI_IO, 181157114Sscottl MFI_CMD_PD_SCSI_IO, 182157114Sscottl MFI_CMD_DCMD, 183157114Sscottl MFI_CMD_ABORT, 184157114Sscottl MFI_CMD_SMP, 185157114Sscottl MFI_CMD_STP 186157114Sscottl} mfi_cmd_t; 187157114Sscottl 188157114Sscottl/* Direct commands */ 189157114Sscottltypedef enum { 190157114Sscottl MFI_DCMD_CTRL_GETINFO = 0x01010000, 191234429Sambrisko MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 192163398Sscottl MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 193163398Sscottl MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 194157114Sscottl MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 195157114Sscottl MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 196157114Sscottl MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 197157114Sscottl MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 198157114Sscottl MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 199196200Sscottl MFI_DCMD_PR_GET_STATUS = 0x01070100, 200196200Sscottl MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 201196200Sscottl MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 202196200Sscottl MFI_DCMD_PR_START = 0x01070400, 203196200Sscottl MFI_DCMD_PR_STOP = 0x01070500, 204196200Sscottl MFI_DCMD_TIME_SECS_GET = 0x01080201, 205196200Sscottl MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 206196200Sscottl MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 207196200Sscottl MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 208196200Sscottl MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 209196200Sscottl MFI_DCMD_PD_GET_LIST = 0x02010000, 210234429Sambrisko MFI_DCMD_PD_LIST_QUERY = 0x02010100, 211196200Sscottl MFI_DCMD_PD_GET_INFO = 0x02020000, 212196200Sscottl MFI_DCMD_PD_STATE_SET = 0x02030100, 213196200Sscottl MFI_DCMD_PD_REBUILD_START = 0x02040100, 214196200Sscottl MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 215196200Sscottl MFI_DCMD_PD_CLEAR_START = 0x02050100, 216196200Sscottl MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 217196200Sscottl MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 218196200Sscottl MFI_DCMD_PD_LOCATE_START = 0x02070100, 219196200Sscottl MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 220234429Sambrisko MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 221234429Sambrisko MFI_DCMD_LD_SYNC = 0x0300e102, 222159811Sps MFI_DCMD_LD_GET_LIST = 0x03010000, 223159811Sps MFI_DCMD_LD_GET_INFO = 0x03020000, 224157114Sscottl MFI_DCMD_LD_GET_PROP = 0x03030000, 225159811Sps MFI_DCMD_LD_SET_PROP = 0x03040000, 226196200Sscottl MFI_DCMD_LD_INIT_START = 0x03060100, 227171821Sjhb MFI_DCMD_LD_DELETE = 0x03090000, 228163398Sscottl MFI_DCMD_CFG_READ = 0x04010000, 229163398Sscottl MFI_DCMD_CFG_ADD = 0x04020000, 230163398Sscottl MFI_DCMD_CFG_CLEAR = 0x04030000, 231196200Sscottl MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 232234429Sambrisko MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 233253244Ssbruno MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100, 234253244Ssbruno MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200, 235253244Ssbruno MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300, 236184897Sambrisko MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 237253244Ssbruno MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500, 238196200Sscottl MFI_DCMD_BBU_GET_STATUS = 0x05010000, 239196200Sscottl MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 240196200Sscottl MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 241250482Smarkj MFI_DCMD_BBU_START_LEARN = 0x05040000, 242250482Smarkj MFI_DCMD_BBU_GET_PROP = 0x05050100, 243250482Smarkj MFI_DCMD_BBU_SET_PROP = 0x05050200, 244157114Sscottl MFI_DCMD_CLUSTER = 0x08000000, 245157114Sscottl MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 246157114Sscottl MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 247157114Sscottl} mfi_dcmd_t; 248157114Sscottl 249157114Sscottl/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 250157114Sscottl#define MFI_FLUSHCACHE_CTRL 0x01 251157114Sscottl#define MFI_FLUSHCACHE_DISK 0x02 252157114Sscottl 253157114Sscottl/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 254157114Sscottl#define MFI_SHUTDOWN_SPINDOWN 0x01 255157114Sscottl 256157114Sscottl/* 257158737Sambrisko * MFI Frame flags 258157114Sscottl */ 259157114Sscottl#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 260157114Sscottl#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 261157114Sscottl#define MFI_FRAME_SGL32 0x0000 262157114Sscottl#define MFI_FRAME_SGL64 0x0002 263157114Sscottl#define MFI_FRAME_SENSE32 0x0000 264157114Sscottl#define MFI_FRAME_SENSE64 0x0004 265157114Sscottl#define MFI_FRAME_DIR_NONE 0x0000 266157114Sscottl#define MFI_FRAME_DIR_WRITE 0x0008 267157114Sscottl#define MFI_FRAME_DIR_READ 0x0010 268157114Sscottl#define MFI_FRAME_DIR_BOTH 0x0018 269234429Sambrisko#define MFI_FRAME_IEEE_SGL 0x0020 270250496Ssmh#define MFI_FRAME_FMT "\20" \ 271250496Ssmh "\1NOPOST" \ 272250496Ssmh "\2SGL64" \ 273250496Ssmh "\3SENSE64" \ 274250496Ssmh "\4WRITE" \ 275250496Ssmh "\5READ" \ 276250496Ssmh "\6IEEESGL" 277157114Sscottl 278234429Sambrisko/* ThunderBolt Specific */ 279234429Sambrisko 280234429Sambrisko/* 281234429Sambrisko * Pre-TB command size and TB command size. 282234429Sambrisko * We will be checking it at the load time for the time being 283234429Sambrisko */ 284234429Sambrisko#define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 285234429Sambrisko 286234429Sambrisko#define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 287234429Sambrisko/* 288234429Sambrisko * We are defining only 128 byte message to reduce memory move over head 289234429Sambrisko * and also it will reduce the SRB extension size by 128byte compared with 290234429Sambrisko * 256 message size 291234429Sambrisko */ 292234429Sambrisko#define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 293234429Sambrisko#define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 294234429Sambrisko#define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 295234429Sambrisko#define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 296234429Sambrisko#define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 297234429Sambrisko#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 298234429Sambrisko 299234429Sambrisko#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 300234429Sambrisko#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 301234429Sambrisko 302234429Sambrisko#define MR_INTERNAL_MFI_FRAMES_SMID 1 303234429Sambrisko#define MR_CTRL_EVENT_WAIT_SMID 2 304234429Sambrisko#define MR_INTERNAL_DRIVER_RESET_SMID 3 305234429Sambrisko 306234429Sambrisko 307157114Sscottl/* MFI Status codes */ 308157114Sscottltypedef enum { 309157114Sscottl MFI_STAT_OK = 0x00, 310157114Sscottl MFI_STAT_INVALID_CMD, 311157114Sscottl MFI_STAT_INVALID_DCMD, 312157114Sscottl MFI_STAT_INVALID_PARAMETER, 313157114Sscottl MFI_STAT_INVALID_SEQUENCE_NUMBER, 314157114Sscottl MFI_STAT_ABORT_NOT_POSSIBLE, 315157114Sscottl MFI_STAT_APP_HOST_CODE_NOT_FOUND, 316157114Sscottl MFI_STAT_APP_IN_USE, 317157114Sscottl MFI_STAT_APP_NOT_INITIALIZED, 318157114Sscottl MFI_STAT_ARRAY_INDEX_INVALID, 319157114Sscottl MFI_STAT_ARRAY_ROW_NOT_EMPTY, 320157114Sscottl MFI_STAT_CONFIG_RESOURCE_CONFLICT, 321157114Sscottl MFI_STAT_DEVICE_NOT_FOUND, 322157114Sscottl MFI_STAT_DRIVE_TOO_SMALL, 323157114Sscottl MFI_STAT_FLASH_ALLOC_FAIL, 324157114Sscottl MFI_STAT_FLASH_BUSY, 325157114Sscottl MFI_STAT_FLASH_ERROR = 0x10, 326157114Sscottl MFI_STAT_FLASH_IMAGE_BAD, 327157114Sscottl MFI_STAT_FLASH_IMAGE_INCOMPLETE, 328157114Sscottl MFI_STAT_FLASH_NOT_OPEN, 329157114Sscottl MFI_STAT_FLASH_NOT_STARTED, 330157114Sscottl MFI_STAT_FLUSH_FAILED, 331157114Sscottl MFI_STAT_HOST_CODE_NOT_FOUNT, 332157114Sscottl MFI_STAT_LD_CC_IN_PROGRESS, 333157114Sscottl MFI_STAT_LD_INIT_IN_PROGRESS, 334157114Sscottl MFI_STAT_LD_LBA_OUT_OF_RANGE, 335157114Sscottl MFI_STAT_LD_MAX_CONFIGURED, 336157114Sscottl MFI_STAT_LD_NOT_OPTIMAL, 337157114Sscottl MFI_STAT_LD_RBLD_IN_PROGRESS, 338157114Sscottl MFI_STAT_LD_RECON_IN_PROGRESS, 339157114Sscottl MFI_STAT_LD_WRONG_RAID_LEVEL, 340157114Sscottl MFI_STAT_MAX_SPARES_EXCEEDED, 341157114Sscottl MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 342157114Sscottl MFI_STAT_MFC_HW_ERROR, 343157114Sscottl MFI_STAT_NO_HW_PRESENT, 344157114Sscottl MFI_STAT_NOT_FOUND, 345157114Sscottl MFI_STAT_NOT_IN_ENCL, 346157114Sscottl MFI_STAT_PD_CLEAR_IN_PROGRESS, 347157114Sscottl MFI_STAT_PD_TYPE_WRONG, 348157114Sscottl MFI_STAT_PR_DISABLED, 349157114Sscottl MFI_STAT_ROW_INDEX_INVALID, 350157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_ACTION, 351157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_DATA, 352157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_PAGE, 353157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_TYPE, 354157114Sscottl MFI_STAT_SCSI_DONE_WITH_ERROR, 355157114Sscottl MFI_STAT_SCSI_IO_FAILED, 356157114Sscottl MFI_STAT_SCSI_RESERVATION_CONFLICT, 357157114Sscottl MFI_STAT_SHUTDOWN_FAILED = 0x30, 358157114Sscottl MFI_STAT_TIME_NOT_SET, 359157114Sscottl MFI_STAT_WRONG_STATE, 360157114Sscottl MFI_STAT_LD_OFFLINE, 361157114Sscottl MFI_STAT_PEER_NOTIFICATION_REJECTED, 362157114Sscottl MFI_STAT_PEER_NOTIFICATION_FAILED, 363157114Sscottl MFI_STAT_RESERVATION_IN_PROGRESS, 364157114Sscottl MFI_STAT_I2C_ERRORS_DETECTED, 365157114Sscottl MFI_STAT_PCI_ERRORS_DETECTED, 366196200Sscottl MFI_STAT_DIAG_FAILED, 367196200Sscottl MFI_STAT_BOOT_MSG_PENDING, 368196200Sscottl MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 369157114Sscottl MFI_STAT_INVALID_STATUS = 0xFF 370157114Sscottl} mfi_status_t; 371157114Sscottl 372157114Sscottltypedef enum { 373157114Sscottl MFI_EVT_CLASS_DEBUG = -2, 374157114Sscottl MFI_EVT_CLASS_PROGRESS = -1, 375157114Sscottl MFI_EVT_CLASS_INFO = 0, 376157114Sscottl MFI_EVT_CLASS_WARNING = 1, 377157114Sscottl MFI_EVT_CLASS_CRITICAL = 2, 378157114Sscottl MFI_EVT_CLASS_FATAL = 3, 379157114Sscottl MFI_EVT_CLASS_DEAD = 4 380157114Sscottl} mfi_evt_class_t; 381157114Sscottl 382157114Sscottltypedef enum { 383157114Sscottl MFI_EVT_LOCALE_LD = 0x0001, 384157114Sscottl MFI_EVT_LOCALE_PD = 0x0002, 385157114Sscottl MFI_EVT_LOCALE_ENCL = 0x0004, 386157114Sscottl MFI_EVT_LOCALE_BBU = 0x0008, 387157114Sscottl MFI_EVT_LOCALE_SAS = 0x0010, 388157114Sscottl MFI_EVT_LOCALE_CTRL = 0x0020, 389157114Sscottl MFI_EVT_LOCALE_CONFIG = 0x0040, 390157114Sscottl MFI_EVT_LOCALE_CLUSTER = 0x0080, 391157114Sscottl MFI_EVT_LOCALE_ALL = 0xffff 392157114Sscottl} mfi_evt_locale_t; 393157114Sscottl 394157114Sscottltypedef enum { 395158737Sambrisko MR_EVT_ARGS_NONE = 0x00, 396158737Sambrisko MR_EVT_ARGS_CDB_SENSE, 397158737Sambrisko MR_EVT_ARGS_LD, 398158737Sambrisko MR_EVT_ARGS_LD_COUNT, 399158737Sambrisko MR_EVT_ARGS_LD_LBA, 400158737Sambrisko MR_EVT_ARGS_LD_OWNER, 401158737Sambrisko MR_EVT_ARGS_LD_LBA_PD_LBA, 402158737Sambrisko MR_EVT_ARGS_LD_PROG, 403158737Sambrisko MR_EVT_ARGS_LD_STATE, 404158737Sambrisko MR_EVT_ARGS_LD_STRIP, 405158737Sambrisko MR_EVT_ARGS_PD, 406158737Sambrisko MR_EVT_ARGS_PD_ERR, 407158737Sambrisko MR_EVT_ARGS_PD_LBA, 408158737Sambrisko MR_EVT_ARGS_PD_LBA_LD, 409158737Sambrisko MR_EVT_ARGS_PD_PROG, 410158737Sambrisko MR_EVT_ARGS_PD_STATE, 411158737Sambrisko MR_EVT_ARGS_PCI, 412158737Sambrisko MR_EVT_ARGS_RATE, 413158737Sambrisko MR_EVT_ARGS_STR, 414158737Sambrisko MR_EVT_ARGS_TIME, 415158737Sambrisko MR_EVT_ARGS_ECC 416157114Sscottl} mfi_evt_args; 417157114Sscottl 418234429Sambrisko#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 419234429Sambrisko#define MR_EVT_PD_REMOVED 0x0070 420234429Sambrisko#define MR_EVT_PD_INSERTED 0x005b 421235135Sambrisko#define MR_EVT_LD_CHANGE 0x0051 422234429Sambrisko 423163398Sscottltypedef enum { 424163398Sscottl MR_LD_CACHE_WRITE_BACK = 0x01, 425163398Sscottl MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 426163398Sscottl MR_LD_CACHE_READ_AHEAD = 0x04, 427163398Sscottl MR_LD_CACHE_READ_ADAPTIVE = 0x08, 428163398Sscottl MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 429163398Sscottl MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 430163398Sscottl MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 431163398Sscottl} mfi_ld_cache; 432196200Sscottl#define MR_LD_CACHE_MASK 0x7f 433163398Sscottl 434196200Sscottl#define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 435196200Sscottl#define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 436196200Sscottl#define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 437196200Sscottl (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 438196200Sscottl#define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 439196200Sscottl#define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 440196200Sscottl#define MR_LD_CACHE_POLICY_IO_CACHED \ 441196200Sscottl (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 442196200Sscottl#define MR_LD_CACHE_POLICY_IO_DIRECT 0 443196200Sscottl 444163398Sscottltypedef enum { 445163398Sscottl MR_PD_CACHE_UNCHANGED = 0, 446163398Sscottl MR_PD_CACHE_ENABLE = 1, 447163398Sscottl MR_PD_CACHE_DISABLE = 2 448163398Sscottl} mfi_pd_cache; 449163398Sscottl 450234429Sambriskotypedef enum { 451234429Sambrisko MR_PD_QUERY_TYPE_ALL = 0, 452234429Sambrisko MR_PD_QUERY_TYPE_STATE = 1, 453234429Sambrisko MR_PD_QUERY_TYPE_POWER_STATE = 2, 454234429Sambrisko MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 455234429Sambrisko MR_PD_QUERY_TYPE_SPEED = 4, 456234429Sambrisko MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 457234429Sambrisko} mfi_pd_query_type; 458234429Sambrisko 459157114Sscottl/* 460157114Sscottl * Other propertities and definitions 461157114Sscottl */ 462157114Sscottl#define MFI_MAX_PD_CHANNELS 2 463157114Sscottl#define MFI_MAX_LD_CHANNELS 2 464157114Sscottl#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 465157114Sscottl#define MFI_MAX_CHANNEL_DEVS 128 466157114Sscottl#define MFI_DEFAULT_ID -1 467157114Sscottl#define MFI_MAX_LUN 8 468157114Sscottl#define MFI_MAX_LD 64 469196200Sscottl#define MFI_MAX_PD 256 470157114Sscottl 471157114Sscottl#define MFI_FRAME_SIZE 64 472157114Sscottl#define MFI_MBOX_SIZE 12 473157114Sscottl 474250496Ssmh/* Firmware flashing can take 50+ seconds */ 475250496Ssmh#define MFI_POLL_TIMEOUT_SECS 60 476157114Sscottl 477157114Sscottl/* Allow for speedier math calculations */ 478157114Sscottl#define MFI_SECTOR_LEN 512 479157114Sscottl 480157114Sscottl/* Scatter Gather elements */ 481157114Sscottlstruct mfi_sg32 { 482157114Sscottl uint32_t addr; 483157114Sscottl uint32_t len; 484157114Sscottl} __packed; 485157114Sscottl 486157114Sscottlstruct mfi_sg64 { 487157114Sscottl uint64_t addr; 488157114Sscottl uint32_t len; 489157114Sscottl} __packed; 490157114Sscottl 491234429Sambriskostruct mfi_sg_skinny { 492234429Sambrisko uint64_t addr; 493234429Sambrisko uint32_t len; 494234429Sambrisko uint32_t flag; 495234429Sambrisko} __packed; 496234429Sambrisko 497157114Sscottlunion mfi_sgl { 498234429Sambrisko struct mfi_sg32 sg32[1]; 499234429Sambrisko struct mfi_sg64 sg64[1]; 500234429Sambrisko struct mfi_sg_skinny sg_skinny[1]; 501157114Sscottl} __packed; 502157114Sscottl 503157114Sscottl/* Message frames. All messages have a common header */ 504157114Sscottlstruct mfi_frame_header { 505157114Sscottl uint8_t cmd; 506157114Sscottl uint8_t sense_len; 507157114Sscottl uint8_t cmd_status; 508157114Sscottl uint8_t scsi_status; 509157114Sscottl uint8_t target_id; 510157114Sscottl uint8_t lun_id; 511157114Sscottl uint8_t cdb_len; 512157114Sscottl uint8_t sg_count; 513157114Sscottl uint32_t context; 514234429Sambrisko /* 515234429Sambrisko * pad0 is MSI Specific. Not used by Driver. Zero the value before 516234429Sambrisko * sending the command to f/w. 517234429Sambrisko */ 518157114Sscottl uint32_t pad0; 519157114Sscottl uint16_t flags; 520175897Sambrisko#define MFI_FRAME_DATAOUT 0x08 521175897Sambrisko#define MFI_FRAME_DATAIN 0x10 522157114Sscottl uint16_t timeout; 523157114Sscottl uint32_t data_len; 524157114Sscottl} __packed; 525157114Sscottl 526157114Sscottlstruct mfi_init_frame { 527157114Sscottl struct mfi_frame_header header; 528157114Sscottl uint32_t qinfo_new_addr_lo; 529157114Sscottl uint32_t qinfo_new_addr_hi; 530157114Sscottl uint32_t qinfo_old_addr_lo; 531157114Sscottl uint32_t qinfo_old_addr_hi; 532234429Sambrisko // Start LSIP200113393 533234429Sambrisko uint32_t driver_ver_lo; /*28h */ 534234429Sambrisko uint32_t driver_ver_hi; /*2Ch */ 535234429Sambrisko 536234429Sambrisko uint32_t reserved[4]; 537234429Sambrisko // End LSIP200113393 538157114Sscottl} __packed; 539157114Sscottl 540234429Sambrisko/* 541234429Sambrisko * Define MFI Address Context union. 542234429Sambrisko */ 543234429Sambrisko#ifdef MFI_ADDRESS_IS_uint64_t 544234429Sambrisko typedef uint64_t MFI_ADDRESS; 545234429Sambrisko#else 546234429Sambrisko typedef union _MFI_ADDRESS { 547234429Sambrisko struct { 548234429Sambrisko uint32_t addressLow; 549234429Sambrisko uint32_t addressHigh; 550234429Sambrisko } u; 551234429Sambrisko uint64_t address; 552234429Sambrisko } MFI_ADDRESS, *PMFI_ADDRESS; 553234429Sambrisko#endif 554234429Sambrisko 555157114Sscottl#define MFI_IO_FRAME_SIZE 40 556157114Sscottlstruct mfi_io_frame { 557157114Sscottl struct mfi_frame_header header; 558157114Sscottl uint32_t sense_addr_lo; 559157114Sscottl uint32_t sense_addr_hi; 560157114Sscottl uint32_t lba_lo; 561157114Sscottl uint32_t lba_hi; 562157114Sscottl union mfi_sgl sgl; 563157114Sscottl} __packed; 564157114Sscottl 565157114Sscottl#define MFI_PASS_FRAME_SIZE 48 566157114Sscottlstruct mfi_pass_frame { 567157114Sscottl struct mfi_frame_header header; 568157114Sscottl uint32_t sense_addr_lo; 569157114Sscottl uint32_t sense_addr_hi; 570157114Sscottl uint8_t cdb[16]; 571157114Sscottl union mfi_sgl sgl; 572157114Sscottl} __packed; 573157114Sscottl 574157114Sscottl#define MFI_DCMD_FRAME_SIZE 40 575157114Sscottlstruct mfi_dcmd_frame { 576157114Sscottl struct mfi_frame_header header; 577157114Sscottl uint32_t opcode; 578157114Sscottl uint8_t mbox[MFI_MBOX_SIZE]; 579157114Sscottl union mfi_sgl sgl; 580157114Sscottl} __packed; 581157114Sscottl 582157114Sscottlstruct mfi_abort_frame { 583157114Sscottl struct mfi_frame_header header; 584157114Sscottl uint32_t abort_context; 585234429Sambrisko /* pad is changed to reserved.*/ 586234429Sambrisko uint32_t reserved0; 587157114Sscottl uint32_t abort_mfi_addr_lo; 588157114Sscottl uint32_t abort_mfi_addr_hi; 589234429Sambrisko uint32_t reserved1[6]; 590157114Sscottl} __packed; 591157114Sscottl 592157114Sscottlstruct mfi_smp_frame { 593157114Sscottl struct mfi_frame_header header; 594157114Sscottl uint64_t sas_addr; 595157114Sscottl union { 596157114Sscottl struct mfi_sg32 sg32[2]; 597157114Sscottl struct mfi_sg64 sg64[2]; 598157114Sscottl } sgl; 599157114Sscottl} __packed; 600157114Sscottl 601157114Sscottlstruct mfi_stp_frame { 602157114Sscottl struct mfi_frame_header header; 603157114Sscottl uint16_t fis[10]; 604157114Sscottl uint32_t stp_flags; 605157114Sscottl union { 606157114Sscottl struct mfi_sg32 sg32[2]; 607157114Sscottl struct mfi_sg64 sg64[2]; 608157114Sscottl } sgl; 609157114Sscottl} __packed; 610157114Sscottl 611157114Sscottlunion mfi_frame { 612157114Sscottl struct mfi_frame_header header; 613157114Sscottl struct mfi_init_frame init; 614234429Sambrisko /* ThunderBolt Initialization */ 615157114Sscottl struct mfi_io_frame io; 616157114Sscottl struct mfi_pass_frame pass; 617157114Sscottl struct mfi_dcmd_frame dcmd; 618157114Sscottl struct mfi_abort_frame abort; 619157114Sscottl struct mfi_smp_frame smp; 620157114Sscottl struct mfi_stp_frame stp; 621157114Sscottl uint8_t bytes[MFI_FRAME_SIZE]; 622157114Sscottl}; 623157114Sscottl 624157114Sscottl#define MFI_SENSE_LEN 128 625157114Sscottlstruct mfi_sense { 626157114Sscottl uint8_t data[MFI_SENSE_LEN]; 627157114Sscottl}; 628157114Sscottl 629157114Sscottl/* The queue init structure that is passed with the init message */ 630157114Sscottlstruct mfi_init_qinfo { 631157114Sscottl uint32_t flags; 632157114Sscottl uint32_t rq_entries; 633157114Sscottl uint32_t rq_addr_lo; 634157114Sscottl uint32_t rq_addr_hi; 635157114Sscottl uint32_t pi_addr_lo; 636157114Sscottl uint32_t pi_addr_hi; 637157114Sscottl uint32_t ci_addr_lo; 638157114Sscottl uint32_t ci_addr_hi; 639157114Sscottl} __packed; 640157114Sscottl 641157114Sscottl/* SAS (?) controller properties, part of mfi_ctrl_info */ 642157114Sscottlstruct mfi_ctrl_props { 643157114Sscottl uint16_t seq_num; 644157114Sscottl uint16_t pred_fail_poll_interval; 645157114Sscottl uint16_t intr_throttle_cnt; 646157114Sscottl uint16_t intr_throttle_timeout; 647157114Sscottl uint8_t rebuild_rate; 648157114Sscottl uint8_t patrol_read_rate; 649157114Sscottl uint8_t bgi_rate; 650157114Sscottl uint8_t cc_rate; 651157114Sscottl uint8_t recon_rate; 652157114Sscottl uint8_t cache_flush_interval; 653157114Sscottl uint8_t spinup_drv_cnt; 654157114Sscottl uint8_t spinup_delay; 655157114Sscottl uint8_t cluster_enable; 656157114Sscottl uint8_t coercion_mode; 657157114Sscottl uint8_t alarm_enable; 658157114Sscottl uint8_t disable_auto_rebuild; 659157114Sscottl uint8_t disable_battery_warn; 660157114Sscottl uint8_t ecc_bucket_size; 661157114Sscottl uint16_t ecc_bucket_leak_rate; 662157114Sscottl uint8_t restore_hotspare_on_insertion; 663157114Sscottl uint8_t expose_encl_devices; 664234429Sambrisko uint8_t maintainPdFailHistory; 665234429Sambrisko uint8_t disallowHostRequestReordering; 666234429Sambrisko /* set TRUE to abort CC on detecting an inconsistency */ 667234429Sambrisko uint8_t abortCCOnError; 668234429Sambrisko /* load balance mode (MR_LOAD_BALANCE_MODE) */ 669234429Sambrisko uint8_t loadBalanceMode; 670234429Sambrisko /* 671234429Sambrisko * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 672234429Sambrisko * h/w mechansim like GPIO pins 673234429Sambrisko * 1 - disable auto detect SGPIO, 674234429Sambrisko * 2 - disable i2c SEP auto detect 675234429Sambrisko * 3 - disable both auto detect 676234429Sambrisko */ 677234429Sambrisko uint8_t disableAutoDetectBackplane; 678234429Sambrisko /* 679234429Sambrisko * % of source LD to be reserved for a VDs snapshot in snapshot 680234429Sambrisko * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 681234429Sambrisko */ 682234429Sambrisko uint8_t snapVDSpace; 683234429Sambrisko 684234429Sambrisko /* 685234429Sambrisko * Add properties that can be controlled by a bit in the following 686234429Sambrisko * structure. 687234429Sambrisko */ 688234429Sambrisko struct { 689234429Sambrisko /* set TRUE to disable copyBack (0=copback enabled) */ 690234429Sambrisko uint32_t copyBackDisabled :1; 691234429Sambrisko uint32_t SMARTerEnabled :1; 692234429Sambrisko uint32_t prCorrectUnconfiguredAreas :1; 693234429Sambrisko uint32_t useFdeOnly :1; 694234429Sambrisko uint32_t disableNCQ :1; 695234429Sambrisko uint32_t SSDSMARTerEnabled :1; 696234429Sambrisko uint32_t SSDPatrolReadEnabled :1; 697234429Sambrisko uint32_t enableSpinDownUnconfigured :1; 698234429Sambrisko uint32_t autoEnhancedImport :1; 699234429Sambrisko uint32_t enableSecretKeyControl :1; 700234429Sambrisko uint32_t disableOnlineCtrlReset :1; 701234429Sambrisko uint32_t allowBootWithPinnedCache :1; 702234429Sambrisko uint32_t disableSpinDownHS :1; 703234429Sambrisko uint32_t enableJBOD :1; 704234429Sambrisko uint32_t reserved :18; 705234429Sambrisko } OnOffProperties; 706234429Sambrisko /* 707234429Sambrisko * % of source LD to be reserved for auto snapshot in snapshot 708234429Sambrisko * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 709234429Sambrisko */ 710234429Sambrisko uint8_t autoSnapVDSpace; 711234429Sambrisko /* 712234429Sambrisko * Snapshot writeable VIEWs capacity as a % of source LD capacity: 713234429Sambrisko * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 714234429Sambrisko */ 715234429Sambrisko uint8_t viewSpace; 716234429Sambrisko /* # of idle minutes before device is spun down (0=use FW defaults) */ 717234429Sambrisko uint16_t spinDownTime; 718234429Sambrisko uint8_t reserved[24]; 719157114Sscottl} __packed; 720157114Sscottl 721157114Sscottl/* PCI information about the card. */ 722157114Sscottlstruct mfi_info_pci { 723157114Sscottl uint16_t vendor; 724157114Sscottl uint16_t device; 725157114Sscottl uint16_t subvendor; 726157114Sscottl uint16_t subdevice; 727157114Sscottl uint8_t reserved[24]; 728157114Sscottl} __packed; 729157114Sscottl 730157114Sscottl/* Host (front end) interface information */ 731157114Sscottlstruct mfi_info_host { 732157114Sscottl uint8_t type; 733157114Sscottl#define MFI_INFO_HOST_PCIX 0x01 734157114Sscottl#define MFI_INFO_HOST_PCIE 0x02 735157114Sscottl#define MFI_INFO_HOST_ISCSI 0x04 736157114Sscottl#define MFI_INFO_HOST_SAS3G 0x08 737157114Sscottl uint8_t reserved[6]; 738157114Sscottl uint8_t port_count; 739157114Sscottl uint64_t port_addr[8]; 740157114Sscottl} __packed; 741157114Sscottl 742157114Sscottl/* Device (back end) interface information */ 743157114Sscottlstruct mfi_info_device { 744157114Sscottl uint8_t type; 745157114Sscottl#define MFI_INFO_DEV_SPI 0x01 746157114Sscottl#define MFI_INFO_DEV_SAS3G 0x02 747157114Sscottl#define MFI_INFO_DEV_SATA1 0x04 748157114Sscottl#define MFI_INFO_DEV_SATA3G 0x08 749157114Sscottl uint8_t reserved[6]; 750157114Sscottl uint8_t port_count; 751157114Sscottl uint64_t port_addr[8]; 752157114Sscottl} __packed; 753157114Sscottl 754157114Sscottl/* Firmware component information */ 755157114Sscottlstruct mfi_info_component { 756157114Sscottl char name[8]; 757157114Sscottl char version[32]; 758157114Sscottl char build_date[16]; 759157114Sscottl char build_time[16]; 760157114Sscottl} __packed; 761157114Sscottl 762163398Sscottl/* Controller default settings */ 763163398Sscottlstruct mfi_defaults { 764163398Sscottl uint64_t sas_addr; 765163398Sscottl uint8_t phy_polarity; 766163398Sscottl uint8_t background_rate; 767163398Sscottl uint8_t stripe_size; 768163398Sscottl uint8_t flush_time; 769163398Sscottl uint8_t write_back; 770163398Sscottl uint8_t read_ahead; 771163398Sscottl uint8_t cache_when_bbu_bad; 772163398Sscottl uint8_t cached_io; 773163398Sscottl uint8_t smart_mode; 774163398Sscottl uint8_t alarm_disable; 775163398Sscottl uint8_t coercion; 776163398Sscottl uint8_t zrc_config; 777163398Sscottl uint8_t dirty_led_shows_drive_activity; 778163398Sscottl uint8_t bios_continue_on_error; 779163398Sscottl uint8_t spindown_mode; 780163398Sscottl uint8_t allowed_device_types; 781163398Sscottl uint8_t allow_mix_in_enclosure; 782163398Sscottl uint8_t allow_mix_in_ld; 783163398Sscottl uint8_t allow_sata_in_cluster; 784163398Sscottl uint8_t max_chained_enclosures; 785163398Sscottl uint8_t disable_ctrl_r; 786163398Sscottl uint8_t enabel_web_bios; 787163398Sscottl uint8_t phy_polarity_split; 788163398Sscottl uint8_t direct_pd_mapping; 789163398Sscottl uint8_t bios_enumerate_lds; 790163398Sscottl uint8_t restored_hot_spare_on_insertion; 791163398Sscottl uint8_t expose_enclosure_devices; 792163398Sscottl uint8_t maintain_pd_fail_history; 793163398Sscottl uint8_t resv[28]; 794163398Sscottl} __packed; 795157114Sscottl 796163398Sscottl/* Controller default settings */ 797163398Sscottlstruct mfi_bios_data { 798163398Sscottl uint16_t boot_target_id; 799163398Sscottl uint8_t do_not_int_13; 800163398Sscottl uint8_t continue_on_error; 801163398Sscottl uint8_t verbose; 802163398Sscottl uint8_t geometry; 803163398Sscottl uint8_t expose_all_drives; 804163398Sscottl uint8_t reserved[56]; 805163398Sscottl uint8_t check_sum; 806163398Sscottl} __packed; 807163398Sscottl 808157114Sscottl/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 809157114Sscottlstruct mfi_ctrl_info { 810157114Sscottl struct mfi_info_pci pci; 811157114Sscottl struct mfi_info_host host; 812157114Sscottl struct mfi_info_device device; 813157114Sscottl 814157114Sscottl /* Firmware components that are present and active. */ 815157114Sscottl uint32_t image_check_word; 816157114Sscottl uint32_t image_component_count; 817157114Sscottl struct mfi_info_component image_component[8]; 818157114Sscottl 819157114Sscottl /* Firmware components that have been flashed but are inactive */ 820157114Sscottl uint32_t pending_image_component_count; 821157114Sscottl struct mfi_info_component pending_image_component[8]; 822157114Sscottl 823157114Sscottl uint8_t max_arms; 824157114Sscottl uint8_t max_spans; 825157114Sscottl uint8_t max_arrays; 826157114Sscottl uint8_t max_lds; 827157114Sscottl char product_name[80]; 828157114Sscottl char serial_number[32]; 829157114Sscottl uint32_t hw_present; 830157114Sscottl#define MFI_INFO_HW_BBU 0x01 831157114Sscottl#define MFI_INFO_HW_ALARM 0x02 832157114Sscottl#define MFI_INFO_HW_NVRAM 0x04 833157114Sscottl#define MFI_INFO_HW_UART 0x08 834157114Sscottl uint32_t current_fw_time; 835157114Sscottl uint16_t max_cmds; 836157114Sscottl uint16_t max_sg_elements; 837157114Sscottl uint32_t max_request_size; 838157114Sscottl uint16_t lds_present; 839157114Sscottl uint16_t lds_degraded; 840157114Sscottl uint16_t lds_offline; 841157114Sscottl uint16_t pd_present; 842157114Sscottl uint16_t pd_disks_present; 843157114Sscottl uint16_t pd_disks_pred_failure; 844157114Sscottl uint16_t pd_disks_failed; 845157114Sscottl uint16_t nvram_size; 846157114Sscottl uint16_t memory_size; 847157114Sscottl uint16_t flash_size; 848157114Sscottl uint16_t ram_correctable_errors; 849157114Sscottl uint16_t ram_uncorrectable_errors; 850157114Sscottl uint8_t cluster_allowed; 851157114Sscottl uint8_t cluster_active; 852157114Sscottl uint16_t max_strips_per_io; 853157114Sscottl 854157114Sscottl uint32_t raid_levels; 855157114Sscottl#define MFI_INFO_RAID_0 0x01 856157114Sscottl#define MFI_INFO_RAID_1 0x02 857157114Sscottl#define MFI_INFO_RAID_5 0x04 858157114Sscottl#define MFI_INFO_RAID_1E 0x08 859157114Sscottl#define MFI_INFO_RAID_6 0x10 860157114Sscottl 861157114Sscottl uint32_t adapter_ops; 862158737Sambrisko#define MFI_INFO_AOPS_RBLD_RATE 0x0001 863157114Sscottl#define MFI_INFO_AOPS_CC_RATE 0x0002 864157114Sscottl#define MFI_INFO_AOPS_BGI_RATE 0x0004 865157114Sscottl#define MFI_INFO_AOPS_RECON_RATE 0x0008 866157114Sscottl#define MFI_INFO_AOPS_PATROL_RATE 0x0010 867157114Sscottl#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 868157114Sscottl#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 869157114Sscottl#define MFI_INFO_AOPS_BBU 0x0080 870157114Sscottl#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 871157114Sscottl#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 872157114Sscottl#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 873157114Sscottl#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 874157114Sscottl#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 875157114Sscottl#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 876157114Sscottl#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 877157114Sscottl 878157114Sscottl uint32_t ld_ops; 879157114Sscottl#define MFI_INFO_LDOPS_READ_POLICY 0x01 880157114Sscottl#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 881157114Sscottl#define MFI_INFO_LDOPS_IO_POLICY 0x04 882157114Sscottl#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 883157114Sscottl#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 884157114Sscottl 885157114Sscottl struct { 886157114Sscottl uint8_t min; 887157114Sscottl uint8_t max; 888157114Sscottl uint8_t reserved[2]; 889157114Sscottl } __packed stripe_sz_ops; 890157114Sscottl 891157114Sscottl uint32_t pd_ops; 892157114Sscottl#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 893157114Sscottl#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 894157114Sscottl#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 895157114Sscottl 896157114Sscottl uint32_t pd_mix_support; 897157114Sscottl#define MFI_INFO_PDMIX_SAS 0x01 898157114Sscottl#define MFI_INFO_PDMIX_SATA 0x02 899157114Sscottl#define MFI_INFO_PDMIX_ENCL 0x04 900157114Sscottl#define MFI_INFO_PDMIX_LD 0x08 901157114Sscottl#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 902157114Sscottl 903157114Sscottl uint8_t ecc_bucket_count; 904157114Sscottl uint8_t reserved2[11]; 905157114Sscottl struct mfi_ctrl_props properties; 906157114Sscottl char package_version[0x60]; 907157114Sscottl uint8_t pad[0x800 - 0x6a0]; 908157114Sscottl} __packed; 909157114Sscottl 910158737Sambrisko/* keep track of an event. */ 911158737Sambriskounion mfi_evt { 912158737Sambrisko struct { 913158737Sambrisko uint16_t locale; 914158737Sambrisko uint8_t reserved; 915222589Semaste int8_t evt_class; 916158737Sambrisko } members; 917158737Sambrisko uint32_t word; 918158737Sambrisko} __packed; 919158737Sambrisko 920158737Sambrisko/* event log state. */ 921158737Sambriskostruct mfi_evt_log_state { 922158737Sambrisko uint32_t newest_seq_num; 923158737Sambrisko uint32_t oldest_seq_num; 924158737Sambrisko uint32_t clear_seq_num; 925158737Sambrisko uint32_t shutdown_seq_num; 926158737Sambrisko uint32_t boot_seq_num; 927158737Sambrisko} __packed; 928158737Sambrisko 929158737Sambriskostruct mfi_progress { 930158737Sambrisko uint16_t progress; 931158737Sambrisko uint16_t elapsed_seconds; 932158737Sambrisko} __packed; 933158737Sambrisko 934158737Sambriskostruct mfi_evt_ld { 935158737Sambrisko uint16_t target_id; 936158737Sambrisko uint8_t ld_index; 937158737Sambrisko uint8_t reserved; 938158737Sambrisko} __packed; 939158737Sambrisko 940158737Sambriskostruct mfi_evt_pd { 941158737Sambrisko uint16_t device_id; 942158737Sambrisko uint8_t enclosure_index; 943158737Sambrisko uint8_t slot_number; 944158737Sambrisko} __packed; 945158737Sambrisko 946158737Sambrisko/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 947158737Sambriskostruct mfi_evt_detail { 948158737Sambrisko uint32_t seq; 949158737Sambrisko uint32_t time; 950158737Sambrisko uint32_t code; 951222589Semaste union mfi_evt evt_class; 952158737Sambrisko uint8_t arg_type; 953158737Sambrisko uint8_t reserved1[15]; 954158737Sambrisko 955158737Sambrisko union { 956158737Sambrisko struct { 957158737Sambrisko struct mfi_evt_pd pd; 958158737Sambrisko uint8_t cdb_len; 959158737Sambrisko uint8_t sense_len; 960158737Sambrisko uint8_t reserved[2]; 961158737Sambrisko uint8_t cdb[16]; 962158737Sambrisko uint8_t sense[64]; 963158737Sambrisko } cdb_sense; 964158737Sambrisko 965158737Sambrisko struct mfi_evt_ld ld; 966158737Sambrisko 967158737Sambrisko struct { 968158737Sambrisko struct mfi_evt_ld ld; 969158737Sambrisko uint64_t count; 970158737Sambrisko } ld_count; 971158737Sambrisko 972158737Sambrisko struct { 973158737Sambrisko uint64_t lba; 974158737Sambrisko struct mfi_evt_ld ld; 975158737Sambrisko } ld_lba; 976158737Sambrisko 977158737Sambrisko struct { 978158737Sambrisko struct mfi_evt_ld ld; 979158737Sambrisko uint32_t pre_owner; 980158737Sambrisko uint32_t new_owner; 981158737Sambrisko } ld_owner; 982158737Sambrisko 983158737Sambrisko struct { 984158737Sambrisko uint64_t ld_lba; 985158737Sambrisko uint64_t pd_lba; 986158737Sambrisko struct mfi_evt_ld ld; 987158737Sambrisko struct mfi_evt_pd pd; 988158737Sambrisko } ld_lba_pd_lba; 989158737Sambrisko 990158737Sambrisko struct { 991158737Sambrisko struct mfi_evt_ld ld; 992158737Sambrisko struct mfi_progress prog; 993158737Sambrisko } ld_prog; 994158737Sambrisko 995158737Sambrisko struct { 996158737Sambrisko struct mfi_evt_ld ld; 997158737Sambrisko uint32_t prev_state; 998158737Sambrisko uint32_t new_state; 999158737Sambrisko } ld_state; 1000158737Sambrisko 1001158737Sambrisko struct { 1002158737Sambrisko uint64_t strip; 1003158737Sambrisko struct mfi_evt_ld ld; 1004158737Sambrisko } ld_strip; 1005158737Sambrisko 1006158737Sambrisko struct mfi_evt_pd pd; 1007158737Sambrisko 1008158737Sambrisko struct { 1009158737Sambrisko struct mfi_evt_pd pd; 1010158737Sambrisko uint32_t err; 1011158737Sambrisko } pd_err; 1012158737Sambrisko 1013158737Sambrisko struct { 1014158737Sambrisko uint64_t lba; 1015158737Sambrisko struct mfi_evt_pd pd; 1016158737Sambrisko } pd_lba; 1017158737Sambrisko 1018158737Sambrisko struct { 1019158737Sambrisko uint64_t lba; 1020158737Sambrisko struct mfi_evt_pd pd; 1021158737Sambrisko struct mfi_evt_ld ld; 1022158737Sambrisko } pd_lba_ld; 1023158737Sambrisko 1024158737Sambrisko struct { 1025158737Sambrisko struct mfi_evt_pd pd; 1026158737Sambrisko struct mfi_progress prog; 1027158737Sambrisko } pd_prog; 1028158737Sambrisko 1029158737Sambrisko struct { 1030158737Sambrisko struct mfi_evt_pd ld; 1031158737Sambrisko uint32_t prev_state; 1032158737Sambrisko uint32_t new_state; 1033158737Sambrisko } pd_state; 1034158737Sambrisko 1035158737Sambrisko struct { 1036158737Sambrisko uint16_t venderId; 1037158737Sambrisko uint16_t deviceId; 1038158737Sambrisko uint16_t subVenderId; 1039158737Sambrisko uint16_t subDeviceId; 1040158737Sambrisko } pci; 1041158737Sambrisko 1042158737Sambrisko uint32_t rate; 1043158737Sambrisko 1044158737Sambrisko char str[96]; 1045158737Sambrisko 1046158737Sambrisko struct { 1047158737Sambrisko uint32_t rtc; 1048158737Sambrisko uint16_t elapsedSeconds; 1049158737Sambrisko } time; 1050158737Sambrisko 1051158737Sambrisko struct { 1052158737Sambrisko uint32_t ecar; 1053158737Sambrisko uint32_t elog; 1054158737Sambrisko char str[64]; 1055158737Sambrisko } ecc; 1056158737Sambrisko 1057158737Sambrisko uint8_t b[96]; 1058158737Sambrisko uint16_t s[48]; 1059158737Sambrisko uint32_t w[24]; 1060158737Sambrisko uint64_t d[12]; 1061158737Sambrisko } args; 1062158737Sambrisko 1063158737Sambrisko char description[128]; 1064158737Sambrisko} __packed; 1065158737Sambrisko 1066162118Sambriskostruct mfi_evt_list { 1067162118Sambrisko uint32_t count; 1068162118Sambrisko uint32_t reserved; 1069162118Sambrisko struct mfi_evt_detail event[1]; 1070158737Sambrisko} __packed; 1071158737Sambrisko 1072163398Sscottlunion mfi_pd_ref { 1073163398Sscottl struct { 1074163398Sscottl uint16_t device_id; 1075163398Sscottl uint16_t seq_num; 1076163398Sscottl } v; 1077163398Sscottl uint32_t ref; 1078159811Sps} __packed; 1079159811Sps 1080163398Sscottlunion mfi_pd_ddf_type { 1081163398Sscottl struct { 1082163398Sscottl union { 1083163398Sscottl struct { 1084163398Sscottl uint16_t forced_pd_guid : 1; 1085163398Sscottl uint16_t in_vd : 1; 1086163398Sscottl uint16_t is_global_spare : 1; 1087163398Sscottl uint16_t is_spare : 1; 1088163398Sscottl uint16_t is_foreign : 1; 1089163398Sscottl uint16_t reserved : 7; 1090163398Sscottl uint16_t intf : 4; 1091163398Sscottl } pd_type; 1092163398Sscottl uint16_t type; 1093163398Sscottl } v; 1094163398Sscottl uint16_t reserved; 1095163398Sscottl } ddf; 1096163398Sscottl struct { 1097163398Sscottl uint32_t reserved; 1098163398Sscottl } non_disk; 1099163398Sscottl uint32_t type; 1100163398Sscottl} __packed; 1101163398Sscottl 1102163398Sscottlstruct mfi_pd_progress { 1103196200Sscottl uint32_t active; 1104196200Sscottl#define MFI_PD_PROGRESS_REBUILD (1<<0) 1105196200Sscottl#define MFI_PD_PROGRESS_PATROL (1<<1) 1106196200Sscottl#define MFI_PD_PROGRESS_CLEAR (1<<2) 1107163398Sscottl struct mfi_progress rbld; 1108163398Sscottl struct mfi_progress patrol; 1109163398Sscottl struct mfi_progress clear; 1110163398Sscottl struct mfi_progress reserved[4]; 1111163398Sscottl} __packed; 1112163398Sscottl 1113163398Sscottlstruct mfi_pd_info { 1114163398Sscottl union mfi_pd_ref ref; 1115163398Sscottl uint8_t inquiry_data[96]; 1116163398Sscottl uint8_t vpd_page83[64]; 1117163398Sscottl uint8_t not_supported; 1118163398Sscottl uint8_t scsi_dev_type; 1119163398Sscottl uint8_t connected_port_bitmap; 1120163398Sscottl uint8_t device_speed; 1121163398Sscottl uint32_t media_err_count; 1122163398Sscottl uint32_t other_err_count; 1123163398Sscottl uint32_t pred_fail_count; 1124163398Sscottl uint32_t last_pred_fail_event_seq_num; 1125196200Sscottl uint16_t fw_state; /* MFI_PD_STATE_* */ 1126196200Sscottl uint8_t disabled_for_removal; 1127163398Sscottl uint8_t link_speed; 1128163398Sscottl union mfi_pd_ddf_type state; 1129163398Sscottl struct { 1130163398Sscottl uint8_t count; 1131163398Sscottl uint8_t is_path_broken; 1132163398Sscottl uint8_t reserved[6]; 1133163398Sscottl uint64_t sas_addr[4]; 1134163398Sscottl } path_info; 1135163398Sscottl uint64_t raw_size; 1136163398Sscottl uint64_t non_coerced_size; 1137163398Sscottl uint64_t coerced_size; 1138163398Sscottl uint16_t encl_device_id; 1139163398Sscottl uint8_t encl_index; 1140163398Sscottl uint8_t slot_number; 1141163398Sscottl struct mfi_pd_progress prog_info; 1142163398Sscottl uint8_t bad_block_table_full; 1143163398Sscottl uint8_t unusable_in_current_config; 1144163398Sscottl uint8_t vpd_page83_ext[64]; 1145163398Sscottl uint8_t reserved[512-358]; 1146163398Sscottl} __packed; 1147163398Sscottl 1148163398Sscottlstruct mfi_pd_address { 1149163398Sscottl uint16_t device_id; 1150163398Sscottl uint16_t encl_device_id; 1151163398Sscottl uint8_t encl_index; 1152163398Sscottl uint8_t slot_number; 1153196200Sscottl uint8_t scsi_dev_type; /* 0 = disk */ 1154163398Sscottl uint8_t connect_port_bitmap; 1155163398Sscottl uint64_t sas_addr[2]; 1156163398Sscottl} __packed; 1157163398Sscottl 1158234429Sambrisko#define MAX_SYS_PDS 240 1159163398Sscottlstruct mfi_pd_list { 1160163398Sscottl uint32_t size; 1161163398Sscottl uint32_t count; 1162234429Sambrisko struct mfi_pd_address addr[MAX_SYS_PDS]; 1163163398Sscottl} __packed; 1164163398Sscottl 1165196200Sscottlenum mfi_pd_state { 1166196200Sscottl MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1167196200Sscottl MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1168196200Sscottl MFI_PD_STATE_HOT_SPARE = 0x02, 1169196200Sscottl MFI_PD_STATE_OFFLINE = 0x10, 1170196200Sscottl MFI_PD_STATE_FAILED = 0x11, 1171196200Sscottl MFI_PD_STATE_REBUILD = 0x14, 1172214130Spluknet MFI_PD_STATE_ONLINE = 0x18, 1173214130Spluknet MFI_PD_STATE_COPYBACK = 0x20, 1174214130Spluknet MFI_PD_STATE_SYSTEM = 0x40 1175196200Sscottl}; 1176196200Sscottl 1177234429Sambrisko/* 1178234429Sambrisko * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1179234429Sambrisko * Adding a #define to denote this. 1180234429Sambrisko */ 1181234429Sambrisko#define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1182234429Sambrisko 1183163398Sscottlunion mfi_ld_ref { 1184163398Sscottl struct { 1185163398Sscottl uint8_t target_id; 1186163398Sscottl uint8_t reserved; 1187163398Sscottl uint16_t seq; 1188163398Sscottl } v; 1189163398Sscottl uint32_t ref; 1190163398Sscottl} __packed; 1191163398Sscottl 1192159811Spsstruct mfi_ld_list { 1193159811Sps uint32_t ld_count; 1194159811Sps uint32_t reserved1; 1195159811Sps struct { 1196163398Sscottl union mfi_ld_ref ld; 1197159811Sps uint8_t state; 1198159811Sps uint8_t reserved2[3]; 1199159811Sps uint64_t size; 1200159811Sps } ld_list[MFI_MAX_LD]; 1201159811Sps} __packed; 1202159811Sps 1203159811Spsenum mfi_ld_access { 1204159811Sps MFI_LD_ACCESS_RW = 0, 1205159811Sps MFI_LD_ACCSSS_RO = 2, 1206159811Sps MFI_LD_ACCESS_BLOCKED = 3, 1207159811Sps}; 1208159811Sps#define MFI_LD_ACCESS_MASK 3 1209159811Sps 1210159811Spsenum mfi_ld_state { 1211159811Sps MFI_LD_STATE_OFFLINE = 0, 1212159811Sps MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1213159811Sps MFI_LD_STATE_DEGRADED = 2, 1214159811Sps MFI_LD_STATE_OPTIMAL = 3 1215159811Sps}; 1216159811Sps 1217159811Spsstruct mfi_ld_props { 1218163398Sscottl union mfi_ld_ref ld; 1219159811Sps char name[16]; 1220159811Sps uint8_t default_cache_policy; 1221159811Sps uint8_t access_policy; 1222159811Sps uint8_t disk_cache_policy; 1223159811Sps uint8_t current_cache_policy; 1224159811Sps uint8_t no_bgi; 1225159811Sps uint8_t reserved[7]; 1226159811Sps} __packed; 1227159811Sps 1228159811Spsstruct mfi_ld_params { 1229159811Sps uint8_t primary_raid_level; 1230159811Sps uint8_t raid_level_qualifier; 1231159811Sps uint8_t secondary_raid_level; 1232159811Sps uint8_t stripe_size; 1233159811Sps uint8_t num_drives; 1234159811Sps uint8_t span_depth; 1235159811Sps uint8_t state; 1236159811Sps uint8_t init_state; 1237196200Sscottl#define MFI_LD_PARAMS_INIT_NO 0 1238196200Sscottl#define MFI_LD_PARAMS_INIT_QUICK 1 1239196200Sscottl#define MFI_LD_PARAMS_INIT_FULL 2 1240159811Sps uint8_t is_consistent; 1241234429Sambrisko uint8_t reserved1[6]; 1242234429Sambrisko uint8_t isSSCD; 1243234429Sambrisko uint8_t reserved2[16]; 1244159811Sps} __packed; 1245159811Sps 1246159811Spsstruct mfi_ld_progress { 1247159811Sps uint32_t active; 1248159811Sps#define MFI_LD_PROGRESS_CC (1<<0) 1249159811Sps#define MFI_LD_PROGRESS_BGI (1<<1) 1250159811Sps#define MFI_LD_PROGRESS_FGI (1<<2) 1251196200Sscottl#define MFI_LD_PROGRESS_RECON (1<<3) 1252159811Sps struct mfi_progress cc; 1253159811Sps struct mfi_progress bgi; 1254159811Sps struct mfi_progress fgi; 1255159811Sps struct mfi_progress recon; 1256159811Sps struct mfi_progress reserved[4]; 1257159811Sps} __packed; 1258159811Sps 1259159811Spsstruct mfi_span { 1260159811Sps uint64_t start_block; 1261159811Sps uint64_t num_blocks; 1262159811Sps uint16_t array_ref; 1263159811Sps uint8_t reserved[6]; 1264159811Sps} __packed; 1265159811Sps 1266159811Sps#define MFI_MAX_SPAN_DEPTH 8 1267159811Spsstruct mfi_ld_config { 1268159811Sps struct mfi_ld_props properties; 1269159811Sps struct mfi_ld_params params; 1270159811Sps struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1271159811Sps} __packed; 1272159811Sps 1273159811Spsstruct mfi_ld_info { 1274159811Sps struct mfi_ld_config ld_config; 1275159811Sps uint64_t size; 1276159811Sps struct mfi_ld_progress progress; 1277159811Sps uint16_t cluster_owner; 1278159811Sps uint8_t reconstruct_active; 1279159811Sps uint8_t reserved1[1]; 1280159811Sps uint8_t vpd_page83[64]; 1281159811Sps uint8_t reserved2[16]; 1282159811Sps} __packed; 1283159811Sps 1284234429Sambrisko#define MFI_MAX_ARRAYS 16 1285163398Sscottlstruct mfi_spare { 1286163398Sscottl union mfi_pd_ref ref; 1287196200Sscottl uint8_t spare_type; 1288196200Sscottl#define MFI_SPARE_DEDICATED (1 << 0) 1289196200Sscottl#define MFI_SPARE_REVERTIBLE (1 << 1) 1290196200Sscottl#define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1291163398Sscottl uint8_t reserved[2]; 1292163398Sscottl uint8_t array_count; 1293234429Sambrisko uint16_t array_ref[MFI_MAX_ARRAYS]; 1294163398Sscottl} __packed; 1295163398Sscottl 1296234429Sambrisko#define MFI_MAX_ROW_SIZE 32 1297163398Sscottlstruct mfi_array { 1298163398Sscottl uint64_t size; 1299163398Sscottl uint8_t num_drives; 1300163398Sscottl uint8_t reserved; 1301163398Sscottl uint16_t array_ref; 1302163398Sscottl uint8_t pad[20]; 1303163398Sscottl struct { 1304196200Sscottl union mfi_pd_ref ref; /* 0xffff == missing drive */ 1305196200Sscottl uint16_t fw_state; /* MFI_PD_STATE_* */ 1306163398Sscottl struct { 1307163398Sscottl uint8_t pd; 1308163398Sscottl uint8_t slot; 1309163398Sscottl } encl; 1310234429Sambrisko } pd[MFI_MAX_ROW_SIZE]; 1311163398Sscottl} __packed; 1312163398Sscottl 1313163398Sscottlstruct mfi_config_data { 1314163398Sscottl uint32_t size; 1315163398Sscottl uint16_t array_count; 1316163398Sscottl uint16_t array_size; 1317163398Sscottl uint16_t log_drv_count; 1318163398Sscottl uint16_t log_drv_size; 1319163398Sscottl uint16_t spares_count; 1320163398Sscottl uint16_t spares_size; 1321163398Sscottl uint8_t reserved[16]; 1322196200Sscottl struct mfi_array array[0]; 1323196200Sscottl struct mfi_ld_config ld[0]; 1324196200Sscottl struct mfi_spare spare[0]; 1325163398Sscottl} __packed; 1326163398Sscottl 1327196200Sscottlstruct mfi_bbu_capacity_info { 1328196200Sscottl uint16_t relative_charge; 1329196200Sscottl uint16_t absolute_charge; 1330196200Sscottl uint16_t remaining_capacity; 1331196200Sscottl uint16_t full_charge_capacity; 1332196200Sscottl uint16_t run_time_to_empty; 1333196200Sscottl uint16_t average_time_to_empty; 1334196200Sscottl uint16_t average_time_to_full; 1335196200Sscottl uint16_t cycle_count; 1336196200Sscottl uint16_t max_error; 1337196200Sscottl uint16_t remaining_capacity_alarm; 1338196200Sscottl uint16_t remaining_time_alarm; 1339196200Sscottl uint8_t reserved[26]; 1340196200Sscottl} __packed; 1341196200Sscottl 1342196200Sscottlstruct mfi_bbu_design_info { 1343196200Sscottl uint32_t mfg_date; 1344196200Sscottl uint16_t design_capacity; 1345196200Sscottl uint16_t design_voltage; 1346196200Sscottl uint16_t spec_info; 1347196200Sscottl uint16_t serial_number; 1348196200Sscottl uint16_t pack_stat_config; 1349196200Sscottl uint8_t mfg_name[12]; 1350196200Sscottl uint8_t device_name[8]; 1351196200Sscottl uint8_t device_chemistry[8]; 1352196200Sscottl uint8_t mfg_data[8]; 1353196200Sscottl uint8_t reserved[17]; 1354196200Sscottl} __packed; 1355196200Sscottl 1356196200Sscottlstruct mfi_ibbu_state { 1357196200Sscottl uint16_t gas_guage_status; 1358196200Sscottl uint16_t relative_charge; 1359196200Sscottl uint16_t charger_system_state; 1360196200Sscottl uint16_t charger_system_ctrl; 1361196200Sscottl uint16_t charging_current; 1362196200Sscottl uint16_t absolute_charge; 1363196200Sscottl uint16_t max_error; 1364196200Sscottl uint8_t reserved[18]; 1365196200Sscottl} __packed; 1366196200Sscottl 1367196200Sscottlstruct mfi_bbu_state { 1368196200Sscottl uint16_t gas_guage_status; 1369196200Sscottl uint16_t relative_charge; 1370196200Sscottl uint16_t charger_status; 1371196200Sscottl uint16_t remaining_capacity; 1372196200Sscottl uint16_t full_charge_capacity; 1373196200Sscottl uint8_t is_SOH_good; 1374196200Sscottl uint8_t reserved[21]; 1375196200Sscottl} __packed; 1376196200Sscottl 1377250482Smarkjstruct mfi_bbu_properties { 1378250482Smarkj uint32_t auto_learn_period; 1379250482Smarkj uint32_t next_learn_time; 1380250482Smarkj uint8_t learn_delay_interval; 1381250482Smarkj uint8_t auto_learn_mode; 1382250482Smarkj uint8_t bbu_mode; 1383250482Smarkj uint8_t reserved[21]; 1384250482Smarkj} __packed; 1385250482Smarkj 1386196200Sscottlunion mfi_bbu_status_detail { 1387196200Sscottl struct mfi_ibbu_state ibbu; 1388196200Sscottl struct mfi_bbu_state bbu; 1389196200Sscottl}; 1390196200Sscottl 1391196200Sscottlstruct mfi_bbu_status { 1392196200Sscottl uint8_t battery_type; 1393196200Sscottl#define MFI_BBU_TYPE_NONE 0 1394196200Sscottl#define MFI_BBU_TYPE_IBBU 1 1395234429Sambrisko#define MFI_BBU_TYPE_BBU 2 1396196200Sscottl uint8_t reserved; 1397196200Sscottl uint16_t voltage; 1398196200Sscottl int16_t current; 1399196200Sscottl uint16_t temperature; 1400196200Sscottl uint32_t fw_status; 1401196200Sscottl#define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1402196200Sscottl#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1403196200Sscottl#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1404235738Ssbruno#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1405235738Ssbruno#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1406235738Ssbruno#define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1407235738Ssbruno#define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1408235738Ssbruno#define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1409235738Ssbruno#define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1410235738Ssbruno#define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1411196200Sscottl uint8_t pad[20]; 1412196200Sscottl union mfi_bbu_status_detail detail; 1413196200Sscottl} __packed; 1414196200Sscottl 1415196200Sscottlenum mfi_pr_state { 1416196200Sscottl MFI_PR_STATE_STOPPED = 0, 1417196200Sscottl MFI_PR_STATE_READY = 1, 1418196200Sscottl MFI_PR_STATE_ACTIVE = 2, 1419196200Sscottl MFI_PR_STATE_ABORTED = 0xff 1420196200Sscottl}; 1421196200Sscottl 1422196200Sscottlstruct mfi_pr_status { 1423196200Sscottl uint32_t num_iteration; 1424196200Sscottl uint8_t state; 1425196200Sscottl uint8_t num_pd_done; 1426196200Sscottl uint8_t reserved[10]; 1427196200Sscottl}; 1428196200Sscottl 1429196200Sscottlenum mfi_pr_opmode { 1430196200Sscottl MFI_PR_OPMODE_AUTO = 0, 1431196200Sscottl MFI_PR_OPMODE_MANUAL = 1, 1432196200Sscottl MFI_PR_OPMODE_DISABLED = 2 1433196200Sscottl}; 1434196200Sscottl 1435196200Sscottlstruct mfi_pr_properties { 1436196200Sscottl uint8_t op_mode; 1437196200Sscottl uint8_t max_pd; 1438196200Sscottl uint8_t reserved; 1439196200Sscottl uint8_t exclude_ld_count; 1440196200Sscottl uint16_t excluded_ld[MFI_MAX_LD]; 1441196200Sscottl uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1442196200Sscottl uint8_t last_pd_map[MFI_MAX_PD / 8]; 1443196200Sscottl uint32_t next_exec; 1444196200Sscottl uint32_t exec_freq; 1445196200Sscottl uint32_t clear_freq; 1446196200Sscottl}; 1447196200Sscottl 1448234429Sambrisko/* ThunderBolt support */ 1449234429Sambrisko 1450234429Sambrisko/* 1451234429Sambrisko * Raid Context structure which describes MegaRAID specific IO Paramenters 1452234429Sambrisko * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1453234429Sambrisko */ 1454234429Sambriskotypedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1455234429Sambrisko uint16_t resvd0; /* 0x00 - 0x01 */ 1456234429Sambrisko uint16_t timeoutValue; /* 0x02 - 0x03 */ 1457234429Sambrisko uint8_t regLockFlags; 1458234429Sambrisko uint8_t armId; 1459234429Sambrisko uint16_t TargetID; /* 0x06 - 0x07 */ 1460234429Sambrisko 1461234429Sambrisko uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1462234429Sambrisko 1463234429Sambrisko uint32_t RegLockLength; /* 0x10 - 0x13 */ 1464234429Sambrisko 1465234429Sambrisko uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1466234429Sambrisko uint8_t exStatus; /* 0x16 */ 1467234429Sambrisko uint8_t Status; /* 0x17 status */ 1468234429Sambrisko 1469234429Sambrisko uint8_t RAIDFlags; /* 0x18 */ 1470234429Sambrisko uint8_t numSGE; /* 0x19 numSge */ 1471234429Sambrisko uint16_t configSeqNum; /* 0x1A - 0x1B */ 1472234429Sambrisko uint8_t spanArm; /* 0x1C */ 1473234429Sambrisko uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1474234429Sambrisko} MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1475234429Sambrisko 1476234429Sambrisko/***************************************************************************** 1477234429Sambrisko* 1478234429Sambrisko* Message Functions 1479234429Sambrisko* 1480234429Sambrisko*****************************************************************************/ 1481234429Sambrisko 1482234429Sambrisko#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1483234429Sambrisko#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1484234429Sambrisko#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1485234429Sambrisko#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1486234429Sambrisko#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1487234429Sambrisko#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1488234429Sambrisko#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1489234429Sambrisko#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1490234429Sambrisko#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1491234429Sambrisko#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1492234429Sambrisko#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1493234429Sambrisko#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1494234429Sambrisko#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1495234429Sambrisko#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1496234429Sambrisko#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1497234429Sambrisko#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1498234429Sambrisko#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1499234429Sambrisko#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1500234429Sambrisko#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1501234429Sambrisko#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1502234429Sambrisko#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1503234429Sambrisko#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1504234429Sambrisko#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1505234429Sambrisko#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1506234429Sambrisko#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1507234429Sambrisko#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1508234429Sambrisko#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1509234429Sambrisko#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1510234429Sambrisko#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1511234429Sambrisko#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1512234429Sambrisko 1513234429Sambrisko/* Doorbell functions */ 1514234429Sambrisko#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1515234429Sambrisko#define MPI2_FUNCTION_HANDSHAKE (0x42) 1516234429Sambrisko 1517234429Sambrisko/***************************************************************************** 1518234429Sambrisko* 1519234429Sambrisko* MPI Version Definitions 1520234429Sambrisko* 1521234429Sambrisko*****************************************************************************/ 1522234429Sambrisko 1523234429Sambrisko#define MPI2_VERSION_MAJOR (0x02) 1524234429Sambrisko#define MPI2_VERSION_MINOR (0x00) 1525234429Sambrisko#define MPI2_VERSION_MAJOR_MASK (0xFF00) 1526234429Sambrisko#define MPI2_VERSION_MAJOR_SHIFT (8) 1527234429Sambrisko#define MPI2_VERSION_MINOR_MASK (0x00FF) 1528234429Sambrisko#define MPI2_VERSION_MINOR_SHIFT (0) 1529234429Sambrisko#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1530234429Sambrisko MPI2_VERSION_MINOR) 1531234429Sambrisko 1532234429Sambrisko#define MPI2_VERSION_02_00 (0x0200) 1533234429Sambrisko 1534234429Sambrisko/* versioning for this MPI header set */ 1535234429Sambrisko#define MPI2_HEADER_VERSION_UNIT (0x10) 1536234429Sambrisko#define MPI2_HEADER_VERSION_DEV (0x00) 1537234429Sambrisko#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1538234429Sambrisko#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1539234429Sambrisko#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1540234429Sambrisko#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1541234429Sambrisko#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1542234429Sambrisko MPI2_HEADER_VERSION_DEV) 1543234429Sambrisko 1544234429Sambrisko 1545234429Sambrisko/* IOCInit Request message */ 1546234429Sambriskostruct MPI2_IOC_INIT_REQUEST { 1547234429Sambrisko uint8_t WhoInit; /* 0x00 */ 1548234429Sambrisko uint8_t Reserved1; /* 0x01 */ 1549234429Sambrisko uint8_t ChainOffset; /* 0x02 */ 1550234429Sambrisko uint8_t Function; /* 0x03 */ 1551234429Sambrisko uint16_t Reserved2; /* 0x04 */ 1552234429Sambrisko uint8_t Reserved3; /* 0x06 */ 1553234429Sambrisko uint8_t MsgFlags; /* 0x07 */ 1554234429Sambrisko uint8_t VP_ID; /* 0x08 */ 1555234429Sambrisko uint8_t VF_ID; /* 0x09 */ 1556234429Sambrisko uint16_t Reserved4; /* 0x0A */ 1557234429Sambrisko uint16_t MsgVersion; /* 0x0C */ 1558234429Sambrisko uint16_t HeaderVersion; /* 0x0E */ 1559234429Sambrisko uint32_t Reserved5; /* 0x10 */ 1560234429Sambrisko uint16_t Reserved6; /* 0x14 */ 1561234429Sambrisko uint8_t Reserved7; /* 0x16 */ 1562234429Sambrisko uint8_t HostMSIxVectors; /* 0x17 */ 1563234429Sambrisko uint16_t Reserved8; /* 0x18 */ 1564234429Sambrisko uint16_t SystemRequestFrameSize; /* 0x1A */ 1565234429Sambrisko uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1566234429Sambrisko uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1567234429Sambrisko uint32_t SenseBufferAddressHigh; /* 0x20 */ 1568234429Sambrisko uint32_t SystemReplyAddressHigh; /* 0x24 */ 1569234429Sambrisko uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1570234429Sambrisko uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1571234429Sambrisko uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1572234429Sambrisko uint64_t TimeStamp; /* 0x40 */ 1573234429Sambrisko}; 1574234429Sambrisko 1575234429Sambrisko/* WhoInit values */ 1576234429Sambrisko#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1577234429Sambrisko#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1578234429Sambrisko#define MPI2_WHOINIT_ROM_BIOS (0x02) 1579234429Sambrisko#define MPI2_WHOINIT_PCI_PEER (0x03) 1580234429Sambrisko#define MPI2_WHOINIT_HOST_DRIVER (0x04) 1581234429Sambrisko#define MPI2_WHOINIT_MANUFACTURER (0x05) 1582234429Sambrisko 1583234429Sambriskostruct MPI2_SGE_CHAIN_UNION { 1584234429Sambrisko uint16_t Length; 1585234429Sambrisko uint8_t NextChainOffset; 1586234429Sambrisko uint8_t Flags; 1587234429Sambrisko union { 1588234429Sambrisko uint32_t Address32; 1589234429Sambrisko uint64_t Address64; 1590234429Sambrisko } u; 1591234429Sambrisko}; 1592234429Sambrisko 1593234429Sambriskostruct MPI2_IEEE_SGE_SIMPLE32 { 1594234429Sambrisko uint32_t Address; 1595234429Sambrisko uint32_t FlagsLength; 1596234429Sambrisko}; 1597234429Sambrisko 1598234429Sambriskostruct MPI2_IEEE_SGE_SIMPLE64 { 1599234429Sambrisko uint64_t Address; 1600234429Sambrisko uint32_t Length; 1601234429Sambrisko uint16_t Reserved1; 1602234429Sambrisko uint8_t Reserved2; 1603234429Sambrisko uint8_t Flags; 1604234429Sambrisko}; 1605234429Sambrisko 1606234429Sambriskotypedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1607234429Sambrisko struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1608234429Sambrisko struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1609234429Sambrisko} MPI2_IEEE_SGE_SIMPLE_UNION; 1610234429Sambrisko 1611234429Sambriskotypedef struct _MPI2_SGE_SIMPLE_UNION { 1612234429Sambrisko uint32_t FlagsLength; 1613234429Sambrisko union { 1614234429Sambrisko uint32_t Address32; 1615234429Sambrisko uint64_t Address64; 1616234429Sambrisko } u; 1617234429Sambrisko} MPI2_SGE_SIMPLE_UNION; 1618234429Sambrisko 1619234429Sambrisko/**************************************************************************** 1620234429Sambrisko* IEEE SGE field definitions and masks 1621234429Sambrisko****************************************************************************/ 1622234429Sambrisko 1623234429Sambrisko/* Flags field bit definitions */ 1624234429Sambrisko 1625234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1626234429Sambrisko 1627234429Sambrisko#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1628234429Sambrisko 1629234429Sambrisko#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1630234429Sambrisko 1631234429Sambrisko/* Element Type */ 1632234429Sambrisko 1633234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1634234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1635234429Sambrisko 1636234429Sambrisko/* Data Location Address Space */ 1637234429Sambrisko 1638234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1639234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1640234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1641234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1642234429Sambrisko#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1643234429Sambrisko 1644234429Sambrisko/* Address Size */ 1645234429Sambrisko 1646234429Sambrisko#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1647234429Sambrisko#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1648234429Sambrisko 1649234429Sambrisko/*******************/ 1650234429Sambrisko/* SCSI IO Control bits */ 1651234429Sambrisko#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1652234429Sambrisko#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1653234429Sambrisko 1654234429Sambrisko#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1655234429Sambrisko#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1656234429Sambrisko#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1657234429Sambrisko#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1658234429Sambrisko#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1659234429Sambrisko 1660234429Sambrisko#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1661234429Sambrisko#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1662234429Sambrisko 1663234429Sambrisko#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1664234429Sambrisko#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1665234429Sambrisko#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1666234429Sambrisko#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1667234429Sambrisko#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1668234429Sambrisko 1669234429Sambrisko#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1670234429Sambrisko#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1671234429Sambrisko#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1672234429Sambrisko#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1673234429Sambrisko 1674234429Sambrisko/*******************/ 1675234429Sambrisko 1676234429Sambriskotypedef struct { 1677234429Sambrisko uint8_t CDB[20]; /* 0x00 */ 1678234429Sambrisko uint32_t PrimaryReferenceTag; /* 0x14 */ 1679234429Sambrisko uint16_t PrimaryApplicationTag; /* 0x18 */ 1680234429Sambrisko uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1681234429Sambrisko uint32_t TransferLength; /* 0x1C */ 1682234429Sambrisko} MPI2_SCSI_IO_CDB_EEDP32; 1683234429Sambrisko 1684234429Sambrisko 1685234429Sambriskotypedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1686234429Sambrisko struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1687234429Sambrisko struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1688234429Sambrisko} MPI2_IEEE_SGE_CHAIN_UNION; 1689234429Sambrisko 1690234429Sambriskotypedef union _MPI2_SIMPLE_SGE_UNION { 1691234429Sambrisko MPI2_SGE_SIMPLE_UNION MpiSimple; 1692234429Sambrisko MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1693234429Sambrisko} MPI2_SIMPLE_SGE_UNION; 1694234429Sambrisko 1695234429Sambriskotypedef union _MPI2_SGE_IO_UNION { 1696234429Sambrisko MPI2_SGE_SIMPLE_UNION MpiSimple; 1697234429Sambrisko struct MPI2_SGE_CHAIN_UNION MpiChain; 1698234429Sambrisko MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1699234429Sambrisko MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1700234429Sambrisko} MPI2_SGE_IO_UNION; 1701234429Sambrisko 1702234429Sambriskotypedef union { 1703234429Sambrisko uint8_t CDB32[32]; 1704234429Sambrisko MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1705234429Sambrisko MPI2_SGE_SIMPLE_UNION SGE; 1706234429Sambrisko} MPI2_SCSI_IO_CDB_UNION; 1707234429Sambrisko 1708234429Sambrisko 1709234429Sambrisko/* MPI 2.5 SGLs */ 1710234429Sambrisko 1711234429Sambrisko#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1712234429Sambrisko 1713234429Sambriskotypedef struct _MPI25_IEEE_SGE_CHAIN64 { 1714234429Sambrisko uint64_t Address; 1715234429Sambrisko uint32_t Length; 1716234429Sambrisko uint16_t Reserved1; 1717234429Sambrisko uint8_t NextChainOffset; 1718234429Sambrisko uint8_t Flags; 1719234429Sambrisko} MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1720234429Sambrisko 1721234429Sambrisko/* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1722234429Sambrisko 1723234429Sambrisko 1724234429Sambrisko/********/ 1725234429Sambrisko 1726234429Sambrisko/* 1727234429Sambrisko * RAID SCSI IO Request Message 1728234429Sambrisko * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1729234429Sambrisko */ 1730234429Sambriskostruct mfi_mpi2_request_raid_scsi_io { 1731234429Sambrisko uint16_t DevHandle; /* 0x00 */ 1732234429Sambrisko uint8_t ChainOffset; /* 0x02 */ 1733234429Sambrisko uint8_t Function; /* 0x03 */ 1734234429Sambrisko uint16_t Reserved1; /* 0x04 */ 1735234429Sambrisko uint8_t Reserved2; /* 0x06 */ 1736234429Sambrisko uint8_t MsgFlags; /* 0x07 */ 1737234429Sambrisko uint8_t VP_ID; /* 0x08 */ 1738234429Sambrisko uint8_t VF_ID; /* 0x09 */ 1739234429Sambrisko uint16_t Reserved3; /* 0x0A */ 1740234429Sambrisko uint32_t SenseBufferLowAddress; /* 0x0C */ 1741234429Sambrisko uint16_t SGLFlags; /* 0x10 */ 1742234429Sambrisko uint8_t SenseBufferLength; /* 0x12 */ 1743234429Sambrisko uint8_t Reserved4; /* 0x13 */ 1744234429Sambrisko uint8_t SGLOffset0; /* 0x14 */ 1745234429Sambrisko uint8_t SGLOffset1; /* 0x15 */ 1746234429Sambrisko uint8_t SGLOffset2; /* 0x16 */ 1747234429Sambrisko uint8_t SGLOffset3; /* 0x17 */ 1748234429Sambrisko uint32_t SkipCount; /* 0x18 */ 1749234429Sambrisko uint32_t DataLength; /* 0x1C */ 1750234429Sambrisko uint32_t BidirectionalDataLength; /* 0x20 */ 1751234429Sambrisko uint16_t IoFlags; /* 0x24 */ 1752234429Sambrisko uint16_t EEDPFlags; /* 0x26 */ 1753234429Sambrisko uint32_t EEDPBlockSize; /* 0x28 */ 1754234429Sambrisko uint32_t SecondaryReferenceTag; /* 0x2C */ 1755234429Sambrisko uint16_t SecondaryApplicationTag; /* 0x30 */ 1756234429Sambrisko uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1757234429Sambrisko uint8_t LUN[8]; /* 0x34 */ 1758234429Sambrisko uint32_t Control; /* 0x3C */ 1759234429Sambrisko MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1760234429Sambrisko MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1761234429Sambrisko MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1762234429Sambrisko} __packed; 1763234429Sambrisko 1764234429Sambrisko/* 1765234429Sambrisko * MPT RAID MFA IO Descriptor. 1766234429Sambrisko */ 1767234429Sambriskotypedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1768234429Sambrisko uint32_t RequestFlags : 8; 1769234429Sambrisko uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1770234429Sambrisko uint32_t MessageAddress2; /* bits 61:32 */ 1771234429Sambrisko} MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1772234429Sambrisko 1773234429Sambriskostruct mfi_mpi2_request_header { 1774234429Sambrisko uint8_t RequestFlags; /* 0x00 */ 1775234429Sambrisko uint8_t MSIxIndex; /* 0x01 */ 1776234429Sambrisko uint16_t SMID; /* 0x02 */ 1777234429Sambrisko uint16_t LMID; /* 0x04 */ 1778234429Sambrisko}; 1779234429Sambrisko 1780234429Sambrisko/* defines for the RequestFlags field */ 1781234429Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1782234429Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1783234429Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1784234429Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1785234429Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1786234429Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1787234429Sambrisko 1788234429Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1789234429Sambrisko 1790234429Sambriskostruct mfi_mpi2_request_high_priority { 1791234429Sambrisko struct mfi_mpi2_request_header header; 1792234429Sambrisko uint16_t reserved; 1793234429Sambrisko}; 1794234429Sambrisko 1795234429Sambriskostruct mfi_mpi2_request_scsi_io { 1796234429Sambrisko struct mfi_mpi2_request_header header; 1797234429Sambrisko uint16_t scsi_io_dev_handle; 1798234429Sambrisko}; 1799234429Sambrisko 1800234429Sambriskostruct mfi_mpi2_request_scsi_target { 1801234429Sambrisko struct mfi_mpi2_request_header header; 1802234429Sambrisko uint16_t scsi_target_io_index; 1803234429Sambrisko}; 1804234429Sambrisko 1805234429Sambrisko/* Request Descriptors */ 1806234429Sambriskounion mfi_mpi2_request_descriptor { 1807234429Sambrisko struct mfi_mpi2_request_header header; 1808234429Sambrisko struct mfi_mpi2_request_high_priority high_priority; 1809234429Sambrisko struct mfi_mpi2_request_scsi_io scsi_io; 1810234429Sambrisko struct mfi_mpi2_request_scsi_target scsi_target; 1811234429Sambrisko uint64_t words; 1812234429Sambrisko}; 1813234429Sambrisko 1814234429Sambrisko 1815234429Sambriskostruct mfi_mpi2_reply_header { 1816234429Sambrisko uint8_t ReplyFlags; /* 0x00 */ 1817234429Sambrisko uint8_t MSIxIndex; /* 0x01 */ 1818234429Sambrisko uint16_t SMID; /* 0x02 */ 1819234429Sambrisko}; 1820234429Sambrisko 1821234429Sambrisko/* defines for the ReplyFlags field */ 1822234429Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1823234429Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1824234429Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1825234429Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1826234429Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1827234429Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1828234429Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1829234429Sambrisko 1830234429Sambrisko/* values for marking a reply descriptor as unused */ 1831234429Sambrisko#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1832234429Sambrisko#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1833234429Sambrisko 1834234429Sambriskostruct mfi_mpi2_reply_default { 1835234429Sambrisko struct mfi_mpi2_reply_header header; 1836234429Sambrisko uint32_t DescriptorTypeDependent2; 1837234429Sambrisko}; 1838234429Sambrisko 1839234429Sambriskostruct mfi_mpi2_reply_address { 1840234429Sambrisko struct mfi_mpi2_reply_header header; 1841234429Sambrisko uint32_t ReplyFrameAddress; 1842234429Sambrisko}; 1843234429Sambrisko 1844234429Sambriskostruct mfi_mpi2_reply_scsi_io { 1845234429Sambrisko struct mfi_mpi2_reply_header header; 1846234429Sambrisko uint16_t TaskTag; /* 0x04 */ 1847234429Sambrisko uint16_t Reserved1; /* 0x06 */ 1848234429Sambrisko}; 1849234429Sambrisko 1850234429Sambriskostruct mfi_mpi2_reply_target_assist { 1851234429Sambrisko struct mfi_mpi2_reply_header header; 1852234429Sambrisko uint8_t SequenceNumber; /* 0x04 */ 1853234429Sambrisko uint8_t Reserved1; /* 0x04 */ 1854234429Sambrisko uint16_t IoIndex; /* 0x06 */ 1855234429Sambrisko}; 1856234429Sambrisko 1857234429Sambriskostruct mfi_mpi2_reply_target_cmd_buffer { 1858234429Sambrisko struct mfi_mpi2_reply_header header; 1859234429Sambrisko uint8_t SequenceNumber; /* 0x04 */ 1860234429Sambrisko uint8_t Flags; /* 0x04 */ 1861234429Sambrisko uint16_t InitiatorDevHandle; /* 0x06 */ 1862234429Sambrisko uint16_t IoIndex; /* 0x06 */ 1863234429Sambrisko}; 1864234429Sambrisko 1865234429Sambriskostruct mfi_mpi2_reply_raid_accel { 1866234429Sambrisko struct mfi_mpi2_reply_header header; 1867234429Sambrisko uint8_t SequenceNumber; /* 0x04 */ 1868234429Sambrisko uint32_t Reserved; /* 0x04 */ 1869234429Sambrisko}; 1870234429Sambrisko 1871234429Sambrisko/* union of Reply Descriptors */ 1872234429Sambriskounion mfi_mpi2_reply_descriptor { 1873234429Sambrisko struct mfi_mpi2_reply_header header; 1874234429Sambrisko struct mfi_mpi2_reply_scsi_io scsi_io; 1875234429Sambrisko struct mfi_mpi2_reply_target_assist target_assist; 1876234429Sambrisko struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1877234429Sambrisko struct mfi_mpi2_reply_raid_accel raid_accel; 1878234429Sambrisko struct mfi_mpi2_reply_default reply_default; 1879234429Sambrisko uint64_t words; 1880234429Sambrisko}; 1881234429Sambrisko 1882234429Sambriskostruct IO_REQUEST_INFO { 1883234429Sambrisko uint64_t ldStartBlock; 1884234429Sambrisko uint32_t numBlocks; 1885234429Sambrisko uint16_t ldTgtId; 1886234429Sambrisko uint8_t isRead; 1887234429Sambrisko uint16_t devHandle; 1888234429Sambrisko uint64_t pdBlock; 1889234429Sambrisko uint8_t fpOkForIo; 1890234429Sambrisko}; 1891234429Sambrisko 1892169611Sscottl#define MFI_SCSI_MAX_TARGETS 128 1893169611Sscottl#define MFI_SCSI_MAX_LUNS 8 1894169611Sscottl#define MFI_SCSI_INITIATOR_ID 255 1895169611Sscottl#define MFI_SCSI_MAX_CMDS 8 1896169611Sscottl#define MFI_SCSI_MAX_CDB_LEN 16 1897169611Sscottl 1898157114Sscottl#endif /* _MFIREG_H */ 1899