1177595Sweongyo/*- 2177595Sweongyo * Copyright (c) 2007 Marvell Semiconductor, Inc. 3177595Sweongyo * Copyright (c) 2007 Sam Leffler, Errno Consulting 4177595Sweongyo * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 5177595Sweongyo * All rights reserved. 6177595Sweongyo * 7177595Sweongyo * Redistribution and use in source and binary forms, with or without 8177595Sweongyo * modification, are permitted provided that the following conditions 9177595Sweongyo * are met: 10177595Sweongyo * 1. Redistributions of source code must retain the above copyright 11177595Sweongyo * notice, this list of conditions and the following disclaimer, 12177595Sweongyo * without modification. 13177595Sweongyo * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14177595Sweongyo * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15177595Sweongyo * redistribution must be conditioned upon including a substantially 16177595Sweongyo * similar Disclaimer requirement for further binary redistribution. 17177595Sweongyo * 18177595Sweongyo * NO WARRANTY 19177595Sweongyo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20177595Sweongyo * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21177595Sweongyo * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22177595Sweongyo * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23177595Sweongyo * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24177595Sweongyo * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25177595Sweongyo * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26177595Sweongyo * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27177595Sweongyo * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28177595Sweongyo * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29177595Sweongyo * THE POSSIBILITY OF SUCH DAMAGES. 30177595Sweongyo */ 31177595Sweongyo 32177595Sweongyo#include <sys/cdefs.h> 33177595Sweongyo#ifdef __FreeBSD__ 34177595Sweongyo__FBSDID("$FreeBSD$"); 35177595Sweongyo#endif 36177595Sweongyo 37177595Sweongyo#include <sys/param.h> 38177595Sweongyo#include <sys/systm.h> 39177595Sweongyo#include <sys/endian.h> 40177595Sweongyo#include <sys/kernel.h> 41177595Sweongyo#include <sys/firmware.h> 42177595Sweongyo#include <sys/socket.h> 43177595Sweongyo 44177595Sweongyo#include <machine/bus.h> 45177595Sweongyo#include <sys/bus.h> 46177595Sweongyo 47177595Sweongyo#include <net/if.h> 48177595Sweongyo#include <net/if_dl.h> 49177595Sweongyo#include <net/if_media.h> 50177595Sweongyo 51177595Sweongyo#include <net80211/ieee80211_var.h> 52177595Sweongyo 53177595Sweongyo#include <dev/malo/if_malo.h> 54177595Sweongyo 55177595Sweongyo#define MALO_WAITOK 1 56177595Sweongyo#define MALO_NOWAIT 0 57177595Sweongyo 58177595Sweongyo#define _CMD_SETUP(pCmd, _type, _cmd) do { \ 59177595Sweongyo pCmd = (_type *)&mh->mh_cmdbuf[0]; \ 60177595Sweongyo memset(pCmd, 0, sizeof(_type)); \ 61177595Sweongyo pCmd->cmdhdr.cmd = htole16(_cmd); \ 62177595Sweongyo pCmd->cmdhdr.length = htole16(sizeof(_type)); \ 63177595Sweongyo} while (0) 64177595Sweongyo 65177595Sweongyostatic __inline uint32_t 66177595Sweongyomalo_hal_read4(struct malo_hal *mh, bus_size_t off) 67177595Sweongyo{ 68177595Sweongyo return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off); 69177595Sweongyo} 70177595Sweongyo 71177595Sweongyostatic __inline void 72177595Sweongyomalo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val) 73177595Sweongyo{ 74177595Sweongyo bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val); 75177595Sweongyo} 76177595Sweongyo 77177595Sweongyostatic void 78177595Sweongyomalo_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 79177595Sweongyo{ 80177595Sweongyo bus_addr_t *paddr = (bus_addr_t*) arg; 81177595Sweongyo 82177595Sweongyo KASSERT(error == 0, ("error %u on bus_dma callback", error)); 83177595Sweongyo *paddr = segs->ds_addr; 84177595Sweongyo} 85177595Sweongyo 86177595Sweongyo/* 87177595Sweongyo * Setup for communication with the device. We allocate 88177595Sweongyo * a command buffer and map it for bus dma use. The pci 89177595Sweongyo * device id is used to identify whether the device has 90177595Sweongyo * SRAM on it (in which case f/w download must include a 91177595Sweongyo * memory controller reset). All bus i/o operations happen 92177595Sweongyo * in BAR 1; the driver passes in the tag and handle we need. 93177595Sweongyo */ 94177595Sweongyostruct malo_hal * 95177595Sweongyomalo_hal_attach(device_t dev, uint16_t devid, 96177595Sweongyo bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag) 97177595Sweongyo{ 98177595Sweongyo int error; 99177595Sweongyo struct malo_hal *mh; 100177595Sweongyo 101177595Sweongyo mh = malloc(sizeof(struct malo_hal), M_DEVBUF, M_NOWAIT | M_ZERO); 102177595Sweongyo if (mh == NULL) 103177595Sweongyo return NULL; 104177595Sweongyo 105177595Sweongyo mh->mh_dev = dev; 106177595Sweongyo mh->mh_ioh = ioh; 107177595Sweongyo mh->mh_iot = iot; 108177595Sweongyo 109177595Sweongyo snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname), 110177595Sweongyo "%s_hal", device_get_nameunit(dev)); 111177595Sweongyo mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF); 112177595Sweongyo 113177595Sweongyo /* 114177595Sweongyo * Allocate the command buffer and map into the address 115177595Sweongyo * space of the h/w. We request "coherent" memory which 116177595Sweongyo * will be uncached on some architectures. 117177595Sweongyo */ 118177595Sweongyo error = bus_dma_tag_create(tag, /* parent */ 119177595Sweongyo PAGE_SIZE, 0, /* alignment, bounds */ 120177595Sweongyo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 121177595Sweongyo BUS_SPACE_MAXADDR, /* highaddr */ 122177595Sweongyo NULL, NULL, /* filter, filterarg */ 123177595Sweongyo MALO_CMDBUF_SIZE, /* maxsize */ 124177595Sweongyo 1, /* nsegments */ 125177595Sweongyo MALO_CMDBUF_SIZE, /* maxsegsize */ 126177595Sweongyo BUS_DMA_ALLOCNOW, /* flags */ 127177595Sweongyo NULL, /* lockfunc */ 128177595Sweongyo NULL, /* lockarg */ 129177595Sweongyo &mh->mh_dmat); 130177595Sweongyo if (error != 0) { 131190550Sweongyo device_printf(dev, "unable to allocate memory for cmd tag, " 132177595Sweongyo "error %u\n", error); 133177595Sweongyo goto fail; 134177595Sweongyo } 135177595Sweongyo 136177595Sweongyo /* allocate descriptors */ 137177595Sweongyo error = bus_dmamap_create(mh->mh_dmat, BUS_DMA_NOWAIT, &mh->mh_dmamap); 138177595Sweongyo if (error != 0) { 139177595Sweongyo device_printf(dev, "unable to create dmamap for cmd buffers, " 140177595Sweongyo "error %u\n", error); 141177595Sweongyo goto fail; 142177595Sweongyo } 143177595Sweongyo 144177595Sweongyo error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf, 145177595Sweongyo BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 146177595Sweongyo &mh->mh_dmamap); 147177595Sweongyo if (error != 0) { 148177595Sweongyo device_printf(dev, "unable to allocate memory for cmd buffer, " 149177595Sweongyo "error %u\n", error); 150177595Sweongyo goto fail; 151177595Sweongyo } 152177595Sweongyo 153177595Sweongyo error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap, 154177595Sweongyo mh->mh_cmdbuf, MALO_CMDBUF_SIZE, 155177595Sweongyo malo_hal_load_cb, &mh->mh_cmdaddr, 156177595Sweongyo BUS_DMA_NOWAIT); 157177595Sweongyo if (error != 0) { 158177595Sweongyo device_printf(dev, "unable to load cmd buffer, error %u\n", 159177595Sweongyo error); 160177595Sweongyo goto fail; 161177595Sweongyo } 162177595Sweongyo 163177595Sweongyo return (mh); 164177595Sweongyo 165177595Sweongyofail: 166177595Sweongyo if (mh->mh_dmamap != NULL) { 167177595Sweongyo bus_dmamap_unload(mh->mh_dmat, mh->mh_dmamap); 168177595Sweongyo if (mh->mh_cmdbuf != NULL) 169177595Sweongyo bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, 170177595Sweongyo mh->mh_dmamap); 171177595Sweongyo bus_dmamap_destroy(mh->mh_dmat, mh->mh_dmamap); 172177595Sweongyo } 173177595Sweongyo if (mh->mh_dmat) 174177595Sweongyo bus_dma_tag_destroy(mh->mh_dmat); 175190541Sweongyo free(mh, M_DEVBUF); 176177595Sweongyo 177177595Sweongyo return (NULL); 178177595Sweongyo} 179177595Sweongyo 180177595Sweongyo/* 181177595Sweongyo * Low level firmware cmd block handshake support. 182177595Sweongyo */ 183177595Sweongyo 184177595Sweongyostatic void 185177595Sweongyomalo_hal_send_cmd(struct malo_hal *mh) 186177595Sweongyo{ 187177595Sweongyo uint32_t dummy; 188177595Sweongyo 189177595Sweongyo bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 190177595Sweongyo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 191177595Sweongyo 192177595Sweongyo malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 193177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 194177595Sweongyo 195177595Sweongyo malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 196177595Sweongyo MALO_H2ARIC_BIT_DOOR_BELL); 197177595Sweongyo} 198177595Sweongyo 199177595Sweongyostatic int 200177595Sweongyomalo_hal_waitforcmd(struct malo_hal *mh, uint16_t cmd) 201177595Sweongyo{ 202177595Sweongyo#define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000 203177595Sweongyo int i; 204177595Sweongyo 205177595Sweongyo for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) { 206177595Sweongyo if (mh->mh_cmdbuf[0] == le16toh(cmd)) 207177595Sweongyo return 1; 208177595Sweongyo 209177595Sweongyo DELAY(1 * 1000); 210177595Sweongyo } 211177595Sweongyo 212177595Sweongyo return 0; 213177595Sweongyo#undef MAX_WAIT_FW_COMPLETE_ITERATIONS 214177595Sweongyo} 215177595Sweongyo 216177595Sweongyostatic int 217177595Sweongyomalo_hal_execute_cmd(struct malo_hal *mh, unsigned short cmd) 218177595Sweongyo{ 219177595Sweongyo MALO_HAL_LOCK_ASSERT(mh); 220177595Sweongyo 221177595Sweongyo if ((mh->mh_flags & MHF_FWHANG) && 222177595Sweongyo (mh->mh_debug & MALO_HAL_DEBUG_IGNHANG) == 0) { 223177595Sweongyo device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n", 224177595Sweongyo cmd); 225177595Sweongyo return ENXIO; 226177595Sweongyo } 227177595Sweongyo 228177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 229177595Sweongyo device_printf(mh->mh_dev, "%s: device not present!\n", 230177595Sweongyo __func__); 231177595Sweongyo return EIO; 232177595Sweongyo } 233177595Sweongyo 234177595Sweongyo malo_hal_send_cmd(mh); 235177595Sweongyo if (!malo_hal_waitforcmd(mh, cmd | 0x8000)) { 236177595Sweongyo device_printf(mh->mh_dev, 237177595Sweongyo "timeout waiting for f/w cmd 0x%x\n", cmd); 238177595Sweongyo mh->mh_flags |= MHF_FWHANG; 239177595Sweongyo return ETIMEDOUT; 240177595Sweongyo } 241177595Sweongyo 242177595Sweongyo bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 243177595Sweongyo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 244177595Sweongyo 245177595Sweongyo return 0; 246177595Sweongyo} 247177595Sweongyo 248177595Sweongyostatic int 249177595Sweongyomalo_hal_get_cal_table(struct malo_hal *mh, uint8_t annex, uint8_t index) 250177595Sweongyo{ 251177595Sweongyo struct malo_cmd_caltable *cmd; 252177595Sweongyo int ret; 253177595Sweongyo 254177595Sweongyo MALO_HAL_LOCK_ASSERT(mh); 255177595Sweongyo 256177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_caltable, MALO_HOSTCMD_GET_CALTABLE); 257177595Sweongyo cmd->annex = annex; 258177595Sweongyo cmd->index = index; 259177595Sweongyo 260177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_CALTABLE); 261177595Sweongyo if (ret == 0 && cmd->caltbl[0] != annex && annex != 0 && annex != 255) 262177595Sweongyo ret = EIO; 263177595Sweongyo return ret; 264177595Sweongyo} 265177595Sweongyo 266177595Sweongyostatic int 267177595Sweongyomalo_hal_get_pwrcal_table(struct malo_hal *mh, struct malo_hal_caldata *cal) 268177595Sweongyo{ 269177595Sweongyo const uint8_t *data; 270177595Sweongyo int len; 271177595Sweongyo 272177595Sweongyo MALO_HAL_LOCK(mh); 273177595Sweongyo /* NB: we hold the lock so it's ok to use cmdbuf */ 274177595Sweongyo data = ((const struct malo_cmd_caltable *) mh->mh_cmdbuf)->caltbl; 275177595Sweongyo if (malo_hal_get_cal_table(mh, 33, 0) == 0) { 276177595Sweongyo len = (data[2] | (data[3] << 8)) - 12; 277177595Sweongyo /* XXX validate len */ 278177595Sweongyo memcpy(cal->pt_ratetable_20m, &data[12], len); 279177595Sweongyo } 280177595Sweongyo mh->mh_flags |= MHF_CALDATA; 281177595Sweongyo MALO_HAL_UNLOCK(mh); 282177595Sweongyo 283177595Sweongyo return 0; 284177595Sweongyo} 285177595Sweongyo 286177595Sweongyo/* 287177595Sweongyo * Reset internal state after a firmware download. 288177595Sweongyo */ 289177595Sweongyostatic int 290177595Sweongyomalo_hal_resetstate(struct malo_hal *mh) 291177595Sweongyo{ 292177595Sweongyo /* 293177595Sweongyo * Fetch cal data for later use. 294177595Sweongyo * XXX may want to fetch other stuff too. 295177595Sweongyo */ 296177595Sweongyo if ((mh->mh_flags & MHF_CALDATA) == 0) 297177595Sweongyo malo_hal_get_pwrcal_table(mh, &mh->mh_caldata); 298177595Sweongyo return 0; 299177595Sweongyo} 300177595Sweongyo 301177595Sweongyostatic void 302177595Sweongyomalo_hal_fw_reset(struct malo_hal *mh) 303177595Sweongyo{ 304177595Sweongyo 305177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 306177595Sweongyo device_printf(mh->mh_dev, "%s: device not present!\n", 307177595Sweongyo __func__); 308177595Sweongyo return; 309177595Sweongyo } 310177595Sweongyo 311177595Sweongyo malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, MALO_ISR_RESET); 312177595Sweongyo mh->mh_flags &= ~MHF_FWHANG; 313177595Sweongyo} 314177595Sweongyo 315177595Sweongyostatic void 316177595Sweongyomalo_hal_trigger_pcicmd(struct malo_hal *mh) 317177595Sweongyo{ 318177595Sweongyo uint32_t dummy; 319177595Sweongyo 320177595Sweongyo bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE); 321177595Sweongyo 322177595Sweongyo malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 323177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 324177595Sweongyo 325177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 326177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 327177595Sweongyo 328177595Sweongyo malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 329177595Sweongyo MALO_H2ARIC_BIT_DOOR_BELL); 330177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 331177595Sweongyo} 332177595Sweongyo 333177595Sweongyostatic int 334177595Sweongyomalo_hal_waitfor(struct malo_hal *mh, uint32_t val) 335177595Sweongyo{ 336177595Sweongyo int i; 337177595Sweongyo 338177595Sweongyo for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 339177595Sweongyo DELAY(MALO_FW_CHECK_USECS); 340177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == val) 341177595Sweongyo return 0; 342177595Sweongyo } 343177595Sweongyo 344177595Sweongyo return -1; 345177595Sweongyo} 346177595Sweongyo 347177595Sweongyo/* 348177595Sweongyo * Firmware block xmit when talking to the boot-rom. 349177595Sweongyo */ 350177595Sweongyostatic int 351177595Sweongyomalo_hal_send_helper(struct malo_hal *mh, int bsize, 352177595Sweongyo const void *data, size_t dsize, int waitfor) 353177595Sweongyo{ 354177595Sweongyo mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 355177595Sweongyo mh->mh_cmdbuf[1] = htole16(bsize); 356177595Sweongyo memcpy(&mh->mh_cmdbuf[4], data , dsize); 357177595Sweongyo 358177595Sweongyo malo_hal_trigger_pcicmd(mh); 359177595Sweongyo 360177595Sweongyo if (waitfor == MALO_NOWAIT) 361177595Sweongyo goto pass; 362177595Sweongyo 363177595Sweongyo /* XXX 2000 vs 200 */ 364177595Sweongyo if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 365177595Sweongyo device_printf(mh->mh_dev, 366177595Sweongyo "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 367177595Sweongyo __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 368177595Sweongyo 369177595Sweongyo return ETIMEDOUT; 370177595Sweongyo } 371177595Sweongyo 372177595Sweongyopass: 373177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 374177595Sweongyo 375177595Sweongyo return (0); 376177595Sweongyo} 377177595Sweongyo 378177595Sweongyostatic int 379177595Sweongyomalo_hal_fwload_helper(struct malo_hal *mh, char *helper) 380177595Sweongyo{ 381177595Sweongyo const struct firmware *fw; 382177595Sweongyo int error; 383177595Sweongyo 384177595Sweongyo fw = firmware_get(helper); 385177595Sweongyo if (fw == NULL) { 386177595Sweongyo device_printf(mh->mh_dev, "could not read microcode %s!\n", 387177595Sweongyo helper); 388177595Sweongyo return (EIO); 389177595Sweongyo } 390177595Sweongyo 391177819Sweongyo device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 392177595Sweongyo helper, fw->datasize); 393177595Sweongyo 394177595Sweongyo error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize, 395177595Sweongyo MALO_WAITOK); 396177595Sweongyo if (error != 0) 397177595Sweongyo goto fail; 398177595Sweongyo 399177595Sweongyo /* tell the card we're done and... */ 400177595Sweongyo error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT); 401177595Sweongyo 402177595Sweongyofail: 403177595Sweongyo firmware_put(fw, FIRMWARE_UNLOAD); 404177595Sweongyo 405177595Sweongyo return (error); 406177595Sweongyo} 407177595Sweongyo 408177595Sweongyo/* 409177595Sweongyo * Firmware block xmit when talking to the 1st-stage loader. 410177595Sweongyo */ 411177595Sweongyostatic int 412177595Sweongyomalo_hal_send_main(struct malo_hal *mh, const void *data, size_t dsize, 413177595Sweongyo uint16_t seqnum, int waitfor) 414177595Sweongyo{ 415177595Sweongyo mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 416177595Sweongyo mh->mh_cmdbuf[1] = htole16(dsize); 417177595Sweongyo mh->mh_cmdbuf[2] = htole16(seqnum); 418177595Sweongyo mh->mh_cmdbuf[3] = 0; 419177595Sweongyo memcpy(&mh->mh_cmdbuf[4], data, dsize); 420177595Sweongyo 421177595Sweongyo malo_hal_trigger_pcicmd(mh); 422177595Sweongyo 423177595Sweongyo if (waitfor == MALO_NOWAIT) 424177595Sweongyo goto pass; 425177595Sweongyo 426177595Sweongyo if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 427177595Sweongyo device_printf(mh->mh_dev, 428177595Sweongyo "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 429177595Sweongyo __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 430177595Sweongyo 431177595Sweongyo return ETIMEDOUT; 432177595Sweongyo } 433177595Sweongyo 434177595Sweongyopass: 435177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 436177595Sweongyo 437177595Sweongyo return 0; 438177595Sweongyo} 439177595Sweongyo 440177595Sweongyostatic int 441177595Sweongyomalo_hal_fwload_main(struct malo_hal *mh, char *firmware) 442177595Sweongyo{ 443177595Sweongyo const struct firmware *fw; 444177595Sweongyo const uint8_t *fp; 445177595Sweongyo int error; 446177595Sweongyo size_t count; 447177595Sweongyo uint16_t seqnum; 448177595Sweongyo uint32_t blocksize; 449177595Sweongyo 450177595Sweongyo error = 0; 451177595Sweongyo 452177595Sweongyo fw = firmware_get(firmware); 453177595Sweongyo if (fw == NULL) { 454177595Sweongyo device_printf(mh->mh_dev, "could not read firmware %s!\n", 455177595Sweongyo firmware); 456177595Sweongyo return (EIO); 457177595Sweongyo } 458177595Sweongyo 459177819Sweongyo device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 460177595Sweongyo firmware, fw->datasize); 461177595Sweongyo 462177595Sweongyo seqnum = 1; 463177595Sweongyo for (count = 0; count < fw->datasize; count += blocksize) { 464177595Sweongyo blocksize = MIN(256, fw->datasize - count); 465177595Sweongyo fp = (const uint8_t *)fw->data + count; 466177595Sweongyo 467177595Sweongyo error = malo_hal_send_main(mh, fp, blocksize, seqnum++, 468177595Sweongyo MALO_NOWAIT); 469177595Sweongyo if (error != 0) 470177595Sweongyo goto fail; 471177595Sweongyo DELAY(500); 472177595Sweongyo } 473177595Sweongyo 474177595Sweongyo /* 475177595Sweongyo * send a command with size 0 to tell that the firmware has been 476177595Sweongyo * uploaded 477177595Sweongyo */ 478177595Sweongyo error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT); 479177595Sweongyo DELAY(100); 480177595Sweongyo 481177595Sweongyofail: 482177595Sweongyo firmware_put(fw, FIRMWARE_UNLOAD); 483177595Sweongyo 484177595Sweongyo return (error); 485177595Sweongyo} 486177595Sweongyo 487177595Sweongyoint 488177595Sweongyomalo_hal_fwload(struct malo_hal *mh, char *helper, char *firmware) 489177595Sweongyo{ 490177595Sweongyo int error, i; 491177595Sweongyo uint32_t fwreadysig, opmode; 492177595Sweongyo 493177595Sweongyo /* 494177595Sweongyo * NB: now malo(4) supports only STA mode. It will be better if it 495177595Sweongyo * supports AP mode. 496177595Sweongyo */ 497177595Sweongyo fwreadysig = MALO_HOSTCMD_STA_FWRDY_SIGNATURE; 498177595Sweongyo opmode = MALO_HOSTCMD_STA_MODE; 499177595Sweongyo 500177595Sweongyo malo_hal_fw_reset(mh); 501177595Sweongyo 502177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CLEAR_SEL, 503177595Sweongyo MALO_A2HRIC_BIT_MASK); 504177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CAUSE, 0x00); 505177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0x00); 506177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 507177595Sweongyo MALO_A2HRIC_BIT_MASK); 508177595Sweongyo 509177595Sweongyo error = malo_hal_fwload_helper(mh, helper); 510177595Sweongyo if (error != 0) { 511177595Sweongyo device_printf(mh->mh_dev, "failed to load bootrom loader.\n"); 512177595Sweongyo goto fail; 513177595Sweongyo } 514177595Sweongyo 515177595Sweongyo DELAY(200 * MALO_FW_CHECK_USECS); 516177595Sweongyo 517177595Sweongyo error = malo_hal_fwload_main(mh, firmware); 518177595Sweongyo if (error != 0) { 519177595Sweongyo device_printf(mh->mh_dev, "failed to load firmware.\n"); 520177595Sweongyo goto fail; 521177595Sweongyo } 522177595Sweongyo 523177595Sweongyo /* 524177595Sweongyo * Wait for firmware to startup; we monitor the INT_CODE register 525177595Sweongyo * waiting for a signature to written back indicating it's ready to go. 526177595Sweongyo */ 527177595Sweongyo mh->mh_cmdbuf[1] = 0; 528177595Sweongyo 529177595Sweongyo if (opmode != MALO_HOSTCMD_STA_MODE) 530177595Sweongyo malo_hal_trigger_pcicmd(mh); 531177595Sweongyo 532177595Sweongyo for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 533177595Sweongyo malo_hal_write4(mh, MALO_REG_GEN_PTR, opmode); 534177595Sweongyo DELAY(MALO_FW_CHECK_USECS); 535177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == fwreadysig) { 536177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 537177595Sweongyo return malo_hal_resetstate(mh); 538177595Sweongyo } 539177595Sweongyo } 540177595Sweongyo 541177595Sweongyo return ETIMEDOUT; 542177595Sweongyofail: 543177595Sweongyo malo_hal_fw_reset(mh); 544177595Sweongyo 545177595Sweongyo return (error); 546177595Sweongyo} 547177595Sweongyo 548177595Sweongyo/* 549177595Sweongyo * Return "hw specs". Note this must be the first cmd MUST be done after 550177595Sweongyo * a firmware download or the f/w will lockup. 551177595Sweongyo */ 552177595Sweongyoint 553177595Sweongyomalo_hal_gethwspecs(struct malo_hal *mh, struct malo_hal_hwspec *hw) 554177595Sweongyo{ 555177595Sweongyo struct malo_cmd_get_hwspec *cmd; 556177595Sweongyo int ret; 557177595Sweongyo 558177595Sweongyo MALO_HAL_LOCK(mh); 559177595Sweongyo 560177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_get_hwspec, MALO_HOSTCMD_GET_HW_SPEC); 561177595Sweongyo memset(&cmd->permaddr[0], 0xff, IEEE80211_ADDR_LEN); 562177595Sweongyo cmd->ul_fw_awakecookie = htole32((unsigned int)mh->mh_cmdaddr + 2048); 563177595Sweongyo 564177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_HW_SPEC); 565177595Sweongyo if (ret == 0) { 566177595Sweongyo IEEE80211_ADDR_COPY(hw->macaddr, cmd->permaddr); 567177595Sweongyo hw->wcbbase[0] = le32toh(cmd->wcbbase0) & 0x0000ffff; 568177595Sweongyo hw->wcbbase[1] = le32toh(cmd->wcbbase1) & 0x0000ffff; 569177595Sweongyo hw->wcbbase[2] = le32toh(cmd->wcbbase2) & 0x0000ffff; 570177595Sweongyo hw->wcbbase[3] = le32toh(cmd->wcbbase3) & 0x0000ffff; 571177595Sweongyo hw->rxdesc_read = le32toh(cmd->rxpdrd_ptr)& 0x0000ffff; 572177595Sweongyo hw->rxdesc_write = le32toh(cmd->rxpdwr_ptr)& 0x0000ffff; 573177595Sweongyo hw->regioncode = le16toh(cmd->regioncode) & 0x00ff; 574177595Sweongyo hw->fw_releasenum = le32toh(cmd->fw_releasenum); 575177595Sweongyo hw->maxnum_wcb = le16toh(cmd->num_wcb); 576177595Sweongyo hw->maxnum_mcaddr = le16toh(cmd->num_mcastaddr); 577177595Sweongyo hw->num_antenna = le16toh(cmd->num_antenna); 578177595Sweongyo hw->hwversion = cmd->version; 579177595Sweongyo hw->hostinterface = cmd->hostif; 580177595Sweongyo } 581177595Sweongyo 582177595Sweongyo MALO_HAL_UNLOCK(mh); 583177595Sweongyo 584177595Sweongyo return ret; 585177595Sweongyo} 586177595Sweongyo 587177595Sweongyovoid 588177595Sweongyomalo_hal_detach(struct malo_hal *mh) 589177595Sweongyo{ 590177595Sweongyo 591177595Sweongyo bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap); 592177595Sweongyo bus_dmamap_destroy(mh->mh_dmat, mh->mh_dmamap); 593177595Sweongyo bus_dma_tag_destroy(mh->mh_dmat); 594177595Sweongyo mtx_destroy(&mh->mh_mtx); 595177595Sweongyo free(mh, M_DEVBUF); 596177595Sweongyo} 597177595Sweongyo 598177595Sweongyo/* 599177595Sweongyo * Configure antenna use. Takes effect immediately. 600177595Sweongyo * 601177595Sweongyo * XXX tx antenna setting ignored 602177595Sweongyo * XXX rx antenna setting should always be 3 (for now) 603177595Sweongyo */ 604177595Sweongyoint 605177595Sweongyomalo_hal_setantenna(struct malo_hal *mh, enum malo_hal_antenna dirset, int ant) 606177595Sweongyo{ 607177595Sweongyo struct malo_cmd_rf_antenna *cmd; 608177595Sweongyo int ret; 609177595Sweongyo 610177595Sweongyo if (!(dirset == MHA_ANTENNATYPE_RX || dirset == MHA_ANTENNATYPE_TX)) 611177595Sweongyo return EINVAL; 612177595Sweongyo 613177595Sweongyo MALO_HAL_LOCK(mh); 614177595Sweongyo 615177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_rf_antenna, 616177595Sweongyo MALO_HOSTCMD_802_11_RF_ANTENNA); 617177595Sweongyo cmd->action = htole16(dirset); 618177595Sweongyo if (ant == 0) { /* default to all/both antennae */ 619177595Sweongyo /* XXX never reach now. */ 620177595Sweongyo ant = 3; 621177595Sweongyo } 622177595Sweongyo cmd->mode = htole16(ant); 623177595Sweongyo 624177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_ANTENNA); 625177595Sweongyo 626177595Sweongyo MALO_HAL_UNLOCK(mh); 627177595Sweongyo 628177595Sweongyo return ret; 629177595Sweongyo} 630177595Sweongyo 631177595Sweongyo/* 632177595Sweongyo * Configure radio. Takes effect immediately. 633177595Sweongyo * 634177595Sweongyo * XXX preamble installed after set fixed rate cmd 635177595Sweongyo */ 636177595Sweongyoint 637177595Sweongyomalo_hal_setradio(struct malo_hal *mh, int onoff, 638177595Sweongyo enum malo_hal_preamble preamble) 639177595Sweongyo{ 640177595Sweongyo struct malo_cmd_radio_control *cmd; 641177595Sweongyo int ret; 642177595Sweongyo 643177595Sweongyo MALO_HAL_LOCK(mh); 644177595Sweongyo 645177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_radio_control, 646177595Sweongyo MALO_HOSTCMD_802_11_RADIO_CONTROL); 647177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 648177595Sweongyo if (onoff == 0) 649177595Sweongyo cmd->control = 0; 650177595Sweongyo else 651177595Sweongyo cmd->control = htole16(preamble); 652177595Sweongyo cmd->radio_on = htole16(onoff); 653177595Sweongyo 654177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RADIO_CONTROL); 655177595Sweongyo 656177595Sweongyo MALO_HAL_UNLOCK(mh); 657177595Sweongyo 658177595Sweongyo return ret; 659177595Sweongyo} 660177595Sweongyo 661177595Sweongyo/* 662177595Sweongyo * Set the interrupt mask. 663177595Sweongyo */ 664177595Sweongyovoid 665177595Sweongyomalo_hal_intrset(struct malo_hal *mh, uint32_t mask) 666177595Sweongyo{ 667177595Sweongyo 668177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0); 669177595Sweongyo (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 670177595Sweongyo 671177595Sweongyo mh->mh_imask = mask; 672177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, mask); 673177595Sweongyo (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 674177595Sweongyo} 675177595Sweongyo 676177595Sweongyoint 677177595Sweongyomalo_hal_setchannel(struct malo_hal *mh, const struct malo_hal_channel *chan) 678177595Sweongyo{ 679177595Sweongyo struct malo_cmd_fw_set_rf_channel *cmd; 680177595Sweongyo int ret; 681177595Sweongyo 682177595Sweongyo MALO_HAL_LOCK(mh); 683177595Sweongyo 684177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_fw_set_rf_channel, 685177595Sweongyo MALO_HOSTCMD_SET_RF_CHANNEL); 686177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 687177595Sweongyo cmd->cur_channel = chan->channel; 688177595Sweongyo 689177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RF_CHANNEL); 690177595Sweongyo 691177595Sweongyo MALO_HAL_UNLOCK(mh); 692177595Sweongyo 693177595Sweongyo return ret; 694177595Sweongyo} 695177595Sweongyo 696177595Sweongyoint 697177595Sweongyomalo_hal_settxpower(struct malo_hal *mh, const struct malo_hal_channel *c) 698177595Sweongyo{ 699177595Sweongyo struct malo_cmd_rf_tx_power *cmd; 700177595Sweongyo const struct malo_hal_caldata *cal = &mh->mh_caldata; 701177595Sweongyo uint8_t chan = c->channel; 702177595Sweongyo uint16_t pow; 703177595Sweongyo int i, idx, ret; 704177595Sweongyo 705177595Sweongyo MALO_HAL_LOCK(mh); 706177595Sweongyo 707177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_rf_tx_power, 708177595Sweongyo MALO_HOSTCMD_802_11_RF_TX_POWER); 709177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET_LIST); 710177595Sweongyo for (i = 0; i < 4; i++) { 711177595Sweongyo idx = (chan - 1) * 4 + i; 712177595Sweongyo pow = cal->pt_ratetable_20m[idx]; 713177595Sweongyo cmd->power_levellist[i] = htole16(pow); 714177595Sweongyo } 715177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_TX_POWER); 716177595Sweongyo 717177595Sweongyo MALO_HAL_UNLOCK(mh); 718177595Sweongyo 719177595Sweongyo return ret; 720177595Sweongyo} 721177595Sweongyo 722177595Sweongyoint 723177595Sweongyomalo_hal_setpromisc(struct malo_hal *mh, int enable) 724177595Sweongyo{ 725177595Sweongyo /* XXX need host cmd */ 726177595Sweongyo return 0; 727177595Sweongyo} 728177595Sweongyo 729177595Sweongyoint 730177595Sweongyomalo_hal_setassocid(struct malo_hal *mh, 731177595Sweongyo const uint8_t bssid[IEEE80211_ADDR_LEN], uint16_t associd) 732177595Sweongyo{ 733177595Sweongyo struct malo_cmd_fw_set_aid *cmd; 734177595Sweongyo int ret; 735177595Sweongyo 736177595Sweongyo MALO_HAL_LOCK(mh); 737177595Sweongyo 738177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_fw_set_aid, 739177595Sweongyo MALO_HOSTCMD_SET_AID); 740177595Sweongyo cmd->cmdhdr.seqnum = 1; 741177595Sweongyo cmd->associd = htole16(associd); 742177595Sweongyo IEEE80211_ADDR_COPY(&cmd->macaddr[0], bssid); 743177595Sweongyo 744177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_AID); 745177595Sweongyo MALO_HAL_UNLOCK(mh); 746177595Sweongyo return ret; 747177595Sweongyo} 748177595Sweongyo 749177595Sweongyo/* 750177595Sweongyo * Kick the firmware to tell it there are new tx descriptors 751177595Sweongyo * for processing. The driver says what h/w q has work in 752177595Sweongyo * case the f/w ever gets smarter. 753177595Sweongyo */ 754177595Sweongyovoid 755177595Sweongyomalo_hal_txstart(struct malo_hal *mh, int qnum) 756177595Sweongyo{ 757177595Sweongyo bus_space_write_4(mh->mh_iot, mh->mh_ioh, 758177595Sweongyo MALO_REG_H2A_INTERRUPT_EVENTS, MALO_H2ARIC_BIT_PPA_READY); 759177595Sweongyo (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MALO_REG_INT_CODE); 760177595Sweongyo} 761177595Sweongyo 762177595Sweongyo/* 763177595Sweongyo * Return the current ISR setting and clear the cause. 764177595Sweongyo */ 765177595Sweongyovoid 766177595Sweongyomalo_hal_getisr(struct malo_hal *mh, uint32_t *status) 767177595Sweongyo{ 768177595Sweongyo uint32_t cause; 769177595Sweongyo 770177595Sweongyo cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, 771177595Sweongyo MALO_REG_A2H_INTERRUPT_CAUSE); 772177595Sweongyo if (cause == 0xffffffff) { /* card removed */ 773177595Sweongyo cause = 0; 774177595Sweongyo } else if (cause != 0) { 775177595Sweongyo /* clear cause bits */ 776177595Sweongyo bus_space_write_4(mh->mh_iot, mh->mh_ioh, 777177595Sweongyo MALO_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); 778177595Sweongyo (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, 779177595Sweongyo MALO_REG_INT_CODE); 780177595Sweongyo cause &= mh->mh_imask; 781177595Sweongyo } 782177595Sweongyo 783177595Sweongyo *status = cause; 784177595Sweongyo} 785177595Sweongyo 786177595Sweongyo/* 787177595Sweongyo * Callback from the driver on a cmd done interrupt. Nothing to do right 788177595Sweongyo * now as we spin waiting for cmd completion. 789177595Sweongyo */ 790177595Sweongyovoid 791177595Sweongyomalo_hal_cmddone(struct malo_hal *mh) 792177595Sweongyo{ 793177595Sweongyo /* NB : do nothing. */ 794177595Sweongyo} 795177595Sweongyo 796177595Sweongyoint 797177595Sweongyomalo_hal_prescan(struct malo_hal *mh) 798177595Sweongyo{ 799177595Sweongyo struct malo_cmd_prescan *cmd; 800177595Sweongyo int ret; 801177595Sweongyo 802177595Sweongyo MALO_HAL_LOCK(mh); 803177595Sweongyo 804177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_prescan, MALO_HOSTCMD_SET_PRE_SCAN); 805177595Sweongyo cmd->cmdhdr.seqnum = 1; 806177595Sweongyo 807177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_PRE_SCAN); 808177595Sweongyo 809177595Sweongyo MALO_HAL_UNLOCK(mh); 810177595Sweongyo 811177595Sweongyo return ret; 812177595Sweongyo} 813177595Sweongyo 814177595Sweongyoint 815177595Sweongyomalo_hal_postscan(struct malo_hal *mh, uint8_t *macaddr, uint8_t ibsson) 816177595Sweongyo{ 817177595Sweongyo struct malo_cmd_postscan *cmd; 818177595Sweongyo int ret; 819177595Sweongyo 820177595Sweongyo MALO_HAL_LOCK(mh); 821177595Sweongyo 822177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_postscan, MALO_HOSTCMD_SET_POST_SCAN); 823177595Sweongyo cmd->cmdhdr.seqnum = 1; 824177595Sweongyo cmd->isibss = htole32(ibsson); 825177595Sweongyo IEEE80211_ADDR_COPY(&cmd->bssid[0], macaddr); 826177595Sweongyo 827177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_POST_SCAN); 828177595Sweongyo 829177595Sweongyo MALO_HAL_UNLOCK(mh); 830177595Sweongyo 831177595Sweongyo return ret; 832177595Sweongyo} 833177595Sweongyo 834177595Sweongyoint 835177595Sweongyomalo_hal_set_slot(struct malo_hal *mh, int is_short) 836177595Sweongyo{ 837177595Sweongyo int ret; 838177595Sweongyo struct malo_cmd_fw_setslot *cmd; 839177595Sweongyo 840177595Sweongyo MALO_HAL_LOCK(mh); 841177595Sweongyo 842177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_fw_setslot, MALO_HOSTCMD_SET_SLOT); 843177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 844177595Sweongyo cmd->slot = (is_short == 1 ? 1 : 0); 845177595Sweongyo 846177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_SLOT); 847177595Sweongyo 848177595Sweongyo MALO_HAL_UNLOCK(mh); 849177595Sweongyo 850177595Sweongyo return ret; 851177595Sweongyo} 852177595Sweongyo 853177595Sweongyoint 854177595Sweongyomalo_hal_set_rate(struct malo_hal *mh, uint16_t curmode, uint8_t rate) 855177595Sweongyo{ 856177595Sweongyo int i, ret; 857177595Sweongyo struct malo_cmd_set_rate *cmd; 858177595Sweongyo 859177595Sweongyo MALO_HAL_LOCK(mh); 860177595Sweongyo 861177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_set_rate, MALO_HOSTCMD_SET_RATE); 862177595Sweongyo cmd->aprates[0] = 2; 863177595Sweongyo cmd->aprates[1] = 4; 864177595Sweongyo cmd->aprates[2] = 11; 865177595Sweongyo cmd->aprates[3] = 22; 866177595Sweongyo if (curmode == IEEE80211_MODE_11G) { 867177595Sweongyo cmd->aprates[4] = 0; /* XXX reserved? */ 868177595Sweongyo cmd->aprates[5] = 12; 869177595Sweongyo cmd->aprates[6] = 18; 870177595Sweongyo cmd->aprates[7] = 24; 871177595Sweongyo cmd->aprates[8] = 36; 872177595Sweongyo cmd->aprates[9] = 48; 873177595Sweongyo cmd->aprates[10] = 72; 874177595Sweongyo cmd->aprates[11] = 96; 875177595Sweongyo cmd->aprates[12] = 108; 876177595Sweongyo } 877177595Sweongyo 878177595Sweongyo if (rate != 0) { 879177595Sweongyo /* fixed rate */ 880177595Sweongyo for (i = 0; i < 13; i++) { 881177595Sweongyo if (cmd->aprates[i] == rate) { 882177595Sweongyo cmd->rateindex = i; 883177595Sweongyo cmd->dataratetype = 1; 884177595Sweongyo break; 885177595Sweongyo } 886177595Sweongyo } 887177595Sweongyo } 888177595Sweongyo 889177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RATE); 890177595Sweongyo 891177595Sweongyo MALO_HAL_UNLOCK(mh); 892177595Sweongyo 893177595Sweongyo return ret; 894177595Sweongyo} 895177595Sweongyo 896177595Sweongyoint 897177595Sweongyomalo_hal_setmcast(struct malo_hal *mh, int nmc, const uint8_t macs[]) 898177595Sweongyo{ 899177595Sweongyo struct malo_cmd_mcast *cmd; 900177595Sweongyo int ret; 901177595Sweongyo 902177595Sweongyo if (nmc > MALO_HAL_MCAST_MAX) 903177595Sweongyo return EINVAL; 904177595Sweongyo 905177595Sweongyo MALO_HAL_LOCK(mh); 906177595Sweongyo 907177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_mcast, MALO_HOSTCMD_MAC_MULTICAST_ADR); 908177595Sweongyo memcpy(cmd->maclist, macs, nmc * IEEE80211_ADDR_LEN); 909177595Sweongyo cmd->numaddr = htole16(nmc); 910177595Sweongyo cmd->action = htole16(0xffff); 911177595Sweongyo 912177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_MAC_MULTICAST_ADR); 913177595Sweongyo 914177595Sweongyo MALO_HAL_UNLOCK(mh); 915177595Sweongyo 916177595Sweongyo return ret; 917177595Sweongyo} 918