ixv.h revision 217131
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixv.h 217131 2011-01-07 23:19:13Z jfv $*/ 34 35 36#ifndef _IXV_H_ 37#define _IXV_H_ 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/mbuf.h> 43#include <sys/protosw.h> 44#include <sys/socket.h> 45#include <sys/malloc.h> 46#include <sys/kernel.h> 47#include <sys/module.h> 48#include <sys/sockio.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/bpf.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56 57#include <net/bpf.h> 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in_systm.h> 62#include <netinet/in.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65#include <netinet/ip6.h> 66#include <netinet/tcp.h> 67#include <netinet/tcp_lro.h> 68#include <netinet/udp.h> 69 70#include <machine/in_cksum.h> 71 72#include <sys/bus.h> 73#include <machine/bus.h> 74#include <sys/rman.h> 75#include <machine/resource.h> 76#include <vm/vm.h> 77#include <vm/pmap.h> 78#include <machine/clock.h> 79#include <dev/pci/pcivar.h> 80#include <dev/pci/pcireg.h> 81#include <sys/proc.h> 82#include <sys/sysctl.h> 83#include <sys/endian.h> 84#include <sys/taskqueue.h> 85#include <sys/pcpu.h> 86#include <sys/smp.h> 87#include <machine/smp.h> 88 89#include "ixgbe_api.h" 90#include "ixgbe_vf.h" 91 92/* Tunables */ 93 94/* 95 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 96 * number of transmit descriptors allocated by the driver. Increasing this 97 * value allows the driver to queue more transmits. Each descriptor is 16 98 * bytes. Performance tests have show the 2K value to be optimal for top 99 * performance. 100 */ 101#define DEFAULT_TXD 1024 102#define PERFORM_TXD 2048 103#define MAX_TXD 4096 104#define MIN_TXD 64 105 106/* 107 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 108 * number of receive descriptors allocated for each RX queue. Increasing this 109 * value allows the driver to buffer more incoming packets. Each descriptor 110 * is 16 bytes. A receive buffer is also allocated for each descriptor. 111 * 112 * Note: with 8 rings and a dual port card, it is possible to bump up 113 * against the system mbuf pool limit, you can tune nmbclusters 114 * to adjust for this. 115 */ 116#define DEFAULT_RXD 1024 117#define PERFORM_RXD 2048 118#define MAX_RXD 4096 119#define MIN_RXD 64 120 121/* Alignment for rings */ 122#define DBA_ALIGN 128 123 124/* 125 * This parameter controls the maximum no of times the driver will loop in 126 * the isr. Minimum Value = 1 127 */ 128#define MAX_LOOP 10 129 130/* 131 * This is the max watchdog interval, ie. the time that can 132 * pass between any two TX clean operations, such only happening 133 * when the TX hardware is functioning. 134 */ 135#define IXV_WATCHDOG (10 * hz) 136 137/* 138 * This parameters control when the driver calls the routine to reclaim 139 * transmit descriptors. 140 */ 141#define IXV_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 142#define IXV_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 143 144#define IXV_MAX_FRAME_SIZE 0x3F00 145 146/* Flow control constants */ 147#define IXV_FC_PAUSE 0xFFFF 148#define IXV_FC_HI 0x20000 149#define IXV_FC_LO 0x10000 150 151/* Defines for printing debug information */ 152#define DEBUG_INIT 0 153#define DEBUG_IOCTL 0 154#define DEBUG_HW 0 155 156#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 157#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 158#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 159#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 160#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 161#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 162#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 163#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 164#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 165 166#define MAX_NUM_MULTICAST_ADDRESSES 128 167#define IXV_EITR_DEFAULT 128 168#define IXV_SCATTER 32 169#define IXV_RX_HDR 128 170#define MSIX_BAR 3 171#define IXV_TSO_SIZE 65535 172#define IXV_BR_SIZE 4096 173#define IXV_LINK_ITR 2000 174#define TX_BUFFER_SIZE ((u32) 1514) 175#define VFTA_SIZE 128 176 177/* Offload bits in mbuf flag */ 178#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 179 180/* 181 ***************************************************************************** 182 * vendor_info_array 183 * 184 * This array contains the list of Subvendor/Subdevice IDs on which the driver 185 * should load. 186 * 187 ***************************************************************************** 188 */ 189typedef struct _ixv_vendor_info_t { 190 unsigned int vendor_id; 191 unsigned int device_id; 192 unsigned int subvendor_id; 193 unsigned int subdevice_id; 194 unsigned int index; 195} ixv_vendor_info_t; 196 197 198struct ixv_tx_buf { 199 u32 eop_index; 200 struct mbuf *m_head; 201 bus_dmamap_t map; 202}; 203 204struct ixv_rx_buf { 205 struct mbuf *m_head; 206 struct mbuf *m_pack; 207 struct mbuf *fmp; 208 bus_dmamap_t hmap; 209 bus_dmamap_t pmap; 210}; 211 212/* 213 * Bus dma allocation structure used by ixv_dma_malloc and ixv_dma_free. 214 */ 215struct ixv_dma_alloc { 216 bus_addr_t dma_paddr; 217 caddr_t dma_vaddr; 218 bus_dma_tag_t dma_tag; 219 bus_dmamap_t dma_map; 220 bus_dma_segment_t dma_seg; 221 bus_size_t dma_size; 222 int dma_nseg; 223}; 224 225/* 226** Driver queue struct: this is the interrupt container 227** for the associated tx and rx ring. 228*/ 229struct ix_queue { 230 struct adapter *adapter; 231 u32 msix; /* This queue's MSIX vector */ 232 u32 eims; /* This queue's EIMS bit */ 233 u32 eitr_setting; 234 u32 eitr; /* cached reg */ 235 struct resource *res; 236 void *tag; 237 struct tx_ring *txr; 238 struct rx_ring *rxr; 239 struct task que_task; 240 struct taskqueue *tq; 241 u64 irqs; 242}; 243 244/* 245 * The transmit ring, one per queue 246 */ 247struct tx_ring { 248 struct adapter *adapter; 249 struct mtx tx_mtx; 250 u32 me; 251 bool watchdog_check; 252 int watchdog_time; 253 union ixgbe_adv_tx_desc *tx_base; 254 struct ixv_dma_alloc txdma; 255 u32 next_avail_desc; 256 u32 next_to_clean; 257 struct ixv_tx_buf *tx_buffers; 258 volatile u16 tx_avail; 259 u32 txd_cmd; 260 bus_dma_tag_t txtag; 261 char mtx_name[16]; 262 struct buf_ring *br; 263 /* Soft Stats */ 264 u32 bytes; 265 u32 packets; 266 u64 no_desc_avail; 267 u64 total_packets; 268}; 269 270 271/* 272 * The Receive ring, one per rx queue 273 */ 274struct rx_ring { 275 struct adapter *adapter; 276 struct mtx rx_mtx; 277 u32 me; 278 union ixgbe_adv_rx_desc *rx_base; 279 struct ixv_dma_alloc rxdma; 280 struct lro_ctrl lro; 281 bool lro_enabled; 282 bool hdr_split; 283 bool discard; 284 u32 next_to_refresh; 285 u32 next_to_check; 286 char mtx_name[16]; 287 struct ixv_rx_buf *rx_buffers; 288 bus_dma_tag_t htag; 289 bus_dma_tag_t ptag; 290 291 u32 bytes; /* Used for AIM calc */ 292 u32 packets; 293 294 /* Soft stats */ 295 u64 rx_irq; 296 u64 rx_split_packets; 297 u64 rx_packets; 298 u64 rx_bytes; 299 u64 rx_discarded; 300}; 301 302/* Our adapter structure */ 303struct adapter { 304 struct ifnet *ifp; 305 struct ixgbe_hw hw; 306 307 struct ixgbe_osdep osdep; 308 struct device *dev; 309 310 struct resource *pci_mem; 311 struct resource *msix_mem; 312 313 /* 314 * Interrupt resources: this set is 315 * either used for legacy, or for Link 316 * when doing MSIX 317 */ 318 void *tag; 319 struct resource *res; 320 321 struct ifmedia media; 322 struct callout timer; 323 int msix; 324 int if_flags; 325 326 struct mtx core_mtx; 327 328 eventhandler_tag vlan_attach; 329 eventhandler_tag vlan_detach; 330 331 u16 num_vlans; 332 u16 num_queues; 333 334 /* Info about the board itself */ 335 bool link_active; 336 u16 max_frame_size; 337 u32 link_speed; 338 bool link_up; 339 u32 mbxvec; 340 341 /* Mbuf cluster size */ 342 u32 rx_mbuf_sz; 343 344 /* Support for pluggable optics */ 345 struct task mbx_task; /* Mailbox tasklet */ 346 struct taskqueue *tq; 347 348 /* 349 ** Queues: 350 ** This is the irq holder, it has 351 ** and RX/TX pair or rings associated 352 ** with it. 353 */ 354 struct ix_queue *queues; 355 356 /* 357 * Transmit rings: 358 * Allocated at run time, an array of rings. 359 */ 360 struct tx_ring *tx_rings; 361 int num_tx_desc; 362 363 /* 364 * Receive rings: 365 * Allocated at run time, an array of rings. 366 */ 367 struct rx_ring *rx_rings; 368 int num_rx_desc; 369 u64 que_mask; 370 u32 rx_process_limit; 371 372 /* Misc stats maintained by the driver */ 373 unsigned long dropped_pkts; 374 unsigned long mbuf_defrag_failed; 375 unsigned long mbuf_header_failed; 376 unsigned long mbuf_packet_failed; 377 unsigned long no_tx_map_avail; 378 unsigned long no_tx_dma_setup; 379 unsigned long watchdog_events; 380 unsigned long tso_tx; 381 unsigned long mbx_irq; 382 383 struct ixgbevf_hw_stats stats; 384}; 385 386 387#define IXV_CORE_LOCK_INIT(_sc, _name) \ 388 mtx_init(&(_sc)->core_mtx, _name, "IXV Core Lock", MTX_DEF) 389#define IXV_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 390#define IXV_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 391#define IXV_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 392#define IXV_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 393#define IXV_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 394#define IXV_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 395#define IXV_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 396#define IXV_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 397#define IXV_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 398#define IXV_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 399#define IXV_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 400#define IXV_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 401 402/* Workaround to make 8.0 buildable */ 403#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 404static __inline int 405drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 406{ 407#ifdef ALTQ 408 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 409 return (1); 410#endif 411 return (!buf_ring_empty(br)); 412} 413#endif 414#endif /* _IXV_H_ */ 415