ixv.h revision 215911
1215911Sjfv/****************************************************************************** 2215911Sjfv 3215911Sjfv Copyright (c) 2001-2010, Intel Corporation 4215911Sjfv All rights reserved. 5215911Sjfv 6215911Sjfv Redistribution and use in source and binary forms, with or without 7215911Sjfv modification, are permitted provided that the following conditions are met: 8215911Sjfv 9215911Sjfv 1. Redistributions of source code must retain the above copyright notice, 10215911Sjfv this list of conditions and the following disclaimer. 11215911Sjfv 12215911Sjfv 2. Redistributions in binary form must reproduce the above copyright 13215911Sjfv notice, this list of conditions and the following disclaimer in the 14215911Sjfv documentation and/or other materials provided with the distribution. 15215911Sjfv 16215911Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17215911Sjfv contributors may be used to endorse or promote products derived from 18215911Sjfv this software without specific prior written permission. 19215911Sjfv 20215911Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21215911Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22215911Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23215911Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24215911Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25215911Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26215911Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27215911Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28215911Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29215911Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30215911Sjfv POSSIBILITY OF SUCH DAMAGE. 31215911Sjfv 32215911Sjfv******************************************************************************/ 33215911Sjfv/*$FreeBSD: head/sys/dev/ixgbe/ixv.h 215911 2010-11-26 22:46:32Z jfv $*/ 34215911Sjfv 35215911Sjfv 36215911Sjfv#ifndef _IXV_H_ 37215911Sjfv#define _IXV_H_ 38215911Sjfv 39215911Sjfv 40215911Sjfv#include <sys/param.h> 41215911Sjfv#include <sys/systm.h> 42215911Sjfv#include <sys/mbuf.h> 43215911Sjfv#include <sys/protosw.h> 44215911Sjfv#include <sys/socket.h> 45215911Sjfv#include <sys/malloc.h> 46215911Sjfv#include <sys/kernel.h> 47215911Sjfv#include <sys/module.h> 48215911Sjfv#include <sys/sockio.h> 49215911Sjfv 50215911Sjfv#include <net/if.h> 51215911Sjfv#include <net/if_arp.h> 52215911Sjfv#include <net/bpf.h> 53215911Sjfv#include <net/ethernet.h> 54215911Sjfv#include <net/if_dl.h> 55215911Sjfv#include <net/if_media.h> 56215911Sjfv 57215911Sjfv#include <net/bpf.h> 58215911Sjfv#include <net/if_types.h> 59215911Sjfv#include <net/if_vlan_var.h> 60215911Sjfv 61215911Sjfv#include <netinet/in_systm.h> 62215911Sjfv#include <netinet/in.h> 63215911Sjfv#include <netinet/if_ether.h> 64215911Sjfv#include <netinet/ip.h> 65215911Sjfv#include <netinet/ip6.h> 66215911Sjfv#include <netinet/tcp.h> 67215911Sjfv#include <netinet/tcp_lro.h> 68215911Sjfv#include <netinet/udp.h> 69215911Sjfv 70215911Sjfv#include <machine/in_cksum.h> 71215911Sjfv 72215911Sjfv#include <sys/bus.h> 73215911Sjfv#include <machine/bus.h> 74215911Sjfv#include <sys/rman.h> 75215911Sjfv#include <machine/resource.h> 76215911Sjfv#include <vm/vm.h> 77215911Sjfv#include <vm/pmap.h> 78215911Sjfv#include <machine/clock.h> 79215911Sjfv#include <dev/pci/pcivar.h> 80215911Sjfv#include <dev/pci/pcireg.h> 81215911Sjfv#include <sys/proc.h> 82215911Sjfv#include <sys/sysctl.h> 83215911Sjfv#include <sys/endian.h> 84215911Sjfv#include <sys/taskqueue.h> 85215911Sjfv#include <sys/pcpu.h> 86215911Sjfv#include <sys/smp.h> 87215911Sjfv#include <machine/smp.h> 88215911Sjfv 89215911Sjfv#include "ixgbe_api.h" 90215911Sjfv#include "ixgbe_vf.h" 91215911Sjfv 92215911Sjfv/* Tunables */ 93215911Sjfv 94215911Sjfv/* 95215911Sjfv * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 96215911Sjfv * number of transmit descriptors allocated by the driver. Increasing this 97215911Sjfv * value allows the driver to queue more transmits. Each descriptor is 16 98215911Sjfv * bytes. Performance tests have show the 2K value to be optimal for top 99215911Sjfv * performance. 100215911Sjfv */ 101215911Sjfv#define DEFAULT_TXD 1024 102215911Sjfv#define PERFORM_TXD 2048 103215911Sjfv#define MAX_TXD 4096 104215911Sjfv#define MIN_TXD 64 105215911Sjfv 106215911Sjfv/* 107215911Sjfv * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 108215911Sjfv * number of receive descriptors allocated for each RX queue. Increasing this 109215911Sjfv * value allows the driver to buffer more incoming packets. Each descriptor 110215911Sjfv * is 16 bytes. A receive buffer is also allocated for each descriptor. 111215911Sjfv * 112215911Sjfv * Note: with 8 rings and a dual port card, it is possible to bump up 113215911Sjfv * against the system mbuf pool limit, you can tune nmbclusters 114215911Sjfv * to adjust for this. 115215911Sjfv */ 116215911Sjfv#define DEFAULT_RXD 1024 117215911Sjfv#define PERFORM_RXD 2048 118215911Sjfv#define MAX_RXD 4096 119215911Sjfv#define MIN_RXD 64 120215911Sjfv 121215911Sjfv/* Alignment for rings */ 122215911Sjfv#define DBA_ALIGN 128 123215911Sjfv 124215911Sjfv/* 125215911Sjfv * This parameter controls the maximum no of times the driver will loop in 126215911Sjfv * the isr. Minimum Value = 1 127215911Sjfv */ 128215911Sjfv#define MAX_LOOP 10 129215911Sjfv 130215911Sjfv/* 131215911Sjfv * This is the max watchdog interval, ie. the time that can 132215911Sjfv * pass between any two TX clean operations, such only happening 133215911Sjfv * when the TX hardware is functioning. 134215911Sjfv */ 135215911Sjfv#define IXV_WATCHDOG (10 * hz) 136215911Sjfv 137215911Sjfv/* 138215911Sjfv * This parameters control when the driver calls the routine to reclaim 139215911Sjfv * transmit descriptors. 140215911Sjfv */ 141215911Sjfv#define IXV_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 142215911Sjfv#define IXV_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 143215911Sjfv 144215911Sjfv#define IXV_MAX_FRAME_SIZE 0x3F00 145215911Sjfv 146215911Sjfv/* Flow control constants */ 147215911Sjfv#define IXV_FC_PAUSE 0xFFFF 148215911Sjfv#define IXV_FC_HI 0x20000 149215911Sjfv#define IXV_FC_LO 0x10000 150215911Sjfv 151215911Sjfv/* Defines for printing debug information */ 152215911Sjfv#define DEBUG_INIT 0 153215911Sjfv#define DEBUG_IOCTL 0 154215911Sjfv#define DEBUG_HW 0 155215911Sjfv 156215911Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 157215911Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 158215911Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 159215911Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 160215911Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 161215911Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 162215911Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 163215911Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 164215911Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 165215911Sjfv 166215911Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 167215911Sjfv#define IXV_EITR_DEFAULT 128 168215911Sjfv#define IXV_SCATTER 32 169215911Sjfv#define IXV_RX_HDR 128 170215911Sjfv#define MSIX_BAR 3 171215911Sjfv#define IXV_TSO_SIZE 65535 172215911Sjfv#define IXV_BR_SIZE 4096 173215911Sjfv#define IXV_LINK_ITR 2000 174215911Sjfv#define TX_BUFFER_SIZE ((u32) 1514) 175215911Sjfv#define VFTA_SIZE 128 176215911Sjfv 177215911Sjfv/* Offload bits in mbuf flag */ 178215911Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 179215911Sjfv 180215911Sjfv/* 181215911Sjfv ***************************************************************************** 182215911Sjfv * vendor_info_array 183215911Sjfv * 184215911Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 185215911Sjfv * should load. 186215911Sjfv * 187215911Sjfv ***************************************************************************** 188215911Sjfv */ 189215911Sjfvtypedef struct _ixv_vendor_info_t { 190215911Sjfv unsigned int vendor_id; 191215911Sjfv unsigned int device_id; 192215911Sjfv unsigned int subvendor_id; 193215911Sjfv unsigned int subdevice_id; 194215911Sjfv unsigned int index; 195215911Sjfv} ixv_vendor_info_t; 196215911Sjfv 197215911Sjfv 198215911Sjfvstruct ixv_tx_buf { 199215911Sjfv u32 eop_index; 200215911Sjfv struct mbuf *m_head; 201215911Sjfv bus_dmamap_t map; 202215911Sjfv}; 203215911Sjfv 204215911Sjfvstruct ixv_rx_buf { 205215911Sjfv struct mbuf *m_head; 206215911Sjfv struct mbuf *m_pack; 207215911Sjfv struct mbuf *fmp; 208215911Sjfv bus_dmamap_t hmap; 209215911Sjfv bus_dmamap_t pmap; 210215911Sjfv}; 211215911Sjfv 212215911Sjfv/* 213215911Sjfv * Bus dma allocation structure used by ixv_dma_malloc and ixv_dma_free. 214215911Sjfv */ 215215911Sjfvstruct ixv_dma_alloc { 216215911Sjfv bus_addr_t dma_paddr; 217215911Sjfv caddr_t dma_vaddr; 218215911Sjfv bus_dma_tag_t dma_tag; 219215911Sjfv bus_dmamap_t dma_map; 220215911Sjfv bus_dma_segment_t dma_seg; 221215911Sjfv bus_size_t dma_size; 222215911Sjfv int dma_nseg; 223215911Sjfv}; 224215911Sjfv 225215911Sjfv/* 226215911Sjfv** Driver queue struct: this is the interrupt container 227215911Sjfv** for the associated tx and rx ring. 228215911Sjfv*/ 229215911Sjfvstruct ix_queue { 230215911Sjfv struct adapter *adapter; 231215911Sjfv u32 msix; /* This queue's MSIX vector */ 232215911Sjfv u32 eims; /* This queue's EIMS bit */ 233215911Sjfv u32 eitr_setting; 234215911Sjfv u32 eitr; /* cached reg */ 235215911Sjfv struct resource *res; 236215911Sjfv void *tag; 237215911Sjfv struct tx_ring *txr; 238215911Sjfv struct rx_ring *rxr; 239215911Sjfv struct task que_task; 240215911Sjfv struct taskqueue *tq; 241215911Sjfv u64 irqs; 242215911Sjfv}; 243215911Sjfv 244215911Sjfv/* 245215911Sjfv * The transmit ring, one per queue 246215911Sjfv */ 247215911Sjfvstruct tx_ring { 248215911Sjfv struct adapter *adapter; 249215911Sjfv struct mtx tx_mtx; 250215911Sjfv u32 me; 251215911Sjfv bool watchdog_check; 252215911Sjfv int watchdog_time; 253215911Sjfv union ixgbe_adv_tx_desc *tx_base; 254215911Sjfv struct ixv_dma_alloc txdma; 255215911Sjfv u32 next_avail_desc; 256215911Sjfv u32 next_to_clean; 257215911Sjfv struct ixv_tx_buf *tx_buffers; 258215911Sjfv volatile u16 tx_avail; 259215911Sjfv u32 txd_cmd; 260215911Sjfv bus_dma_tag_t txtag; 261215911Sjfv char mtx_name[16]; 262215911Sjfv struct buf_ring *br; 263215911Sjfv /* Soft Stats */ 264215911Sjfv u32 bytes; 265215911Sjfv u32 packets; 266215911Sjfv u64 no_desc_avail; 267215911Sjfv u64 total_packets; 268215911Sjfv}; 269215911Sjfv 270215911Sjfv 271215911Sjfv/* 272215911Sjfv * The Receive ring, one per rx queue 273215911Sjfv */ 274215911Sjfvstruct rx_ring { 275215911Sjfv struct adapter *adapter; 276215911Sjfv struct mtx rx_mtx; 277215911Sjfv u32 me; 278215911Sjfv union ixgbe_adv_rx_desc *rx_base; 279215911Sjfv struct ixv_dma_alloc rxdma; 280215911Sjfv struct lro_ctrl lro; 281215911Sjfv bool lro_enabled; 282215911Sjfv bool hdr_split; 283215911Sjfv bool discard; 284215911Sjfv u32 next_to_refresh; 285215911Sjfv u32 next_to_check; 286215911Sjfv char mtx_name[16]; 287215911Sjfv struct ixv_rx_buf *rx_buffers; 288215911Sjfv bus_dma_tag_t htag; 289215911Sjfv bus_dma_tag_t ptag; 290215911Sjfv 291215911Sjfv u32 bytes; /* Used for AIM calc */ 292215911Sjfv u32 packets; 293215911Sjfv 294215911Sjfv /* Soft stats */ 295215911Sjfv u64 rx_irq; 296215911Sjfv u64 rx_split_packets; 297215911Sjfv u64 rx_packets; 298215911Sjfv u64 rx_bytes; 299215911Sjfv u64 rx_discarded; 300215911Sjfv}; 301215911Sjfv 302215911Sjfv/* Our adapter structure */ 303215911Sjfvstruct adapter { 304215911Sjfv struct ifnet *ifp; 305215911Sjfv struct ixgbe_hw hw; 306215911Sjfv 307215911Sjfv struct ixgbe_osdep osdep; 308215911Sjfv struct device *dev; 309215911Sjfv 310215911Sjfv struct resource *pci_mem; 311215911Sjfv struct resource *msix_mem; 312215911Sjfv 313215911Sjfv /* 314215911Sjfv * Interrupt resources: this set is 315215911Sjfv * either used for legacy, or for Link 316215911Sjfv * when doing MSIX 317215911Sjfv */ 318215911Sjfv void *tag; 319215911Sjfv struct resource *res; 320215911Sjfv 321215911Sjfv struct ifmedia media; 322215911Sjfv struct callout timer; 323215911Sjfv int msix; 324215911Sjfv int if_flags; 325215911Sjfv 326215911Sjfv struct mtx core_mtx; 327215911Sjfv 328215911Sjfv eventhandler_tag vlan_attach; 329215911Sjfv eventhandler_tag vlan_detach; 330215911Sjfv 331215911Sjfv u16 num_vlans; 332215911Sjfv u16 num_queues; 333215911Sjfv 334215911Sjfv /* Info about the board itself */ 335215911Sjfv bool link_active; 336215911Sjfv u16 max_frame_size; 337215911Sjfv u32 link_speed; 338215911Sjfv bool link_up; 339215911Sjfv u32 mbxvec; 340215911Sjfv 341215911Sjfv /* Mbuf cluster size */ 342215911Sjfv u32 rx_mbuf_sz; 343215911Sjfv 344215911Sjfv /* Support for pluggable optics */ 345215911Sjfv struct task mbx_task; /* Mailbox tasklet */ 346215911Sjfv struct taskqueue *tq; 347215911Sjfv 348215911Sjfv /* 349215911Sjfv ** Queues: 350215911Sjfv ** This is the irq holder, it has 351215911Sjfv ** and RX/TX pair or rings associated 352215911Sjfv ** with it. 353215911Sjfv */ 354215911Sjfv struct ix_queue *queues; 355215911Sjfv 356215911Sjfv /* 357215911Sjfv * Transmit rings: 358215911Sjfv * Allocated at run time, an array of rings. 359215911Sjfv */ 360215911Sjfv struct tx_ring *tx_rings; 361215911Sjfv int num_tx_desc; 362215911Sjfv 363215911Sjfv /* 364215911Sjfv * Receive rings: 365215911Sjfv * Allocated at run time, an array of rings. 366215911Sjfv */ 367215911Sjfv struct rx_ring *rx_rings; 368215911Sjfv int num_rx_desc; 369215911Sjfv u64 que_mask; 370215911Sjfv u32 rx_process_limit; 371215911Sjfv 372215911Sjfv /* Misc stats maintained by the driver */ 373215911Sjfv unsigned long dropped_pkts; 374215911Sjfv unsigned long mbuf_defrag_failed; 375215911Sjfv unsigned long mbuf_header_failed; 376215911Sjfv unsigned long mbuf_packet_failed; 377215911Sjfv unsigned long no_tx_map_avail; 378215911Sjfv unsigned long no_tx_dma_setup; 379215911Sjfv unsigned long watchdog_events; 380215911Sjfv unsigned long tso_tx; 381215911Sjfv unsigned long mbx_irq; 382215911Sjfv 383215911Sjfv struct ixgbevf_hw_stats stats; 384215911Sjfv}; 385215911Sjfv 386215911Sjfv 387215911Sjfv#define IXV_CORE_LOCK_INIT(_sc, _name) \ 388215911Sjfv mtx_init(&(_sc)->core_mtx, _name, "IXV Core Lock", MTX_DEF) 389215911Sjfv#define IXV_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 390215911Sjfv#define IXV_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 391215911Sjfv#define IXV_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 392215911Sjfv#define IXV_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 393215911Sjfv#define IXV_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 394215911Sjfv#define IXV_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 395215911Sjfv#define IXV_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 396215911Sjfv#define IXV_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 397215911Sjfv#define IXV_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 398215911Sjfv#define IXV_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 399215911Sjfv#define IXV_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 400215911Sjfv#define IXV_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 401215911Sjfv 402215911Sjfv/* Workaround to make 8.0 buildable */ 403215911Sjfv#if __FreeBSD_version < 800504 404215911Sjfvstatic __inline int 405215911Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 406215911Sjfv{ 407215911Sjfv#ifdef ALTQ 408215911Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 409215911Sjfv return (1); 410215911Sjfv#endif 411215911Sjfv return (!buf_ring_empty(br)); 412215911Sjfv} 413215911Sjfv#endif 414215911Sjfv#endif /* _IXV_H_ */ 415