ixgbe_type.h revision 267654
1/****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: releng/9.3/sys/dev/ixgbe/ixgbe_type.h 252898 2013-07-06 21:38:55Z jfv $*/ 34 35#ifndef _IXGBE_TYPE_H_ 36#define _IXGBE_TYPE_H_ 37 38/* 39 * The following is a brief description of the error categories used by the 40 * ERROR_REPORT* macros. 41 * 42 * - IXGBE_ERROR_INVALID_STATE 43 * This category is for errors which represent a serious failure state that is 44 * unexpected, and could be potentially harmful to device operation. It should 45 * not be used for errors relating to issues that can be worked around or 46 * ignored. 47 * 48 * - IXGBE_ERROR_POLLING 49 * This category is for errors related to polling/timeout issues and should be 50 * used in any case where the timeout occured, or a failure to obtain a lock, or 51 * failure to receive data within the time limit. 52 * 53 * - IXGBE_ERROR_CAUTION 54 * This category should be used for reporting issues that may be the cause of 55 * other errors, such as temperature warnings. It should indicate an event which 56 * could be serious, but hasn't necessarily caused problems yet. 57 * 58 * - IXGBE_ERROR_SOFTWARE 59 * This category is intended for errors due to software state preventing 60 * something. The category is not intended for errors due to bad arguments, or 61 * due to unsupported features. It should be used when a state occurs which 62 * prevents action but is not a serious issue. 63 * 64 * - IXGBE_ERROR_ARGUMENT 65 * This category is for when a bad or invalid argument is passed. It should be 66 * used whenever a function is called and error checking has detected the 67 * argument is wrong or incorrect. 68 * 69 * - IXGBE_ERROR_UNSUPPORTED 70 * This category is for errors which are due to unsupported circumstances or 71 * configuration issues. It should not be used when the issue is due to an 72 * invalid argument, but for when something has occurred that is unsupported 73 * (Ex: Flow control autonegotiation or an unsupported SFP+ module.) 74 */ 75 76#include "ixgbe_osdep.h" 77 78 79/* Vendor ID */ 80#define IXGBE_INTEL_VENDOR_ID 0x8086 81 82/* Device IDs */ 83#define IXGBE_DEV_ID_82598 0x10B6 84#define IXGBE_DEV_ID_82598_BX 0x1508 85#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 86#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 87#define IXGBE_DEV_ID_82598AT 0x10C8 88#define IXGBE_DEV_ID_82598AT2 0x150B 89#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 90#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 91#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 92#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 93#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 94#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 95#define IXGBE_DEV_ID_82599_KX4 0x10F7 96#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 97#define IXGBE_DEV_ID_82599_KR 0x1517 98#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 99#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 100#define IXGBE_DEV_ID_82599_CX4 0x10F9 101#define IXGBE_DEV_ID_82599_SFP 0x10FB 102#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 103#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 104#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 105#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 106#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B 107#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976 108#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A 109#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 110#define IXGBE_DEV_ID_82599_SFP_EM 0x1507 111#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 112#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 113#define IXGBE_DEV_ID_82599EN_SFP 0x1557 114#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 115#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 116#define IXGBE_DEV_ID_82599_T3_LOM 0x151C 117#define IXGBE_DEV_ID_82599_VF 0x10ED 118#define IXGBE_DEV_ID_82599_VF_HV 0x152E 119#define IXGBE_DEV_ID_82599_BYPASS 0x155D 120#define IXGBE_DEV_ID_X540T 0x1528 121#define IXGBE_DEV_ID_X540_VF 0x1515 122#define IXGBE_DEV_ID_X540_VF_HV 0x1530 123#define IXGBE_DEV_ID_X540_BYPASS 0x155C 124 125/* General Registers */ 126#define IXGBE_CTRL 0x00000 127#define IXGBE_STATUS 0x00008 128#define IXGBE_CTRL_EXT 0x00018 129#define IXGBE_ESDP 0x00020 130#define IXGBE_EODSDP 0x00028 131#define IXGBE_I2CCTL 0x00028 132#define IXGBE_PHY_GPIO 0x00028 133#define IXGBE_MAC_GPIO 0x00030 134#define IXGBE_PHYINT_STATUS0 0x00100 135#define IXGBE_PHYINT_STATUS1 0x00104 136#define IXGBE_PHYINT_STATUS2 0x00108 137#define IXGBE_LEDCTL 0x00200 138#define IXGBE_FRTIMER 0x00048 139#define IXGBE_TCPTIMER 0x0004C 140#define IXGBE_CORESPARE 0x00600 141#define IXGBE_EXVET 0x05078 142 143/* NVM Registers */ 144#define IXGBE_EEC 0x10010 145#define IXGBE_EERD 0x10014 146#define IXGBE_EEWR 0x10018 147#define IXGBE_FLA 0x1001C 148#define IXGBE_EEMNGCTL 0x10110 149#define IXGBE_EEMNGDATA 0x10114 150#define IXGBE_FLMNGCTL 0x10118 151#define IXGBE_FLMNGDATA 0x1011C 152#define IXGBE_FLMNGCNT 0x10120 153#define IXGBE_FLOP 0x1013C 154#define IXGBE_GRC 0x10200 155#define IXGBE_SRAMREL 0x10210 156#define IXGBE_PHYDBG 0x10218 157 158/* General Receive Control */ 159#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 160#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 161 162#define IXGBE_VPDDIAG0 0x10204 163#define IXGBE_VPDDIAG1 0x10208 164 165/* I2CCTL Bit Masks */ 166#define IXGBE_I2C_CLK_IN 0x00000001 167#define IXGBE_I2C_CLK_OUT 0x00000002 168#define IXGBE_I2C_DATA_IN 0x00000004 169#define IXGBE_I2C_DATA_OUT 0x00000008 170#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 171 172 173/* Interrupt Registers */ 174#define IXGBE_EICR 0x00800 175#define IXGBE_EICS 0x00808 176#define IXGBE_EIMS 0x00880 177#define IXGBE_EIMC 0x00888 178#define IXGBE_EIAC 0x00810 179#define IXGBE_EIAM 0x00890 180#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 181#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 182#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 183#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 184/* 82599 EITR is only 12 bits, with the lower 3 always zero */ 185/* 186 * 82598 EITR is 16 bits but set the limits based on the max 187 * supported by all ixgbe hardware 188 */ 189#define IXGBE_MAX_INT_RATE 488281 190#define IXGBE_MIN_INT_RATE 956 191#define IXGBE_MAX_EITR 0x00000FF8 192#define IXGBE_MIN_EITR 8 193#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 194 (0x012300 + (((_i) - 24) * 4))) 195#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 196#define IXGBE_EITR_LLI_MOD 0x00008000 197#define IXGBE_EITR_CNT_WDIS 0x80000000 198#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 199#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 200#define IXGBE_EITRSEL 0x00894 201#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 202#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 203#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 204#define IXGBE_GPIE 0x00898 205 206/* Flow Control Registers */ 207#define IXGBE_FCADBUL 0x03210 208#define IXGBE_FCADBUH 0x03214 209#define IXGBE_FCAMACL 0x04328 210#define IXGBE_FCAMACH 0x0432C 211#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 212#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 213#define IXGBE_PFCTOP 0x03008 214#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 215#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 216#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 217#define IXGBE_FCRTV 0x032A0 218#define IXGBE_FCCFG 0x03D00 219#define IXGBE_TFCS 0x0CE00 220 221/* Receive DMA Registers */ 222#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 223 (0x0D000 + (((_i) - 64) * 0x40))) 224#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 225 (0x0D004 + (((_i) - 64) * 0x40))) 226#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 227 (0x0D008 + (((_i) - 64) * 0x40))) 228#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 229 (0x0D010 + (((_i) - 64) * 0x40))) 230#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 231 (0x0D018 + (((_i) - 64) * 0x40))) 232#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 233 (0x0D028 + (((_i) - 64) * 0x40))) 234#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 235 (0x0D02C + (((_i) - 64) * 0x40))) 236#define IXGBE_RSCDBU 0x03028 237#define IXGBE_RDDCC 0x02F20 238#define IXGBE_RXMEMWRAP 0x03190 239#define IXGBE_STARCTRL 0x03024 240/* 241 * Split and Replication Receive Control Registers 242 * 00-15 : 0x02100 + n*4 243 * 16-64 : 0x01014 + n*0x40 244 * 64-127: 0x0D014 + (n-64)*0x40 245 */ 246#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 247 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 248 (0x0D014 + (((_i) - 64) * 0x40)))) 249/* 250 * Rx DCA Control Register: 251 * 00-15 : 0x02200 + n*4 252 * 16-64 : 0x0100C + n*0x40 253 * 64-127: 0x0D00C + (n-64)*0x40 254 */ 255#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 256 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 257 (0x0D00C + (((_i) - 64) * 0x40)))) 258#define IXGBE_RDRXCTL 0x02F00 259/* 8 of these 0x03C00 - 0x03C1C */ 260#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 261#define IXGBE_RXCTRL 0x03000 262#define IXGBE_DROPEN 0x03D04 263#define IXGBE_RXPBSIZE_SHIFT 10 264#define IXGBE_RXPBSIZE_MASK 0x000FFC00 265 266/* Receive Registers */ 267#define IXGBE_RXCSUM 0x05000 268#define IXGBE_RFCTL 0x05008 269#define IXGBE_DRECCCTL 0x02F08 270#define IXGBE_DRECCCTL_DISABLE 0 271#define IXGBE_DRECCCTL2 0x02F8C 272 273/* Multicast Table Array - 128 entries */ 274#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 275#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 276 (0x0A200 + ((_i) * 8))) 277#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 278 (0x0A204 + ((_i) * 8))) 279#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 280#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 281/* Packet split receive type */ 282#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 283 (0x0EA00 + ((_i) * 4))) 284/* array of 4096 1-bit vlan filters */ 285#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 286/*array of 4096 4-bit vlan vmdq indices */ 287#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 288#define IXGBE_FCTRL 0x05080 289#define IXGBE_VLNCTRL 0x05088 290#define IXGBE_MCSTCTRL 0x05090 291#define IXGBE_MRQC 0x05818 292#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 293#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 294#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 295#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 296#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 297#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 298#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 299#define IXGBE_RQTC 0x0EC70 300#define IXGBE_MTQC 0x08120 301#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 302#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 303#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 304#define IXGBE_VT_CTL 0x051B0 305#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 306/* 64 Mailboxes, 16 DW each */ 307#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) 308#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 309#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 310#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 311#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 312#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 313#define IXGBE_QDE 0x2F04 314#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 315#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 316#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 317#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 318#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 319#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 320#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 321#define IXGBE_RXFECCERR0 0x051B8 322#define IXGBE_LLITHRESH 0x0EC90 323#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 324#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 325#define IXGBE_IMIRVP 0x05AC0 326#define IXGBE_VMD_CTL 0x0581C 327#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 328#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 329 330 331/* Flow Director registers */ 332#define IXGBE_FDIRCTRL 0x0EE00 333#define IXGBE_FDIRHKEY 0x0EE68 334#define IXGBE_FDIRSKEY 0x0EE6C 335#define IXGBE_FDIRDIP4M 0x0EE3C 336#define IXGBE_FDIRSIP4M 0x0EE40 337#define IXGBE_FDIRTCPM 0x0EE44 338#define IXGBE_FDIRUDPM 0x0EE48 339#define IXGBE_FDIRIP6M 0x0EE74 340#define IXGBE_FDIRM 0x0EE70 341 342/* Flow Director Stats registers */ 343#define IXGBE_FDIRFREE 0x0EE38 344#define IXGBE_FDIRLEN 0x0EE4C 345#define IXGBE_FDIRUSTAT 0x0EE50 346#define IXGBE_FDIRFSTAT 0x0EE54 347#define IXGBE_FDIRMATCH 0x0EE58 348#define IXGBE_FDIRMISS 0x0EE5C 349 350/* Flow Director Programming registers */ 351#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 352#define IXGBE_FDIRIPSA 0x0EE18 353#define IXGBE_FDIRIPDA 0x0EE1C 354#define IXGBE_FDIRPORT 0x0EE20 355#define IXGBE_FDIRVLAN 0x0EE24 356#define IXGBE_FDIRHASH 0x0EE28 357#define IXGBE_FDIRCMD 0x0EE2C 358 359/* Transmit DMA registers */ 360#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/ 361#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 362#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 363#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 364#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 365#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 366#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 367#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 368#define IXGBE_DTXCTL 0x07E00 369 370#define IXGBE_DMATXCTL 0x04A80 371#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 372#define IXGBE_PFDTXGSWC 0x08220 373#define IXGBE_DTXMXSZRQ 0x08100 374#define IXGBE_DTXTCPFLGL 0x04A88 375#define IXGBE_DTXTCPFLGH 0x04A8C 376#define IXGBE_LBDRPEN 0x0CA00 377#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 378 379#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 380#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 381#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 382#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 383 384#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 385 386/* Anti-spoofing defines */ 387#define IXGBE_SPOOF_MACAS_MASK 0xFF 388#define IXGBE_SPOOF_VLANAS_MASK 0xFF00 389#define IXGBE_SPOOF_VLANAS_SHIFT 8 390#define IXGBE_PFVFSPOOF_REG_COUNT 8 391/* 16 of these (0-15) */ 392#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 393/* Tx DCA Control register : 128 of these (0-127) */ 394#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 395#define IXGBE_TIPG 0x0CB00 396#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 397#define IXGBE_MNGTXMAP 0x0CD10 398#define IXGBE_TIPG_FIBER_DEFAULT 3 399#define IXGBE_TXPBSIZE_SHIFT 10 400 401/* Wake up registers */ 402#define IXGBE_WUC 0x05800 403#define IXGBE_WUFC 0x05808 404#define IXGBE_WUS 0x05810 405#define IXGBE_IPAV 0x05838 406#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 407#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 408 409#define IXGBE_WUPL 0x05900 410#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 411 412#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */ 413/* Ext Flexible Host Filter Table */ 414#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) 415 416/* Four Flexible Filters are supported */ 417#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 418 419/* Six Flexible Filters are supported */ 420#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6 421#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 422 423/* Each Flexible Filter is at most 128 (0x80) bytes in length */ 424#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 425#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 426#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 427 428/* Definitions for power management and wakeup registers */ 429/* Wake Up Control */ 430#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 431#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 432#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 433 434/* Wake Up Filter Control */ 435#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 436#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 437#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 438#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 439#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 440#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 441#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 442#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 443#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 444 445#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 446#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 447#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 448#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 449#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 450#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 451#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 452#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 453/* Mask for Ext. flex filters */ 454#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 455#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */ 456#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */ 457#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 458 459/* Wake Up Status */ 460#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 461#define IXGBE_WUS_MAG IXGBE_WUFC_MAG 462#define IXGBE_WUS_EX IXGBE_WUFC_EX 463#define IXGBE_WUS_MC IXGBE_WUFC_MC 464#define IXGBE_WUS_BC IXGBE_WUFC_BC 465#define IXGBE_WUS_ARP IXGBE_WUFC_ARP 466#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 467#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 468#define IXGBE_WUS_MNG IXGBE_WUFC_MNG 469#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 470#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 471#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 472#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 473#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 474#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 475#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 476 477#define IXGBE_WUPL_LENGTH_MASK 0xFFFF 478 479/* DCB registers */ 480#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8 481#define IXGBE_RMCS 0x03D00 482#define IXGBE_DPMCS 0x07F40 483#define IXGBE_PDPMCS 0x0CD00 484#define IXGBE_RUPPBMR 0x050A0 485#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 486#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 487#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 488#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 489#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 490#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 491 492 493 494/* Security Control Registers */ 495#define IXGBE_SECTXCTRL 0x08800 496#define IXGBE_SECTXSTAT 0x08804 497#define IXGBE_SECTXBUFFAF 0x08808 498#define IXGBE_SECTXMINIFG 0x08810 499#define IXGBE_SECRXCTRL 0x08D00 500#define IXGBE_SECRXSTAT 0x08D04 501 502/* Security Bit Fields and Masks */ 503#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 504#define IXGBE_SECTXCTRL_TX_DIS 0x00000002 505#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 506 507#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 508#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 509 510#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 511#define IXGBE_SECRXCTRL_RX_DIS 0x00000002 512 513#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 514#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 515 516/* LinkSec (MacSec) Registers */ 517#define IXGBE_LSECTXCAP 0x08A00 518#define IXGBE_LSECRXCAP 0x08F00 519#define IXGBE_LSECTXCTRL 0x08A04 520#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 521#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 522#define IXGBE_LSECTXSA 0x08A10 523#define IXGBE_LSECTXPN0 0x08A14 524#define IXGBE_LSECTXPN1 0x08A18 525#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 526#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 527#define IXGBE_LSECRXCTRL 0x08F04 528#define IXGBE_LSECRXSCL 0x08F08 529#define IXGBE_LSECRXSCH 0x08F0C 530#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 531#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 532#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 533#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 534#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 535#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 536#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 537#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 538#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 539#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 540#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 541#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 542#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 543#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 544#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 545#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 546#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 547#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 548#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 549#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 550#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 551#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 552 553/* LinkSec (MacSec) Bit Fields and Masks */ 554#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 555#define IXGBE_LSECTXCAP_SUM_SHIFT 16 556#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 557#define IXGBE_LSECRXCAP_SUM_SHIFT 16 558 559#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 560#define IXGBE_LSECTXCTRL_DISABLE 0x0 561#define IXGBE_LSECTXCTRL_AUTH 0x1 562#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 563#define IXGBE_LSECTXCTRL_AISCI 0x00000020 564#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 565#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 566 567#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 568#define IXGBE_LSECRXCTRL_EN_SHIFT 2 569#define IXGBE_LSECRXCTRL_DISABLE 0x0 570#define IXGBE_LSECRXCTRL_CHECK 0x1 571#define IXGBE_LSECRXCTRL_STRICT 0x2 572#define IXGBE_LSECRXCTRL_DROP 0x3 573#define IXGBE_LSECRXCTRL_PLSH 0x00000040 574#define IXGBE_LSECRXCTRL_RP 0x00000080 575#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 576 577/* IpSec Registers */ 578#define IXGBE_IPSTXIDX 0x08900 579#define IXGBE_IPSTXSALT 0x08904 580#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 581#define IXGBE_IPSRXIDX 0x08E00 582#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 583#define IXGBE_IPSRXSPI 0x08E14 584#define IXGBE_IPSRXIPIDX 0x08E18 585#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 586#define IXGBE_IPSRXSALT 0x08E2C 587#define IXGBE_IPSRXMOD 0x08E30 588 589#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 590 591/* DCB registers */ 592#define IXGBE_RTRPCS 0x02430 593#define IXGBE_RTTDCS 0x04900 594#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 595#define IXGBE_RTTPCS 0x0CD00 596#define IXGBE_RTRUP2TC 0x03020 597#define IXGBE_RTTUP2TC 0x0C800 598#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 599#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 600#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 601#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 602#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 603#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 604#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 605#define IXGBE_RTTDQSEL 0x04904 606#define IXGBE_RTTDT1C 0x04908 607#define IXGBE_RTTDT1S 0x0490C 608#define IXGBE_RTTDTECC 0x04990 609#define IXGBE_RTTDTECC_NO_BCN 0x00000100 610 611#define IXGBE_RTTBCNRC 0x04984 612#define IXGBE_RTTBCNRC_RS_ENA 0x80000000 613#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 614#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 615#define IXGBE_RTTBCNRC_RF_INT_MASK \ 616 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 617#define IXGBE_RTTBCNRM 0x04980 618 619/* BCN (for DCB) Registers */ 620#define IXGBE_RTTBCNRS 0x04988 621#define IXGBE_RTTBCNCR 0x08B00 622#define IXGBE_RTTBCNACH 0x08B04 623#define IXGBE_RTTBCNACL 0x08B08 624#define IXGBE_RTTBCNTG 0x04A90 625#define IXGBE_RTTBCNIDX 0x08B0C 626#define IXGBE_RTTBCNCP 0x08B10 627#define IXGBE_RTFRTIMER 0x08B14 628#define IXGBE_RTTBCNRTT 0x05150 629#define IXGBE_RTTBCNRD 0x0498C 630 631 632/* FCoE DMA Context Registers */ 633#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 634#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 635#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 636#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 637#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 638#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 639#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 640#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 641#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 642#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 643#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 644#define IXGBE_FCBUFF_OFFSET_SHIFT 16 645#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 646#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 647#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 648#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 649#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 650/* FCoE SOF/EOF */ 651#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 652#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 653#define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 654#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 655/* FCoE Filter Context Registers */ 656#define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 657#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 658#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 659#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 660#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 661#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 662#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 663#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 664#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 665#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 666/* FCoE Receive Control */ 667#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 668#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 669#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 670#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 671#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 672#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 673#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 674#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 675#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 676#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 677#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 678/* FCoE Redirection */ 679#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 680#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 681#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 682#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 683#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */ 684#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 685#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 686 687/* Stats registers */ 688#define IXGBE_CRCERRS 0x04000 689#define IXGBE_ILLERRC 0x04004 690#define IXGBE_ERRBC 0x04008 691#define IXGBE_MSPDC 0x04010 692#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 693#define IXGBE_MLFC 0x04034 694#define IXGBE_MRFC 0x04038 695#define IXGBE_RLEC 0x04040 696#define IXGBE_LXONTXC 0x03F60 697#define IXGBE_LXONRXC 0x0CF60 698#define IXGBE_LXOFFTXC 0x03F68 699#define IXGBE_LXOFFRXC 0x0CF68 700#define IXGBE_LXONRXCNT 0x041A4 701#define IXGBE_LXOFFRXCNT 0x041A8 702#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 703#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 704#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 705#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 706#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 707#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 708#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 709#define IXGBE_PRC64 0x0405C 710#define IXGBE_PRC127 0x04060 711#define IXGBE_PRC255 0x04064 712#define IXGBE_PRC511 0x04068 713#define IXGBE_PRC1023 0x0406C 714#define IXGBE_PRC1522 0x04070 715#define IXGBE_GPRC 0x04074 716#define IXGBE_BPRC 0x04078 717#define IXGBE_MPRC 0x0407C 718#define IXGBE_GPTC 0x04080 719#define IXGBE_GORCL 0x04088 720#define IXGBE_GORCH 0x0408C 721#define IXGBE_GOTCL 0x04090 722#define IXGBE_GOTCH 0x04094 723#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 724#define IXGBE_RUC 0x040A4 725#define IXGBE_RFC 0x040A8 726#define IXGBE_ROC 0x040AC 727#define IXGBE_RJC 0x040B0 728#define IXGBE_MNGPRC 0x040B4 729#define IXGBE_MNGPDC 0x040B8 730#define IXGBE_MNGPTC 0x0CF90 731#define IXGBE_TORL 0x040C0 732#define IXGBE_TORH 0x040C4 733#define IXGBE_TPR 0x040D0 734#define IXGBE_TPT 0x040D4 735#define IXGBE_PTC64 0x040D8 736#define IXGBE_PTC127 0x040DC 737#define IXGBE_PTC255 0x040E0 738#define IXGBE_PTC511 0x040E4 739#define IXGBE_PTC1023 0x040E8 740#define IXGBE_PTC1522 0x040EC 741#define IXGBE_MPTC 0x040F0 742#define IXGBE_BPTC 0x040F4 743#define IXGBE_XEC 0x04120 744#define IXGBE_SSVPC 0x08780 745 746#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 747#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 748 (0x08600 + ((_i) * 4))) 749#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 750 751#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 752#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 753#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 754#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 755#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 756#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 757#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 758#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 759#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 760#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */ 761#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 762#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 763#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 764#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 765#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 766#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 767#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ 768#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ 769#define IXGBE_O2BGPTC 0x041C4 770#define IXGBE_O2BSPC 0x087B0 771#define IXGBE_B2OSPC 0x041C0 772#define IXGBE_B2OGPRC 0x02F90 773#define IXGBE_BUPRC 0x04180 774#define IXGBE_BMPRC 0x04184 775#define IXGBE_BBPRC 0x04188 776#define IXGBE_BUPTC 0x0418C 777#define IXGBE_BMPTC 0x04190 778#define IXGBE_BBPTC 0x04194 779#define IXGBE_BCRCERRS 0x04198 780#define IXGBE_BXONRXC 0x0419C 781#define IXGBE_BXOFFRXC 0x041E0 782#define IXGBE_BXONTXC 0x041E4 783#define IXGBE_BXOFFTXC 0x041E8 784#define IXGBE_PCRC8ECL 0x0E810 785#define IXGBE_PCRC8ECH 0x0E811 786#define IXGBE_PCRC8ECH_MASK 0x1F 787#define IXGBE_LDPCECL 0x0E820 788#define IXGBE_LDPCECH 0x0E821 789 790/* Management */ 791#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 792#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 793#define IXGBE_MANC 0x05820 794#define IXGBE_MFVAL 0x05824 795#define IXGBE_MANC2H 0x05860 796#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 797#define IXGBE_MIPAF 0x058B0 798#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 799#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 800#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 801#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 802#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 803#define IXGBE_LSWFW 0x15014 804#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ 805#define IXGBE_BMCIPVAL 0x05060 806#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001 807#define IXGBE_BMCIP_IPADDR_VALID 0x00000002 808 809/* Management Bit Fields and Masks */ 810#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 811#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */ 812#define IXGBE_MANC_EN_BMC2OS_SHIFT 28 813 814/* Firmware Semaphore Register */ 815#define IXGBE_FWSM_MODE_MASK 0xE 816#define IXGBE_FWSM_TS_ENABLED 0x1 817#define IXGBE_FWSM_FW_MODE_PT 0x4 818 819/* ARC Subsystem registers */ 820#define IXGBE_HICR 0x15F00 821#define IXGBE_FWSTS 0x15F0C 822#define IXGBE_HSMC0R 0x15F04 823#define IXGBE_HSMC1R 0x15F08 824#define IXGBE_SWSR 0x15F10 825#define IXGBE_HFDR 0x15FE8 826#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 827 828#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 829/* Driver sets this bit when done to put command in RAM */ 830#define IXGBE_HICR_C 0x02 831#define IXGBE_HICR_SV 0x04 /* Status Validity */ 832#define IXGBE_HICR_FW_RESET_ENABLE 0x40 833#define IXGBE_HICR_FW_RESET 0x80 834 835/* PCI-E registers */ 836#define IXGBE_GCR 0x11000 837#define IXGBE_GTV 0x11004 838#define IXGBE_FUNCTAG 0x11008 839#define IXGBE_GLT 0x1100C 840#define IXGBE_PCIEPIPEADR 0x11004 841#define IXGBE_PCIEPIPEDAT 0x11008 842#define IXGBE_GSCL_1 0x11010 843#define IXGBE_GSCL_2 0x11014 844#define IXGBE_GSCL_3 0x11018 845#define IXGBE_GSCL_4 0x1101C 846#define IXGBE_GSCN_0 0x11020 847#define IXGBE_GSCN_1 0x11024 848#define IXGBE_GSCN_2 0x11028 849#define IXGBE_GSCN_3 0x1102C 850#define IXGBE_FACTPS 0x10150 851#define IXGBE_PCIEANACTL 0x11040 852#define IXGBE_SWSM 0x10140 853#define IXGBE_FWSM 0x10148 854#define IXGBE_GSSR 0x10160 855#define IXGBE_MREVID 0x11064 856#define IXGBE_DCA_ID 0x11070 857#define IXGBE_DCA_CTRL 0x11074 858#define IXGBE_SWFW_SYNC IXGBE_GSSR 859 860/* PCI-E registers 82599-Specific */ 861#define IXGBE_GCR_EXT 0x11050 862#define IXGBE_GSCL_5_82599 0x11030 863#define IXGBE_GSCL_6_82599 0x11034 864#define IXGBE_GSCL_7_82599 0x11038 865#define IXGBE_GSCL_8_82599 0x1103C 866#define IXGBE_PHYADR_82599 0x11040 867#define IXGBE_PHYDAT_82599 0x11044 868#define IXGBE_PHYCTL_82599 0x11048 869#define IXGBE_PBACLR_82599 0x11068 870#define IXGBE_CIAA_82599 0x11088 871#define IXGBE_CIAD_82599 0x1108C 872#define IXGBE_PICAUSE 0x110B0 873#define IXGBE_PIENA 0x110B8 874#define IXGBE_CDQ_MBR_82599 0x110B4 875#define IXGBE_PCIESPARE 0x110BC 876#define IXGBE_MISC_REG_82599 0x110F0 877#define IXGBE_ECC_CTRL_0_82599 0x11100 878#define IXGBE_ECC_CTRL_1_82599 0x11104 879#define IXGBE_ECC_STATUS_82599 0x110E0 880#define IXGBE_BAR_CTRL_82599 0x110F4 881 882/* PCI Express Control */ 883#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 884#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 885#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 886#define IXGBE_GCR_CAP_VER2 0x00040000 887 888#define IXGBE_GCR_EXT_MSIX_EN 0x80000000 889#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 890#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 891#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 892#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 893#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 894 IXGBE_GCR_EXT_VT_MODE_64) 895#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003 896/* Time Sync Registers */ 897#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 898#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 899#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 900#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 901#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 902#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 903#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 904#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 905#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 906#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 907#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 908#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 909#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 910#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 911#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 912#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 913#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 914#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 915#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 916#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 917#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 918#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 919#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 920#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 921#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 922#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 923#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 924 925/* Diagnostic Registers */ 926#define IXGBE_RDSTATCTL 0x02C20 927#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 928#define IXGBE_RDHMPN 0x02F08 929#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 930#define IXGBE_RDPROBE 0x02F20 931#define IXGBE_RDMAM 0x02F30 932#define IXGBE_RDMAD 0x02F34 933#define IXGBE_TDHMPN 0x07F08 934#define IXGBE_TDHMPN2 0x082FC 935#define IXGBE_TXDESCIC 0x082CC 936#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 937#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 938#define IXGBE_TDPROBE 0x07F20 939#define IXGBE_TXBUFCTRL 0x0C600 940#define IXGBE_TXBUFDATA0 0x0C610 941#define IXGBE_TXBUFDATA1 0x0C614 942#define IXGBE_TXBUFDATA2 0x0C618 943#define IXGBE_TXBUFDATA3 0x0C61C 944#define IXGBE_RXBUFCTRL 0x03600 945#define IXGBE_RXBUFDATA0 0x03610 946#define IXGBE_RXBUFDATA1 0x03614 947#define IXGBE_RXBUFDATA2 0x03618 948#define IXGBE_RXBUFDATA3 0x0361C 949#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 950#define IXGBE_RFVAL 0x050A4 951#define IXGBE_MDFTC1 0x042B8 952#define IXGBE_MDFTC2 0x042C0 953#define IXGBE_MDFTFIFO1 0x042C4 954#define IXGBE_MDFTFIFO2 0x042C8 955#define IXGBE_MDFTS 0x042CC 956#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 957#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 958#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 959#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 960#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 961#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 962#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 963#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 964#define IXGBE_PCIEECCCTL 0x1106C 965#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 966#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 967#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 968#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 969#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 970#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 971#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 972#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 973#define IXGBE_PCIEECCCTL0 0x11100 974#define IXGBE_PCIEECCCTL1 0x11104 975#define IXGBE_RXDBUECC 0x03F70 976#define IXGBE_TXDBUECC 0x0CF70 977#define IXGBE_RXDBUEST 0x03F74 978#define IXGBE_TXDBUEST 0x0CF74 979#define IXGBE_PBTXECC 0x0C300 980#define IXGBE_PBRXECC 0x03300 981#define IXGBE_GHECCR 0x110B0 982 983/* MAC Registers */ 984#define IXGBE_PCS1GCFIG 0x04200 985#define IXGBE_PCS1GLCTL 0x04208 986#define IXGBE_PCS1GLSTA 0x0420C 987#define IXGBE_PCS1GDBG0 0x04210 988#define IXGBE_PCS1GDBG1 0x04214 989#define IXGBE_PCS1GANA 0x04218 990#define IXGBE_PCS1GANLP 0x0421C 991#define IXGBE_PCS1GANNP 0x04220 992#define IXGBE_PCS1GANLPNP 0x04224 993#define IXGBE_HLREG0 0x04240 994#define IXGBE_HLREG1 0x04244 995#define IXGBE_PAP 0x04248 996#define IXGBE_MACA 0x0424C 997#define IXGBE_APAE 0x04250 998#define IXGBE_ARD 0x04254 999#define IXGBE_AIS 0x04258 1000#define IXGBE_MSCA 0x0425C 1001#define IXGBE_MSRWD 0x04260 1002#define IXGBE_MLADD 0x04264 1003#define IXGBE_MHADD 0x04268 1004#define IXGBE_MAXFRS 0x04268 1005#define IXGBE_TREG 0x0426C 1006#define IXGBE_PCSS1 0x04288 1007#define IXGBE_PCSS2 0x0428C 1008#define IXGBE_XPCSS 0x04290 1009#define IXGBE_MFLCN 0x04294 1010#define IXGBE_SERDESC 0x04298 1011#define IXGBE_MACS 0x0429C 1012#define IXGBE_AUTOC 0x042A0 1013#define IXGBE_LINKS 0x042A4 1014#define IXGBE_LINKS2 0x04324 1015#define IXGBE_AUTOC2 0x042A8 1016#define IXGBE_AUTOC3 0x042AC 1017#define IXGBE_ANLP1 0x042B0 1018#define IXGBE_ANLP2 0x042B4 1019#define IXGBE_MACC 0x04330 1020#define IXGBE_ATLASCTL 0x04800 1021#define IXGBE_MMNGC 0x042D0 1022#define IXGBE_ANLPNP1 0x042D4 1023#define IXGBE_ANLPNP2 0x042D8 1024#define IXGBE_KRPCSFC 0x042E0 1025#define IXGBE_KRPCSS 0x042E4 1026#define IXGBE_FECS1 0x042E8 1027#define IXGBE_FECS2 0x042EC 1028#define IXGBE_SMADARCTL 0x14F10 1029#define IXGBE_MPVC 0x04318 1030#define IXGBE_SGMIIC 0x04314 1031 1032/* Statistics Registers */ 1033#define IXGBE_RXNFGPC 0x041B0 1034#define IXGBE_RXNFGBCL 0x041B4 1035#define IXGBE_RXNFGBCH 0x041B8 1036#define IXGBE_RXDGPC 0x02F50 1037#define IXGBE_RXDGBCL 0x02F54 1038#define IXGBE_RXDGBCH 0x02F58 1039#define IXGBE_RXDDGPC 0x02F5C 1040#define IXGBE_RXDDGBCL 0x02F60 1041#define IXGBE_RXDDGBCH 0x02F64 1042#define IXGBE_RXLPBKGPC 0x02F68 1043#define IXGBE_RXLPBKGBCL 0x02F6C 1044#define IXGBE_RXLPBKGBCH 0x02F70 1045#define IXGBE_RXDLPBKGPC 0x02F74 1046#define IXGBE_RXDLPBKGBCL 0x02F78 1047#define IXGBE_RXDLPBKGBCH 0x02F7C 1048#define IXGBE_TXDGPC 0x087A0 1049#define IXGBE_TXDGBCL 0x087A4 1050#define IXGBE_TXDGBCH 0x087A8 1051 1052#define IXGBE_RXDSTATCTRL 0x02F40 1053 1054/* Copper Pond 2 link timeout */ 1055#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 1056 1057/* Omer CORECTL */ 1058#define IXGBE_CORECTL 0x014F00 1059/* BARCTRL */ 1060#define IXGBE_BARCTRL 0x110F4 1061#define IXGBE_BARCTRL_FLSIZE 0x0700 1062#define IXGBE_BARCTRL_FLSIZE_SHIFT 8 1063#define IXGBE_BARCTRL_CSRSIZE 0x2000 1064 1065/* RSCCTL Bit Masks */ 1066#define IXGBE_RSCCTL_RSCEN 0x01 1067#define IXGBE_RSCCTL_MAXDESC_1 0x00 1068#define IXGBE_RSCCTL_MAXDESC_4 0x04 1069#define IXGBE_RSCCTL_MAXDESC_8 0x08 1070#define IXGBE_RSCCTL_MAXDESC_16 0x0C 1071#define IXGBE_RSCCTL_TS_DIS 0x02 1072 1073/* RSCDBU Bit Masks */ 1074#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 1075#define IXGBE_RSCDBU_RSCACKDIS 0x00000080 1076 1077/* RDRXCTL Bit Masks */ 1078#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */ 1079#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1080#define IXGBE_RDRXCTL_MVMEN 0x00000020 1081#define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020 1082#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1083#define IXGBE_RDRXCTL_RSC_PUSH 0x00000080 1084#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1085#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1086#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/ 1087#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */ 1088#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */ 1089 1090/* RQTC Bit Masks and Shifts */ 1091#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 1092#define IXGBE_RQTC_TC0_MASK (0x7 << 0) 1093#define IXGBE_RQTC_TC1_MASK (0x7 << 4) 1094#define IXGBE_RQTC_TC2_MASK (0x7 << 8) 1095#define IXGBE_RQTC_TC3_MASK (0x7 << 12) 1096#define IXGBE_RQTC_TC4_MASK (0x7 << 16) 1097#define IXGBE_RQTC_TC5_MASK (0x7 << 20) 1098#define IXGBE_RQTC_TC6_MASK (0x7 << 24) 1099#define IXGBE_RQTC_TC7_MASK (0x7 << 28) 1100 1101/* PSRTYPE.RQPL Bit masks and shift */ 1102#define IXGBE_PSRTYPE_RQPL_MASK 0x7 1103#define IXGBE_PSRTYPE_RQPL_SHIFT 29 1104 1105/* CTRL Bit Masks */ 1106#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 1107#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 1108#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 1109#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 1110 1111/* FACTPS */ 1112#define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ 1113#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1114 1115/* MHADD Bit Masks */ 1116#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1117#define IXGBE_MHADD_MFS_SHIFT 16 1118 1119/* Extended Device Control */ 1120#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1121#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1122#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1123#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1124 1125/* Direct Cache Access (DCA) definitions */ 1126#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1127#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1128 1129#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1130#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1131 1132#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1133#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1134#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1135#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ 1136#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ 1137#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ 1138#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ 1139#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1140#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1141 1142#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1143#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1144#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1145#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1146#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1147#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1148#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1149#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1150 1151/* MSCA Bit Masks */ 1152#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */ 1153#define IXGBE_MSCA_NP_ADDR_SHIFT 0 1154#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */ 1155#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */ 1156#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1157#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1158#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1159#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1160#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1161#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */ 1162#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */ 1163#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/ 1164#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1165#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1166#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */ 1167#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */ 1168#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1169#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */ 1170 1171/* MSRWD bit masks */ 1172#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1173#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1174#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1175#define IXGBE_MSRWD_READ_DATA_SHIFT 16 1176 1177/* Atlas registers */ 1178#define IXGBE_ATLAS_PDN_LPBK 0x24 1179#define IXGBE_ATLAS_PDN_10G 0xB 1180#define IXGBE_ATLAS_PDN_1G 0xC 1181#define IXGBE_ATLAS_PDN_AN 0xD 1182 1183/* Atlas bit masks */ 1184#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1185#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1186#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1187#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1188#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1189 1190/* Omer bit masks */ 1191#define IXGBE_CORECTL_WRITE_CMD 0x00010000 1192 1193/* Device Type definitions for new protocol MDIO commands */ 1194#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 1195#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 1196#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 1197#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 1198#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 1199#define IXGBE_TWINAX_DEV 1 1200 1201#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1202 1203#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ 1204#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1205#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1206#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ 1207#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1208#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1209 1210#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 1211#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1212#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 1213#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 1214#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 1215#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 1216#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 1217#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 1218#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 1219#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 1220#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 1221#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ 1222#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 1223#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 1224#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 1225#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 1226#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 1227 1228#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */ 1229#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1230#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1231#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1232 1233/* MII clause 22/28 definitions */ 1234#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 1235 1236#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 1237#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1238#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1239#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 1240#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 1241#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1242#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1243#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 1244#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ 1245#define IXGBE_MII_RESTART 0x200 1246#define IXGBE_MII_AUTONEG_COMPLETE 0x20 1247#define IXGBE_MII_AUTONEG_LINK_UP 0x04 1248#define IXGBE_MII_AUTONEG_REG 0x0 1249 1250#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1251#define IXGBE_MAX_PHY_ADDR 32 1252 1253/* PHY IDs*/ 1254#define TN1010_PHY_ID 0x00A19410 1255#define TNX_FW_REV 0xB 1256#define X540_PHY_ID 0x01540200 1257#define AQ_FW_REV 0x20 1258#define QT2022_PHY_ID 0x0043A400 1259#define ATH_PHY_ID 0x03429050 1260 1261/* PHY Types */ 1262#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 1263 1264/* Special PHY Init Routine */ 1265#define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1266#define IXGBE_PHY_INIT_END_NL 0xFFFF 1267#define IXGBE_CONTROL_MASK_NL 0xF000 1268#define IXGBE_DATA_MASK_NL 0x0FFF 1269#define IXGBE_CONTROL_SHIFT_NL 12 1270#define IXGBE_DELAY_NL 0 1271#define IXGBE_DATA_NL 1 1272#define IXGBE_CONTROL_NL 0x000F 1273#define IXGBE_CONTROL_EOL_NL 0x0FFF 1274#define IXGBE_CONTROL_SOL_NL 0x0000 1275 1276/* General purpose Interrupt Enable */ 1277#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1278#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1279#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1280#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1281#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1282#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1283#define IXGBE_GPIE_EIAME 0x40000000 1284#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1285#define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1286#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1287#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1288#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1289#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1290 1291/* Packet Buffer Initialization */ 1292#define IXGBE_MAX_PACKET_BUFFERS 8 1293 1294#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1295#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1296#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1297#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1298#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1299#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1300#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */ 1301#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 1302 1303#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1304#define IXGBE_MAX_PB 8 1305 1306/* Packet buffer allocation strategies */ 1307enum { 1308 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1309#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1310 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1311#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1312}; 1313 1314/* Transmit Flow Control status */ 1315#define IXGBE_TFCS_TXOFF 0x00000001 1316#define IXGBE_TFCS_TXOFF0 0x00000100 1317#define IXGBE_TFCS_TXOFF1 0x00000200 1318#define IXGBE_TFCS_TXOFF2 0x00000400 1319#define IXGBE_TFCS_TXOFF3 0x00000800 1320#define IXGBE_TFCS_TXOFF4 0x00001000 1321#define IXGBE_TFCS_TXOFF5 0x00002000 1322#define IXGBE_TFCS_TXOFF6 0x00004000 1323#define IXGBE_TFCS_TXOFF7 0x00008000 1324 1325/* TCP Timer */ 1326#define IXGBE_TCPTIMER_KS 0x00000100 1327#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1328#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1329#define IXGBE_TCPTIMER_LOOP 0x00000800 1330#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1331 1332/* HLREG0 Bit Masks */ 1333#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1334#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1335#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1336#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1337#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1338#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1339#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1340#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1341#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1342#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1343#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1344#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1345#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1346#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1347#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1348 1349/* VMD_CTL bitmasks */ 1350#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1351#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1352 1353/* VT_CTL bitmasks */ 1354#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1355#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1356#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1357#define IXGBE_VT_CTL_POOL_SHIFT 7 1358#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1359 1360/* VMOLR bitmasks */ 1361#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1362#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1363#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1364#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1365#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1366 1367/* VFRE bitmask */ 1368#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1369 1370#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1371 1372/* RDHMPN and TDHMPN bitmasks */ 1373#define IXGBE_RDHMPN_RDICADDR 0x007FF800 1374#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1375#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1376#define IXGBE_TDHMPN_TDICADDR 0x003FF800 1377#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1378#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1379 1380#define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1381#define IXGBE_RDMAM_DWORD_SHIFT 9 1382#define IXGBE_RDMAM_DESC_COMP_FIFO 1 1383#define IXGBE_RDMAM_DFC_CMD_FIFO 2 1384#define IXGBE_RDMAM_RSC_HEADER_ADDR 3 1385#define IXGBE_RDMAM_TCN_STATUS_RAM 4 1386#define IXGBE_RDMAM_WB_COLL_FIFO 5 1387#define IXGBE_RDMAM_QSC_CNT_RAM 6 1388#define IXGBE_RDMAM_QSC_FCOE_RAM 7 1389#define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1390#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1391#define IXGBE_RDMAM_QSC_RSC_RAM 0xB 1392#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1393#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1394#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1395#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1396#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 1397#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 1398#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1399#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1400#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1401#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1402#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1403#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1404#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 1405#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 1406#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1407#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1408#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1409#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1410#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 1411#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 1412 1413#define IXGBE_TXDESCIC_READY 0x80000000 1414 1415/* Receive Checksum Control */ 1416#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1417#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1418 1419/* FCRTL Bit Masks */ 1420#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1421#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1422 1423/* PAP bit masks*/ 1424#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1425 1426/* RMCS Bit Masks */ 1427#define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */ 1428/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1429#define IXGBE_RMCS_RAC 0x00000004 1430/* Deficit Fixed Prio ena */ 1431#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC 1432#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1433#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1434#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1435 1436/* FCCFG Bit Masks */ 1437#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1438#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1439 1440/* Interrupt register bitmasks */ 1441 1442/* Extended Interrupt Cause Read */ 1443#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1444#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1445#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1446#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1447#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1448#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1449#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1450#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1451#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1452#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 1453#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1454#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1455#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1456#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1457#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1458#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1459#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1460#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1461 1462/* Extended Interrupt Cause Set */ 1463#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1464#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1465#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1466#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1467#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1468#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1469#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1470#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1471#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1472#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1473#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1474#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1475#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1476#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1477#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1478#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1479 1480/* Extended Interrupt Mask Set */ 1481#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1482#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1483#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1484#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1485#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1486#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1487#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1488#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */ 1489#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1490#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1491#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1492#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1493#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1494#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1495#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1496#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1497#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1498 1499/* Extended Interrupt Mask Clear */ 1500#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1501#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1502#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1503#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1504#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1505#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1506#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1507#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1508#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1509#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1510#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1511#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1512#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1513#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1514#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1515#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1516 1517#define IXGBE_EIMS_ENABLE_MASK ( \ 1518 IXGBE_EIMS_RTX_QUEUE | \ 1519 IXGBE_EIMS_LSC | \ 1520 IXGBE_EIMS_TCP_TIMER | \ 1521 IXGBE_EIMS_OTHER) 1522 1523/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1524#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1525#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1526#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1527#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1528#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1529#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1530#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1531#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1532#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1533#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1534#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1535#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1536#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1537#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1538#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1539#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1540#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1541#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */ 1542#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1543#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1544#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1545#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1546#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1547 1548#define IXGBE_MAX_FTQF_FILTERS 128 1549#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1550#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1551#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1552#define IXGBE_FTQF_PROTOCOL_SCTP 2 1553#define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1554#define IXGBE_FTQF_PRIORITY_SHIFT 2 1555#define IXGBE_FTQF_POOL_MASK 0x0000003F 1556#define IXGBE_FTQF_POOL_SHIFT 8 1557#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1558#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1559#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1560#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1561#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1562#define IXGBE_FTQF_DEST_PORT_MASK 0x17 1563#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1564#define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1565#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1566 1567/* Interrupt clear mask */ 1568#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1569 1570/* Interrupt Vector Allocation Registers */ 1571#define IXGBE_IVAR_REG_NUM 25 1572#define IXGBE_IVAR_REG_NUM_82599 64 1573#define IXGBE_IVAR_TXRX_ENTRY 96 1574#define IXGBE_IVAR_RX_ENTRY 64 1575#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1576#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1577#define IXGBE_IVAR_TX_ENTRY 32 1578 1579#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1580#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1581 1582#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1583 1584#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1585 1586/* ETYPE Queue Filter/Select Bit Masks */ 1587#define IXGBE_MAX_ETQF_FILTERS 8 1588#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 1589#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 1590#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1591#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1592#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 1593#define IXGBE_ETQF_POOL_SHIFT 20 1594 1595#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1596#define IXGBE_ETQS_RX_QUEUE_SHIFT 16 1597#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 1598#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 1599 1600/* 1601 * ETQF filter list: one static filter per filter consumer. This is 1602 * to avoid filter collisions later. Add new filters 1603 * here!! 1604 * 1605 * Current filters: 1606 * EAPOL 802.1x (0x888e): Filter 0 1607 * FCoE (0x8906): Filter 2 1608 * 1588 (0x88f7): Filter 3 1609 * FIP (0x8914): Filter 4 1610 */ 1611#define IXGBE_ETQF_FILTER_EAPOL 0 1612#define IXGBE_ETQF_FILTER_FCOE 2 1613#define IXGBE_ETQF_FILTER_1588 3 1614#define IXGBE_ETQF_FILTER_FIP 4 1615/* VLAN Control Bit Masks */ 1616#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1617#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1618#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 1619#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1620#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1621 1622/* VLAN pool filtering masks */ 1623#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 1624#define IXGBE_VLVF_ENTRIES 64 1625#define IXGBE_VLVF_VLANID_MASK 0x00000FFF 1626/* Per VF Port VLAN insertion rules */ 1627#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 1628#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 1629 1630#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1631 1632/* STATUS Bit Masks */ 1633#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1634#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 1635#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */ 1636 1637#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1638#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1639 1640/* ESDP Bit Masks */ 1641#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 1642#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 1643#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 1644#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 1645#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 1646#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 1647#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 1648#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */ 1649#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 1650#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 1651#define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */ 1652#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */ 1653#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */ 1654#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 1655#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */ 1656#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */ 1657#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */ 1658#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 1659 1660 1661/* LEDCTL Bit Masks */ 1662#define IXGBE_LED_IVRT_BASE 0x00000040 1663#define IXGBE_LED_BLINK_BASE 0x00000080 1664#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 1665#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 1666#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 1667#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 1668#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 1669#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 1670 1671/* LED modes */ 1672#define IXGBE_LED_LINK_UP 0x0 1673#define IXGBE_LED_LINK_10G 0x1 1674#define IXGBE_LED_MAC 0x2 1675#define IXGBE_LED_FILTER 0x3 1676#define IXGBE_LED_LINK_ACTIVE 0x4 1677#define IXGBE_LED_LINK_1G 0x5 1678#define IXGBE_LED_ON 0xE 1679#define IXGBE_LED_OFF 0xF 1680 1681/* AUTOC Bit Masks */ 1682#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 1683#define IXGBE_AUTOC_KX4_SUPP 0x80000000 1684#define IXGBE_AUTOC_KX_SUPP 0x40000000 1685#define IXGBE_AUTOC_PAUSE 0x30000000 1686#define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1687#define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1688#define IXGBE_AUTOC_RF 0x08000000 1689#define IXGBE_AUTOC_PD_TMR 0x06000000 1690#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1691#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1692#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1693#define IXGBE_AUTOC_FECA 0x00040000 1694#define IXGBE_AUTOC_FECR 0x00020000 1695#define IXGBE_AUTOC_KR_SUPP 0x00010000 1696#define IXGBE_AUTOC_AN_RESTART 0x00001000 1697#define IXGBE_AUTOC_FLU 0x00000001 1698#define IXGBE_AUTOC_LMS_SHIFT 13 1699#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 1700#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1701#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 1702#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1703#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1704#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1705#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1706#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1707#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 1708#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1709#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1710#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1711 1712#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 1713#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1714#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1715#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1716#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1717#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1718#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1719#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1720#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1721#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1722#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1723 1724#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1725#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1726#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1727#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1728#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1729#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1730#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 1731#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 1732 1733#define IXGBE_MACC_FLU 0x00000001 1734#define IXGBE_MACC_FSV_10G 0x00030000 1735#define IXGBE_MACC_FS 0x00040000 1736#define IXGBE_MAC_RX2TX_LPBK 0x00000002 1737 1738/* LINKS Bit Masks */ 1739#define IXGBE_LINKS_KX_AN_COMP 0x80000000 1740#define IXGBE_LINKS_UP 0x40000000 1741#define IXGBE_LINKS_SPEED 0x20000000 1742#define IXGBE_LINKS_MODE 0x18000000 1743#define IXGBE_LINKS_RX_MODE 0x06000000 1744#define IXGBE_LINKS_TX_MODE 0x01800000 1745#define IXGBE_LINKS_XGXS_EN 0x00400000 1746#define IXGBE_LINKS_SGMII_EN 0x02000000 1747#define IXGBE_LINKS_PCS_1G_EN 0x00200000 1748#define IXGBE_LINKS_1G_AN_EN 0x00100000 1749#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1750#define IXGBE_LINKS_1G_SYNC 0x00040000 1751#define IXGBE_LINKS_10G_ALIGN 0x00020000 1752#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 1753#define IXGBE_LINKS_TL_FAULT 0x00001000 1754#define IXGBE_LINKS_SIGNAL 0x00000F00 1755 1756#define IXGBE_LINKS_SPEED_82599 0x30000000 1757#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 1758#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 1759#define IXGBE_LINKS_SPEED_100_82599 0x10000000 1760#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1761#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1762 1763#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1764 1765/* PCS1GLSTA Bit Masks */ 1766#define IXGBE_PCS1GLSTA_LINK_OK 1 1767#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 1768#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 1769#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 1770#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 1771#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 1772#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 1773 1774#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 1775#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 1776 1777/* PCS1GLCTL Bit Masks */ 1778#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 1779#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 1780#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 1781#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1782#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1783#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1784 1785/* ANLP1 Bit Masks */ 1786#define IXGBE_ANLP1_PAUSE 0x0C00 1787#define IXGBE_ANLP1_SYM_PAUSE 0x0400 1788#define IXGBE_ANLP1_ASM_PAUSE 0x0800 1789#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 1790 1791/* SW Semaphore Register bitmasks */ 1792#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1793#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1794#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1795#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 1796 1797/* SW_FW_SYNC/GSSR definitions */ 1798#define IXGBE_GSSR_EEP_SM 0x0001 1799#define IXGBE_GSSR_PHY0_SM 0x0002 1800#define IXGBE_GSSR_PHY1_SM 0x0004 1801#define IXGBE_GSSR_MAC_CSR_SM 0x0008 1802#define IXGBE_GSSR_FLASH_SM 0x0010 1803#define IXGBE_GSSR_SW_MNG_SM 0x0400 1804 1805/* FW Status register bitmask */ 1806#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 1807 1808/* EEC Register */ 1809#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 1810#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 1811#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 1812#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 1813#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 1814#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1815#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 1816#define IXGBE_EEC_FWE_SHIFT 4 1817#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 1818#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 1819#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 1820#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 1821#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 1822#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 1823#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 1824/* EEPROM Addressing bits based on type (0-small, 1-large) */ 1825#define IXGBE_EEC_ADDR_SIZE 0x00000400 1826#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 1827#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 1828 1829#define IXGBE_EEC_SIZE_SHIFT 11 1830#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 1831#define IXGBE_EEPROM_OPCODE_BITS 8 1832 1833/* Part Number String Length */ 1834#define IXGBE_PBANUM_LENGTH 11 1835 1836/* Checksum and EEPROM pointers */ 1837#define IXGBE_PBANUM_PTR_GUARD 0xFAFA 1838#define IXGBE_EEPROM_CHECKSUM 0x3F 1839#define IXGBE_EEPROM_SUM 0xBABA 1840#define IXGBE_PCIE_ANALOG_PTR 0x03 1841#define IXGBE_ATLAS0_CONFIG_PTR 0x04 1842#define IXGBE_PHY_PTR 0x04 1843#define IXGBE_ATLAS1_CONFIG_PTR 0x05 1844#define IXGBE_OPTION_ROM_PTR 0x05 1845#define IXGBE_PCIE_GENERAL_PTR 0x06 1846#define IXGBE_PCIE_CONFIG0_PTR 0x07 1847#define IXGBE_PCIE_CONFIG1_PTR 0x08 1848#define IXGBE_CORE0_PTR 0x09 1849#define IXGBE_CORE1_PTR 0x0A 1850#define IXGBE_MAC0_PTR 0x0B 1851#define IXGBE_MAC1_PTR 0x0C 1852#define IXGBE_CSR0_CONFIG_PTR 0x0D 1853#define IXGBE_CSR1_CONFIG_PTR 0x0E 1854#define IXGBE_FW_PTR 0x0F 1855#define IXGBE_PBANUM0_PTR 0x15 1856#define IXGBE_PBANUM1_PTR 0x16 1857#define IXGBE_ALT_MAC_ADDR_PTR 0x37 1858#define IXGBE_FREE_SPACE_PTR 0X3E 1859 1860#define IXGBE_SAN_MAC_ADDR_PTR 0x28 1861#define IXGBE_DEVICE_CAPS 0x2C 1862#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 1863#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 1864#define IXGBE_MAX_MSIX_VECTORS_82599 0x40 1865#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1866#define IXGBE_MAX_MSIX_VECTORS_82598 0x13 1867 1868/* MSI-X capability fields masks */ 1869#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 1870 1871/* Legacy EEPROM word offsets */ 1872#define IXGBE_ISCSI_BOOT_CAPS 0x0033 1873#define IXGBE_ISCSI_SETUP_PORT_0 0x0030 1874#define IXGBE_ISCSI_SETUP_PORT_1 0x0034 1875 1876/* EEPROM Commands - SPI */ 1877#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 1878#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 1879#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 1880#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 1881#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 1882#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 1883/* EEPROM reset Write Enable latch */ 1884#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 1885#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 1886#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 1887#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 1888#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 1889#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1890 1891/* EEPROM Read Register */ 1892#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 1893#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 1894#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 1895#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1896#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */ 1897#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */ 1898 1899#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 1900 1901#define IXGBE_EEPROM_PAGE_SIZE_MAX 128 1902#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */ 1903#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */ 1904#define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ 1905#define IXGBE_EEPROM_CCD_BIT 2 1906 1907#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 1908#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */ 1909#endif 1910 1911/* Number of 5 microseconds we wait for EERD read and 1912 * EERW write to complete */ 1913#define IXGBE_EERD_EEWR_ATTEMPTS 100000 1914 1915/* # attempts we wait for flush update to complete */ 1916#define IXGBE_FLUDONE_ATTEMPTS 20000 1917 1918#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 1919#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 1920#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 1921#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 1922 1923#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1924#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 1925#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 1926#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 1927#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 1928#define IXGBE_FW_LESM_STATE_1 0x1 1929#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 1930#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1931#define IXGBE_FW_PATCH_VERSION_4 0x7 1932#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 1933#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 1934#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 1935#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 1936#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 1937#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 1938#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */ 1939#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */ 1940#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */ 1941#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */ 1942#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */ 1943#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */ 1944#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */ 1945 1946/* FW header offset */ 1947#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1948#define IXGBE_X540_FW_MODULE_MASK 0x7FFF 1949/* 4KB multiplier */ 1950#define IXGBE_X540_FW_MODULE_LENGTH 0x1000 1951/* version word 2 (month & day) */ 1952#define IXGBE_X540_FW_PATCH_VERSION_2 0x5 1953/* version word 3 (silicon compatibility & year) */ 1954#define IXGBE_X540_FW_PATCH_VERSION_3 0x6 1955/* version word 4 (major & minor numbers) */ 1956#define IXGBE_X540_FW_PATCH_VERSION_4 0x7 1957 1958#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 1959#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 1960#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 1961 1962/* PCI Bus Info */ 1963#define IXGBE_PCI_DEVICE_STATUS 0xAA 1964#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 1965#define IXGBE_PCI_LINK_STATUS 0xB2 1966#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 1967#define IXGBE_PCI_LINK_WIDTH 0x3F0 1968#define IXGBE_PCI_LINK_WIDTH_1 0x10 1969#define IXGBE_PCI_LINK_WIDTH_2 0x20 1970#define IXGBE_PCI_LINK_WIDTH_4 0x40 1971#define IXGBE_PCI_LINK_WIDTH_8 0x80 1972#define IXGBE_PCI_LINK_SPEED 0xF 1973#define IXGBE_PCI_LINK_SPEED_2500 0x1 1974#define IXGBE_PCI_LINK_SPEED_5000 0x2 1975#define IXGBE_PCI_LINK_SPEED_8000 0x3 1976#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 1977#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 1978#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 1979 1980#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf 1981#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 1982#define IXGBE_PCIDEVCTRL2_50_100us 0x1 1983#define IXGBE_PCIDEVCTRL2_1_2ms 0x2 1984#define IXGBE_PCIDEVCTRL2_16_32ms 0x5 1985#define IXGBE_PCIDEVCTRL2_65_130ms 0x6 1986#define IXGBE_PCIDEVCTRL2_260_520ms 0x9 1987#define IXGBE_PCIDEVCTRL2_1_2s 0xa 1988#define IXGBE_PCIDEVCTRL2_4_8s 0xd 1989#define IXGBE_PCIDEVCTRL2_17_34s 0xe 1990 1991/* Number of 100 microseconds we wait for PCI Express master disable */ 1992#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1993 1994/* Check whether address is multicast. This is little-endian specific check.*/ 1995#define IXGBE_IS_MULTICAST(Address) \ 1996 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 1997 1998/* Check whether an address is broadcast. */ 1999#define IXGBE_IS_BROADCAST(Address) \ 2000 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 2001 (((u8 *)(Address))[1] == ((u8)0xff))) 2002 2003/* RAH */ 2004#define IXGBE_RAH_VIND_MASK 0x003C0000 2005#define IXGBE_RAH_VIND_SHIFT 18 2006#define IXGBE_RAH_AV 0x80000000 2007#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 2008 2009/* Header split receive */ 2010#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 2011#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 2012#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 2013#define IXGBE_RFCTL_RSC_DIS 0x00000010 2014#define IXGBE_RFCTL_NFSW_DIS 0x00000040 2015#define IXGBE_RFCTL_NFSR_DIS 0x00000080 2016#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 2017#define IXGBE_RFCTL_NFS_VER_SHIFT 8 2018#define IXGBE_RFCTL_NFS_VER_2 0 2019#define IXGBE_RFCTL_NFS_VER_3 1 2020#define IXGBE_RFCTL_NFS_VER_4 2 2021#define IXGBE_RFCTL_IPV6_DIS 0x00000400 2022#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 2023#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 2024#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 2025#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 2026 2027/* Transmit Config masks */ 2028#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 2029#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 2030#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 2031/* Enable short packet padding to 64 bytes */ 2032#define IXGBE_TX_PAD_ENABLE 0x00000400 2033#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 2034/* This allows for 16K packets + 4k for vlan */ 2035#define IXGBE_MAX_FRAME_SZ 0x40040000 2036 2037#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 2038#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 2039 2040/* Receive Config masks */ 2041#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 2042#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */ 2043#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */ 2044#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */ 2045#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */ 2046#define IXGBE_RXDCTL_RLPML_EN 0x00008000 2047#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 2048 2049#define IXGBE_TSAUXC_EN_CLK 0x00000004 2050#define IXGBE_TSAUXC_SYNCLK 0x00000008 2051#define IXGBE_TSAUXC_SDP0_INT 0x00000040 2052 2053#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 2054#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 2055 2056#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 2057#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 2058#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 2059#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 2060#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 2061#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 2062#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 2063 2064#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 2065#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 2066#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 2067#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 2068#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 2069#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 2070 2071#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 2072#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 2073#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 2074#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 2075#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 2076#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 2077#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 2078#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 2079#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 2080#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00 2081#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 2082 2083#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 2084#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 2085#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 2086#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 2087#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 2088#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 2089/* Receive Priority Flow Control Enable */ 2090#define IXGBE_FCTRL_RPFCE 0x00004000 2091#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 2092#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 2093#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 2094#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 2095#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 2096#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */ 2097#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */ 2098 2099/* Multiple Receive Queue Control */ 2100#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 2101#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 2102#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 2103#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 2104#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 2105#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 2106#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 2107#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 2108#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 2109#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 2110#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2111#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 2112#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2113#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 2114#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 2115#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2116#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 2117#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2118#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2119#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2120#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 2121#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 2122 2123/* Queue Drop Enable */ 2124#define IXGBE_QDE_ENABLE 0x00000001 2125#define IXGBE_QDE_IDX_MASK 0x00007F00 2126#define IXGBE_QDE_IDX_SHIFT 8 2127#define IXGBE_QDE_WRITE 0x00010000 2128#define IXGBE_QDE_READ 0x00020000 2129 2130#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 2131#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 2132#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 2133#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2134#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 2135#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 2136#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 2137#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 2138#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 2139 2140#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 2141#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 2142#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 2143#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 2144#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 2145/* Multiple Transmit Queue Command Register */ 2146#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 2147#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 2148#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 2149#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 2150#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 2151#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */ 2152#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 2153 2154/* Receive Descriptor bit definitions */ 2155#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 2156#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 2157#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 2158#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 2159#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 2160#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 2161#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 2162#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 2163#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 2164#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 2165#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 2166#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 2167#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 2168#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 2169#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2170#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 2171#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 2172#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 2173#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 2174#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 2175#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 2176#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 2177#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 2178#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 2179#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 2180#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 2181#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 2182#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 2183#define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */ 2184#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ 2185#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 2186#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 2187#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 2188#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 2189#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 2190#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 2191#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 2192#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 2193#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 2194#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 2195#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 2196#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 2197#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 2198#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 2199#define IXGBE_RXD_PRI_SHIFT 13 2200#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 2201#define IXGBE_RXD_CFI_SHIFT 12 2202 2203#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 2204#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 2205#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 2206#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 2207#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 2208#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 2209#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 2210#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 2211#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 2212#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 2213#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 2214#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */ 2215 2216/* PSRTYPE bit definitions */ 2217#define IXGBE_PSRTYPE_TCPHDR 0x00000010 2218#define IXGBE_PSRTYPE_UDPHDR 0x00000020 2219#define IXGBE_PSRTYPE_IPV4HDR 0x00000100 2220#define IXGBE_PSRTYPE_IPV6HDR 0x00000200 2221#define IXGBE_PSRTYPE_L2HDR 0x00001000 2222 2223/* SRRCTL bit definitions */ 2224#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2225#define IXGBE_SRRCTL_RDMTS_SHIFT 22 2226#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 2227#define IXGBE_SRRCTL_DROP_EN 0x10000000 2228#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 2229#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 2230#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 2231#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2232#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2233#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2234#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2235#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 2236 2237#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 2238#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 2239 2240#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 2241#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 2242#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2243#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2244#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2245#define IXGBE_RXDADV_RSCCNT_SHIFT 17 2246#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2247#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2248#define IXGBE_RXDADV_SPH 0x8000 2249 2250/* RSS Hash results */ 2251#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2252#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2253#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2254#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2255#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2256#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2257#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2258#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2259#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2260#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2261 2262/* RSS Packet Types as indicated in the receive descriptor. */ 2263#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2264#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2265#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2266#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2267#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2268#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2269#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2270#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2271#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2272#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2273#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2274#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2275#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2276#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2277#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2278 2279/* Security Processing bit Indication */ 2280#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 2281#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 2282#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 2283#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 2284#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 2285 2286/* Masks to determine if packets should be dropped due to frame errors */ 2287#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2288 IXGBE_RXD_ERR_CE | \ 2289 IXGBE_RXD_ERR_LE | \ 2290 IXGBE_RXD_ERR_PE | \ 2291 IXGBE_RXD_ERR_OSE | \ 2292 IXGBE_RXD_ERR_USE) 2293 2294#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2295 IXGBE_RXDADV_ERR_CE | \ 2296 IXGBE_RXDADV_ERR_LE | \ 2297 IXGBE_RXDADV_ERR_PE | \ 2298 IXGBE_RXDADV_ERR_OSE | \ 2299 IXGBE_RXDADV_ERR_USE) 2300 2301#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE 2302 2303/* Multicast bit mask */ 2304#define IXGBE_MCSTCTRL_MFE 0x4 2305 2306/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2307#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2308#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2309#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2310 2311/* Vlan-specific macros */ 2312#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2313#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2314#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2315#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2316 2317/* SR-IOV specific macros */ 2318#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 2319#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 2320#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) 2321#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2322 2323/* Little Endian defines */ 2324#ifndef __le16 2325#define __le16 u16 2326#endif 2327#ifndef __le32 2328#define __le32 u32 2329#endif 2330#ifndef __le64 2331#define __le64 u64 2332 2333#endif 2334#ifndef __be16 2335/* Big Endian defines */ 2336#define __be16 u16 2337#define __be32 u32 2338#define __be64 u64 2339 2340#endif 2341enum ixgbe_fdir_pballoc_type { 2342 IXGBE_FDIR_PBALLOC_NONE = 0, 2343 IXGBE_FDIR_PBALLOC_64K = 1, 2344 IXGBE_FDIR_PBALLOC_128K = 2, 2345 IXGBE_FDIR_PBALLOC_256K = 3, 2346}; 2347 2348/* Flow Director register values */ 2349#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 2350#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 2351#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 2352#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 2353#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 2354#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 2355#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 2356#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2357#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2358#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2359#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 2360#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 2361#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 2362 2363#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 2364#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 2365#define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2366#define IXGBE_FDIRM_VLANID 0x00000001 2367#define IXGBE_FDIRM_VLANP 0x00000002 2368#define IXGBE_FDIRM_POOL 0x00000004 2369#define IXGBE_FDIRM_L4P 0x00000008 2370#define IXGBE_FDIRM_FLEX 0x00000010 2371#define IXGBE_FDIRM_DIPv6 0x00000020 2372 2373#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2374#define IXGBE_FDIRFREE_FREE_SHIFT 0 2375#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2376#define IXGBE_FDIRFREE_COLL_SHIFT 16 2377#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2378#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2379#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2380#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2381#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2382#define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2383#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2384#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2385#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2386#define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2387#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2388#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2389#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2390#define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2391#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2392#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2393 2394#define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2395#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2396#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2397#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2398#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 2399#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2400#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2401#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2402#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2403#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2404#define IXGBE_FDIRCMD_IPV6 0x00000080 2405#define IXGBE_FDIRCMD_CLEARHT 0x00000100 2406#define IXGBE_FDIRCMD_DROP 0x00000200 2407#define IXGBE_FDIRCMD_INT 0x00000400 2408#define IXGBE_FDIRCMD_LAST 0x00000800 2409#define IXGBE_FDIRCMD_COLLISION 0x00001000 2410#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2411#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 2412#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 2413#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2414#define IXGBE_FDIR_INIT_DONE_POLL 10 2415#define IXGBE_FDIRCMD_CMD_POLL 10 2416 2417#define IXGBE_FDIR_DROP_QUEUE 127 2418 2419#define IXGBE_STATUS_OVERHEATING_BIT 20 /* STATUS overtemp bit num */ 2420/* iTS sensor related defines*/ 2421#define IXGBE_TEMP_STATUS_ADDR_X540 0xC830 2422#define IXGBE_TEMP_VALUE_ADDR_X540 0xC820 2423#define IXGBE_TEMP_PROV_2_ADDR_X540 0xC421 2424#define IXGBE_TEMP_PROV_4_ADDR_X540 0xC423 2425#define IXGBE_TEMP_STATUS_PAGE_X540 0x1E 2426#define IXGBE_TEMP_HIGH_FAILURE_BIT_X540 0xE 2427#define IXGBE_TEMP_HIGH_WARNING_BIT_X540 0xC 2428 2429/* Manageablility Host Interface defines */ 2430#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2431#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2432#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 2433 2434/* CEM Support */ 2435#define FW_CEM_HDR_LEN 0x4 2436#define FW_CEM_CMD_DRIVER_INFO 0xDD 2437#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2438#define FW_CEM_CMD_RESERVED 0X0 2439#define FW_CEM_UNUSED_VER 0x0 2440#define FW_CEM_MAX_RETRIES 3 2441#define FW_CEM_RESP_STATUS_SUCCESS 0x1 2442 2443/* Host Interface Command Structures */ 2444 2445struct ixgbe_hic_hdr { 2446 u8 cmd; 2447 u8 buf_len; 2448 union { 2449 u8 cmd_resv; 2450 u8 ret_status; 2451 } cmd_or_resp; 2452 u8 checksum; 2453}; 2454 2455struct ixgbe_hic_drv_info { 2456 struct ixgbe_hic_hdr hdr; 2457 u8 port_num; 2458 u8 ver_sub; 2459 u8 ver_build; 2460 u8 ver_min; 2461 u8 ver_maj; 2462 u8 pad; /* end spacing to ensure length is mult. of dword */ 2463 u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 2464}; 2465 2466/* Transmit Descriptor - Legacy */ 2467struct ixgbe_legacy_tx_desc { 2468 u64 buffer_addr; /* Address of the descriptor's data buffer */ 2469 union { 2470 __le32 data; 2471 struct { 2472 __le16 length; /* Data buffer length */ 2473 u8 cso; /* Checksum offset */ 2474 u8 cmd; /* Descriptor control */ 2475 } flags; 2476 } lower; 2477 union { 2478 __le32 data; 2479 struct { 2480 u8 status; /* Descriptor status */ 2481 u8 css; /* Checksum start */ 2482 __le16 vlan; 2483 } fields; 2484 } upper; 2485}; 2486 2487/* Transmit Descriptor - Advanced */ 2488union ixgbe_adv_tx_desc { 2489 struct { 2490 __le64 buffer_addr; /* Address of descriptor's data buf */ 2491 __le32 cmd_type_len; 2492 __le32 olinfo_status; 2493 } read; 2494 struct { 2495 __le64 rsvd; /* Reserved */ 2496 __le32 nxtseq_seed; 2497 __le32 status; 2498 } wb; 2499}; 2500 2501/* Receive Descriptor - Legacy */ 2502struct ixgbe_legacy_rx_desc { 2503 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 2504 __le16 length; /* Length of data DMAed into data buffer */ 2505 __le16 csum; /* Packet checksum */ 2506 u8 status; /* Descriptor status */ 2507 u8 errors; /* Descriptor Errors */ 2508 __le16 vlan; 2509}; 2510 2511/* Receive Descriptor - Advanced */ 2512union ixgbe_adv_rx_desc { 2513 struct { 2514 __le64 pkt_addr; /* Packet buffer address */ 2515 __le64 hdr_addr; /* Header buffer address */ 2516 } read; 2517 struct { 2518 struct { 2519 union { 2520 __le32 data; 2521 struct { 2522 __le16 pkt_info; /* RSS, Pkt type */ 2523 __le16 hdr_info; /* Splithdr, hdrlen */ 2524 } hs_rss; 2525 } lo_dword; 2526 union { 2527 __le32 rss; /* RSS Hash */ 2528 struct { 2529 __le16 ip_id; /* IP id */ 2530 __le16 csum; /* Packet Checksum */ 2531 } csum_ip; 2532 } hi_dword; 2533 } lower; 2534 struct { 2535 __le32 status_error; /* ext status/error */ 2536 __le16 length; /* Packet length */ 2537 __le16 vlan; /* VLAN tag */ 2538 } upper; 2539 } wb; /* writeback */ 2540}; 2541 2542/* Context descriptors */ 2543struct ixgbe_adv_tx_context_desc { 2544 __le32 vlan_macip_lens; 2545 __le32 seqnum_seed; 2546 __le32 type_tucmd_mlhl; 2547 __le32 mss_l4len_idx; 2548}; 2549 2550/* Adv Transmit Descriptor Config Masks */ 2551#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 2552#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 2553#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */ 2554#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 2555#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 2556#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 2557#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */ 2558#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */ 2559#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 2560#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 2561#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 2562#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 2563#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */ 2564#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 2565#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2566#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 2567#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 2568#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 2569#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 2570#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 2571#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 2572#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 2573 IXGBE_ADVTXD_POPTS_SHIFT) 2574#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 2575 IXGBE_ADVTXD_POPTS_SHIFT) 2576#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 2577#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 2578#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 2579/* 1st&Last TSO-full iSCSI PDU */ 2580#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 2581#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 2582#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2583#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2584#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2585#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2586#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2587#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2588#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2589#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 2590#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ 2591#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 2592#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2593#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2594#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2595#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 2596#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 2597#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 2598#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ 2599#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ 2600#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 2601#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 2602#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 2603#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 2604#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2605#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2606 2607/* Autonegotiation advertised speeds */ 2608typedef u32 ixgbe_autoneg_advertised; 2609/* Link speed */ 2610typedef u32 ixgbe_link_speed; 2611#define IXGBE_LINK_SPEED_UNKNOWN 0 2612#define IXGBE_LINK_SPEED_100_FULL 0x0008 2613#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 2614#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 2615#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 2616 IXGBE_LINK_SPEED_10GB_FULL) 2617#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 2618 IXGBE_LINK_SPEED_1GB_FULL | \ 2619 IXGBE_LINK_SPEED_10GB_FULL) 2620 2621/* Physical layer type */ 2622typedef u32 ixgbe_physical_layer; 2623#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 2624#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 2625#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 2626#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 2627#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 2628#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 2629#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 2630#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 2631#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 2632#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 2633#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 2634#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 2635#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 2636#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 2637#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000 2638#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000 2639 2640/* Flow Control Data Sheet defined values 2641 * Calculation and defines taken from 802.1bb Annex O 2642 */ 2643 2644/* BitTimes (BT) conversion */ 2645#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 2646#define IXGBE_B2BT(BT) (BT * 8) 2647 2648/* Calculate Delay to respond to PFC */ 2649#define IXGBE_PFC_D 672 2650 2651/* Calculate Cable Delay */ 2652#define IXGBE_CABLE_DC 5556 /* Delay Copper */ 2653#define IXGBE_CABLE_DO 5000 /* Delay Optical */ 2654 2655/* Calculate Interface Delay X540 */ 2656#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 2657#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 2658#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 2659 2660#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 2661 2662/* Calculate Interface Delay 82598, 82599 */ 2663#define IXGBE_PHY_D 12800 2664#define IXGBE_MAC_D 4096 2665#define IXGBE_XAUI_D (2 * 1024) 2666 2667#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 2668 2669/* Calculate Delay incurred from higher layer */ 2670#define IXGBE_HD 6144 2671 2672/* Calculate PCI Bus delay for low thresholds */ 2673#define IXGBE_PCI_DELAY 10000 2674 2675/* Calculate X540 delay value in bit times */ 2676#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 2677 ((36 * \ 2678 (IXGBE_B2BT(_max_frame_link) + \ 2679 IXGBE_PFC_D + \ 2680 (2 * IXGBE_CABLE_DC) + \ 2681 (2 * IXGBE_ID_X540) + \ 2682 IXGBE_HD) / 25 + 1) + \ 2683 2 * IXGBE_B2BT(_max_frame_tc)) 2684 2685/* Calculate 82599, 82598 delay value in bit times */ 2686#define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 2687 ((36 * \ 2688 (IXGBE_B2BT(_max_frame_link) + \ 2689 IXGBE_PFC_D + \ 2690 (2 * IXGBE_CABLE_DC) + \ 2691 (2 * IXGBE_ID) + \ 2692 IXGBE_HD) / 25 + 1) + \ 2693 2 * IXGBE_B2BT(_max_frame_tc)) 2694 2695/* Calculate low threshold delay values */ 2696#define IXGBE_LOW_DV_X540(_max_frame_tc) \ 2697 (2 * IXGBE_B2BT(_max_frame_tc) + \ 2698 (36 * IXGBE_PCI_DELAY / 25) + 1) 2699#define IXGBE_LOW_DV(_max_frame_tc) \ 2700 (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 2701 2702/* Software ATR hash keys */ 2703#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 2704#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 2705 2706/* Software ATR input stream values and masks */ 2707#define IXGBE_ATR_HASH_MASK 0x7fff 2708#define IXGBE_ATR_L4TYPE_MASK 0x3 2709#define IXGBE_ATR_L4TYPE_UDP 0x1 2710#define IXGBE_ATR_L4TYPE_TCP 0x2 2711#define IXGBE_ATR_L4TYPE_SCTP 0x3 2712#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 2713enum ixgbe_atr_flow_type { 2714 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 2715 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 2716 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 2717 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 2718 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 2719 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 2720 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 2721 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 2722}; 2723 2724/* Flow Director ATR input struct. */ 2725union ixgbe_atr_input { 2726 /* 2727 * Byte layout in order, all values with MSB first: 2728 * 2729 * vm_pool - 1 byte 2730 * flow_type - 1 byte 2731 * vlan_id - 2 bytes 2732 * src_ip - 16 bytes 2733 * dst_ip - 16 bytes 2734 * src_port - 2 bytes 2735 * dst_port - 2 bytes 2736 * flex_bytes - 2 bytes 2737 * bkt_hash - 2 bytes 2738 */ 2739 struct { 2740 u8 vm_pool; 2741 u8 flow_type; 2742 __be16 vlan_id; 2743 __be32 dst_ip[4]; 2744 __be32 src_ip[4]; 2745 __be16 src_port; 2746 __be16 dst_port; 2747 __be16 flex_bytes; 2748 __be16 bkt_hash; 2749 } formatted; 2750 __be32 dword_stream[11]; 2751}; 2752 2753/* Flow Director compressed ATR hash input struct */ 2754union ixgbe_atr_hash_dword { 2755 struct { 2756 u8 vm_pool; 2757 u8 flow_type; 2758 __be16 vlan_id; 2759 } formatted; 2760 __be32 ip; 2761 struct { 2762 __be16 src; 2763 __be16 dst; 2764 } port; 2765 __be16 flex_bytes; 2766 __be32 dword; 2767}; 2768 2769 2770/* 2771 * Unavailable: The FCoE Boot Option ROM is not present in the flash. 2772 * Disabled: Present; boot order is not set for any targets on the port. 2773 * Enabled: Present; boot order is set for at least one target on the port. 2774 */ 2775enum ixgbe_fcoe_boot_status { 2776 ixgbe_fcoe_bootstatus_disabled = 0, 2777 ixgbe_fcoe_bootstatus_enabled = 1, 2778 ixgbe_fcoe_bootstatus_unavailable = 0xFFFF 2779}; 2780 2781enum ixgbe_eeprom_type { 2782 ixgbe_eeprom_uninitialized = 0, 2783 ixgbe_eeprom_spi, 2784 ixgbe_flash, 2785 ixgbe_eeprom_none /* No NVM support */ 2786}; 2787 2788enum ixgbe_mac_type { 2789 ixgbe_mac_unknown = 0, 2790 ixgbe_mac_82598EB, 2791 ixgbe_mac_82599EB, 2792 ixgbe_mac_82599_vf, 2793 ixgbe_mac_X540, 2794 ixgbe_mac_X540_vf, 2795 ixgbe_num_macs 2796}; 2797 2798enum ixgbe_phy_type { 2799 ixgbe_phy_unknown = 0, 2800 ixgbe_phy_none, 2801 ixgbe_phy_tn, 2802 ixgbe_phy_aq, 2803 ixgbe_phy_cu_unknown, 2804 ixgbe_phy_qt, 2805 ixgbe_phy_xaui, 2806 ixgbe_phy_nl, 2807 ixgbe_phy_sfp_passive_tyco, 2808 ixgbe_phy_sfp_passive_unknown, 2809 ixgbe_phy_sfp_active_unknown, 2810 ixgbe_phy_sfp_avago, 2811 ixgbe_phy_sfp_ftl, 2812 ixgbe_phy_sfp_ftl_active, 2813 ixgbe_phy_sfp_unknown, 2814 ixgbe_phy_sfp_intel, 2815 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ 2816 ixgbe_phy_generic 2817}; 2818 2819/* 2820 * SFP+ module type IDs: 2821 * 2822 * ID Module Type 2823 * ============= 2824 * 0 SFP_DA_CU 2825 * 1 SFP_SR 2826 * 2 SFP_LR 2827 * 3 SFP_DA_CU_CORE0 - 82599-specific 2828 * 4 SFP_DA_CU_CORE1 - 82599-specific 2829 * 5 SFP_SR/LR_CORE0 - 82599-specific 2830 * 6 SFP_SR/LR_CORE1 - 82599-specific 2831 */ 2832enum ixgbe_sfp_type { 2833 ixgbe_sfp_type_da_cu = 0, 2834 ixgbe_sfp_type_sr = 1, 2835 ixgbe_sfp_type_lr = 2, 2836 ixgbe_sfp_type_da_cu_core0 = 3, 2837 ixgbe_sfp_type_da_cu_core1 = 4, 2838 ixgbe_sfp_type_srlr_core0 = 5, 2839 ixgbe_sfp_type_srlr_core1 = 6, 2840 ixgbe_sfp_type_da_act_lmt_core0 = 7, 2841 ixgbe_sfp_type_da_act_lmt_core1 = 8, 2842 ixgbe_sfp_type_1g_cu_core0 = 9, 2843 ixgbe_sfp_type_1g_cu_core1 = 10, 2844 ixgbe_sfp_type_1g_sx_core0 = 11, 2845 ixgbe_sfp_type_1g_sx_core1 = 12, 2846 ixgbe_sfp_type_not_present = 0xFFFE, 2847 ixgbe_sfp_type_unknown = 0xFFFF 2848}; 2849 2850enum ixgbe_media_type { 2851 ixgbe_media_type_unknown = 0, 2852 ixgbe_media_type_fiber, 2853 ixgbe_media_type_fiber_fixed, 2854 ixgbe_media_type_copper, 2855 ixgbe_media_type_backplane, 2856 ixgbe_media_type_cx4, 2857 ixgbe_media_type_virtual 2858}; 2859 2860/* Flow Control Settings */ 2861enum ixgbe_fc_mode { 2862 ixgbe_fc_none = 0, 2863 ixgbe_fc_rx_pause, 2864 ixgbe_fc_tx_pause, 2865 ixgbe_fc_full, 2866 ixgbe_fc_default 2867}; 2868 2869/* Smart Speed Settings */ 2870#define IXGBE_SMARTSPEED_MAX_RETRIES 3 2871enum ixgbe_smart_speed { 2872 ixgbe_smart_speed_auto = 0, 2873 ixgbe_smart_speed_on, 2874 ixgbe_smart_speed_off 2875}; 2876 2877/* PCI bus types */ 2878enum ixgbe_bus_type { 2879 ixgbe_bus_type_unknown = 0, 2880 ixgbe_bus_type_pci, 2881 ixgbe_bus_type_pcix, 2882 ixgbe_bus_type_pci_express, 2883 ixgbe_bus_type_reserved 2884}; 2885 2886/* PCI bus speeds */ 2887enum ixgbe_bus_speed { 2888 ixgbe_bus_speed_unknown = 0, 2889 ixgbe_bus_speed_33 = 33, 2890 ixgbe_bus_speed_66 = 66, 2891 ixgbe_bus_speed_100 = 100, 2892 ixgbe_bus_speed_120 = 120, 2893 ixgbe_bus_speed_133 = 133, 2894 ixgbe_bus_speed_2500 = 2500, 2895 ixgbe_bus_speed_5000 = 5000, 2896 ixgbe_bus_speed_8000 = 8000, 2897 ixgbe_bus_speed_reserved 2898}; 2899 2900/* PCI bus widths */ 2901enum ixgbe_bus_width { 2902 ixgbe_bus_width_unknown = 0, 2903 ixgbe_bus_width_pcie_x1 = 1, 2904 ixgbe_bus_width_pcie_x2 = 2, 2905 ixgbe_bus_width_pcie_x4 = 4, 2906 ixgbe_bus_width_pcie_x8 = 8, 2907 ixgbe_bus_width_32 = 32, 2908 ixgbe_bus_width_64 = 64, 2909 ixgbe_bus_width_reserved 2910}; 2911 2912struct ixgbe_addr_filter_info { 2913 u32 num_mc_addrs; 2914 u32 rar_used_count; 2915 u32 mta_in_use; 2916 u32 overflow_promisc; 2917 bool user_set_promisc; 2918}; 2919 2920/* Bus parameters */ 2921struct ixgbe_bus_info { 2922 enum ixgbe_bus_speed speed; 2923 enum ixgbe_bus_width width; 2924 enum ixgbe_bus_type type; 2925 2926 u16 func; 2927 u16 lan_id; 2928}; 2929 2930/* Flow control parameters */ 2931struct ixgbe_fc_info { 2932 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */ 2933 u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */ 2934 u16 pause_time; /* Flow Control Pause timer */ 2935 bool send_xon; /* Flow control send XON */ 2936 bool strict_ieee; /* Strict IEEE mode */ 2937 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 2938 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 2939 enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 2940 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 2941}; 2942 2943/* Statistics counters collected by the MAC */ 2944struct ixgbe_hw_stats { 2945 u64 crcerrs; 2946 u64 illerrc; 2947 u64 errbc; 2948 u64 mspdc; 2949 u64 mpctotal; 2950 u64 mpc[8]; 2951 u64 mlfc; 2952 u64 mrfc; 2953 u64 rlec; 2954 u64 lxontxc; 2955 u64 lxonrxc; 2956 u64 lxofftxc; 2957 u64 lxoffrxc; 2958 u64 pxontxc[8]; 2959 u64 pxonrxc[8]; 2960 u64 pxofftxc[8]; 2961 u64 pxoffrxc[8]; 2962 u64 prc64; 2963 u64 prc127; 2964 u64 prc255; 2965 u64 prc511; 2966 u64 prc1023; 2967 u64 prc1522; 2968 u64 gprc; 2969 u64 bprc; 2970 u64 mprc; 2971 u64 gptc; 2972 u64 gorc; 2973 u64 gotc; 2974 u64 rnbc[8]; 2975 u64 ruc; 2976 u64 rfc; 2977 u64 roc; 2978 u64 rjc; 2979 u64 mngprc; 2980 u64 mngpdc; 2981 u64 mngptc; 2982 u64 tor; 2983 u64 tpr; 2984 u64 tpt; 2985 u64 ptc64; 2986 u64 ptc127; 2987 u64 ptc255; 2988 u64 ptc511; 2989 u64 ptc1023; 2990 u64 ptc1522; 2991 u64 mptc; 2992 u64 bptc; 2993 u64 xec; 2994 u64 qprc[16]; 2995 u64 qptc[16]; 2996 u64 qbrc[16]; 2997 u64 qbtc[16]; 2998 u64 qprdc[16]; 2999 u64 pxon2offc[8]; 3000 u64 fdirustat_add; 3001 u64 fdirustat_remove; 3002 u64 fdirfstat_fadd; 3003 u64 fdirfstat_fremove; 3004 u64 fdirmatch; 3005 u64 fdirmiss; 3006 u64 fccrc; 3007 u64 fclast; 3008 u64 fcoerpdc; 3009 u64 fcoeprc; 3010 u64 fcoeptc; 3011 u64 fcoedwrc; 3012 u64 fcoedwtc; 3013 u64 fcoe_noddp; 3014 u64 fcoe_noddp_ext_buff; 3015 u64 ldpcec; 3016 u64 pcrc8ec; 3017 u64 b2ospc; 3018 u64 b2ogprc; 3019 u64 o2bgptc; 3020 u64 o2bspc; 3021}; 3022 3023/* forward declaration */ 3024struct ixgbe_hw; 3025 3026/* iterator type for walking multicast address lists */ 3027typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 3028 u32 *vmdq); 3029 3030/* Function pointer table */ 3031struct ixgbe_eeprom_operations { 3032 s32 (*init_params)(struct ixgbe_hw *); 3033 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 3034 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3035 s32 (*write)(struct ixgbe_hw *, u16, u16); 3036 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3037 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 3038 s32 (*update_checksum)(struct ixgbe_hw *); 3039 u16 (*calc_checksum)(struct ixgbe_hw *); 3040}; 3041 3042struct ixgbe_mac_operations { 3043 s32 (*init_hw)(struct ixgbe_hw *); 3044 s32 (*reset_hw)(struct ixgbe_hw *); 3045 s32 (*start_hw)(struct ixgbe_hw *); 3046 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 3047 void (*enable_relaxed_ordering)(struct ixgbe_hw *); 3048 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 3049 u32 (*get_supported_physical_layer)(struct ixgbe_hw *); 3050 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 3051 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 3052 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); 3053 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 3054 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 3055 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *); 3056 s32 (*stop_adapter)(struct ixgbe_hw *); 3057 s32 (*get_bus_info)(struct ixgbe_hw *); 3058 void (*set_lan_id)(struct ixgbe_hw *); 3059 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 3060 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 3061 s32 (*setup_sfp)(struct ixgbe_hw *); 3062 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 3063 s32 (*disable_sec_rx_path)(struct ixgbe_hw *); 3064 s32 (*enable_sec_rx_path)(struct ixgbe_hw *); 3065 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16); 3066 void (*release_swfw_sync)(struct ixgbe_hw *, u16); 3067 3068 /* Link */ 3069 void (*disable_tx_laser)(struct ixgbe_hw *); 3070 void (*enable_tx_laser)(struct ixgbe_hw *); 3071 void (*flap_tx_laser)(struct ixgbe_hw *); 3072 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3073 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 3074 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 3075 bool *); 3076 3077 /* Packet Buffer manipulation */ 3078 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int); 3079 3080 /* LED */ 3081 s32 (*led_on)(struct ixgbe_hw *, u32); 3082 s32 (*led_off)(struct ixgbe_hw *, u32); 3083 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 3084 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 3085 3086 /* RAR, Multicast, VLAN */ 3087 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 3088 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); 3089 s32 (*clear_rar)(struct ixgbe_hw *, u32); 3090 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); 3091 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 3092 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 3093 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 3094 s32 (*init_rx_addrs)(struct ixgbe_hw *); 3095 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3096 ixgbe_mc_addr_itr); 3097 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3098 ixgbe_mc_addr_itr, bool clear); 3099 s32 (*enable_mc)(struct ixgbe_hw *); 3100 s32 (*disable_mc)(struct ixgbe_hw *); 3101 s32 (*clear_vfta)(struct ixgbe_hw *); 3102 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 3103 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *); 3104 s32 (*init_uta_tables)(struct ixgbe_hw *); 3105 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 3106 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 3107 3108 /* Flow Control */ 3109 s32 (*fc_enable)(struct ixgbe_hw *); 3110 3111 /* Manageability interface */ 3112 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); 3113 s32 (*dmac_config)(struct ixgbe_hw *hw); 3114 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); 3115 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); 3116 void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map); 3117}; 3118 3119struct ixgbe_phy_operations { 3120 s32 (*identify)(struct ixgbe_hw *); 3121 s32 (*identify_sfp)(struct ixgbe_hw *); 3122 s32 (*init)(struct ixgbe_hw *); 3123 s32 (*reset)(struct ixgbe_hw *); 3124 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 3125 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 3126 s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); 3127 s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); 3128 s32 (*setup_link)(struct ixgbe_hw *); 3129 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3130 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 3131 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 3132 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 3133 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 3134 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 3135 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 3136 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 3137 void (*i2c_bus_clear)(struct ixgbe_hw *); 3138 s32 (*check_overtemp)(struct ixgbe_hw *); 3139}; 3140 3141struct ixgbe_eeprom_info { 3142 struct ixgbe_eeprom_operations ops; 3143 enum ixgbe_eeprom_type type; 3144 u32 semaphore_delay; 3145 u16 word_size; 3146 u16 address_bits; 3147 u16 word_page_size; 3148}; 3149 3150#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 3151struct ixgbe_mac_info { 3152 struct ixgbe_mac_operations ops; 3153 enum ixgbe_mac_type type; 3154 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3155 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3156 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3157 /* prefix for World Wide Node Name (WWNN) */ 3158 u16 wwnn_prefix; 3159 /* prefix for World Wide Port Name (WWPN) */ 3160 u16 wwpn_prefix; 3161#define IXGBE_MAX_MTA 128 3162 u32 mta_shadow[IXGBE_MAX_MTA]; 3163 s32 mc_filter_type; 3164 u32 mcft_size; 3165 u32 vft_size; 3166 u32 num_rar_entries; 3167 u32 rar_highwater; 3168 u32 rx_pb_size; 3169 u32 max_tx_queues; 3170 u32 max_rx_queues; 3171 u32 orig_autoc; 3172 u32 cached_autoc; 3173 u8 san_mac_rar_index; 3174 bool get_link_status; 3175 u32 orig_autoc2; 3176 u16 max_msix_vectors; 3177 bool arc_subsystem_valid; 3178 bool orig_link_settings_stored; 3179 bool autotry_restart; 3180 u8 flags; 3181}; 3182 3183struct ixgbe_phy_info { 3184 struct ixgbe_phy_operations ops; 3185 enum ixgbe_phy_type type; 3186 u32 addr; 3187 u32 id; 3188 enum ixgbe_sfp_type sfp_type; 3189 bool sfp_setup_needed; 3190 u32 revision; 3191 enum ixgbe_media_type media_type; 3192 bool reset_disable; 3193 ixgbe_autoneg_advertised autoneg_advertised; 3194 enum ixgbe_smart_speed smart_speed; 3195 bool smart_speed_active; 3196 bool multispeed_fiber; 3197 bool reset_if_overtemp; 3198}; 3199 3200#include "ixgbe_mbx.h" 3201 3202struct ixgbe_mbx_operations { 3203 void (*init_params)(struct ixgbe_hw *hw); 3204 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 3205 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 3206 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3207 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3208 s32 (*check_for_msg)(struct ixgbe_hw *, u16); 3209 s32 (*check_for_ack)(struct ixgbe_hw *, u16); 3210 s32 (*check_for_rst)(struct ixgbe_hw *, u16); 3211}; 3212 3213struct ixgbe_mbx_stats { 3214 u32 msgs_tx; 3215 u32 msgs_rx; 3216 3217 u32 acks; 3218 u32 reqs; 3219 u32 rsts; 3220}; 3221 3222struct ixgbe_mbx_info { 3223 struct ixgbe_mbx_operations ops; 3224 struct ixgbe_mbx_stats stats; 3225 u32 timeout; 3226 u32 usec_delay; 3227 u32 v2p_mailbox; 3228 u16 size; 3229}; 3230 3231struct ixgbe_hw { 3232 u8 *hw_addr; 3233 void *back; 3234 struct ixgbe_mac_info mac; 3235 struct ixgbe_addr_filter_info addr_ctrl; 3236 struct ixgbe_fc_info fc; 3237 struct ixgbe_phy_info phy; 3238 struct ixgbe_eeprom_info eeprom; 3239 struct ixgbe_bus_info bus; 3240 struct ixgbe_mbx_info mbx; 3241 u16 device_id; 3242 u16 vendor_id; 3243 u16 subsystem_device_id; 3244 u16 subsystem_vendor_id; 3245 u8 revision_id; 3246 bool adapter_stopped; 3247 int api_version; 3248 bool force_full_reset; 3249 bool allow_unsupported_sfp; 3250 bool mng_fw_enabled; 3251 bool wol_enabled; 3252}; 3253 3254#define ixgbe_call_func(hw, func, params, error) \ 3255 (func != NULL) ? func params : error 3256 3257 3258/* Error Codes */ 3259#define IXGBE_SUCCESS 0 3260#define IXGBE_ERR_EEPROM -1 3261#define IXGBE_ERR_EEPROM_CHECKSUM -2 3262#define IXGBE_ERR_PHY -3 3263#define IXGBE_ERR_CONFIG -4 3264#define IXGBE_ERR_PARAM -5 3265#define IXGBE_ERR_MAC_TYPE -6 3266#define IXGBE_ERR_UNKNOWN_PHY -7 3267#define IXGBE_ERR_LINK_SETUP -8 3268#define IXGBE_ERR_ADAPTER_STOPPED -9 3269#define IXGBE_ERR_INVALID_MAC_ADDR -10 3270#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 3271#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 3272#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 3273#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 3274#define IXGBE_ERR_RESET_FAILED -15 3275#define IXGBE_ERR_SWFW_SYNC -16 3276#define IXGBE_ERR_PHY_ADDR_INVALID -17 3277#define IXGBE_ERR_I2C -18 3278#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 3279#define IXGBE_ERR_SFP_NOT_PRESENT -20 3280#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 3281#define IXGBE_ERR_NO_SAN_ADDR_PTR -22 3282#define IXGBE_ERR_FDIR_REINIT_FAILED -23 3283#define IXGBE_ERR_EEPROM_VERSION -24 3284#define IXGBE_ERR_NO_SPACE -25 3285#define IXGBE_ERR_OVERTEMP -26 3286#define IXGBE_ERR_FC_NOT_NEGOTIATED -27 3287#define IXGBE_ERR_FC_NOT_SUPPORTED -28 3288#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 3289#define IXGBE_ERR_PBA_SECTION -31 3290#define IXGBE_ERR_INVALID_ARGUMENT -32 3291#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 3292#define IXGBE_ERR_OUT_OF_MEM -34 3293#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36 3294#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37 3295 3296#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 3297 3298#endif /* _IXGBE_TYPE_H_ */ 3299