ixgbe_type.h revision 248287
1/****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/9/sys/dev/ixgbe/ixgbe_type.h 248287 2013-03-14 21:39:39Z jfv $*/ 34 35#ifndef _IXGBE_TYPE_H_ 36#define _IXGBE_TYPE_H_ 37 38#include "ixgbe_osdep.h" 39 40 41/* Device IDs */ 42#define IXGBE_DEV_ID_82598 0x10B6 43#define IXGBE_DEV_ID_82598_BX 0x1508 44#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 45#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 46#define IXGBE_DEV_ID_82598AT 0x10C8 47#define IXGBE_DEV_ID_82598AT2 0x150B 48#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 49#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 50#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 51#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 52#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 53#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 54#define IXGBE_DEV_ID_82599_KX4 0x10F7 55#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 56#define IXGBE_DEV_ID_82599_KR 0x1517 57#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 58#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 59#define IXGBE_DEV_ID_82599_CX4 0x10F9 60#define IXGBE_DEV_ID_82599_SFP 0x10FB 61#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 62#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 63#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 64#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 65#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A 66#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 67#define IXGBE_DEV_ID_82599_SFP_EM 0x1507 68#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 69#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 70#define IXGBE_DEV_ID_82599EN_SFP 0x1557 71#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 72#define IXGBE_DEV_ID_82599_T3_LOM 0x151C 73#define IXGBE_DEV_ID_82599_VF 0x10ED 74#define IXGBE_DEV_ID_82599_VF_HV 0x152E 75#define IXGBE_DEV_ID_82599_BYPASS 0x155D 76#define IXGBE_DEV_ID_X540T 0x1528 77#define IXGBE_DEV_ID_X540_VF 0x1515 78#define IXGBE_DEV_ID_X540_VF_HV 0x1530 79#define IXGBE_DEV_ID_X540_BYPASS 0x155C 80 81/* General Registers */ 82#define IXGBE_CTRL 0x00000 83#define IXGBE_STATUS 0x00008 84#define IXGBE_CTRL_EXT 0x00018 85#define IXGBE_ESDP 0x00020 86#define IXGBE_EODSDP 0x00028 87#define IXGBE_I2CCTL 0x00028 88#define IXGBE_PHY_GPIO 0x00028 89#define IXGBE_MAC_GPIO 0x00030 90#define IXGBE_PHYINT_STATUS0 0x00100 91#define IXGBE_PHYINT_STATUS1 0x00104 92#define IXGBE_PHYINT_STATUS2 0x00108 93#define IXGBE_LEDCTL 0x00200 94#define IXGBE_FRTIMER 0x00048 95#define IXGBE_TCPTIMER 0x0004C 96#define IXGBE_CORESPARE 0x00600 97#define IXGBE_EXVET 0x05078 98 99/* NVM Registers */ 100#define IXGBE_EEC 0x10010 101#define IXGBE_EERD 0x10014 102#define IXGBE_EEWR 0x10018 103#define IXGBE_FLA 0x1001C 104#define IXGBE_EEMNGCTL 0x10110 105#define IXGBE_EEMNGDATA 0x10114 106#define IXGBE_FLMNGCTL 0x10118 107#define IXGBE_FLMNGDATA 0x1011C 108#define IXGBE_FLMNGCNT 0x10120 109#define IXGBE_FLOP 0x1013C 110#define IXGBE_GRC 0x10200 111#define IXGBE_SRAMREL 0x10210 112#define IXGBE_PHYDBG 0x10218 113 114/* General Receive Control */ 115#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 116#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 117 118#define IXGBE_VPDDIAG0 0x10204 119#define IXGBE_VPDDIAG1 0x10208 120 121/* I2CCTL Bit Masks */ 122#define IXGBE_I2C_CLK_IN 0x00000001 123#define IXGBE_I2C_CLK_OUT 0x00000002 124#define IXGBE_I2C_DATA_IN 0x00000004 125#define IXGBE_I2C_DATA_OUT 0x00000008 126#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 127 128 129/* Interrupt Registers */ 130#define IXGBE_EICR 0x00800 131#define IXGBE_EICS 0x00808 132#define IXGBE_EIMS 0x00880 133#define IXGBE_EIMC 0x00888 134#define IXGBE_EIAC 0x00810 135#define IXGBE_EIAM 0x00890 136#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 137#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 138#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 139#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 140/* 82599 EITR is only 12 bits, with the lower 3 always zero */ 141/* 142 * 82598 EITR is 16 bits but set the limits based on the max 143 * supported by all ixgbe hardware 144 */ 145#define IXGBE_MAX_INT_RATE 488281 146#define IXGBE_MIN_INT_RATE 956 147#define IXGBE_MAX_EITR 0x00000FF8 148#define IXGBE_MIN_EITR 8 149#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 150 (0x012300 + (((_i) - 24) * 4))) 151#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 152#define IXGBE_EITR_LLI_MOD 0x00008000 153#define IXGBE_EITR_CNT_WDIS 0x80000000 154#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 155#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 156#define IXGBE_EITRSEL 0x00894 157#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 158#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 159#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 160#define IXGBE_GPIE 0x00898 161 162/* Flow Control Registers */ 163#define IXGBE_FCADBUL 0x03210 164#define IXGBE_FCADBUH 0x03214 165#define IXGBE_FCAMACL 0x04328 166#define IXGBE_FCAMACH 0x0432C 167#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 168#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 169#define IXGBE_PFCTOP 0x03008 170#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 171#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 172#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 173#define IXGBE_FCRTV 0x032A0 174#define IXGBE_FCCFG 0x03D00 175#define IXGBE_TFCS 0x0CE00 176 177/* Receive DMA Registers */ 178#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 179 (0x0D000 + (((_i) - 64) * 0x40))) 180#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 181 (0x0D004 + (((_i) - 64) * 0x40))) 182#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 183 (0x0D008 + (((_i) - 64) * 0x40))) 184#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 185 (0x0D010 + (((_i) - 64) * 0x40))) 186#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 187 (0x0D018 + (((_i) - 64) * 0x40))) 188#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 189 (0x0D028 + (((_i) - 64) * 0x40))) 190#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 191 (0x0D02C + (((_i) - 64) * 0x40))) 192#define IXGBE_RSCDBU 0x03028 193#define IXGBE_RDDCC 0x02F20 194#define IXGBE_RXMEMWRAP 0x03190 195#define IXGBE_STARCTRL 0x03024 196/* 197 * Split and Replication Receive Control Registers 198 * 00-15 : 0x02100 + n*4 199 * 16-64 : 0x01014 + n*0x40 200 * 64-127: 0x0D014 + (n-64)*0x40 201 */ 202#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 203 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 204 (0x0D014 + (((_i) - 64) * 0x40)))) 205/* 206 * Rx DCA Control Register: 207 * 00-15 : 0x02200 + n*4 208 * 16-64 : 0x0100C + n*0x40 209 * 64-127: 0x0D00C + (n-64)*0x40 210 */ 211#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 212 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 213 (0x0D00C + (((_i) - 64) * 0x40)))) 214#define IXGBE_RDRXCTL 0x02F00 215#define IXGBE_RDRXCTL_RSC_PUSH 0x80 216/* 8 of these 0x03C00 - 0x03C1C */ 217#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 218#define IXGBE_RXCTRL 0x03000 219#define IXGBE_DROPEN 0x03D04 220#define IXGBE_RXPBSIZE_SHIFT 10 221 222/* Receive Registers */ 223#define IXGBE_RXCSUM 0x05000 224#define IXGBE_RFCTL 0x05008 225#define IXGBE_DRECCCTL 0x02F08 226#define IXGBE_DRECCCTL_DISABLE 0 227#define IXGBE_DRECCCTL2 0x02F8C 228 229/* Multicast Table Array - 128 entries */ 230#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 231#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 232 (0x0A200 + ((_i) * 8))) 233#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 234 (0x0A204 + ((_i) * 8))) 235#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 236#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 237/* Packet split receive type */ 238#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 239 (0x0EA00 + ((_i) * 4))) 240/* array of 4096 1-bit vlan filters */ 241#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 242/*array of 4096 4-bit vlan vmdq indices */ 243#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 244#define IXGBE_FCTRL 0x05080 245#define IXGBE_VLNCTRL 0x05088 246#define IXGBE_MCSTCTRL 0x05090 247#define IXGBE_MRQC 0x05818 248#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 249#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 250#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 251#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 252#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 253#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 254#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 255#define IXGBE_RQTC 0x0EC70 256#define IXGBE_MTQC 0x08120 257#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 258#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 259#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 260#define IXGBE_VT_CTL 0x051B0 261#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 262/* 64 Mailboxes, 16 DW each */ 263#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) 264#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 265#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 266#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 267#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 268#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 269#define IXGBE_QDE 0x2F04 270#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 271#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 272#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 273#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 274#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 275#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 276#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 277#define IXGBE_RXFECCERR0 0x051B8 278#define IXGBE_LLITHRESH 0x0EC90 279#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 280#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 281#define IXGBE_IMIRVP 0x05AC0 282#define IXGBE_VMD_CTL 0x0581C 283#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 284#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 285 286 287/* Flow Director registers */ 288#define IXGBE_FDIRCTRL 0x0EE00 289#define IXGBE_FDIRHKEY 0x0EE68 290#define IXGBE_FDIRSKEY 0x0EE6C 291#define IXGBE_FDIRDIP4M 0x0EE3C 292#define IXGBE_FDIRSIP4M 0x0EE40 293#define IXGBE_FDIRTCPM 0x0EE44 294#define IXGBE_FDIRUDPM 0x0EE48 295#define IXGBE_FDIRIP6M 0x0EE74 296#define IXGBE_FDIRM 0x0EE70 297 298/* Flow Director Stats registers */ 299#define IXGBE_FDIRFREE 0x0EE38 300#define IXGBE_FDIRLEN 0x0EE4C 301#define IXGBE_FDIRUSTAT 0x0EE50 302#define IXGBE_FDIRFSTAT 0x0EE54 303#define IXGBE_FDIRMATCH 0x0EE58 304#define IXGBE_FDIRMISS 0x0EE5C 305 306/* Flow Director Programming registers */ 307#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 308#define IXGBE_FDIRIPSA 0x0EE18 309#define IXGBE_FDIRIPDA 0x0EE1C 310#define IXGBE_FDIRPORT 0x0EE20 311#define IXGBE_FDIRVLAN 0x0EE24 312#define IXGBE_FDIRHASH 0x0EE28 313#define IXGBE_FDIRCMD 0x0EE2C 314 315/* Transmit DMA registers */ 316#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/ 317#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 318#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 319#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 320#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 321#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 322#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 323#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 324#define IXGBE_DTXCTL 0x07E00 325 326#define IXGBE_DMATXCTL 0x04A80 327#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 328#define IXGBE_PFDTXGSWC 0x08220 329#define IXGBE_DTXMXSZRQ 0x08100 330#define IXGBE_DTXTCPFLGL 0x04A88 331#define IXGBE_DTXTCPFLGH 0x04A8C 332#define IXGBE_LBDRPEN 0x0CA00 333#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 334 335#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 336#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 337#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 338#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 339 340#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 341 342/* Anti-spoofing defines */ 343#define IXGBE_SPOOF_MACAS_MASK 0xFF 344#define IXGBE_SPOOF_VLANAS_MASK 0xFF00 345#define IXGBE_SPOOF_VLANAS_SHIFT 8 346#define IXGBE_PFVFSPOOF_REG_COUNT 8 347/* 16 of these (0-15) */ 348#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 349/* Tx DCA Control register : 128 of these (0-127) */ 350#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 351#define IXGBE_TIPG 0x0CB00 352#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 353#define IXGBE_MNGTXMAP 0x0CD10 354#define IXGBE_TIPG_FIBER_DEFAULT 3 355#define IXGBE_TXPBSIZE_SHIFT 10 356 357/* Wake up registers */ 358#define IXGBE_WUC 0x05800 359#define IXGBE_WUFC 0x05808 360#define IXGBE_WUS 0x05810 361#define IXGBE_IPAV 0x05838 362#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 363#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 364 365#define IXGBE_WUPL 0x05900 366#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 367 368#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */ 369/* Ext Flexible Host Filter Table */ 370#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) 371 372/* Four Flexible Filters are supported */ 373#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 374 375/* Six Flexible Filters are supported */ 376#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6 377#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 378 379/* Each Flexible Filter is at most 128 (0x80) bytes in length */ 380#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 381#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 382#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 383 384/* Definitions for power management and wakeup registers */ 385/* Wake Up Control */ 386#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 387#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 388#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 389 390/* Wake Up Filter Control */ 391#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 392#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 393#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 394#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 395#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 396#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 397#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 398#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 399#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 400 401#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 402#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 403#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 404#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 405#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 406#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 407#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 408#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 409/* Mask for Ext. flex filters */ 410#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 411#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */ 412#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */ 413#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 414 415/* Wake Up Status */ 416#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 417#define IXGBE_WUS_MAG IXGBE_WUFC_MAG 418#define IXGBE_WUS_EX IXGBE_WUFC_EX 419#define IXGBE_WUS_MC IXGBE_WUFC_MC 420#define IXGBE_WUS_BC IXGBE_WUFC_BC 421#define IXGBE_WUS_ARP IXGBE_WUFC_ARP 422#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 423#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 424#define IXGBE_WUS_MNG IXGBE_WUFC_MNG 425#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 426#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 427#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 428#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 429#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 430#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 431#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 432 433#define IXGBE_WUPL_LENGTH_MASK 0xFFFF 434 435/* DCB registers */ 436#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8 437#define IXGBE_RMCS 0x03D00 438#define IXGBE_DPMCS 0x07F40 439#define IXGBE_PDPMCS 0x0CD00 440#define IXGBE_RUPPBMR 0x050A0 441#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 442#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 443#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 444#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 445#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 446#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 447 448 449/* Security Control Registers */ 450#define IXGBE_SECTXCTRL 0x08800 451#define IXGBE_SECTXSTAT 0x08804 452#define IXGBE_SECTXBUFFAF 0x08808 453#define IXGBE_SECTXMINIFG 0x08810 454#define IXGBE_SECRXCTRL 0x08D00 455#define IXGBE_SECRXSTAT 0x08D04 456 457/* Security Bit Fields and Masks */ 458#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 459#define IXGBE_SECTXCTRL_TX_DIS 0x00000002 460#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 461 462#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 463#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 464 465#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 466#define IXGBE_SECRXCTRL_RX_DIS 0x00000002 467 468#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 469#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 470 471/* LinkSec (MacSec) Registers */ 472#define IXGBE_LSECTXCAP 0x08A00 473#define IXGBE_LSECRXCAP 0x08F00 474#define IXGBE_LSECTXCTRL 0x08A04 475#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 476#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 477#define IXGBE_LSECTXSA 0x08A10 478#define IXGBE_LSECTXPN0 0x08A14 479#define IXGBE_LSECTXPN1 0x08A18 480#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 481#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 482#define IXGBE_LSECRXCTRL 0x08F04 483#define IXGBE_LSECRXSCL 0x08F08 484#define IXGBE_LSECRXSCH 0x08F0C 485#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 486#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 487#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 488#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 489#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 490#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 491#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 492#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 493#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 494#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 495#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 496#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 497#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 498#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 499#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 500#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 501#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 502#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 503#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 504#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 505#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 506#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 507 508/* LinkSec (MacSec) Bit Fields and Masks */ 509#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 510#define IXGBE_LSECTXCAP_SUM_SHIFT 16 511#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 512#define IXGBE_LSECRXCAP_SUM_SHIFT 16 513 514#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 515#define IXGBE_LSECTXCTRL_DISABLE 0x0 516#define IXGBE_LSECTXCTRL_AUTH 0x1 517#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 518#define IXGBE_LSECTXCTRL_AISCI 0x00000020 519#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 520#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 521 522#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 523#define IXGBE_LSECRXCTRL_EN_SHIFT 2 524#define IXGBE_LSECRXCTRL_DISABLE 0x0 525#define IXGBE_LSECRXCTRL_CHECK 0x1 526#define IXGBE_LSECRXCTRL_STRICT 0x2 527#define IXGBE_LSECRXCTRL_DROP 0x3 528#define IXGBE_LSECRXCTRL_PLSH 0x00000040 529#define IXGBE_LSECRXCTRL_RP 0x00000080 530#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 531 532/* IpSec Registers */ 533#define IXGBE_IPSTXIDX 0x08900 534#define IXGBE_IPSTXSALT 0x08904 535#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 536#define IXGBE_IPSRXIDX 0x08E00 537#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 538#define IXGBE_IPSRXSPI 0x08E14 539#define IXGBE_IPSRXIPIDX 0x08E18 540#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 541#define IXGBE_IPSRXSALT 0x08E2C 542#define IXGBE_IPSRXMOD 0x08E30 543 544#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 545 546/* DCB registers */ 547#define IXGBE_RTRPCS 0x02430 548#define IXGBE_RTTDCS 0x04900 549#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 550#define IXGBE_RTTPCS 0x0CD00 551#define IXGBE_RTRUP2TC 0x03020 552#define IXGBE_RTTUP2TC 0x0C800 553#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 554#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 555#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 556#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 557#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 558#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 559#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 560#define IXGBE_RTTDQSEL 0x04904 561#define IXGBE_RTTDT1C 0x04908 562#define IXGBE_RTTDT1S 0x0490C 563#define IXGBE_RTTDTECC 0x04990 564#define IXGBE_RTTDTECC_NO_BCN 0x00000100 565 566#define IXGBE_RTTBCNRC 0x04984 567#define IXGBE_RTTBCNRC_RS_ENA 0x80000000 568#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 569#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 570#define IXGBE_RTTBCNRC_RF_INT_MASK \ 571 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 572#define IXGBE_RTTBCNRM 0x04980 573 574/* BCN (for DCB) Registers */ 575#define IXGBE_RTTBCNRS 0x04988 576#define IXGBE_RTTBCNCR 0x08B00 577#define IXGBE_RTTBCNACH 0x08B04 578#define IXGBE_RTTBCNACL 0x08B08 579#define IXGBE_RTTBCNTG 0x04A90 580#define IXGBE_RTTBCNIDX 0x08B0C 581#define IXGBE_RTTBCNCP 0x08B10 582#define IXGBE_RTFRTIMER 0x08B14 583#define IXGBE_RTTBCNRTT 0x05150 584#define IXGBE_RTTBCNRD 0x0498C 585 586 587/* FCoE DMA Context Registers */ 588#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 589#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 590#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 591#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 592#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0*/ 593#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) 594#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 595#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 596#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 597#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 598#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 599#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 600#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 601#define IXGBE_FCBUFF_OFFSET_SHIFT 16 602#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 603#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 604#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 605#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 606#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 607/* FCoE SOF/EOF */ 608#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 609#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 610#define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 611#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 612/* FCoE Filter Context Registers */ 613#define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 614#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 615#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 616#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 617#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 618#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 619#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 620#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 621#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 622#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 623/* FCoE Receive Control */ 624#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 625#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 626#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 627#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 628#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 629#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 630#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 631#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 632#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 633#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 634#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 635/* FCoE Redirection */ 636#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 637#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 638#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 639#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 640#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */ 641#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 642#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 643 644/* Stats registers */ 645#define IXGBE_CRCERRS 0x04000 646#define IXGBE_ILLERRC 0x04004 647#define IXGBE_ERRBC 0x04008 648#define IXGBE_MSPDC 0x04010 649#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 650#define IXGBE_MLFC 0x04034 651#define IXGBE_MRFC 0x04038 652#define IXGBE_RLEC 0x04040 653#define IXGBE_LXONTXC 0x03F60 654#define IXGBE_LXONRXC 0x0CF60 655#define IXGBE_LXOFFTXC 0x03F68 656#define IXGBE_LXOFFRXC 0x0CF68 657#define IXGBE_LXONRXCNT 0x041A4 658#define IXGBE_LXOFFRXCNT 0x041A8 659#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 660#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 661#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 662#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 663#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 664#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 665#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 666#define IXGBE_PRC64 0x0405C 667#define IXGBE_PRC127 0x04060 668#define IXGBE_PRC255 0x04064 669#define IXGBE_PRC511 0x04068 670#define IXGBE_PRC1023 0x0406C 671#define IXGBE_PRC1522 0x04070 672#define IXGBE_GPRC 0x04074 673#define IXGBE_BPRC 0x04078 674#define IXGBE_MPRC 0x0407C 675#define IXGBE_GPTC 0x04080 676#define IXGBE_GORCL 0x04088 677#define IXGBE_GORCH 0x0408C 678#define IXGBE_GOTCL 0x04090 679#define IXGBE_GOTCH 0x04094 680#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 681#define IXGBE_RUC 0x040A4 682#define IXGBE_RFC 0x040A8 683#define IXGBE_ROC 0x040AC 684#define IXGBE_RJC 0x040B0 685#define IXGBE_MNGPRC 0x040B4 686#define IXGBE_MNGPDC 0x040B8 687#define IXGBE_MNGPTC 0x0CF90 688#define IXGBE_TORL 0x040C0 689#define IXGBE_TORH 0x040C4 690#define IXGBE_TPR 0x040D0 691#define IXGBE_TPT 0x040D4 692#define IXGBE_PTC64 0x040D8 693#define IXGBE_PTC127 0x040DC 694#define IXGBE_PTC255 0x040E0 695#define IXGBE_PTC511 0x040E4 696#define IXGBE_PTC1023 0x040E8 697#define IXGBE_PTC1522 0x040EC 698#define IXGBE_MPTC 0x040F0 699#define IXGBE_BPTC 0x040F4 700#define IXGBE_XEC 0x04120 701#define IXGBE_SSVPC 0x08780 702 703#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 704#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 705 (0x08600 + ((_i) * 4))) 706#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 707 708#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 709#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 710#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 711#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 712#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 713#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 714#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 715#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 716#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 717#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */ 718#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 719#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 720#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 721#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 722#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 723#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 724#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ 725#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ 726#define IXGBE_O2BGPTC 0x041C4 727#define IXGBE_O2BSPC 0x087B0 728#define IXGBE_B2OSPC 0x041C0 729#define IXGBE_B2OGPRC 0x02F90 730#define IXGBE_BUPRC 0x04180 731#define IXGBE_BMPRC 0x04184 732#define IXGBE_BBPRC 0x04188 733#define IXGBE_BUPTC 0x0418C 734#define IXGBE_BMPTC 0x04190 735#define IXGBE_BBPTC 0x04194 736#define IXGBE_BCRCERRS 0x04198 737#define IXGBE_BXONRXC 0x0419C 738#define IXGBE_BXOFFRXC 0x041E0 739#define IXGBE_BXONTXC 0x041E4 740#define IXGBE_BXOFFTXC 0x041E8 741#define IXGBE_PCRC8ECL 0x0E810 742#define IXGBE_PCRC8ECH 0x0E811 743#define IXGBE_PCRC8ECH_MASK 0x1F 744#define IXGBE_LDPCECL 0x0E820 745#define IXGBE_LDPCECH 0x0E821 746 747/* Management */ 748#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 749#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 750#define IXGBE_MANC 0x05820 751#define IXGBE_MFVAL 0x05824 752#define IXGBE_MANC2H 0x05860 753#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 754#define IXGBE_MIPAF 0x058B0 755#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 756#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 757#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 758#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 759#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 760#define IXGBE_LSWFW 0x15014 761#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ 762#define IXGBE_BMCIPVAL 0x05060 763#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001 764#define IXGBE_BMCIP_IPADDR_VALID 0x00000002 765 766/* Management Bit Fields and Masks */ 767#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 768#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */ 769#define IXGBE_MANC_EN_BMC2OS_SHIFT 28 770 771/* Firmware Semaphore Register */ 772#define IXGBE_FWSM_MODE_MASK 0xE 773#define IXGBE_FWSM_TS_ENABLED 0x1 774#define IXGBE_FWSM_FW_MODE_PT 0x4 775 776/* ARC Subsystem registers */ 777#define IXGBE_HICR 0x15F00 778#define IXGBE_FWSTS 0x15F0C 779#define IXGBE_HSMC0R 0x15F04 780#define IXGBE_HSMC1R 0x15F08 781#define IXGBE_SWSR 0x15F10 782#define IXGBE_HFDR 0x15FE8 783#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 784 785#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 786/* Driver sets this bit when done to put command in RAM */ 787#define IXGBE_HICR_C 0x02 788#define IXGBE_HICR_SV 0x04 /* Status Validity */ 789#define IXGBE_HICR_FW_RESET_ENABLE 0x40 790#define IXGBE_HICR_FW_RESET 0x80 791 792/* PCI-E registers */ 793#define IXGBE_GCR 0x11000 794#define IXGBE_GTV 0x11004 795#define IXGBE_FUNCTAG 0x11008 796#define IXGBE_GLT 0x1100C 797#define IXGBE_PCIEPIPEADR 0x11004 798#define IXGBE_PCIEPIPEDAT 0x11008 799#define IXGBE_GSCL_1 0x11010 800#define IXGBE_GSCL_2 0x11014 801#define IXGBE_GSCL_3 0x11018 802#define IXGBE_GSCL_4 0x1101C 803#define IXGBE_GSCN_0 0x11020 804#define IXGBE_GSCN_1 0x11024 805#define IXGBE_GSCN_2 0x11028 806#define IXGBE_GSCN_3 0x1102C 807#define IXGBE_FACTPS 0x10150 808#define IXGBE_PCIEANACTL 0x11040 809#define IXGBE_SWSM 0x10140 810#define IXGBE_FWSM 0x10148 811#define IXGBE_GSSR 0x10160 812#define IXGBE_MREVID 0x11064 813#define IXGBE_DCA_ID 0x11070 814#define IXGBE_DCA_CTRL 0x11074 815#define IXGBE_SWFW_SYNC IXGBE_GSSR 816 817/* PCI-E registers 82599-Specific */ 818#define IXGBE_GCR_EXT 0x11050 819#define IXGBE_GSCL_5_82599 0x11030 820#define IXGBE_GSCL_6_82599 0x11034 821#define IXGBE_GSCL_7_82599 0x11038 822#define IXGBE_GSCL_8_82599 0x1103C 823#define IXGBE_PHYADR_82599 0x11040 824#define IXGBE_PHYDAT_82599 0x11044 825#define IXGBE_PHYCTL_82599 0x11048 826#define IXGBE_PBACLR_82599 0x11068 827#define IXGBE_CIAA_82599 0x11088 828#define IXGBE_CIAD_82599 0x1108C 829#define IXGBE_PICAUSE 0x110B0 830#define IXGBE_PIENA 0x110B8 831#define IXGBE_CDQ_MBR_82599 0x110B4 832#define IXGBE_PCIESPARE 0x110BC 833#define IXGBE_MISC_REG_82599 0x110F0 834#define IXGBE_ECC_CTRL_0_82599 0x11100 835#define IXGBE_ECC_CTRL_1_82599 0x11104 836#define IXGBE_ECC_STATUS_82599 0x110E0 837#define IXGBE_BAR_CTRL_82599 0x110F4 838 839/* PCI Express Control */ 840#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 841#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 842#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 843#define IXGBE_GCR_CAP_VER2 0x00040000 844 845#define IXGBE_GCR_EXT_MSIX_EN 0x80000000 846#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 847#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 848#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 849#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 850#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 851 IXGBE_GCR_EXT_VT_MODE_64) 852#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003 853/* Time Sync Registers */ 854#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 855#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 856#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 857#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 858#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 859#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 860#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 861#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 862#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 863#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 864#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 865#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 866#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 867#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 868#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 869#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 870#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 871#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 872#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 873#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 874#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 875#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 876#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 877#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 878#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 879#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 880#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 881 882/* Diagnostic Registers */ 883#define IXGBE_RDSTATCTL 0x02C20 884#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 885#define IXGBE_RDHMPN 0x02F08 886#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 887#define IXGBE_RDPROBE 0x02F20 888#define IXGBE_RDMAM 0x02F30 889#define IXGBE_RDMAD 0x02F34 890#define IXGBE_TDSTATCTL 0x07C20 891#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 892#define IXGBE_TDHMPN 0x07F08 893#define IXGBE_TDHMPN2 0x082FC 894#define IXGBE_TXDESCIC 0x082CC 895#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 896#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 897#define IXGBE_TDPROBE 0x07F20 898#define IXGBE_TXBUFCTRL 0x0C600 899#define IXGBE_TXBUFDATA0 0x0C610 900#define IXGBE_TXBUFDATA1 0x0C614 901#define IXGBE_TXBUFDATA2 0x0C618 902#define IXGBE_TXBUFDATA3 0x0C61C 903#define IXGBE_RXBUFCTRL 0x03600 904#define IXGBE_RXBUFDATA0 0x03610 905#define IXGBE_RXBUFDATA1 0x03614 906#define IXGBE_RXBUFDATA2 0x03618 907#define IXGBE_RXBUFDATA3 0x0361C 908#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 909#define IXGBE_RFVAL 0x050A4 910#define IXGBE_MDFTC1 0x042B8 911#define IXGBE_MDFTC2 0x042C0 912#define IXGBE_MDFTFIFO1 0x042C4 913#define IXGBE_MDFTFIFO2 0x042C8 914#define IXGBE_MDFTS 0x042CC 915#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 916#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 917#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 918#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 919#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 920#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 921#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 922#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 923#define IXGBE_PCIEECCCTL 0x1106C 924#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 925#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 926#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 927#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 928#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 929#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 930#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 931#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 932#define IXGBE_PCIEECCCTL0 0x11100 933#define IXGBE_PCIEECCCTL1 0x11104 934#define IXGBE_RXDBUECC 0x03F70 935#define IXGBE_TXDBUECC 0x0CF70 936#define IXGBE_RXDBUEST 0x03F74 937#define IXGBE_TXDBUEST 0x0CF74 938#define IXGBE_PBTXECC 0x0C300 939#define IXGBE_PBRXECC 0x03300 940#define IXGBE_GHECCR 0x110B0 941 942/* MAC Registers */ 943#define IXGBE_PCS1GCFIG 0x04200 944#define IXGBE_PCS1GLCTL 0x04208 945#define IXGBE_PCS1GLSTA 0x0420C 946#define IXGBE_PCS1GDBG0 0x04210 947#define IXGBE_PCS1GDBG1 0x04214 948#define IXGBE_PCS1GANA 0x04218 949#define IXGBE_PCS1GANLP 0x0421C 950#define IXGBE_PCS1GANNP 0x04220 951#define IXGBE_PCS1GANLPNP 0x04224 952#define IXGBE_HLREG0 0x04240 953#define IXGBE_HLREG1 0x04244 954#define IXGBE_PAP 0x04248 955#define IXGBE_MACA 0x0424C 956#define IXGBE_APAE 0x04250 957#define IXGBE_ARD 0x04254 958#define IXGBE_AIS 0x04258 959#define IXGBE_MSCA 0x0425C 960#define IXGBE_MSRWD 0x04260 961#define IXGBE_MLADD 0x04264 962#define IXGBE_MHADD 0x04268 963#define IXGBE_MAXFRS 0x04268 964#define IXGBE_TREG 0x0426C 965#define IXGBE_PCSS1 0x04288 966#define IXGBE_PCSS2 0x0428C 967#define IXGBE_XPCSS 0x04290 968#define IXGBE_MFLCN 0x04294 969#define IXGBE_SERDESC 0x04298 970#define IXGBE_MACS 0x0429C 971#define IXGBE_AUTOC 0x042A0 972#define IXGBE_LINKS 0x042A4 973#define IXGBE_LINKS2 0x04324 974#define IXGBE_AUTOC2 0x042A8 975#define IXGBE_AUTOC3 0x042AC 976#define IXGBE_ANLP1 0x042B0 977#define IXGBE_ANLP2 0x042B4 978#define IXGBE_MACC 0x04330 979#define IXGBE_ATLASCTL 0x04800 980#define IXGBE_MMNGC 0x042D0 981#define IXGBE_ANLPNP1 0x042D4 982#define IXGBE_ANLPNP2 0x042D8 983#define IXGBE_KRPCSFC 0x042E0 984#define IXGBE_KRPCSS 0x042E4 985#define IXGBE_FECS1 0x042E8 986#define IXGBE_FECS2 0x042EC 987#define IXGBE_SMADARCTL 0x14F10 988#define IXGBE_MPVC 0x04318 989#define IXGBE_SGMIIC 0x04314 990 991/* Statistics Registers */ 992#define IXGBE_RXNFGPC 0x041B0 993#define IXGBE_RXNFGBCL 0x041B4 994#define IXGBE_RXNFGBCH 0x041B8 995#define IXGBE_RXDGPC 0x02F50 996#define IXGBE_RXDGBCL 0x02F54 997#define IXGBE_RXDGBCH 0x02F58 998#define IXGBE_RXDDGPC 0x02F5C 999#define IXGBE_RXDDGBCL 0x02F60 1000#define IXGBE_RXDDGBCH 0x02F64 1001#define IXGBE_RXLPBKGPC 0x02F68 1002#define IXGBE_RXLPBKGBCL 0x02F6C 1003#define IXGBE_RXLPBKGBCH 0x02F70 1004#define IXGBE_RXDLPBKGPC 0x02F74 1005#define IXGBE_RXDLPBKGBCL 0x02F78 1006#define IXGBE_RXDLPBKGBCH 0x02F7C 1007#define IXGBE_TXDGPC 0x087A0 1008#define IXGBE_TXDGBCL 0x087A4 1009#define IXGBE_TXDGBCH 0x087A8 1010 1011#define IXGBE_RXDSTATCTRL 0x02F40 1012 1013/* Copper Pond 2 link timeout */ 1014#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 1015 1016/* Omer CORECTL */ 1017#define IXGBE_CORECTL 0x014F00 1018/* BARCTRL */ 1019#define IXGBE_BARCTRL 0x110F4 1020#define IXGBE_BARCTRL_FLSIZE 0x0700 1021#define IXGBE_BARCTRL_FLSIZE_SHIFT 8 1022#define IXGBE_BARCTRL_CSRSIZE 0x2000 1023 1024/* RSCCTL Bit Masks */ 1025#define IXGBE_RSCCTL_RSCEN 0x01 1026#define IXGBE_RSCCTL_MAXDESC_1 0x00 1027#define IXGBE_RSCCTL_MAXDESC_4 0x04 1028#define IXGBE_RSCCTL_MAXDESC_8 0x08 1029#define IXGBE_RSCCTL_MAXDESC_16 0x0C 1030#define IXGBE_RSCCTL_TS_DIS 0x02 1031 1032/* RSCDBU Bit Masks */ 1033#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 1034#define IXGBE_RSCDBU_RSCACKDIS 0x00000080 1035 1036/* RDRXCTL Bit Masks */ 1037#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */ 1038#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1039#define IXGBE_RDRXCTL_MVMEN 0x00000020 1040#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1041#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1042#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1043#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/ 1044#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */ 1045#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */ 1046 1047/* RQTC Bit Masks and Shifts */ 1048#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 1049#define IXGBE_RQTC_TC0_MASK (0x7 << 0) 1050#define IXGBE_RQTC_TC1_MASK (0x7 << 4) 1051#define IXGBE_RQTC_TC2_MASK (0x7 << 8) 1052#define IXGBE_RQTC_TC3_MASK (0x7 << 12) 1053#define IXGBE_RQTC_TC4_MASK (0x7 << 16) 1054#define IXGBE_RQTC_TC5_MASK (0x7 << 20) 1055#define IXGBE_RQTC_TC6_MASK (0x7 << 24) 1056#define IXGBE_RQTC_TC7_MASK (0x7 << 28) 1057 1058/* PSRTYPE.RQPL Bit masks and shift */ 1059#define IXGBE_PSRTYPE_RQPL_MASK 0x7 1060#define IXGBE_PSRTYPE_RQPL_SHIFT 29 1061 1062/* CTRL Bit Masks */ 1063#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 1064#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 1065#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 1066#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 1067 1068/* FACTPS */ 1069#define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ 1070#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1071 1072/* MHADD Bit Masks */ 1073#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1074#define IXGBE_MHADD_MFS_SHIFT 16 1075 1076/* Extended Device Control */ 1077#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1078#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1079#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1080#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1081 1082/* Direct Cache Access (DCA) definitions */ 1083#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1084#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1085 1086#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1087#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1088 1089#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1090#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1091#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1092#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ 1093#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ 1094#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ 1095#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ 1096#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1097#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1098 1099#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1100#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1101#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1102#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1103#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1104#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1105#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1106#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1107 1108/* MSCA Bit Masks */ 1109#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */ 1110#define IXGBE_MSCA_NP_ADDR_SHIFT 0 1111#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */ 1112#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */ 1113#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1114#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1115#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1116#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1117#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1118#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */ 1119#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */ 1120#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/ 1121#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1122#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1123#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */ 1124#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */ 1125#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1126#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */ 1127 1128/* MSRWD bit masks */ 1129#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1130#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1131#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1132#define IXGBE_MSRWD_READ_DATA_SHIFT 16 1133 1134/* Atlas registers */ 1135#define IXGBE_ATLAS_PDN_LPBK 0x24 1136#define IXGBE_ATLAS_PDN_10G 0xB 1137#define IXGBE_ATLAS_PDN_1G 0xC 1138#define IXGBE_ATLAS_PDN_AN 0xD 1139 1140/* Atlas bit masks */ 1141#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1142#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1143#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1144#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1145#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1146 1147/* Omer bit masks */ 1148#define IXGBE_CORECTL_WRITE_CMD 0x00010000 1149 1150/* Device Type definitions for new protocol MDIO commands */ 1151#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 1152#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 1153#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 1154#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 1155#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 1156#define IXGBE_TWINAX_DEV 1 1157 1158#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1159 1160#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ 1161#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1162#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1163#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ 1164#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1165#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1166 1167#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 1168#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1169#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 1170#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 1171#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 1172#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 1173#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 1174#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 1175#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 1176#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 1177#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 1178#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ 1179#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 1180#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 1181#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 1182#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 1183#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 1184 1185#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */ 1186#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1187#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1188#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1189 1190/* MII clause 22/28 definitions */ 1191#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 1192 1193#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 1194#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1195#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1196#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 1197#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 1198#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1199#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1200#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 1201#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ 1202#define IXGBE_MII_RESTART 0x200 1203#define IXGBE_MII_AUTONEG_COMPLETE 0x20 1204#define IXGBE_MII_AUTONEG_LINK_UP 0x04 1205#define IXGBE_MII_AUTONEG_REG 0x0 1206 1207#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1208#define IXGBE_MAX_PHY_ADDR 32 1209 1210/* PHY IDs*/ 1211#define TN1010_PHY_ID 0x00A19410 1212#define TNX_FW_REV 0xB 1213#define X540_PHY_ID 0x01540200 1214#define AQ_FW_REV 0x20 1215#define QT2022_PHY_ID 0x0043A400 1216#define ATH_PHY_ID 0x03429050 1217 1218/* PHY Types */ 1219#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 1220 1221/* Special PHY Init Routine */ 1222#define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1223#define IXGBE_PHY_INIT_END_NL 0xFFFF 1224#define IXGBE_CONTROL_MASK_NL 0xF000 1225#define IXGBE_DATA_MASK_NL 0x0FFF 1226#define IXGBE_CONTROL_SHIFT_NL 12 1227#define IXGBE_DELAY_NL 0 1228#define IXGBE_DATA_NL 1 1229#define IXGBE_CONTROL_NL 0x000F 1230#define IXGBE_CONTROL_EOL_NL 0x0FFF 1231#define IXGBE_CONTROL_SOL_NL 0x0000 1232 1233/* General purpose Interrupt Enable */ 1234#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1235#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1236#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1237#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1238#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1239#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1240#define IXGBE_GPIE_EIAME 0x40000000 1241#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1242#define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1243#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1244#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1245#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1246#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1247 1248/* Packet Buffer Initialization */ 1249#define IXGBE_MAX_PACKET_BUFFERS 8 1250 1251#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1252#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1253#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1254#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1255#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1256#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1257#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */ 1258#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 1259 1260#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1261#define IXGBE_MAX_PB 8 1262 1263/* Packet buffer allocation strategies */ 1264enum { 1265 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1266#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1267 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1268#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1269}; 1270 1271/* Transmit Flow Control status */ 1272#define IXGBE_TFCS_TXOFF 0x00000001 1273#define IXGBE_TFCS_TXOFF0 0x00000100 1274#define IXGBE_TFCS_TXOFF1 0x00000200 1275#define IXGBE_TFCS_TXOFF2 0x00000400 1276#define IXGBE_TFCS_TXOFF3 0x00000800 1277#define IXGBE_TFCS_TXOFF4 0x00001000 1278#define IXGBE_TFCS_TXOFF5 0x00002000 1279#define IXGBE_TFCS_TXOFF6 0x00004000 1280#define IXGBE_TFCS_TXOFF7 0x00008000 1281 1282/* TCP Timer */ 1283#define IXGBE_TCPTIMER_KS 0x00000100 1284#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1285#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1286#define IXGBE_TCPTIMER_LOOP 0x00000800 1287#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1288 1289/* HLREG0 Bit Masks */ 1290#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1291#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1292#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1293#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1294#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1295#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1296#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1297#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1298#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1299#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1300#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1301#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1302#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1303#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1304#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1305 1306/* VMD_CTL bitmasks */ 1307#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1308#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1309 1310/* VT_CTL bitmasks */ 1311#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1312#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1313#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1314#define IXGBE_VT_CTL_POOL_SHIFT 7 1315#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1316 1317/* VMOLR bitmasks */ 1318#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1319#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1320#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1321#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1322#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1323 1324/* VFRE bitmask */ 1325#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1326 1327#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1328 1329/* RDHMPN and TDHMPN bitmasks */ 1330#define IXGBE_RDHMPN_RDICADDR 0x007FF800 1331#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1332#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1333#define IXGBE_TDHMPN_TDICADDR 0x003FF800 1334#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1335#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1336 1337#define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1338#define IXGBE_RDMAM_DWORD_SHIFT 9 1339#define IXGBE_RDMAM_DESC_COMP_FIFO 1 1340#define IXGBE_RDMAM_DFC_CMD_FIFO 2 1341#define IXGBE_RDMAM_RSC_HEADER_ADDR 3 1342#define IXGBE_RDMAM_TCN_STATUS_RAM 4 1343#define IXGBE_RDMAM_WB_COLL_FIFO 5 1344#define IXGBE_RDMAM_QSC_CNT_RAM 6 1345#define IXGBE_RDMAM_QSC_FCOE_RAM 7 1346#define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1347#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1348#define IXGBE_RDMAM_QSC_RSC_RAM 0xB 1349#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1350#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1351#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1352#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1353#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 1354#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 1355#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1356#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1357#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1358#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1359#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1360#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1361#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 1362#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 1363#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1364#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1365#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1366#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1367#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 1368#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 1369 1370#define IXGBE_TXDESCIC_READY 0x80000000 1371 1372/* Receive Checksum Control */ 1373#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1374#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1375 1376/* FCRTL Bit Masks */ 1377#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1378#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1379 1380/* PAP bit masks*/ 1381#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1382 1383/* RMCS Bit Masks */ 1384#define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */ 1385/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1386#define IXGBE_RMCS_RAC 0x00000004 1387/* Deficit Fixed Prio ena */ 1388#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC 1389#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1390#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1391#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1392 1393/* FCCFG Bit Masks */ 1394#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1395#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1396 1397/* Interrupt register bitmasks */ 1398 1399/* Extended Interrupt Cause Read */ 1400#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1401#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1402#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1403#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1404#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1405#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1406#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1407#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1408#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1409#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 1410#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1411#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1412#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1413#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1414#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1415#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1416#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1417#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1418 1419/* Extended Interrupt Cause Set */ 1420#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1421#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1422#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1423#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1424#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1425#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1426#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1427#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1428#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1429#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1430#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1431#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1432#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1433#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1434#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1435#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1436 1437/* Extended Interrupt Mask Set */ 1438#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1439#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1440#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1441#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1442#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1443#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1444#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1445#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */ 1446#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1447#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1448#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1449#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1450#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1451#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1452#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1453#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1454#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1455 1456/* Extended Interrupt Mask Clear */ 1457#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1458#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1459#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1460#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1461#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1462#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1463#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1464#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1465#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1466#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1467#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1468#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1469#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1470#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1471#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1472#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1473 1474#define IXGBE_EIMS_ENABLE_MASK ( \ 1475 IXGBE_EIMS_RTX_QUEUE | \ 1476 IXGBE_EIMS_LSC | \ 1477 IXGBE_EIMS_TCP_TIMER | \ 1478 IXGBE_EIMS_OTHER) 1479 1480/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1481#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1482#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1483#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1484#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1485#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1486#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1487#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1488#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1489#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1490#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1491#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1492#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1493#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1494#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1495#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1496#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1497#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1498#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */ 1499#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1500#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1501#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1502#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1503#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1504 1505#define IXGBE_MAX_FTQF_FILTERS 128 1506#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1507#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1508#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1509#define IXGBE_FTQF_PROTOCOL_SCTP 2 1510#define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1511#define IXGBE_FTQF_PRIORITY_SHIFT 2 1512#define IXGBE_FTQF_POOL_MASK 0x0000003F 1513#define IXGBE_FTQF_POOL_SHIFT 8 1514#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1515#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1516#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1517#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1518#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1519#define IXGBE_FTQF_DEST_PORT_MASK 0x17 1520#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1521#define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1522#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1523 1524/* Interrupt clear mask */ 1525#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1526 1527/* Interrupt Vector Allocation Registers */ 1528#define IXGBE_IVAR_REG_NUM 25 1529#define IXGBE_IVAR_REG_NUM_82599 64 1530#define IXGBE_IVAR_TXRX_ENTRY 96 1531#define IXGBE_IVAR_RX_ENTRY 64 1532#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1533#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1534#define IXGBE_IVAR_TX_ENTRY 32 1535 1536#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1537#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1538 1539#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1540 1541#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1542 1543/* ETYPE Queue Filter/Select Bit Masks */ 1544#define IXGBE_MAX_ETQF_FILTERS 8 1545#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 1546#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 1547#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1548#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1549#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 1550#define IXGBE_ETQF_POOL_SHIFT 20 1551 1552#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1553#define IXGBE_ETQS_RX_QUEUE_SHIFT 16 1554#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 1555#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 1556 1557/* 1558 * ETQF filter list: one static filter per filter consumer. This is 1559 * to avoid filter collisions later. Add new filters 1560 * here!! 1561 * 1562 * Current filters: 1563 * EAPOL 802.1x (0x888e): Filter 0 1564 * FCoE (0x8906): Filter 2 1565 * 1588 (0x88f7): Filter 3 1566 * FIP (0x8914): Filter 4 1567 */ 1568#define IXGBE_ETQF_FILTER_EAPOL 0 1569#define IXGBE_ETQF_FILTER_FCOE 2 1570#define IXGBE_ETQF_FILTER_1588 3 1571#define IXGBE_ETQF_FILTER_FIP 4 1572/* VLAN Control Bit Masks */ 1573#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1574#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1575#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 1576#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1577#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1578 1579/* VLAN pool filtering masks */ 1580#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 1581#define IXGBE_VLVF_ENTRIES 64 1582#define IXGBE_VLVF_VLANID_MASK 0x00000FFF 1583/* Per VF Port VLAN insertion rules */ 1584#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 1585#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 1586 1587#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1588 1589/* STATUS Bit Masks */ 1590#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1591#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 1592#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */ 1593 1594#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1595#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1596 1597/* ESDP Bit Masks */ 1598#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 1599#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 1600#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 1601#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 1602#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 1603#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 1604#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 1605#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */ 1606#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 1607#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 1608#define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */ 1609#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */ 1610#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */ 1611#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 1612#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */ 1613#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */ 1614#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */ 1615#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 1616 1617 1618/* LEDCTL Bit Masks */ 1619#define IXGBE_LED_IVRT_BASE 0x00000040 1620#define IXGBE_LED_BLINK_BASE 0x00000080 1621#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 1622#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 1623#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 1624#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 1625#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 1626#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 1627 1628/* LED modes */ 1629#define IXGBE_LED_LINK_UP 0x0 1630#define IXGBE_LED_LINK_10G 0x1 1631#define IXGBE_LED_MAC 0x2 1632#define IXGBE_LED_FILTER 0x3 1633#define IXGBE_LED_LINK_ACTIVE 0x4 1634#define IXGBE_LED_LINK_1G 0x5 1635#define IXGBE_LED_ON 0xE 1636#define IXGBE_LED_OFF 0xF 1637 1638/* AUTOC Bit Masks */ 1639#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 1640#define IXGBE_AUTOC_KX4_SUPP 0x80000000 1641#define IXGBE_AUTOC_KX_SUPP 0x40000000 1642#define IXGBE_AUTOC_PAUSE 0x30000000 1643#define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1644#define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1645#define IXGBE_AUTOC_RF 0x08000000 1646#define IXGBE_AUTOC_PD_TMR 0x06000000 1647#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1648#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1649#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1650#define IXGBE_AUTOC_FECA 0x00040000 1651#define IXGBE_AUTOC_FECR 0x00020000 1652#define IXGBE_AUTOC_KR_SUPP 0x00010000 1653#define IXGBE_AUTOC_AN_RESTART 0x00001000 1654#define IXGBE_AUTOC_FLU 0x00000001 1655#define IXGBE_AUTOC_LMS_SHIFT 13 1656#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 1657#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1658#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 1659#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1660#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1661#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1662#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1663#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1664#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 1665#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1666#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1667#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1668 1669#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 1670#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1671#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1672#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1673#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1674#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1675#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1676#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1677#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1678#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1679#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1680 1681#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1682#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1683#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1684#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1685#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1686#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1687#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 1688 1689#define IXGBE_MACC_FLU 0x00000001 1690#define IXGBE_MACC_FSV_10G 0x00030000 1691#define IXGBE_MACC_FS 0x00040000 1692#define IXGBE_MAC_RX2TX_LPBK 0x00000002 1693 1694/* LINKS Bit Masks */ 1695#define IXGBE_LINKS_KX_AN_COMP 0x80000000 1696#define IXGBE_LINKS_UP 0x40000000 1697#define IXGBE_LINKS_SPEED 0x20000000 1698#define IXGBE_LINKS_MODE 0x18000000 1699#define IXGBE_LINKS_RX_MODE 0x06000000 1700#define IXGBE_LINKS_TX_MODE 0x01800000 1701#define IXGBE_LINKS_XGXS_EN 0x00400000 1702#define IXGBE_LINKS_SGMII_EN 0x02000000 1703#define IXGBE_LINKS_PCS_1G_EN 0x00200000 1704#define IXGBE_LINKS_1G_AN_EN 0x00100000 1705#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1706#define IXGBE_LINKS_1G_SYNC 0x00040000 1707#define IXGBE_LINKS_10G_ALIGN 0x00020000 1708#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 1709#define IXGBE_LINKS_TL_FAULT 0x00001000 1710#define IXGBE_LINKS_SIGNAL 0x00000F00 1711 1712#define IXGBE_LINKS_SPEED_82599 0x30000000 1713#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 1714#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 1715#define IXGBE_LINKS_SPEED_100_82599 0x10000000 1716#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1717#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1718 1719#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1720 1721/* PCS1GLSTA Bit Masks */ 1722#define IXGBE_PCS1GLSTA_LINK_OK 1 1723#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 1724#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 1725#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 1726#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 1727#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 1728#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 1729 1730#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 1731#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 1732 1733/* PCS1GLCTL Bit Masks */ 1734#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 1735#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 1736#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 1737#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1738#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1739#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1740 1741/* ANLP1 Bit Masks */ 1742#define IXGBE_ANLP1_PAUSE 0x0C00 1743#define IXGBE_ANLP1_SYM_PAUSE 0x0400 1744#define IXGBE_ANLP1_ASM_PAUSE 0x0800 1745#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 1746 1747/* SW Semaphore Register bitmasks */ 1748#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1749#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1750#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1751#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 1752 1753/* SW_FW_SYNC/GSSR definitions */ 1754#define IXGBE_GSSR_EEP_SM 0x0001 1755#define IXGBE_GSSR_PHY0_SM 0x0002 1756#define IXGBE_GSSR_PHY1_SM 0x0004 1757#define IXGBE_GSSR_MAC_CSR_SM 0x0008 1758#define IXGBE_GSSR_FLASH_SM 0x0010 1759#define IXGBE_GSSR_SW_MNG_SM 0x0400 1760 1761/* FW Status register bitmask */ 1762#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 1763 1764/* EEC Register */ 1765#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 1766#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 1767#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 1768#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 1769#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 1770#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1771#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 1772#define IXGBE_EEC_FWE_SHIFT 4 1773#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 1774#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 1775#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 1776#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 1777#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 1778#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 1779#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 1780/* EEPROM Addressing bits based on type (0-small, 1-large) */ 1781#define IXGBE_EEC_ADDR_SIZE 0x00000400 1782#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 1783#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 1784 1785#define IXGBE_EEC_SIZE_SHIFT 11 1786#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 1787#define IXGBE_EEPROM_OPCODE_BITS 8 1788 1789/* Part Number String Length */ 1790#define IXGBE_PBANUM_LENGTH 11 1791 1792/* Checksum and EEPROM pointers */ 1793#define IXGBE_PBANUM_PTR_GUARD 0xFAFA 1794#define IXGBE_EEPROM_CHECKSUM 0x3F 1795#define IXGBE_EEPROM_SUM 0xBABA 1796#define IXGBE_PCIE_ANALOG_PTR 0x03 1797#define IXGBE_ATLAS0_CONFIG_PTR 0x04 1798#define IXGBE_PHY_PTR 0x04 1799#define IXGBE_ATLAS1_CONFIG_PTR 0x05 1800#define IXGBE_OPTION_ROM_PTR 0x05 1801#define IXGBE_PCIE_GENERAL_PTR 0x06 1802#define IXGBE_PCIE_CONFIG0_PTR 0x07 1803#define IXGBE_PCIE_CONFIG1_PTR 0x08 1804#define IXGBE_CORE0_PTR 0x09 1805#define IXGBE_CORE1_PTR 0x0A 1806#define IXGBE_MAC0_PTR 0x0B 1807#define IXGBE_MAC1_PTR 0x0C 1808#define IXGBE_CSR0_CONFIG_PTR 0x0D 1809#define IXGBE_CSR1_CONFIG_PTR 0x0E 1810#define IXGBE_FW_PTR 0x0F 1811#define IXGBE_PBANUM0_PTR 0x15 1812#define IXGBE_PBANUM1_PTR 0x16 1813#define IXGBE_ALT_MAC_ADDR_PTR 0x37 1814#define IXGBE_FREE_SPACE_PTR 0X3E 1815 1816#define IXGBE_SAN_MAC_ADDR_PTR 0x28 1817#define IXGBE_DEVICE_CAPS 0x2C 1818#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 1819#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 1820#define IXGBE_MAX_MSIX_VECTORS_82599 0x40 1821#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1822#define IXGBE_MAX_MSIX_VECTORS_82598 0x13 1823 1824/* MSI-X capability fields masks */ 1825#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 1826 1827/* Legacy EEPROM word offsets */ 1828#define IXGBE_ISCSI_BOOT_CAPS 0x0033 1829#define IXGBE_ISCSI_SETUP_PORT_0 0x0030 1830#define IXGBE_ISCSI_SETUP_PORT_1 0x0034 1831 1832/* EEPROM Commands - SPI */ 1833#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 1834#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 1835#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 1836#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 1837#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 1838#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 1839/* EEPROM reset Write Enable latch */ 1840#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 1841#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 1842#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 1843#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 1844#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 1845#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1846 1847/* EEPROM Read Register */ 1848#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 1849#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 1850#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 1851#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1852#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */ 1853#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */ 1854 1855#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 1856 1857#define IXGBE_EEPROM_PAGE_SIZE_MAX 128 1858#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */ 1859#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */ 1860 1861#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 1862#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */ 1863#endif 1864 1865/* Number of 5 microseconds we wait for EERD read and 1866 * EERW write to complete */ 1867#define IXGBE_EERD_EEWR_ATTEMPTS 100000 1868 1869/* # attempts we wait for flush update to complete */ 1870#define IXGBE_FLUDONE_ATTEMPTS 20000 1871 1872#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 1873#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 1874#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 1875#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 1876 1877#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1878#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 1879#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 1880#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 1881#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 1882#define IXGBE_FW_LESM_STATE_1 0x1 1883#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 1884#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1885#define IXGBE_FW_PATCH_VERSION_4 0x7 1886#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 1887#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 1888#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 1889#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 1890#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 1891#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 1892#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */ 1893#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */ 1894#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */ 1895#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */ 1896#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */ 1897#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */ 1898#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */ 1899 1900#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 1901#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 1902#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 1903 1904/* PCI Bus Info */ 1905#define IXGBE_PCI_DEVICE_STATUS 0xAA 1906#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 1907#define IXGBE_PCI_LINK_STATUS 0xB2 1908#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 1909#define IXGBE_PCI_LINK_WIDTH 0x3F0 1910#define IXGBE_PCI_LINK_WIDTH_1 0x10 1911#define IXGBE_PCI_LINK_WIDTH_2 0x20 1912#define IXGBE_PCI_LINK_WIDTH_4 0x40 1913#define IXGBE_PCI_LINK_WIDTH_8 0x80 1914#define IXGBE_PCI_LINK_SPEED 0xF 1915#define IXGBE_PCI_LINK_SPEED_2500 0x1 1916#define IXGBE_PCI_LINK_SPEED_5000 0x2 1917#define IXGBE_PCI_LINK_SPEED_8000 0x3 1918#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 1919#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 1920#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 1921 1922/* Number of 100 microseconds we wait for PCI Express master disable */ 1923#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1924 1925/* Check whether address is multicast. This is little-endian specific check.*/ 1926#define IXGBE_IS_MULTICAST(Address) \ 1927 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 1928 1929/* Check whether an address is broadcast. */ 1930#define IXGBE_IS_BROADCAST(Address) \ 1931 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 1932 (((u8 *)(Address))[1] == ((u8)0xff))) 1933 1934/* RAH */ 1935#define IXGBE_RAH_VIND_MASK 0x003C0000 1936#define IXGBE_RAH_VIND_SHIFT 18 1937#define IXGBE_RAH_AV 0x80000000 1938#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 1939 1940/* Header split receive */ 1941#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 1942#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 1943#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 1944#define IXGBE_RFCTL_RSC_DIS 0x00000010 1945#define IXGBE_RFCTL_NFSW_DIS 0x00000040 1946#define IXGBE_RFCTL_NFSR_DIS 0x00000080 1947#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 1948#define IXGBE_RFCTL_NFS_VER_SHIFT 8 1949#define IXGBE_RFCTL_NFS_VER_2 0 1950#define IXGBE_RFCTL_NFS_VER_3 1 1951#define IXGBE_RFCTL_NFS_VER_4 2 1952#define IXGBE_RFCTL_IPV6_DIS 0x00000400 1953#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 1954#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 1955#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 1956#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1957 1958/* Transmit Config masks */ 1959#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 1960#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 1961#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 1962/* Enable short packet padding to 64 bytes */ 1963#define IXGBE_TX_PAD_ENABLE 0x00000400 1964#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 1965/* This allows for 16K packets + 4k for vlan */ 1966#define IXGBE_MAX_FRAME_SZ 0x40040000 1967 1968#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 1969#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 1970 1971/* Receive Config masks */ 1972#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 1973#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */ 1974#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */ 1975#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */ 1976#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */ 1977#define IXGBE_RXDCTL_RLPML_EN 0x00008000 1978#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 1979 1980#define IXGBE_TSAUXC_EN_CLK 0x00000004 1981#define IXGBE_TSAUXC_SYNCLK 0x00000008 1982#define IXGBE_TSAUXC_SDP0_INT 0x00000040 1983 1984#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 1985#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 1986 1987#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 1988#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 1989#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 1990#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 1991#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 1992#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 1993#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 1994 1995#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 1996#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 1997#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 1998#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 1999#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 2000#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 2001 2002#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 2003#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 2004#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 2005#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 2006#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 2007#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 2008#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 2009#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 2010#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 2011#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00 2012#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 2013 2014#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 2015#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 2016#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 2017#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 2018#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 2019#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 2020/* Receive Priority Flow Control Enable */ 2021#define IXGBE_FCTRL_RPFCE 0x00004000 2022#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 2023#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 2024#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 2025#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 2026#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 2027#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */ 2028#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */ 2029 2030/* Multiple Receive Queue Control */ 2031#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 2032#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 2033#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 2034#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 2035#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 2036#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 2037#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 2038#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 2039#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 2040#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 2041#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2042#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 2043#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2044#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 2045#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 2046#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2047#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 2048#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2049#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2050#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2051#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 2052#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 2053 2054/* Queue Drop Enable */ 2055#define IXGBE_QDE_ENABLE 0x00000001 2056#define IXGBE_QDE_IDX_MASK 0x00007F00 2057#define IXGBE_QDE_IDX_SHIFT 8 2058#define IXGBE_QDE_WRITE 0x00010000 2059#define IXGBE_QDE_READ 0x00020000 2060 2061#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 2062#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 2063#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 2064#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2065#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 2066#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 2067#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 2068#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 2069#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 2070 2071#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 2072#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 2073#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 2074#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 2075#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 2076/* Multiple Transmit Queue Command Register */ 2077#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 2078#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 2079#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 2080#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 2081#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 2082#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */ 2083#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 2084 2085/* Receive Descriptor bit definitions */ 2086#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 2087#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 2088#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 2089#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 2090#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 2091#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 2092#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 2093#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 2094#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 2095#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 2096#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 2097#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 2098#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 2099#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 2100#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2101#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 2102#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 2103#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 2104#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 2105#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 2106#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 2107#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 2108#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 2109#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 2110#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 2111#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 2112#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 2113#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 2114#define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */ 2115#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ 2116#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 2117#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 2118#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 2119#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 2120#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 2121#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 2122#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 2123#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 2124#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 2125#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 2126#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 2127#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 2128#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 2129#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 2130#define IXGBE_RXD_PRI_SHIFT 13 2131#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 2132#define IXGBE_RXD_CFI_SHIFT 12 2133 2134#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 2135#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 2136#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 2137#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 2138#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 2139#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 2140#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 2141#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 2142#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 2143#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 2144#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 2145#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */ 2146 2147/* PSRTYPE bit definitions */ 2148#define IXGBE_PSRTYPE_TCPHDR 0x00000010 2149#define IXGBE_PSRTYPE_UDPHDR 0x00000020 2150#define IXGBE_PSRTYPE_IPV4HDR 0x00000100 2151#define IXGBE_PSRTYPE_IPV6HDR 0x00000200 2152#define IXGBE_PSRTYPE_L2HDR 0x00001000 2153 2154/* SRRCTL bit definitions */ 2155#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2156#define IXGBE_SRRCTL_RDMTS_SHIFT 22 2157#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 2158#define IXGBE_SRRCTL_DROP_EN 0x10000000 2159#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 2160#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 2161#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 2162#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2163#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2164#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2165#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2166#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 2167 2168#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 2169#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 2170 2171#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 2172#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 2173#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2174#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2175#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2176#define IXGBE_RXDADV_RSCCNT_SHIFT 17 2177#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2178#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2179#define IXGBE_RXDADV_SPH 0x8000 2180 2181/* RSS Hash results */ 2182#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2183#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2184#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2185#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2186#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2187#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2188#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2189#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2190#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2191#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2192 2193/* RSS Packet Types as indicated in the receive descriptor. */ 2194#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2195#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2196#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2197#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2198#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2199#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2200#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2201#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2202#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2203#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2204#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2205#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2206#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2207#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2208#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2209 2210/* Security Processing bit Indication */ 2211#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 2212#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 2213#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 2214#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 2215#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 2216 2217/* Masks to determine if packets should be dropped due to frame errors */ 2218#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2219 IXGBE_RXD_ERR_CE | \ 2220 IXGBE_RXD_ERR_LE | \ 2221 IXGBE_RXD_ERR_PE | \ 2222 IXGBE_RXD_ERR_OSE | \ 2223 IXGBE_RXD_ERR_USE) 2224 2225#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2226 IXGBE_RXDADV_ERR_CE | \ 2227 IXGBE_RXDADV_ERR_LE | \ 2228 IXGBE_RXDADV_ERR_PE | \ 2229 IXGBE_RXDADV_ERR_OSE | \ 2230 IXGBE_RXDADV_ERR_USE) 2231 2232#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE 2233 2234/* Multicast bit mask */ 2235#define IXGBE_MCSTCTRL_MFE 0x4 2236 2237/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2238#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2239#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2240#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2241 2242/* Vlan-specific macros */ 2243#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2244#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2245#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2246#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2247 2248/* SR-IOV specific macros */ 2249#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 2250#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 2251#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) 2252#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2253 2254/* Little Endian defines */ 2255#ifndef __le16 2256#define __le16 u16 2257#endif 2258#ifndef __le32 2259#define __le32 u32 2260#endif 2261#ifndef __le64 2262#define __le64 u64 2263 2264#endif 2265#ifndef __be16 2266/* Big Endian defines */ 2267#define __be16 u16 2268#define __be32 u32 2269#define __be64 u64 2270 2271#endif 2272enum ixgbe_fdir_pballoc_type { 2273 IXGBE_FDIR_PBALLOC_NONE = 0, 2274 IXGBE_FDIR_PBALLOC_64K = 1, 2275 IXGBE_FDIR_PBALLOC_128K = 2, 2276 IXGBE_FDIR_PBALLOC_256K = 3, 2277}; 2278 2279/* Flow Director register values */ 2280#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 2281#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 2282#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 2283#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 2284#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 2285#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 2286#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 2287#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2288#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2289#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2290#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 2291#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 2292#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 2293 2294#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 2295#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 2296#define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2297#define IXGBE_FDIRM_VLANID 0x00000001 2298#define IXGBE_FDIRM_VLANP 0x00000002 2299#define IXGBE_FDIRM_POOL 0x00000004 2300#define IXGBE_FDIRM_L4P 0x00000008 2301#define IXGBE_FDIRM_FLEX 0x00000010 2302#define IXGBE_FDIRM_DIPv6 0x00000020 2303 2304#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2305#define IXGBE_FDIRFREE_FREE_SHIFT 0 2306#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2307#define IXGBE_FDIRFREE_COLL_SHIFT 16 2308#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2309#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2310#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2311#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2312#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2313#define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2314#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2315#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2316#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2317#define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2318#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2319#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2320#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2321#define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2322#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2323#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2324 2325#define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2326#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2327#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2328#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2329#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 2330#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2331#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2332#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2333#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2334#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2335#define IXGBE_FDIRCMD_IPV6 0x00000080 2336#define IXGBE_FDIRCMD_CLEARHT 0x00000100 2337#define IXGBE_FDIRCMD_DROP 0x00000200 2338#define IXGBE_FDIRCMD_INT 0x00000400 2339#define IXGBE_FDIRCMD_LAST 0x00000800 2340#define IXGBE_FDIRCMD_COLLISION 0x00001000 2341#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2342#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 2343#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 2344#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2345#define IXGBE_FDIR_INIT_DONE_POLL 10 2346#define IXGBE_FDIRCMD_CMD_POLL 10 2347 2348#define IXGBE_FDIR_DROP_QUEUE 127 2349 2350#define IXGBE_STATUS_OVERHEATING_BIT 20 /* STATUS overtemp bit num */ 2351 2352/* Manageablility Host Interface defines */ 2353#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2354#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2355#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 2356 2357/* CEM Support */ 2358#define FW_CEM_HDR_LEN 0x4 2359#define FW_CEM_CMD_DRIVER_INFO 0xDD 2360#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2361#define FW_CEM_CMD_RESERVED 0X0 2362#define FW_CEM_UNUSED_VER 0x0 2363#define FW_CEM_MAX_RETRIES 3 2364#define FW_CEM_RESP_STATUS_SUCCESS 0x1 2365 2366/* Host Interface Command Structures */ 2367 2368struct ixgbe_hic_hdr { 2369 u8 cmd; 2370 u8 buf_len; 2371 union { 2372 u8 cmd_resv; 2373 u8 ret_status; 2374 } cmd_or_resp; 2375 u8 checksum; 2376}; 2377 2378struct ixgbe_hic_drv_info { 2379 struct ixgbe_hic_hdr hdr; 2380 u8 port_num; 2381 u8 ver_sub; 2382 u8 ver_build; 2383 u8 ver_min; 2384 u8 ver_maj; 2385 u8 pad; /* end spacing to ensure length is mult. of dword */ 2386 u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 2387}; 2388 2389/* Transmit Descriptor - Legacy */ 2390struct ixgbe_legacy_tx_desc { 2391 u64 buffer_addr; /* Address of the descriptor's data buffer */ 2392 union { 2393 __le32 data; 2394 struct { 2395 __le16 length; /* Data buffer length */ 2396 u8 cso; /* Checksum offset */ 2397 u8 cmd; /* Descriptor control */ 2398 } flags; 2399 } lower; 2400 union { 2401 __le32 data; 2402 struct { 2403 u8 status; /* Descriptor status */ 2404 u8 css; /* Checksum start */ 2405 __le16 vlan; 2406 } fields; 2407 } upper; 2408}; 2409 2410/* Transmit Descriptor - Advanced */ 2411union ixgbe_adv_tx_desc { 2412 struct { 2413 __le64 buffer_addr; /* Address of descriptor's data buf */ 2414 __le32 cmd_type_len; 2415 __le32 olinfo_status; 2416 } read; 2417 struct { 2418 __le64 rsvd; /* Reserved */ 2419 __le32 nxtseq_seed; 2420 __le32 status; 2421 } wb; 2422}; 2423 2424/* Receive Descriptor - Legacy */ 2425struct ixgbe_legacy_rx_desc { 2426 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 2427 __le16 length; /* Length of data DMAed into data buffer */ 2428 __le16 csum; /* Packet checksum */ 2429 u8 status; /* Descriptor status */ 2430 u8 errors; /* Descriptor Errors */ 2431 __le16 vlan; 2432}; 2433 2434/* Receive Descriptor - Advanced */ 2435union ixgbe_adv_rx_desc { 2436 struct { 2437 __le64 pkt_addr; /* Packet buffer address */ 2438 __le64 hdr_addr; /* Header buffer address */ 2439 } read; 2440 struct { 2441 struct { 2442 union { 2443 __le32 data; 2444 struct { 2445 __le16 pkt_info; /* RSS, Pkt type */ 2446 __le16 hdr_info; /* Splithdr, hdrlen */ 2447 } hs_rss; 2448 } lo_dword; 2449 union { 2450 __le32 rss; /* RSS Hash */ 2451 struct { 2452 __le16 ip_id; /* IP id */ 2453 __le16 csum; /* Packet Checksum */ 2454 } csum_ip; 2455 } hi_dword; 2456 } lower; 2457 struct { 2458 __le32 status_error; /* ext status/error */ 2459 __le16 length; /* Packet length */ 2460 __le16 vlan; /* VLAN tag */ 2461 } upper; 2462 } wb; /* writeback */ 2463}; 2464 2465/* Context descriptors */ 2466struct ixgbe_adv_tx_context_desc { 2467 __le32 vlan_macip_lens; 2468 __le32 seqnum_seed; 2469 __le32 type_tucmd_mlhl; 2470 __le32 mss_l4len_idx; 2471}; 2472 2473/* Adv Transmit Descriptor Config Masks */ 2474#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 2475#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 2476#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */ 2477#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 2478#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 2479#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 2480#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */ 2481#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */ 2482#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 2483#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 2484#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 2485#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 2486#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */ 2487#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 2488#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2489#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 2490#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 2491#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 2492#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 2493#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 2494#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 2495#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 2496 IXGBE_ADVTXD_POPTS_SHIFT) 2497#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 2498 IXGBE_ADVTXD_POPTS_SHIFT) 2499#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 2500#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 2501#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 2502/* 1st&Last TSO-full iSCSI PDU */ 2503#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 2504#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 2505#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2506#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2507#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2508#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2509#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2510#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2511#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2512#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 2513#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ 2514#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 2515#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2516#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2517#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2518#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 2519#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 2520#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 2521#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ 2522#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ 2523#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 2524#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 2525#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 2526#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 2527#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2528#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2529 2530/* Autonegotiation advertised speeds */ 2531typedef u32 ixgbe_autoneg_advertised; 2532/* Link speed */ 2533typedef u32 ixgbe_link_speed; 2534#define IXGBE_LINK_SPEED_UNKNOWN 0 2535#define IXGBE_LINK_SPEED_100_FULL 0x0008 2536#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 2537#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 2538#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 2539 IXGBE_LINK_SPEED_10GB_FULL) 2540#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 2541 IXGBE_LINK_SPEED_1GB_FULL | \ 2542 IXGBE_LINK_SPEED_10GB_FULL) 2543 2544/* Physical layer type */ 2545typedef u32 ixgbe_physical_layer; 2546#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 2547#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 2548#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 2549#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 2550#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 2551#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 2552#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 2553#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 2554#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 2555#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 2556#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 2557#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 2558#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 2559#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 2560#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000 2561#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000 2562 2563/* Flow Control Data Sheet defined values 2564 * Calculation and defines taken from 802.1bb Annex O 2565 */ 2566 2567/* BitTimes (BT) conversion */ 2568#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 2569#define IXGBE_B2BT(BT) (BT * 8) 2570 2571/* Calculate Delay to respond to PFC */ 2572#define IXGBE_PFC_D 672 2573 2574/* Calculate Cable Delay */ 2575#define IXGBE_CABLE_DC 5556 /* Delay Copper */ 2576#define IXGBE_CABLE_DO 5000 /* Delay Optical */ 2577 2578/* Calculate Interface Delay X540 */ 2579#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 2580#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 2581#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 2582 2583#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 2584 2585/* Calculate Interface Delay 82598, 82599 */ 2586#define IXGBE_PHY_D 12800 2587#define IXGBE_MAC_D 4096 2588#define IXGBE_XAUI_D (2 * 1024) 2589 2590#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 2591 2592/* Calculate Delay incurred from higher layer */ 2593#define IXGBE_HD 6144 2594 2595/* Calculate PCI Bus delay for low thresholds */ 2596#define IXGBE_PCI_DELAY 10000 2597 2598/* Calculate X540 delay value in bit times */ 2599#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 2600 ((36 * \ 2601 (IXGBE_B2BT(_max_frame_link) + \ 2602 IXGBE_PFC_D + \ 2603 (2 * IXGBE_CABLE_DC) + \ 2604 (2 * IXGBE_ID_X540) + \ 2605 IXGBE_HD) / 25 + 1) + \ 2606 2 * IXGBE_B2BT(_max_frame_tc)) 2607 2608/* Calculate 82599, 82598 delay value in bit times */ 2609#define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 2610 ((36 * \ 2611 (IXGBE_B2BT(_max_frame_link) + \ 2612 IXGBE_PFC_D + \ 2613 (2 * IXGBE_CABLE_DC) + \ 2614 (2 * IXGBE_ID) + \ 2615 IXGBE_HD) / 25 + 1) + \ 2616 2 * IXGBE_B2BT(_max_frame_tc)) 2617 2618/* Calculate low threshold delay values */ 2619#define IXGBE_LOW_DV_X540(_max_frame_tc) \ 2620 (2 * IXGBE_B2BT(_max_frame_tc) + \ 2621 (36 * IXGBE_PCI_DELAY / 25) + 1) 2622#define IXGBE_LOW_DV(_max_frame_tc) \ 2623 (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 2624 2625/* Software ATR hash keys */ 2626#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 2627#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 2628 2629/* Software ATR input stream values and masks */ 2630#define IXGBE_ATR_HASH_MASK 0x7fff 2631#define IXGBE_ATR_L4TYPE_MASK 0x3 2632#define IXGBE_ATR_L4TYPE_UDP 0x1 2633#define IXGBE_ATR_L4TYPE_TCP 0x2 2634#define IXGBE_ATR_L4TYPE_SCTP 0x3 2635#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 2636enum ixgbe_atr_flow_type { 2637 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 2638 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 2639 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 2640 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 2641 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 2642 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 2643 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 2644 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 2645}; 2646 2647/* Flow Director ATR input struct. */ 2648union ixgbe_atr_input { 2649 /* 2650 * Byte layout in order, all values with MSB first: 2651 * 2652 * vm_pool - 1 byte 2653 * flow_type - 1 byte 2654 * vlan_id - 2 bytes 2655 * src_ip - 16 bytes 2656 * dst_ip - 16 bytes 2657 * src_port - 2 bytes 2658 * dst_port - 2 bytes 2659 * flex_bytes - 2 bytes 2660 * bkt_hash - 2 bytes 2661 */ 2662 struct { 2663 u8 vm_pool; 2664 u8 flow_type; 2665 __be16 vlan_id; 2666 __be32 dst_ip[4]; 2667 __be32 src_ip[4]; 2668 __be16 src_port; 2669 __be16 dst_port; 2670 __be16 flex_bytes; 2671 __be16 bkt_hash; 2672 } formatted; 2673 __be32 dword_stream[11]; 2674}; 2675 2676/* Flow Director compressed ATR hash input struct */ 2677union ixgbe_atr_hash_dword { 2678 struct { 2679 u8 vm_pool; 2680 u8 flow_type; 2681 __be16 vlan_id; 2682 } formatted; 2683 __be32 ip; 2684 struct { 2685 __be16 src; 2686 __be16 dst; 2687 } port; 2688 __be16 flex_bytes; 2689 __be32 dword; 2690}; 2691 2692 2693/* 2694 * Unavailable: The FCoE Boot Option ROM is not present in the flash. 2695 * Disabled: Present; boot order is not set for any targets on the port. 2696 * Enabled: Present; boot order is set for at least one target on the port. 2697 */ 2698enum ixgbe_fcoe_boot_status { 2699 ixgbe_fcoe_bootstatus_disabled = 0, 2700 ixgbe_fcoe_bootstatus_enabled = 1, 2701 ixgbe_fcoe_bootstatus_unavailable = 0xFFFF 2702}; 2703 2704enum ixgbe_eeprom_type { 2705 ixgbe_eeprom_uninitialized = 0, 2706 ixgbe_eeprom_spi, 2707 ixgbe_flash, 2708 ixgbe_eeprom_none /* No NVM support */ 2709}; 2710 2711enum ixgbe_mac_type { 2712 ixgbe_mac_unknown = 0, 2713 ixgbe_mac_82598EB, 2714 ixgbe_mac_82599EB, 2715 ixgbe_mac_82599_vf, 2716 ixgbe_mac_X540, 2717 ixgbe_mac_X540_vf, 2718 ixgbe_num_macs 2719}; 2720 2721enum ixgbe_phy_type { 2722 ixgbe_phy_unknown = 0, 2723 ixgbe_phy_none, 2724 ixgbe_phy_tn, 2725 ixgbe_phy_aq, 2726 ixgbe_phy_cu_unknown, 2727 ixgbe_phy_qt, 2728 ixgbe_phy_xaui, 2729 ixgbe_phy_nl, 2730 ixgbe_phy_sfp_passive_tyco, 2731 ixgbe_phy_sfp_passive_unknown, 2732 ixgbe_phy_sfp_active_unknown, 2733 ixgbe_phy_sfp_avago, 2734 ixgbe_phy_sfp_ftl, 2735 ixgbe_phy_sfp_ftl_active, 2736 ixgbe_phy_sfp_unknown, 2737 ixgbe_phy_sfp_intel, 2738 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ 2739 ixgbe_phy_generic 2740}; 2741 2742/* 2743 * SFP+ module type IDs: 2744 * 2745 * ID Module Type 2746 * ============= 2747 * 0 SFP_DA_CU 2748 * 1 SFP_SR 2749 * 2 SFP_LR 2750 * 3 SFP_DA_CU_CORE0 - 82599-specific 2751 * 4 SFP_DA_CU_CORE1 - 82599-specific 2752 * 5 SFP_SR/LR_CORE0 - 82599-specific 2753 * 6 SFP_SR/LR_CORE1 - 82599-specific 2754 */ 2755enum ixgbe_sfp_type { 2756 ixgbe_sfp_type_da_cu = 0, 2757 ixgbe_sfp_type_sr = 1, 2758 ixgbe_sfp_type_lr = 2, 2759 ixgbe_sfp_type_da_cu_core0 = 3, 2760 ixgbe_sfp_type_da_cu_core1 = 4, 2761 ixgbe_sfp_type_srlr_core0 = 5, 2762 ixgbe_sfp_type_srlr_core1 = 6, 2763 ixgbe_sfp_type_da_act_lmt_core0 = 7, 2764 ixgbe_sfp_type_da_act_lmt_core1 = 8, 2765 ixgbe_sfp_type_1g_cu_core0 = 9, 2766 ixgbe_sfp_type_1g_cu_core1 = 10, 2767 ixgbe_sfp_type_1g_sx_core0 = 11, 2768 ixgbe_sfp_type_1g_sx_core1 = 12, 2769 ixgbe_sfp_type_not_present = 0xFFFE, 2770 ixgbe_sfp_type_unknown = 0xFFFF 2771}; 2772 2773enum ixgbe_media_type { 2774 ixgbe_media_type_unknown = 0, 2775 ixgbe_media_type_fiber, 2776 ixgbe_media_type_fiber_fixed, 2777 ixgbe_media_type_copper, 2778 ixgbe_media_type_backplane, 2779 ixgbe_media_type_cx4, 2780 ixgbe_media_type_virtual 2781}; 2782 2783/* Flow Control Settings */ 2784enum ixgbe_fc_mode { 2785 ixgbe_fc_none = 0, 2786 ixgbe_fc_rx_pause, 2787 ixgbe_fc_tx_pause, 2788 ixgbe_fc_full, 2789 ixgbe_fc_default 2790}; 2791 2792/* Smart Speed Settings */ 2793#define IXGBE_SMARTSPEED_MAX_RETRIES 3 2794enum ixgbe_smart_speed { 2795 ixgbe_smart_speed_auto = 0, 2796 ixgbe_smart_speed_on, 2797 ixgbe_smart_speed_off 2798}; 2799 2800/* PCI bus types */ 2801enum ixgbe_bus_type { 2802 ixgbe_bus_type_unknown = 0, 2803 ixgbe_bus_type_pci, 2804 ixgbe_bus_type_pcix, 2805 ixgbe_bus_type_pci_express, 2806 ixgbe_bus_type_reserved 2807}; 2808 2809/* PCI bus speeds */ 2810enum ixgbe_bus_speed { 2811 ixgbe_bus_speed_unknown = 0, 2812 ixgbe_bus_speed_33 = 33, 2813 ixgbe_bus_speed_66 = 66, 2814 ixgbe_bus_speed_100 = 100, 2815 ixgbe_bus_speed_120 = 120, 2816 ixgbe_bus_speed_133 = 133, 2817 ixgbe_bus_speed_2500 = 2500, 2818 ixgbe_bus_speed_5000 = 5000, 2819 ixgbe_bus_speed_8000 = 8000, 2820 ixgbe_bus_speed_reserved 2821}; 2822 2823/* PCI bus widths */ 2824enum ixgbe_bus_width { 2825 ixgbe_bus_width_unknown = 0, 2826 ixgbe_bus_width_pcie_x1 = 1, 2827 ixgbe_bus_width_pcie_x2 = 2, 2828 ixgbe_bus_width_pcie_x4 = 4, 2829 ixgbe_bus_width_pcie_x8 = 8, 2830 ixgbe_bus_width_32 = 32, 2831 ixgbe_bus_width_64 = 64, 2832 ixgbe_bus_width_reserved 2833}; 2834 2835struct ixgbe_addr_filter_info { 2836 u32 num_mc_addrs; 2837 u32 rar_used_count; 2838 u32 mta_in_use; 2839 u32 overflow_promisc; 2840 bool user_set_promisc; 2841}; 2842 2843/* Bus parameters */ 2844struct ixgbe_bus_info { 2845 enum ixgbe_bus_speed speed; 2846 enum ixgbe_bus_width width; 2847 enum ixgbe_bus_type type; 2848 2849 u16 func; 2850 u16 lan_id; 2851}; 2852 2853/* Flow control parameters */ 2854struct ixgbe_fc_info { 2855 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */ 2856 u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */ 2857 u16 pause_time; /* Flow Control Pause timer */ 2858 bool send_xon; /* Flow control send XON */ 2859 bool strict_ieee; /* Strict IEEE mode */ 2860 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 2861 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 2862 enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 2863 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 2864}; 2865 2866/* Statistics counters collected by the MAC */ 2867struct ixgbe_hw_stats { 2868 u64 crcerrs; 2869 u64 illerrc; 2870 u64 errbc; 2871 u64 mspdc; 2872 u64 mpctotal; 2873 u64 mpc[8]; 2874 u64 mlfc; 2875 u64 mrfc; 2876 u64 rlec; 2877 u64 lxontxc; 2878 u64 lxonrxc; 2879 u64 lxofftxc; 2880 u64 lxoffrxc; 2881 u64 pxontxc[8]; 2882 u64 pxonrxc[8]; 2883 u64 pxofftxc[8]; 2884 u64 pxoffrxc[8]; 2885 u64 prc64; 2886 u64 prc127; 2887 u64 prc255; 2888 u64 prc511; 2889 u64 prc1023; 2890 u64 prc1522; 2891 u64 gprc; 2892 u64 bprc; 2893 u64 mprc; 2894 u64 gptc; 2895 u64 gorc; 2896 u64 gotc; 2897 u64 rnbc[8]; 2898 u64 ruc; 2899 u64 rfc; 2900 u64 roc; 2901 u64 rjc; 2902 u64 mngprc; 2903 u64 mngpdc; 2904 u64 mngptc; 2905 u64 tor; 2906 u64 tpr; 2907 u64 tpt; 2908 u64 ptc64; 2909 u64 ptc127; 2910 u64 ptc255; 2911 u64 ptc511; 2912 u64 ptc1023; 2913 u64 ptc1522; 2914 u64 mptc; 2915 u64 bptc; 2916 u64 xec; 2917 u64 qprc[16]; 2918 u64 qptc[16]; 2919 u64 qbrc[16]; 2920 u64 qbtc[16]; 2921 u64 qprdc[16]; 2922 u64 pxon2offc[8]; 2923 u64 fdirustat_add; 2924 u64 fdirustat_remove; 2925 u64 fdirfstat_fadd; 2926 u64 fdirfstat_fremove; 2927 u64 fdirmatch; 2928 u64 fdirmiss; 2929 u64 fccrc; 2930 u64 fclast; 2931 u64 fcoerpdc; 2932 u64 fcoeprc; 2933 u64 fcoeptc; 2934 u64 fcoedwrc; 2935 u64 fcoedwtc; 2936 u64 fcoe_noddp; 2937 u64 fcoe_noddp_ext_buff; 2938 u64 ldpcec; 2939 u64 pcrc8ec; 2940 u64 b2ospc; 2941 u64 b2ogprc; 2942 u64 o2bgptc; 2943 u64 o2bspc; 2944}; 2945 2946/* forward declaration */ 2947struct ixgbe_hw; 2948 2949/* iterator type for walking multicast address lists */ 2950typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 2951 u32 *vmdq); 2952 2953/* Function pointer table */ 2954struct ixgbe_eeprom_operations { 2955 s32 (*init_params)(struct ixgbe_hw *); 2956 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 2957 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 2958 s32 (*write)(struct ixgbe_hw *, u16, u16); 2959 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 2960 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 2961 s32 (*update_checksum)(struct ixgbe_hw *); 2962 u16 (*calc_checksum)(struct ixgbe_hw *); 2963}; 2964 2965struct ixgbe_mac_operations { 2966 s32 (*init_hw)(struct ixgbe_hw *); 2967 s32 (*reset_hw)(struct ixgbe_hw *); 2968 s32 (*start_hw)(struct ixgbe_hw *); 2969 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 2970 void (*enable_relaxed_ordering)(struct ixgbe_hw *); 2971 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 2972 u32 (*get_supported_physical_layer)(struct ixgbe_hw *); 2973 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 2974 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 2975 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); 2976 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 2977 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 2978 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *); 2979 s32 (*stop_adapter)(struct ixgbe_hw *); 2980 s32 (*get_bus_info)(struct ixgbe_hw *); 2981 void (*set_lan_id)(struct ixgbe_hw *); 2982 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 2983 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 2984 s32 (*setup_sfp)(struct ixgbe_hw *); 2985 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 2986 s32 (*disable_sec_rx_path)(struct ixgbe_hw *); 2987 s32 (*enable_sec_rx_path)(struct ixgbe_hw *); 2988 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16); 2989 void (*release_swfw_sync)(struct ixgbe_hw *, u16); 2990 2991 /* Link */ 2992 void (*disable_tx_laser)(struct ixgbe_hw *); 2993 void (*enable_tx_laser)(struct ixgbe_hw *); 2994 void (*flap_tx_laser)(struct ixgbe_hw *); 2995 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 2996 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 2997 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 2998 bool *); 2999 3000 /* Packet Buffer manipulation */ 3001 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int); 3002 3003 /* LED */ 3004 s32 (*led_on)(struct ixgbe_hw *, u32); 3005 s32 (*led_off)(struct ixgbe_hw *, u32); 3006 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 3007 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 3008 3009 /* RAR, Multicast, VLAN */ 3010 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 3011 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); 3012 s32 (*clear_rar)(struct ixgbe_hw *, u32); 3013 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); 3014 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 3015 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 3016 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 3017 s32 (*init_rx_addrs)(struct ixgbe_hw *); 3018 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3019 ixgbe_mc_addr_itr); 3020 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3021 ixgbe_mc_addr_itr, bool clear); 3022 s32 (*enable_mc)(struct ixgbe_hw *); 3023 s32 (*disable_mc)(struct ixgbe_hw *); 3024 s32 (*clear_vfta)(struct ixgbe_hw *); 3025 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 3026 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *); 3027 s32 (*init_uta_tables)(struct ixgbe_hw *); 3028 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 3029 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 3030 3031 /* Flow Control */ 3032 s32 (*fc_enable)(struct ixgbe_hw *); 3033 3034 /* Manageability interface */ 3035 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); 3036}; 3037 3038struct ixgbe_phy_operations { 3039 s32 (*identify)(struct ixgbe_hw *); 3040 s32 (*identify_sfp)(struct ixgbe_hw *); 3041 s32 (*init)(struct ixgbe_hw *); 3042 s32 (*reset)(struct ixgbe_hw *); 3043 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 3044 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 3045 s32 (*setup_link)(struct ixgbe_hw *); 3046 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3047 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 3048 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 3049 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 3050 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 3051 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 3052 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 3053 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 3054 void (*i2c_bus_clear)(struct ixgbe_hw *); 3055 s32 (*check_overtemp)(struct ixgbe_hw *); 3056}; 3057 3058struct ixgbe_eeprom_info { 3059 struct ixgbe_eeprom_operations ops; 3060 enum ixgbe_eeprom_type type; 3061 u32 semaphore_delay; 3062 u16 word_size; 3063 u16 address_bits; 3064 u16 word_page_size; 3065}; 3066 3067#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 3068struct ixgbe_mac_info { 3069 struct ixgbe_mac_operations ops; 3070 enum ixgbe_mac_type type; 3071 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3072 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3073 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 3074 /* prefix for World Wide Node Name (WWNN) */ 3075 u16 wwnn_prefix; 3076 /* prefix for World Wide Port Name (WWPN) */ 3077 u16 wwpn_prefix; 3078#define IXGBE_MAX_MTA 128 3079 u32 mta_shadow[IXGBE_MAX_MTA]; 3080 s32 mc_filter_type; 3081 u32 mcft_size; 3082 u32 vft_size; 3083 u32 num_rar_entries; 3084 u32 rar_highwater; 3085 u32 rx_pb_size; 3086 u32 max_tx_queues; 3087 u32 max_rx_queues; 3088 u32 orig_autoc; 3089 u32 cached_autoc; 3090 u8 san_mac_rar_index; 3091 bool get_link_status; 3092 u32 orig_autoc2; 3093 u16 max_msix_vectors; 3094 bool arc_subsystem_valid; 3095 bool orig_link_settings_stored; 3096 bool autotry_restart; 3097 u8 flags; 3098}; 3099 3100struct ixgbe_phy_info { 3101 struct ixgbe_phy_operations ops; 3102 enum ixgbe_phy_type type; 3103 u32 addr; 3104 u32 id; 3105 enum ixgbe_sfp_type sfp_type; 3106 bool sfp_setup_needed; 3107 u32 revision; 3108 enum ixgbe_media_type media_type; 3109 bool reset_disable; 3110 ixgbe_autoneg_advertised autoneg_advertised; 3111 enum ixgbe_smart_speed smart_speed; 3112 bool smart_speed_active; 3113 bool multispeed_fiber; 3114 bool reset_if_overtemp; 3115}; 3116 3117#include "ixgbe_mbx.h" 3118 3119struct ixgbe_mbx_operations { 3120 void (*init_params)(struct ixgbe_hw *hw); 3121 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 3122 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 3123 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3124 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3125 s32 (*check_for_msg)(struct ixgbe_hw *, u16); 3126 s32 (*check_for_ack)(struct ixgbe_hw *, u16); 3127 s32 (*check_for_rst)(struct ixgbe_hw *, u16); 3128}; 3129 3130struct ixgbe_mbx_stats { 3131 u32 msgs_tx; 3132 u32 msgs_rx; 3133 3134 u32 acks; 3135 u32 reqs; 3136 u32 rsts; 3137}; 3138 3139struct ixgbe_mbx_info { 3140 struct ixgbe_mbx_operations ops; 3141 struct ixgbe_mbx_stats stats; 3142 u32 timeout; 3143 u32 usec_delay; 3144 u32 v2p_mailbox; 3145 u16 size; 3146}; 3147 3148struct ixgbe_hw { 3149 u8 *hw_addr; 3150 void *back; 3151 struct ixgbe_mac_info mac; 3152 struct ixgbe_addr_filter_info addr_ctrl; 3153 struct ixgbe_fc_info fc; 3154 struct ixgbe_phy_info phy; 3155 struct ixgbe_eeprom_info eeprom; 3156 struct ixgbe_bus_info bus; 3157 struct ixgbe_mbx_info mbx; 3158 u16 device_id; 3159 u16 vendor_id; 3160 u16 subsystem_device_id; 3161 u16 subsystem_vendor_id; 3162 u8 revision_id; 3163 bool adapter_stopped; 3164 int api_version; 3165 bool force_full_reset; 3166 bool allow_unsupported_sfp; 3167}; 3168 3169#define ixgbe_call_func(hw, func, params, error) \ 3170 (func != NULL) ? func params : error 3171 3172 3173/* Error Codes */ 3174#define IXGBE_SUCCESS 0 3175#define IXGBE_ERR_EEPROM -1 3176#define IXGBE_ERR_EEPROM_CHECKSUM -2 3177#define IXGBE_ERR_PHY -3 3178#define IXGBE_ERR_CONFIG -4 3179#define IXGBE_ERR_PARAM -5 3180#define IXGBE_ERR_MAC_TYPE -6 3181#define IXGBE_ERR_UNKNOWN_PHY -7 3182#define IXGBE_ERR_LINK_SETUP -8 3183#define IXGBE_ERR_ADAPTER_STOPPED -9 3184#define IXGBE_ERR_INVALID_MAC_ADDR -10 3185#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 3186#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 3187#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 3188#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 3189#define IXGBE_ERR_RESET_FAILED -15 3190#define IXGBE_ERR_SWFW_SYNC -16 3191#define IXGBE_ERR_PHY_ADDR_INVALID -17 3192#define IXGBE_ERR_I2C -18 3193#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 3194#define IXGBE_ERR_SFP_NOT_PRESENT -20 3195#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 3196#define IXGBE_ERR_NO_SAN_ADDR_PTR -22 3197#define IXGBE_ERR_FDIR_REINIT_FAILED -23 3198#define IXGBE_ERR_EEPROM_VERSION -24 3199#define IXGBE_ERR_NO_SPACE -25 3200#define IXGBE_ERR_OVERTEMP -26 3201#define IXGBE_ERR_FC_NOT_NEGOTIATED -27 3202#define IXGBE_ERR_FC_NOT_SUPPORTED -28 3203#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 3204#define IXGBE_ERR_PBA_SECTION -31 3205#define IXGBE_ERR_INVALID_ARGUMENT -32 3206#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 3207#define IXGBE_ERR_OUT_OF_MEM -34 3208#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36 3209 3210#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 3211 3212 3213#endif /* _IXGBE_TYPE_H_ */ 3214