ixgbe_type.h revision 200239
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 200239 2009-12-07 21:30:54Z jfv $*/ 34 35#ifndef _IXGBE_TYPE_H_ 36#define _IXGBE_TYPE_H_ 37 38#include "ixgbe_osdep.h" 39 40 41/* Vendor ID */ 42#define IXGBE_INTEL_VENDOR_ID 0x8086 43 44/* Device IDs */ 45#define IXGBE_DEV_ID_82598 0x10B6 46#define IXGBE_DEV_ID_82598_BX 0x1508 47#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 48#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 49#define IXGBE_DEV_ID_82598AT 0x10C8 50#define IXGBE_DEV_ID_82598AT2 0x150B 51#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 52#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 53#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 54#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 55#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 56#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 57#define IXGBE_DEV_ID_82599_KX4 0x10F7 58#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 59#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 60#define IXGBE_DEV_ID_82599_CX4 0x10F9 61#define IXGBE_DEV_ID_82599_SFP 0x10FB 62#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 63 64/* General Registers */ 65#define IXGBE_CTRL 0x00000 66#define IXGBE_STATUS 0x00008 67#define IXGBE_CTRL_EXT 0x00018 68#define IXGBE_ESDP 0x00020 69#define IXGBE_EODSDP 0x00028 70#define IXGBE_I2CCTL 0x00028 71#define IXGBE_LEDCTL 0x00200 72#define IXGBE_FRTIMER 0x00048 73#define IXGBE_TCPTIMER 0x0004C 74#define IXGBE_CORESPARE 0x00600 75#define IXGBE_EXVET 0x05078 76 77/* NVM Registers */ 78#define IXGBE_EEC 0x10010 79#define IXGBE_EERD 0x10014 80#define IXGBE_EEWR 0x10018 81#define IXGBE_FLA 0x1001C 82#define IXGBE_EEMNGCTL 0x10110 83#define IXGBE_EEMNGDATA 0x10114 84#define IXGBE_FLMNGCTL 0x10118 85#define IXGBE_FLMNGDATA 0x1011C 86#define IXGBE_FLMNGCNT 0x10120 87#define IXGBE_FLOP 0x1013C 88#define IXGBE_GRC 0x10200 89 90/* General Receive Control */ 91#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 92#define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */ 93 94#define IXGBE_VPDDIAG0 0x10204 95#define IXGBE_VPDDIAG1 0x10208 96 97/* I2CCTL Bit Masks */ 98#define IXGBE_I2C_CLK_IN 0x00000001 99#define IXGBE_I2C_CLK_OUT 0x00000002 100#define IXGBE_I2C_DATA_IN 0x00000004 101#define IXGBE_I2C_DATA_OUT 0x00000008 102 103/* Interrupt Registers */ 104#define IXGBE_EICR 0x00800 105#define IXGBE_EICS 0x00808 106#define IXGBE_EIMS 0x00880 107#define IXGBE_EIMC 0x00888 108#define IXGBE_EIAC 0x00810 109#define IXGBE_EIAM 0x00890 110#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 111#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 112#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 113#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 114/* 82599 EITR is only 12 bits, with the lower 3 always zero */ 115/* 116 * 82598 EITR is 16 bits but set the limits based on the max 117 * supported by all ixgbe hardware 118 */ 119#define IXGBE_MAX_INT_RATE 488281 120#define IXGBE_MIN_INT_RATE 956 121#define IXGBE_MAX_EITR 0x00000FF8 122#define IXGBE_MIN_EITR 8 123#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 124 (0x012300 + (((_i) - 24) * 4))) 125#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 126#define IXGBE_EITR_LLI_MOD 0x00008000 127#define IXGBE_EITR_CNT_WDIS 0x80000000 128#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 129#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 130#define IXGBE_EITRSEL 0x00894 131#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 132#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 133#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 134#define IXGBE_GPIE 0x00898 135 136/* Flow Control Registers */ 137#define IXGBE_FCADBUL 0x03210 138#define IXGBE_FCADBUH 0x03214 139#define IXGBE_FCAMACL 0x04328 140#define IXGBE_FCAMACH 0x0432C 141#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 142#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 143#define IXGBE_PFCTOP 0x03008 144#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 145#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 146#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 147#define IXGBE_FCRTV 0x032A0 148#define IXGBE_FCCFG 0x03D00 149#define IXGBE_TFCS 0x0CE00 150 151/* Receive DMA Registers */ 152#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 153 (0x0D000 + ((_i - 64) * 0x40))) 154#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 155 (0x0D004 + ((_i - 64) * 0x40))) 156#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 157 (0x0D008 + ((_i - 64) * 0x40))) 158#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 159 (0x0D010 + ((_i - 64) * 0x40))) 160#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 161 (0x0D018 + ((_i - 64) * 0x40))) 162#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 163 (0x0D028 + ((_i - 64) * 0x40))) 164#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 165 (0x0D02C + ((_i - 64) * 0x40))) 166#define IXGBE_RSCDBU 0x03028 167#define IXGBE_RDDCC 0x02F20 168#define IXGBE_RXMEMWRAP 0x03190 169#define IXGBE_STARCTRL 0x03024 170/* 171 * Split and Replication Receive Control Registers 172 * 00-15 : 0x02100 + n*4 173 * 16-64 : 0x01014 + n*0x40 174 * 64-127: 0x0D014 + (n-64)*0x40 175 */ 176#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 177 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 178 (0x0D014 + ((_i - 64) * 0x40)))) 179/* 180 * Rx DCA Control Register: 181 * 00-15 : 0x02200 + n*4 182 * 16-64 : 0x0100C + n*0x40 183 * 64-127: 0x0D00C + (n-64)*0x40 184 */ 185#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 186 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 187 (0x0D00C + ((_i - 64) * 0x40)))) 188#define IXGBE_RDRXCTL 0x02F00 189#define IXGBE_RDRXCTL_RSC_PUSH 0x80 190#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 191 /* 8 of these 0x03C00 - 0x03C1C */ 192#define IXGBE_RXCTRL 0x03000 193#define IXGBE_DROPEN 0x03D04 194#define IXGBE_RXPBSIZE_SHIFT 10 195 196/* Receive Registers */ 197#define IXGBE_RXCSUM 0x05000 198#define IXGBE_RFCTL 0x05008 199#define IXGBE_DRECCCTL 0x02F08 200#define IXGBE_DRECCCTL_DISABLE 0 201/* Multicast Table Array - 128 entries */ 202#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 203#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 204 (0x0A200 + ((_i) * 8))) 205#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 206 (0x0A204 + ((_i) * 8))) 207#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 208#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 209/* Packet split receive type */ 210#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 211 (0x0EA00 + ((_i) * 4))) 212/* array of 4096 1-bit vlan filters */ 213#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 214/*array of 4096 4-bit vlan vmdq indices */ 215#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 216#define IXGBE_FCTRL 0x05080 217#define IXGBE_VLNCTRL 0x05088 218#define IXGBE_MCSTCTRL 0x05090 219#define IXGBE_MRQC 0x05818 220#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 221#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 222#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 223#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 224#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 225#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 226#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 227#define IXGBE_RQTC 0x0EC70 228#define IXGBE_MTQC 0x08120 229#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 230#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 231#define IXGBE_VT_CTL 0x051B0 232#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 233#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 234#define IXGBE_QDE 0x2F04 235#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 236#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 237#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4)) 238#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 239#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 240#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 241#define IXGBE_LLITHRESH 0x0EC90 242#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 243#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 244#define IXGBE_IMIRVP 0x05AC0 245#define IXGBE_VMD_CTL 0x0581C 246#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 247#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 248 249/* Flow Director registers */ 250#define IXGBE_FDIRCTRL 0x0EE00 251#define IXGBE_FDIRHKEY 0x0EE68 252#define IXGBE_FDIRSKEY 0x0EE6C 253#define IXGBE_FDIRDIP4M 0x0EE3C 254#define IXGBE_FDIRSIP4M 0x0EE40 255#define IXGBE_FDIRTCPM 0x0EE44 256#define IXGBE_FDIRUDPM 0x0EE48 257#define IXGBE_FDIRIP6M 0x0EE74 258#define IXGBE_FDIRM 0x0EE70 259 260/* Flow Director Stats registers */ 261#define IXGBE_FDIRFREE 0x0EE38 262#define IXGBE_FDIRLEN 0x0EE4C 263#define IXGBE_FDIRUSTAT 0x0EE50 264#define IXGBE_FDIRFSTAT 0x0EE54 265#define IXGBE_FDIRMATCH 0x0EE58 266#define IXGBE_FDIRMISS 0x0EE5C 267 268/* Flow Director Programming registers */ 269#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 270#define IXGBE_FDIRIPSA 0x0EE18 271#define IXGBE_FDIRIPDA 0x0EE1C 272#define IXGBE_FDIRPORT 0x0EE20 273#define IXGBE_FDIRVLAN 0x0EE24 274#define IXGBE_FDIRHASH 0x0EE28 275#define IXGBE_FDIRCMD 0x0EE2C 276 277/* Transmit DMA registers */ 278#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ 279#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 280#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 281#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 282#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 283#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 284#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 285#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 286#define IXGBE_DTXCTL 0x07E00 287 288#define IXGBE_DMATXCTL 0x04A80 289#define IXGBE_PFDTXGSWC 0x08220 290#define IXGBE_DTXMXSZRQ 0x08100 291#define IXGBE_DTXTCPFLGL 0x04A88 292#define IXGBE_DTXTCPFLGH 0x04A8C 293#define IXGBE_LBDRPEN 0x0CA00 294#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 295 296#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 297#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 298#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 299#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 300 301#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 302#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ 303/* Tx DCA Control register : 128 of these (0-127) */ 304#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 305#define IXGBE_TIPG 0x0CB00 306#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 307#define IXGBE_MNGTXMAP 0x0CD10 308#define IXGBE_TIPG_FIBER_DEFAULT 3 309#define IXGBE_TXPBSIZE_SHIFT 10 310 311/* Wake up registers */ 312#define IXGBE_WUC 0x05800 313#define IXGBE_WUFC 0x05808 314#define IXGBE_WUS 0x05810 315#define IXGBE_IPAV 0x05838 316#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 317#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 318 319#define IXGBE_WUPL 0x05900 320#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 321#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */ 322#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host 323 * Filter Table */ 324 325#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 326#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 327 328/* Each Flexible Filter is at most 128 (0x80) bytes in length */ 329#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 330#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 331#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 332 333/* Definitions for power management and wakeup registers */ 334/* Wake Up Control */ 335#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 336#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 337#define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/ 338 339/* Wake Up Filter Control */ 340#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 341#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 342#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 343#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 344#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 345#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 346#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 347#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 348#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 349 350#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 351#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 352#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 353#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 354#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 355#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 356#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 357#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 358#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ 359#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */ 360#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 361 362/* Wake Up Status */ 363#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 364#define IXGBE_WUS_MAG IXGBE_WUFC_MAG 365#define IXGBE_WUS_EX IXGBE_WUFC_EX 366#define IXGBE_WUS_MC IXGBE_WUFC_MC 367#define IXGBE_WUS_BC IXGBE_WUFC_BC 368#define IXGBE_WUS_ARP IXGBE_WUFC_ARP 369#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 370#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 371#define IXGBE_WUS_MNG IXGBE_WUFC_MNG 372#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 373#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 374#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 375#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 376#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 377#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 378#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 379 380/* Wake Up Packet Length */ 381#define IXGBE_WUPL_LENGTH_MASK 0xFFFF 382 383/* DCB registers */ 384#define IXGBE_RMCS 0x03D00 385#define IXGBE_DPMCS 0x07F40 386#define IXGBE_PDPMCS 0x0CD00 387#define IXGBE_RUPPBMR 0x050A0 388#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 389#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 390#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 391#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 392#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 393#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 394 395 396/* Security Control Registers */ 397#define IXGBE_SECTXCTRL 0x08800 398#define IXGBE_SECTXSTAT 0x08804 399#define IXGBE_SECTXBUFFAF 0x08808 400#define IXGBE_SECTXMINIFG 0x08810 401#define IXGBE_SECTXSTAT 0x08804 402#define IXGBE_SECRXCTRL 0x08D00 403#define IXGBE_SECRXSTAT 0x08D04 404 405/* Security Bit Fields and Masks */ 406#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 407#define IXGBE_SECTXCTRL_TX_DIS 0x00000002 408#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 409 410#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 411#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 412 413#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 414#define IXGBE_SECRXCTRL_RX_DIS 0x00000002 415 416#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 417#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 418 419/* LinkSec (MacSec) Registers */ 420#define IXGBE_LSECTXCAP 0x08A00 421#define IXGBE_LSECRXCAP 0x08F00 422#define IXGBE_LSECTXCTRL 0x08A04 423#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 424#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 425#define IXGBE_LSECTXSA 0x08A10 426#define IXGBE_LSECTXPN0 0x08A14 427#define IXGBE_LSECTXPN1 0x08A18 428#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 429#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 430#define IXGBE_LSECRXCTRL 0x08F04 431#define IXGBE_LSECRXSCL 0x08F08 432#define IXGBE_LSECRXSCH 0x08F0C 433#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 434#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 435#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 436#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 437#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 438#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 439#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 440#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 441#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 442#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 443#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 444#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 445#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 446#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 447#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 448#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 449#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 450#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 451#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 452#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 453#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 454#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 455 456/* LinkSec (MacSec) Bit Fields and Masks */ 457#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 458#define IXGBE_LSECTXCAP_SUM_SHIFT 16 459#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 460#define IXGBE_LSECRXCAP_SUM_SHIFT 16 461 462#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 463#define IXGBE_LSECTXCTRL_DISABLE 0x0 464#define IXGBE_LSECTXCTRL_AUTH 0x1 465#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 466#define IXGBE_LSECTXCTRL_AISCI 0x00000020 467#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 468#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 469 470#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 471#define IXGBE_LSECRXCTRL_EN_SHIFT 2 472#define IXGBE_LSECRXCTRL_DISABLE 0x0 473#define IXGBE_LSECRXCTRL_CHECK 0x1 474#define IXGBE_LSECRXCTRL_STRICT 0x2 475#define IXGBE_LSECRXCTRL_DROP 0x3 476#define IXGBE_LSECRXCTRL_PLSH 0x00000040 477#define IXGBE_LSECRXCTRL_RP 0x00000080 478#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 479 480/* IpSec Registers */ 481#define IXGBE_IPSTXIDX 0x08900 482#define IXGBE_IPSTXSALT 0x08904 483#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 484#define IXGBE_IPSRXIDX 0x08E00 485#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 486#define IXGBE_IPSRXSPI 0x08E14 487#define IXGBE_IPSRXIPIDX 0x08E18 488#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 489#define IXGBE_IPSRXSALT 0x08E2C 490#define IXGBE_IPSRXMOD 0x08E30 491 492#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 493 494/* DCB registers */ 495#define IXGBE_RTRPCS 0x02430 496#define IXGBE_RTTDCS 0x04900 497#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 498#define IXGBE_RTTPCS 0x0CD00 499#define IXGBE_RTRUP2TC 0x03020 500#define IXGBE_RTTUP2TC 0x0C800 501#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 502#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 503#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 504#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 505#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 506#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 507#define IXGBE_RTTDQSEL 0x04904 508#define IXGBE_RTTDT1C 0x04908 509#define IXGBE_RTTDT1S 0x0490C 510#define IXGBE_RTTDTECC 0x04990 511#define IXGBE_RTTDTECC_NO_BCN 0x00000100 512 513#define IXGBE_RTTBCNRC 0x04984 514 515/* BCN (for DCB) Registers */ 516#define IXGBE_RTTBCNRM 0x04980 517#define IXGBE_RTTBCNRS 0x04988 518#define IXGBE_RTTBCNCR 0x08B00 519#define IXGBE_RTTBCNACH 0x08B04 520#define IXGBE_RTTBCNACL 0x08B08 521#define IXGBE_RTTBCNTG 0x04A90 522#define IXGBE_RTTBCNIDX 0x08B0C 523#define IXGBE_RTTBCNCP 0x08B10 524#define IXGBE_RTFRTIMER 0x08B14 525#define IXGBE_RTTBCNRTT 0x05150 526#define IXGBE_RTTBCNRD 0x0498C 527 528/* FCoE DMA Context Registers */ 529#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 530#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 531#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 532#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 533#define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ 534#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) 535#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 536#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 537#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 538#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 539#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 540#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 541#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 542#define IXGBE_FCBUFF_OFFSET_SHIFT 16 543#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 544#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 545#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 546#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 547#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 548/* FCoE SOF/EOF */ 549#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 550#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 551#define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 552#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 553/* FCoE Filter Context Registers */ 554#define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 555#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 556#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 557#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 558#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 559#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 560#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 561#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 562#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 563#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 564/* FCoE Receive Control */ 565#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 566#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 567#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 568#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 569#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 570#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 571#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 572#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 573#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 574#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 575#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 576/* FCoE Redirection */ 577#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 578#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 579#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 580#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 581#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 582#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 583 584/* Stats registers */ 585#define IXGBE_CRCERRS 0x04000 586#define IXGBE_ILLERRC 0x04004 587#define IXGBE_ERRBC 0x04008 588#define IXGBE_MSPDC 0x04010 589#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 590#define IXGBE_MLFC 0x04034 591#define IXGBE_MRFC 0x04038 592#define IXGBE_RLEC 0x04040 593#define IXGBE_LXONTXC 0x03F60 594#define IXGBE_LXONRXC 0x0CF60 595#define IXGBE_LXOFFTXC 0x03F68 596#define IXGBE_LXOFFRXC 0x0CF68 597#define IXGBE_LXONRXCNT 0x041A4 598#define IXGBE_LXOFFRXCNT 0x041A8 599#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 600#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 601#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 602#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 603#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 604#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 605#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 606#define IXGBE_PRC64 0x0405C 607#define IXGBE_PRC127 0x04060 608#define IXGBE_PRC255 0x04064 609#define IXGBE_PRC511 0x04068 610#define IXGBE_PRC1023 0x0406C 611#define IXGBE_PRC1522 0x04070 612#define IXGBE_GPRC 0x04074 613#define IXGBE_BPRC 0x04078 614#define IXGBE_MPRC 0x0407C 615#define IXGBE_GPTC 0x04080 616#define IXGBE_GORCL 0x04088 617#define IXGBE_GORCH 0x0408C 618#define IXGBE_GOTCL 0x04090 619#define IXGBE_GOTCH 0x04094 620#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 621#define IXGBE_RUC 0x040A4 622#define IXGBE_RFC 0x040A8 623#define IXGBE_ROC 0x040AC 624#define IXGBE_RJC 0x040B0 625#define IXGBE_MNGPRC 0x040B4 626#define IXGBE_MNGPDC 0x040B8 627#define IXGBE_MNGPTC 0x0CF90 628#define IXGBE_TORL 0x040C0 629#define IXGBE_TORH 0x040C4 630#define IXGBE_TPR 0x040D0 631#define IXGBE_TPT 0x040D4 632#define IXGBE_PTC64 0x040D8 633#define IXGBE_PTC127 0x040DC 634#define IXGBE_PTC255 0x040E0 635#define IXGBE_PTC511 0x040E4 636#define IXGBE_PTC1023 0x040E8 637#define IXGBE_PTC1522 0x040EC 638#define IXGBE_MPTC 0x040F0 639#define IXGBE_BPTC 0x040F4 640#define IXGBE_XEC 0x04120 641#define IXGBE_SSVPC 0x08780 642 643#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 644#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 645 (0x08600 + ((_i) * 4))) 646#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 647 648#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 649#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 650#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 651#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 652#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 653#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 654#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 655#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ 656#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 657#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 658#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 659#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 660#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 661#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 662#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ 663#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ 664 665/* Management */ 666#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 667#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 668#define IXGBE_MANC 0x05820 669#define IXGBE_MFVAL 0x05824 670#define IXGBE_MANC2H 0x05860 671#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 672#define IXGBE_MIPAF 0x058B0 673#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 674#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 675#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 676#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 677#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 678#define IXGBE_LSWFW 0x15014 679 680/* ARC Subsystem registers */ 681#define IXGBE_HICR 0x15F00 682#define IXGBE_FWSTS 0x15F0C 683#define IXGBE_HSMC0R 0x15F04 684#define IXGBE_HSMC1R 0x15F08 685#define IXGBE_SWSR 0x15F10 686#define IXGBE_HFDR 0x15FE8 687#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 688 689/* PCI-E registers */ 690#define IXGBE_GCR 0x11000 691#define IXGBE_GTV 0x11004 692#define IXGBE_FUNCTAG 0x11008 693#define IXGBE_GLT 0x1100C 694#define IXGBE_GSCL_1 0x11010 695#define IXGBE_GSCL_2 0x11014 696#define IXGBE_GSCL_3 0x11018 697#define IXGBE_GSCL_4 0x1101C 698#define IXGBE_GSCN_0 0x11020 699#define IXGBE_GSCN_1 0x11024 700#define IXGBE_GSCN_2 0x11028 701#define IXGBE_GSCN_3 0x1102C 702#define IXGBE_FACTPS 0x10150 703#define IXGBE_PCIEANACTL 0x11040 704#define IXGBE_SWSM 0x10140 705#define IXGBE_FWSM 0x10148 706#define IXGBE_GSSR 0x10160 707#define IXGBE_MREVID 0x11064 708#define IXGBE_DCA_ID 0x11070 709#define IXGBE_DCA_CTRL 0x11074 710#define IXGBE_SWFW_SYNC IXGBE_GSSR 711 712/* PCI-E registers 82599-Specific */ 713#define IXGBE_GCR_EXT 0x11050 714#define IXGBE_GSCL_5_82599 0x11030 715#define IXGBE_GSCL_6_82599 0x11034 716#define IXGBE_GSCL_7_82599 0x11038 717#define IXGBE_GSCL_8_82599 0x1103C 718#define IXGBE_PHYADR_82599 0x11040 719#define IXGBE_PHYDAT_82599 0x11044 720#define IXGBE_PHYCTL_82599 0x11048 721#define IXGBE_PBACLR_82599 0x11068 722#define IXGBE_CIAA_82599 0x11088 723#define IXGBE_CIAD_82599 0x1108C 724#define IXGBE_INTRPT_CSR_82599 0x110B0 725#define IXGBE_INTRPT_MASK_82599 0x110B8 726#define IXGBE_CDQ_MBR_82599 0x110B4 727#define IXGBE_MISC_REG_82599 0x110F0 728#define IXGBE_ECC_CTRL_0_82599 0x11100 729#define IXGBE_ECC_CTRL_1_82599 0x11104 730#define IXGBE_ECC_STATUS_82599 0x110E0 731#define IXGBE_BAR_CTRL_82599 0x110F4 732 733/* PCI Express Control */ 734#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 735#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 736#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 737#define IXGBE_GCR_CAP_VER2 0x00040000 738 739/* Time Sync Registers */ 740#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 741#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 742#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 743#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 744#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 745#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 746#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 747#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 748#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 749#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 750#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 751#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 752#define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */ 753 754/* Diagnostic Registers */ 755#define IXGBE_RDSTATCTL 0x02C20 756#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 757#define IXGBE_RDHMPN 0x02F08 758#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 759#define IXGBE_RDPROBE 0x02F20 760#define IXGBE_RDMAM 0x02F30 761#define IXGBE_RDMAD 0x02F34 762#define IXGBE_TDSTATCTL 0x07C20 763#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 764#define IXGBE_TDHMPN 0x07F08 765#define IXGBE_TDHMPN2 0x082FC 766#define IXGBE_TXDESCIC 0x082CC 767#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 768#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 769#define IXGBE_TDPROBE 0x07F20 770#define IXGBE_TXBUFCTRL 0x0C600 771#define IXGBE_TXBUFDATA0 0x0C610 772#define IXGBE_TXBUFDATA1 0x0C614 773#define IXGBE_TXBUFDATA2 0x0C618 774#define IXGBE_TXBUFDATA3 0x0C61C 775#define IXGBE_RXBUFCTRL 0x03600 776#define IXGBE_RXBUFDATA0 0x03610 777#define IXGBE_RXBUFDATA1 0x03614 778#define IXGBE_RXBUFDATA2 0x03618 779#define IXGBE_RXBUFDATA3 0x0361C 780#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 781#define IXGBE_RFVAL 0x050A4 782#define IXGBE_MDFTC1 0x042B8 783#define IXGBE_MDFTC2 0x042C0 784#define IXGBE_MDFTFIFO1 0x042C4 785#define IXGBE_MDFTFIFO2 0x042C8 786#define IXGBE_MDFTS 0x042CC 787#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 788#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 789#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 790#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 791#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 792#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 793#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 794#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 795#define IXGBE_PCIEECCCTL 0x1106C 796#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 797#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 798#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 799#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 800#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 801#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 802#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 803#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 804#define IXGBE_PCIEECCCTL0 0x11100 805#define IXGBE_PCIEECCCTL1 0x11104 806#define IXGBE_RXDBUECC 0x03F70 807#define IXGBE_TXDBUECC 0x0CF70 808#define IXGBE_RXDBUEST 0x03F74 809#define IXGBE_TXDBUEST 0x0CF74 810#define IXGBE_PBTXECC 0x0C300 811#define IXGBE_PBRXECC 0x03300 812#define IXGBE_GHECCR 0x110B0 813 814/* MAC Registers */ 815#define IXGBE_PCS1GCFIG 0x04200 816#define IXGBE_PCS1GLCTL 0x04208 817#define IXGBE_PCS1GLSTA 0x0420C 818#define IXGBE_PCS1GDBG0 0x04210 819#define IXGBE_PCS1GDBG1 0x04214 820#define IXGBE_PCS1GANA 0x04218 821#define IXGBE_PCS1GANLP 0x0421C 822#define IXGBE_PCS1GANNP 0x04220 823#define IXGBE_PCS1GANLPNP 0x04224 824#define IXGBE_HLREG0 0x04240 825#define IXGBE_HLREG1 0x04244 826#define IXGBE_PAP 0x04248 827#define IXGBE_MACA 0x0424C 828#define IXGBE_APAE 0x04250 829#define IXGBE_ARD 0x04254 830#define IXGBE_AIS 0x04258 831#define IXGBE_MSCA 0x0425C 832#define IXGBE_MSRWD 0x04260 833#define IXGBE_MLADD 0x04264 834#define IXGBE_MHADD 0x04268 835#define IXGBE_MAXFRS 0x04268 836#define IXGBE_TREG 0x0426C 837#define IXGBE_PCSS1 0x04288 838#define IXGBE_PCSS2 0x0428C 839#define IXGBE_XPCSS 0x04290 840#define IXGBE_MFLCN 0x04294 841#define IXGBE_SERDESC 0x04298 842#define IXGBE_MACS 0x0429C 843#define IXGBE_AUTOC 0x042A0 844#define IXGBE_LINKS 0x042A4 845#define IXGBE_LINKS2 0x04324 846#define IXGBE_AUTOC2 0x042A8 847#define IXGBE_AUTOC3 0x042AC 848#define IXGBE_ANLP1 0x042B0 849#define IXGBE_ANLP2 0x042B4 850#define IXGBE_ATLASCTL 0x04800 851#define IXGBE_MMNGC 0x042D0 852#define IXGBE_ANLPNP1 0x042D4 853#define IXGBE_ANLPNP2 0x042D8 854#define IXGBE_KRPCSFC 0x042E0 855#define IXGBE_KRPCSS 0x042E4 856#define IXGBE_FECS1 0x042E8 857#define IXGBE_FECS2 0x042EC 858#define IXGBE_SMADARCTL 0x14F10 859#define IXGBE_MPVC 0x04318 860#define IXGBE_SGMIIC 0x04314 861 862/* Copper Pond 2 link timeout */ 863#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 864 865/* Omer CORECTL */ 866#define IXGBE_CORECTL 0x014F00 867/* BARCTRL */ 868#define IXGBE_BARCTRL 0x110F4 869#define IXGBE_BARCTRL_FLSIZE 0x0700 870#define IXGBE_BARCTRL_FLSIZE_SHIFT 8 871#define IXGBE_BARCTRL_CSRSIZE 0x2000 872 873/* RSCCTL Bit Masks */ 874#define IXGBE_RSCCTL_RSCEN 0x01 875#define IXGBE_RSCCTL_MAXDESC_1 0x00 876#define IXGBE_RSCCTL_MAXDESC_4 0x04 877#define IXGBE_RSCCTL_MAXDESC_8 0x08 878#define IXGBE_RSCCTL_MAXDESC_16 0x0C 879 880/* RSCDBU Bit Masks */ 881#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 882#define IXGBE_RSCDBU_RSCACKDIS 0x00000080 883 884/* RDRXCTL Bit Masks */ 885#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ 886#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 887#define IXGBE_RDRXCTL_MVMEN 0x00000020 888#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 889#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 890#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 891#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ 892 893/* RQTC Bit Masks and Shifts */ 894#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 895#define IXGBE_RQTC_TC0_MASK (0x7 << 0) 896#define IXGBE_RQTC_TC1_MASK (0x7 << 4) 897#define IXGBE_RQTC_TC2_MASK (0x7 << 8) 898#define IXGBE_RQTC_TC3_MASK (0x7 << 12) 899#define IXGBE_RQTC_TC4_MASK (0x7 << 16) 900#define IXGBE_RQTC_TC5_MASK (0x7 << 20) 901#define IXGBE_RQTC_TC6_MASK (0x7 << 24) 902#define IXGBE_RQTC_TC7_MASK (0x7 << 28) 903 904/* PSRTYPE.RQPL Bit masks and shift */ 905#define IXGBE_PSRTYPE_RQPL_MASK 0x7 906#define IXGBE_PSRTYPE_RQPL_SHIFT 29 907 908/* CTRL Bit Masks */ 909#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 910#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 911#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 912 913/* FACTPS */ 914#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 915 916/* MHADD Bit Masks */ 917#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 918#define IXGBE_MHADD_MFS_SHIFT 16 919 920/* Extended Device Control */ 921#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 922#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 923#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 924#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 925 926/* Direct Cache Access (DCA) definitions */ 927#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 928#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 929 930#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 931#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 932 933#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 934#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 935#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 936#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 937#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 938#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 939#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */ 940#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */ 941#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */ 942 943#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 944#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 945#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 946#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 947#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 948#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 949 950/* MSCA Bit Masks */ 951#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 952#define IXGBE_MSCA_NP_ADDR_SHIFT 0 953#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 954#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 955#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 956#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 957#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 958#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 959#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 960#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 961#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */ 962#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/ 963#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 964#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 965#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 966#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 967#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 968#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 969 970/* MSRWD bit masks */ 971#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 972#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 973#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 974#define IXGBE_MSRWD_READ_DATA_SHIFT 16 975 976/* Atlas registers */ 977#define IXGBE_ATLAS_PDN_LPBK 0x24 978#define IXGBE_ATLAS_PDN_10G 0xB 979#define IXGBE_ATLAS_PDN_1G 0xC 980#define IXGBE_ATLAS_PDN_AN 0xD 981 982/* Atlas bit masks */ 983#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 984#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 985#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 986#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 987#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 988 989/* Omer bit masks */ 990#define IXGBE_CORECTL_WRITE_CMD 0x00010000 991 992/* Device Type definitions for new protocol MDIO commands */ 993#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 994#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 995#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 996#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 997#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 998#define IXGBE_TWINAX_DEV 1 999 1000#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1001 1002#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ 1003#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1004#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1005#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 1006#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1007#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1008 1009#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 1010#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1011#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 1012#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 1013#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 1014#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 1015#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 1016#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 1017#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 1018#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ 1019#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 1020#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 1021#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 1022#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 1023 1024#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1025#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1026#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1027 1028/* MII clause 22/28 definitions */ 1029#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 1030 1031#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 1032#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1033#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1034#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 1035#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 1036#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1037#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1038#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 1039#define IXGBE_MII_RESTART 0x200 1040#define IXGBE_MII_AUTONEG_COMPLETE 0x20 1041#define IXGBE_MII_AUTONEG_LINK_UP 0x04 1042#define IXGBE_MII_AUTONEG_REG 0x0 1043 1044#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1045#define IXGBE_MAX_PHY_ADDR 32 1046 1047/* PHY IDs*/ 1048#define TN1010_PHY_ID 0x00A19410 1049#define TNX_FW_REV 0xB 1050#define AQ1002_PHY_ID 0x03A1B420 1051#define AQ_FW_REV 0x20 1052#define QT2022_PHY_ID 0x0043A400 1053#define ATH_PHY_ID 0x03429050 1054 1055/* PHY Types */ 1056#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 1057 1058/* Special PHY Init Routine */ 1059#define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1060#define IXGBE_PHY_INIT_END_NL 0xFFFF 1061#define IXGBE_CONTROL_MASK_NL 0xF000 1062#define IXGBE_DATA_MASK_NL 0x0FFF 1063#define IXGBE_CONTROL_SHIFT_NL 12 1064#define IXGBE_DELAY_NL 0 1065#define IXGBE_DATA_NL 1 1066#define IXGBE_CONTROL_NL 0x000F 1067#define IXGBE_CONTROL_EOL_NL 0x0FFF 1068#define IXGBE_CONTROL_SOL_NL 0x0000 1069 1070/* General purpose Interrupt Enable */ 1071#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1072#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1073#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1074#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1075#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1076#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1077#define IXGBE_GPIE_EIAME 0x40000000 1078#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1079#define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1080#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1081#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1082#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1083#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1084 1085/* Transmit Flow Control status */ 1086#define IXGBE_TFCS_TXOFF 0x00000001 1087#define IXGBE_TFCS_TXOFF0 0x00000100 1088#define IXGBE_TFCS_TXOFF1 0x00000200 1089#define IXGBE_TFCS_TXOFF2 0x00000400 1090#define IXGBE_TFCS_TXOFF3 0x00000800 1091#define IXGBE_TFCS_TXOFF4 0x00001000 1092#define IXGBE_TFCS_TXOFF5 0x00002000 1093#define IXGBE_TFCS_TXOFF6 0x00004000 1094#define IXGBE_TFCS_TXOFF7 0x00008000 1095 1096/* TCP Timer */ 1097#define IXGBE_TCPTIMER_KS 0x00000100 1098#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1099#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1100#define IXGBE_TCPTIMER_LOOP 0x00000800 1101#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1102 1103/* HLREG0 Bit Masks */ 1104#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1105#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1106#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1107#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1108#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1109#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1110#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1111#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1112#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1113#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1114#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1115#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1116#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1117#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1118#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1119 1120/* VMD_CTL bitmasks */ 1121#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1122#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1123 1124/* VT_CTL bitmasks */ 1125#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1126#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1127#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1128#define IXGBE_VT_CTL_POOL_SHIFT 7 1129#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1130 1131/* VMOLR bitmasks */ 1132#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1133#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1134#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1135#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1136#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1137 1138/* VFRE bitmask */ 1139#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1140 1141#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1142 1143/* RDHMPN and TDHMPN bitmasks */ 1144#define IXGBE_RDHMPN_RDICADDR 0x007FF800 1145#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1146#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1147#define IXGBE_TDHMPN_TDICADDR 0x003FF800 1148#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1149#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1150 1151#define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1152#define IXGBE_RDMAM_DWORD_SHIFT 9 1153#define IXGBE_RDMAM_DESC_COMP_FIFO 1 1154#define IXGBE_RDMAM_DFC_CMD_FIFO 2 1155#define IXGBE_RDMAM_RSC_HEADER_ADDR 3 1156#define IXGBE_RDMAM_TCN_STATUS_RAM 4 1157#define IXGBE_RDMAM_WB_COLL_FIFO 5 1158#define IXGBE_RDMAM_QSC_CNT_RAM 6 1159#define IXGBE_RDMAM_QSC_FCOE_RAM 7 1160#define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1161#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1162#define IXGBE_RDMAM_QSC_RSC_RAM 0xB 1163#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1164#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1165#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1166#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1167#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 1168#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 1169#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1170#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1171#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1172#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1173#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1174#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1175#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 1176#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 1177#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1178#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1179#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1180#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1181#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 1182#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 1183 1184#define IXGBE_TXDESCIC_READY 0x80000000 1185 1186/* Receive Checksum Control */ 1187#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1188#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1189 1190/* FCRTL Bit Masks */ 1191#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1192#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1193 1194/* PAP bit masks*/ 1195#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1196 1197/* RMCS Bit Masks */ 1198#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 1199/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1200#define IXGBE_RMCS_RAC 0x00000004 1201#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 1202#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1203#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1204#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1205 1206/* FCCFG Bit Masks */ 1207#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1208#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1209 1210/* Interrupt register bitmasks */ 1211 1212/* Extended Interrupt Cause Read */ 1213#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1214#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1215#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1216#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1217#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1218#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1219#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1220#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1221#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1222#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1223#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1224#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1225#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1226#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1227#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1228#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1229 1230/* Extended Interrupt Cause Set */ 1231#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1232#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1233#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1234#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1235#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1236#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1237#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1238#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1239#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1240#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1241#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1242#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1243#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1244#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1245#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1246 1247/* Extended Interrupt Mask Set */ 1248#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1249#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1250#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1251#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1252#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1253#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1254#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1255#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1256#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1257#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1258#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1259#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1260#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1261#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1262#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1263 1264/* Extended Interrupt Mask Clear */ 1265#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1266#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1267#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1268#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1269#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1270#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1271#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1272#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1273#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1274#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1275#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1276#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1277#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1278#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1279#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1280 1281#define IXGBE_EIMS_ENABLE_MASK ( \ 1282 IXGBE_EIMS_RTX_QUEUE | \ 1283 IXGBE_EIMS_LSC | \ 1284 IXGBE_EIMS_TCP_TIMER | \ 1285 IXGBE_EIMS_OTHER) 1286 1287/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1288#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1289#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1290#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1291#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1292#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1293#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1294#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1295#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1296#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1297#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1298#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1299#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1300#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1301#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1302#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1303#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1304#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1305#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ 1306#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1307#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1308#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1309#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1310#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1311 1312#define IXGBE_MAX_FTQF_FILTERS 128 1313#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1314#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1315#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1316#define IXGBE_FTQF_PROTOCOL_SCTP 2 1317#define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1318#define IXGBE_FTQF_PRIORITY_SHIFT 2 1319#define IXGBE_FTQF_POOL_MASK 0x0000003F 1320#define IXGBE_FTQF_POOL_SHIFT 8 1321#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1322#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1323#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1324#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1325#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1326#define IXGBE_FTQF_DEST_PORT_MASK 0x17 1327#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1328#define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1329#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1330 1331/* Interrupt clear mask */ 1332#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1333 1334/* Interrupt Vector Allocation Registers */ 1335#define IXGBE_IVAR_REG_NUM 25 1336#define IXGBE_IVAR_REG_NUM_82599 64 1337#define IXGBE_IVAR_TXRX_ENTRY 96 1338#define IXGBE_IVAR_RX_ENTRY 64 1339#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1340#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1341#define IXGBE_IVAR_TX_ENTRY 32 1342 1343#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1344#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1345 1346#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1347 1348#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1349 1350/* ETYPE Queue Filter/Select Bit Masks */ 1351#define IXGBE_MAX_ETQF_FILTERS 8 1352#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 1353#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 1354#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1355#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1356#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 1357 1358#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1359#define IXGBE_ETQS_RX_QUEUE_SHIFT 16 1360#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 1361#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 1362 1363/* 1364 * ETQF filter list: one static filter per filter consumer. This is 1365 * to avoid filter collisions later. Add new filters 1366 * here!! 1367 * 1368 * Current filters: 1369 * EAPOL 802.1x (0x888e): Filter 0 1370 * FCoE (0x8906): Filter 2 1371 * 1588 (0x88f7): Filter 3 1372 */ 1373#define IXGBE_ETQF_FILTER_EAPOL 0 1374#define IXGBE_ETQF_FILTER_FCOE 2 1375#define IXGBE_ETQF_FILTER_1588 3 1376/* VLAN Control Bit Masks */ 1377#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1378#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1379#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 1380#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1381#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1382 1383/* VLAN pool filtering masks */ 1384#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 1385#define IXGBE_VLVF_ENTRIES 64 1386#define IXGBE_VLVF_VLANID_MASK 0x00000FFF 1387 1388#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1389 1390/* STATUS Bit Masks */ 1391#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1392#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 1393#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 1394 1395#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1396#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1397 1398/* ESDP Bit Masks */ 1399#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 1400#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 1401#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 1402#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 1403#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 1404#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 1405#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 1406#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 1407#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 1408 1409/* LEDCTL Bit Masks */ 1410#define IXGBE_LED_IVRT_BASE 0x00000040 1411#define IXGBE_LED_BLINK_BASE 0x00000080 1412#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 1413#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 1414#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 1415#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 1416#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 1417#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 1418 1419/* LED modes */ 1420#define IXGBE_LED_LINK_UP 0x0 1421#define IXGBE_LED_LINK_10G 0x1 1422#define IXGBE_LED_MAC 0x2 1423#define IXGBE_LED_FILTER 0x3 1424#define IXGBE_LED_LINK_ACTIVE 0x4 1425#define IXGBE_LED_LINK_1G 0x5 1426#define IXGBE_LED_ON 0xE 1427#define IXGBE_LED_OFF 0xF 1428 1429/* AUTOC Bit Masks */ 1430#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 1431#define IXGBE_AUTOC_KX4_SUPP 0x80000000 1432#define IXGBE_AUTOC_KX_SUPP 0x40000000 1433#define IXGBE_AUTOC_PAUSE 0x30000000 1434#define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1435#define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1436#define IXGBE_AUTOC_RF 0x08000000 1437#define IXGBE_AUTOC_PD_TMR 0x06000000 1438#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1439#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1440#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1441#define IXGBE_AUTOC_FECA 0x00040000 1442#define IXGBE_AUTOC_FECR 0x00020000 1443#define IXGBE_AUTOC_KR_SUPP 0x00010000 1444#define IXGBE_AUTOC_AN_RESTART 0x00001000 1445#define IXGBE_AUTOC_FLU 0x00000001 1446#define IXGBE_AUTOC_LMS_SHIFT 13 1447#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 1448#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1449#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 1450#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1451#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1452#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1453#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1454#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1455#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 1456#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1457#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1458#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1459 1460#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 1461#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1462#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1463#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1464#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1465#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1466#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1467#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1468#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1469#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1470#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1471 1472#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1473#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1474#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1475#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1476#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1477#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1478 1479/* LINKS Bit Masks */ 1480#define IXGBE_LINKS_KX_AN_COMP 0x80000000 1481#define IXGBE_LINKS_UP 0x40000000 1482#define IXGBE_LINKS_SPEED 0x20000000 1483#define IXGBE_LINKS_MODE 0x18000000 1484#define IXGBE_LINKS_RX_MODE 0x06000000 1485#define IXGBE_LINKS_TX_MODE 0x01800000 1486#define IXGBE_LINKS_XGXS_EN 0x00400000 1487#define IXGBE_LINKS_SGMII_EN 0x02000000 1488#define IXGBE_LINKS_PCS_1G_EN 0x00200000 1489#define IXGBE_LINKS_1G_AN_EN 0x00100000 1490#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1491#define IXGBE_LINKS_1G_SYNC 0x00040000 1492#define IXGBE_LINKS_10G_ALIGN 0x00020000 1493#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 1494#define IXGBE_LINKS_TL_FAULT 0x00001000 1495#define IXGBE_LINKS_SIGNAL 0x00000F00 1496 1497#define IXGBE_LINKS_SPEED_82599 0x30000000 1498#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 1499#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 1500#define IXGBE_LINKS_SPEED_100_82599 0x10000000 1501#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1502#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1503 1504#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1505 1506/* PCS1GLSTA Bit Masks */ 1507#define IXGBE_PCS1GLSTA_LINK_OK 1 1508#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 1509#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 1510#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 1511#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 1512#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 1513#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 1514 1515#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 1516#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 1517 1518/* PCS1GLCTL Bit Masks */ 1519#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 1520#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 1521#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 1522#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1523#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1524#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1525 1526/* ANLP1 Bit Masks */ 1527#define IXGBE_ANLP1_PAUSE 0x0C00 1528#define IXGBE_ANLP1_SYM_PAUSE 0x0400 1529#define IXGBE_ANLP1_ASM_PAUSE 0x0800 1530 1531/* SW Semaphore Register bitmasks */ 1532#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1533#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1534#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1535#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 1536 1537/* SW_FW_SYNC/GSSR definitions */ 1538#define IXGBE_GSSR_EEP_SM 0x0001 1539#define IXGBE_GSSR_PHY0_SM 0x0002 1540#define IXGBE_GSSR_PHY1_SM 0x0004 1541#define IXGBE_GSSR_MAC_CSR_SM 0x0008 1542#define IXGBE_GSSR_FLASH_SM 0x0010 1543 1544/* EEC Register */ 1545#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 1546#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 1547#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 1548#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 1549#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 1550#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1551#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 1552#define IXGBE_EEC_FWE_SHIFT 4 1553#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 1554#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 1555#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 1556#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 1557#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 1558#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 1559/* EEPROM Addressing bits based on type (0-small, 1-large) */ 1560#define IXGBE_EEC_ADDR_SIZE 0x00000400 1561#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 1562 1563#define IXGBE_EEC_SIZE_SHIFT 11 1564#define IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT 6 1565#define IXGBE_EEPROM_OPCODE_BITS 8 1566 1567/* Checksum and EEPROM pointers */ 1568#define IXGBE_EEPROM_CHECKSUM 0x3F 1569#define IXGBE_EEPROM_SUM 0xBABA 1570#define IXGBE_PCIE_ANALOG_PTR 0x03 1571#define IXGBE_ATLAS0_CONFIG_PTR 0x04 1572#define IXGBE_PHY_PTR 0x04 1573#define IXGBE_ATLAS1_CONFIG_PTR 0x05 1574#define IXGBE_OPTION_ROM_PTR 0x05 1575#define IXGBE_PCIE_GENERAL_PTR 0x06 1576#define IXGBE_PCIE_CONFIG0_PTR 0x07 1577#define IXGBE_PCIE_CONFIG1_PTR 0x08 1578#define IXGBE_CORE0_PTR 0x09 1579#define IXGBE_CORE1_PTR 0x0A 1580#define IXGBE_MAC0_PTR 0x0B 1581#define IXGBE_MAC1_PTR 0x0C 1582#define IXGBE_CSR0_CONFIG_PTR 0x0D 1583#define IXGBE_CSR1_CONFIG_PTR 0x0E 1584#define IXGBE_FW_PTR 0x0F 1585#define IXGBE_PBANUM0_PTR 0x15 1586#define IXGBE_PBANUM1_PTR 0x16 1587#define IXGBE_SAN_MAC_ADDR_PTR 0x28 1588#define IXGBE_DEVICE_CAPS 0x2C 1589#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 1590#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 1591#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1592 1593/* MSI-X capability fields masks */ 1594#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 1595 1596/* Legacy EEPROM word offsets */ 1597#define IXGBE_ISCSI_BOOT_CAPS 0x0033 1598#define IXGBE_ISCSI_SETUP_PORT_0 0x0030 1599#define IXGBE_ISCSI_SETUP_PORT_1 0x0034 1600 1601/* EEPROM Commands - SPI */ 1602#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 1603#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 1604#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 1605#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 1606#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 1607#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 1608/* EEPROM reset Write Enable latch */ 1609#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 1610#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 1611#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 1612#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 1613#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 1614#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1615 1616/* EEPROM Read Register */ 1617#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 1618#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 1619#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 1620#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1621#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1622#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1623 1624#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 1625 1626#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 1627#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1628#endif 1629 1630/* Number of 5 microseconds we wait for EERD read and 1631 * EERW write to complete */ 1632#define IXGBE_EERD_EEWR_ATTEMPTS 100000 1633 1634/* # attempts we wait for flush update to complete */ 1635#define IXGBE_FLUDONE_ATTEMPTS 20000 1636 1637#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 1638#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 1639#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 1640#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 1641 1642#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1643#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 1644#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 1645#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 1646#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 1647#define IXGBE_FW_PATCH_VERSION_4 0x7 1648#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 1649#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */ 1650#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */ 1651#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */ 1652#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */ 1653#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */ 1654#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */ 1655#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ 1656 1657/* PCI Bus Info */ 1658#define IXGBE_PCI_LINK_STATUS 0xB2 1659#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 1660#define IXGBE_PCI_LINK_WIDTH 0x3F0 1661#define IXGBE_PCI_LINK_WIDTH_1 0x10 1662#define IXGBE_PCI_LINK_WIDTH_2 0x20 1663#define IXGBE_PCI_LINK_WIDTH_4 0x40 1664#define IXGBE_PCI_LINK_WIDTH_8 0x80 1665#define IXGBE_PCI_LINK_SPEED 0xF 1666#define IXGBE_PCI_LINK_SPEED_2500 0x1 1667#define IXGBE_PCI_LINK_SPEED_5000 0x2 1668#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 1669#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 1670#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 1671 1672/* Number of 100 microseconds we wait for PCI Express master disable */ 1673#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1674 1675/* Check whether address is multicast. This is little-endian specific check.*/ 1676#define IXGBE_IS_MULTICAST(Address) \ 1677 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 1678 1679/* Check whether an address is broadcast. */ 1680#define IXGBE_IS_BROADCAST(Address) \ 1681 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 1682 (((u8 *)(Address))[1] == ((u8)0xff))) 1683 1684/* RAH */ 1685#define IXGBE_RAH_VIND_MASK 0x003C0000 1686#define IXGBE_RAH_VIND_SHIFT 18 1687#define IXGBE_RAH_AV 0x80000000 1688#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 1689 1690/* Header split receive */ 1691#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 1692#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 1693#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 1694#define IXGBE_RFCTL_NFSW_DIS 0x00000040 1695#define IXGBE_RFCTL_NFSR_DIS 0x00000080 1696#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 1697#define IXGBE_RFCTL_NFS_VER_SHIFT 8 1698#define IXGBE_RFCTL_NFS_VER_2 0 1699#define IXGBE_RFCTL_NFS_VER_3 1 1700#define IXGBE_RFCTL_NFS_VER_4 2 1701#define IXGBE_RFCTL_IPV6_DIS 0x00000400 1702#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 1703#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 1704#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 1705#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1706 1707/* Transmit Config masks */ 1708#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 1709#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 1710#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 1711/* Enable short packet padding to 64 bytes */ 1712#define IXGBE_TX_PAD_ENABLE 0x00000400 1713#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 1714/* This allows for 16K packets + 4k for vlan */ 1715#define IXGBE_MAX_FRAME_SZ 0x40040000 1716 1717#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 1718#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 1719 1720/* Receive Config masks */ 1721#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 1722#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 1723#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 1724#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 1725 1726#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 1727#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 1728#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 1729#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 1730#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 1731#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 1732/* Receive Priority Flow Control Enable */ 1733#define IXGBE_FCTRL_RPFCE 0x00004000 1734#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 1735#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 1736#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 1737#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 1738#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 1739 1740/* Multiple Receive Queue Control */ 1741#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 1742#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 1743#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 1744#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 1745#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 1746#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 1747#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 1748#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 1749#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 1750#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 1751#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 1752#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 1753#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 1754#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 1755#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 1756#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 1757#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 1758#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 1759#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 1760#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 1761#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 1762#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 1763 1764/* Queue Drop Enable */ 1765#define IXGBE_QDE_ENABLE 0x00000001 1766#define IXGBE_QDE_IDX_MASK 0x00007F00 1767#define IXGBE_QDE_IDX_SHIFT 8 1768 1769#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 1770#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 1771#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 1772#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 1773#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 1774#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 1775#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 1776#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 1777#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 1778 1779#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 1780#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 1781#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 1782#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 1783#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 1784/* Multiple Transmit Queue Command Register */ 1785#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 1786#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 1787#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 1788#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 1789#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 1790#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 1791 1792/* Receive Descriptor bit definitions */ 1793#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 1794#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 1795#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 1796#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 1797#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 1798#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 1799#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 1800#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 1801#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 1802#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 1803#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 1804#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 1805#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 1806#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 1807#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 1808#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 1809#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 1810#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 1811#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 1812#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 1813#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 1814#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 1815#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 1816#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 1817#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 1818#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 1819#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 1820#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 1821#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ 1822#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 1823#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 1824#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 1825#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 1826#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 1827#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 1828#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 1829#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 1830#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 1831#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 1832#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 1833#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 1834#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 1835#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 1836#define IXGBE_RXD_PRI_SHIFT 13 1837#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 1838#define IXGBE_RXD_CFI_SHIFT 12 1839 1840#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 1841#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 1842#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 1843#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 1844#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 1845#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 1846#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 1847#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 1848#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 1849#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 1850#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 1851 1852/* PSRTYPE bit definitions */ 1853#define IXGBE_PSRTYPE_TCPHDR 0x00000010 1854#define IXGBE_PSRTYPE_UDPHDR 0x00000020 1855#define IXGBE_PSRTYPE_IPV4HDR 0x00000100 1856#define IXGBE_PSRTYPE_IPV6HDR 0x00000200 1857#define IXGBE_PSRTYPE_L2HDR 0x00001000 1858 1859/* SRRCTL bit definitions */ 1860#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 1861#define IXGBE_SRRCTL_RDMTS_SHIFT 22 1862#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 1863#define IXGBE_SRRCTL_DROP_EN 0x10000000 1864#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 1865#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 1866#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 1867#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 1868#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 1869#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 1870#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 1871#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 1872 1873#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 1874#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 1875 1876#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 1877#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 1878#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 1879#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 1880#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 1881#define IXGBE_RXDADV_RSCCNT_SHIFT 17 1882#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 1883#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 1884#define IXGBE_RXDADV_SPH 0x8000 1885 1886/* RSS Hash results */ 1887#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 1888#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 1889#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 1890#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 1891#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 1892#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 1893#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 1894#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 1895#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 1896#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 1897 1898/* RSS Packet Types as indicated in the receive descriptor. */ 1899#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 1900#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 1901#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 1902#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 1903#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 1904#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 1905#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 1906#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 1907#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 1908#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 1909#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 1910#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 1911#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 1912#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 1913#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 1914 1915/* Security Processing bit Indication */ 1916#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 1917#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 1918#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 1919#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 1920#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 1921 1922/* Masks to determine if packets should be dropped due to frame errors */ 1923#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 1924 IXGBE_RXD_ERR_CE | \ 1925 IXGBE_RXD_ERR_LE | \ 1926 IXGBE_RXD_ERR_PE | \ 1927 IXGBE_RXD_ERR_OSE | \ 1928 IXGBE_RXD_ERR_USE) 1929 1930#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 1931 IXGBE_RXDADV_ERR_CE | \ 1932 IXGBE_RXDADV_ERR_LE | \ 1933 IXGBE_RXDADV_ERR_PE | \ 1934 IXGBE_RXDADV_ERR_OSE | \ 1935 IXGBE_RXDADV_ERR_USE) 1936 1937/* Multicast bit mask */ 1938#define IXGBE_MCSTCTRL_MFE 0x4 1939 1940/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 1941#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 1942#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 1943#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 1944 1945/* Vlan-specific macros */ 1946#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 1947#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 1948#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 1949#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 1950 1951/* SR-IOV specific macros */ 1952#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 1953#define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4)) 1954#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) 1955#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4)) 1956 1957/* Little Endian defines */ 1958#ifndef __le16 1959#define __le16 u16 1960#endif 1961#ifndef __le32 1962#define __le32 u32 1963#endif 1964#ifndef __le64 1965#define __le64 u64 1966 1967#endif 1968#ifndef __be16 1969/* Big Endian defines */ 1970#define __be16 u16 1971#define __be32 u32 1972#define __be64 u64 1973 1974#endif 1975enum ixgbe_fdir_pballoc_type { 1976 IXGBE_FDIR_PBALLOC_64K = 0, 1977 IXGBE_FDIR_PBALLOC_128K, 1978 IXGBE_FDIR_PBALLOC_256K, 1979}; 1980#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 1981 1982/* Flow Director register values */ 1983#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 1984#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 1985#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 1986#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 1987#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 1988#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 1989#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 1990#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 1991#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 1992#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 1993#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 1994#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 1995#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 1996 1997#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 1998#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 1999#define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2000#define IXGBE_FDIRM_VLANID 0x00000001 2001#define IXGBE_FDIRM_VLANP 0x00000002 2002#define IXGBE_FDIRM_POOL 0x00000004 2003#define IXGBE_FDIRM_L3P 0x00000008 2004#define IXGBE_FDIRM_L4P 0x00000010 2005#define IXGBE_FDIRM_FLEX 0x00000020 2006#define IXGBE_FDIRM_DIPv6 0x00000040 2007 2008#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2009#define IXGBE_FDIRFREE_FREE_SHIFT 0 2010#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2011#define IXGBE_FDIRFREE_COLL_SHIFT 16 2012#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2013#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2014#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2015#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2016#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2017#define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2018#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2019#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2020#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2021#define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2022#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2023#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2024#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2025#define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2026#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2027#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2028 2029#define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2030#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2031#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2032#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2033#define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007 2034#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2035#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2036#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2037#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2038#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2039#define IXGBE_FDIRCMD_IPV6 0x00000080 2040#define IXGBE_FDIRCMD_CLEARHT 0x00000100 2041#define IXGBE_FDIRCMD_DROP 0x00000200 2042#define IXGBE_FDIRCMD_INT 0x00000400 2043#define IXGBE_FDIRCMD_LAST 0x00000800 2044#define IXGBE_FDIRCMD_COLLISION 0x00001000 2045#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2046#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 2047#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2048#define IXGBE_FDIR_INIT_DONE_POLL 10 2049#define IXGBE_FDIRCMD_CMD_POLL 10 2050 2051/* Transmit Descriptor - Legacy */ 2052struct ixgbe_legacy_tx_desc { 2053 u64 buffer_addr; /* Address of the descriptor's data buffer */ 2054 union { 2055 __le32 data; 2056 struct { 2057 __le16 length; /* Data buffer length */ 2058 u8 cso; /* Checksum offset */ 2059 u8 cmd; /* Descriptor control */ 2060 } flags; 2061 } lower; 2062 union { 2063 __le32 data; 2064 struct { 2065 u8 status; /* Descriptor status */ 2066 u8 css; /* Checksum start */ 2067 __le16 vlan; 2068 } fields; 2069 } upper; 2070}; 2071 2072/* Transmit Descriptor - Advanced */ 2073union ixgbe_adv_tx_desc { 2074 struct { 2075 __le64 buffer_addr; /* Address of descriptor's data buf */ 2076 __le32 cmd_type_len; 2077 __le32 olinfo_status; 2078 } read; 2079 struct { 2080 __le64 rsvd; /* Reserved */ 2081 __le32 nxtseq_seed; 2082 __le32 status; 2083 } wb; 2084}; 2085 2086/* Receive Descriptor - Legacy */ 2087struct ixgbe_legacy_rx_desc { 2088 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 2089 __le16 length; /* Length of data DMAed into data buffer */ 2090 __le16 csum; /* Packet checksum */ 2091 u8 status; /* Descriptor status */ 2092 u8 errors; /* Descriptor Errors */ 2093 __le16 vlan; 2094}; 2095 2096/* Receive Descriptor - Advanced */ 2097union ixgbe_adv_rx_desc { 2098 struct { 2099 __le64 pkt_addr; /* Packet buffer address */ 2100 __le64 hdr_addr; /* Header buffer address */ 2101 } read; 2102 struct { 2103 struct { 2104 union { 2105 __le32 data; 2106 struct { 2107 __le16 pkt_info; /* RSS, Pkt type */ 2108 __le16 hdr_info; /* Splithdr, hdrlen */ 2109 } hs_rss; 2110 } lo_dword; 2111 union { 2112 __le32 rss; /* RSS Hash */ 2113 struct { 2114 __le16 ip_id; /* IP id */ 2115 __le16 csum; /* Packet Checksum */ 2116 } csum_ip; 2117 } hi_dword; 2118 } lower; 2119 struct { 2120 __le32 status_error; /* ext status/error */ 2121 __le16 length; /* Packet length */ 2122 __le16 vlan; /* VLAN tag */ 2123 } upper; 2124 } wb; /* writeback */ 2125}; 2126 2127/* Context descriptors */ 2128struct ixgbe_adv_tx_context_desc { 2129 __le32 vlan_macip_lens; 2130 __le32 seqnum_seed; 2131 __le32 type_tucmd_mlhl; 2132 __le32 mss_l4len_idx; 2133}; 2134 2135/* Adv Transmit Descriptor Config Masks */ 2136#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 2137#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 2138#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 2139#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 2140#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 2141#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 2142#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 2143#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 2144#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 2145#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 2146#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 2147#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 2148#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 2149#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2150#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 2151#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 2152#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 2153#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 2154#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 2155#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 2156#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 2157 IXGBE_ADVTXD_POPTS_SHIFT) 2158#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 2159 IXGBE_ADVTXD_POPTS_SHIFT) 2160#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 2161#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 2162#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 2163#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ 2164#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 2165#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2166#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2167#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2168#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2169#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2170#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2171#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2172#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 2173#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ 2174#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 2175#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2176#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2177#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2178#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 2179#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 2180#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 2181#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */ 2182#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */ 2183#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 2184#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 2185#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 2186#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 2187#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2188#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2189 2190/* Autonegotiation advertised speeds */ 2191typedef u32 ixgbe_autoneg_advertised; 2192/* Link speed */ 2193typedef u32 ixgbe_link_speed; 2194#define IXGBE_LINK_SPEED_UNKNOWN 0 2195#define IXGBE_LINK_SPEED_100_FULL 0x0008 2196#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 2197#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 2198#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 2199 IXGBE_LINK_SPEED_10GB_FULL) 2200#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 2201 IXGBE_LINK_SPEED_1GB_FULL | \ 2202 IXGBE_LINK_SPEED_10GB_FULL) 2203 2204 2205/* Physical layer type */ 2206typedef u32 ixgbe_physical_layer; 2207#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 2208#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 2209#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 2210#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 2211#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 2212#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 2213#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 2214#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 2215#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 2216#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 2217#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 2218#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 2219#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 2220#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 2221 2222/* Software ATR hash keys */ 2223#define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D 2224#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17 2225 2226/* Software ATR input stream offsets and masks */ 2227#define IXGBE_ATR_VLAN_OFFSET 0 2228#define IXGBE_ATR_SRC_IPV6_OFFSET 2 2229#define IXGBE_ATR_SRC_IPV4_OFFSET 14 2230#define IXGBE_ATR_DST_IPV6_OFFSET 18 2231#define IXGBE_ATR_DST_IPV4_OFFSET 30 2232#define IXGBE_ATR_SRC_PORT_OFFSET 34 2233#define IXGBE_ATR_DST_PORT_OFFSET 36 2234#define IXGBE_ATR_FLEX_BYTE_OFFSET 38 2235#define IXGBE_ATR_VM_POOL_OFFSET 40 2236#define IXGBE_ATR_L4TYPE_OFFSET 41 2237 2238#define IXGBE_ATR_L4TYPE_MASK 0x3 2239#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 2240#define IXGBE_ATR_L4TYPE_UDP 0x1 2241#define IXGBE_ATR_L4TYPE_TCP 0x2 2242#define IXGBE_ATR_L4TYPE_SCTP 0x3 2243#define IXGBE_ATR_HASH_MASK 0x7fff 2244 2245/* Flow Director ATR input struct. */ 2246struct ixgbe_atr_input { 2247 /* Byte layout in order, all values with MSB first: 2248 * 2249 * vlan_id - 2 bytes 2250 * src_ip - 16 bytes 2251 * dst_ip - 16 bytes 2252 * src_port - 2 bytes 2253 * dst_port - 2 bytes 2254 * flex_bytes - 2 bytes 2255 * vm_pool - 1 byte 2256 * l4type - 1 byte 2257 */ 2258 u8 byte_stream[42]; 2259}; 2260 2261enum ixgbe_eeprom_type { 2262 ixgbe_eeprom_uninitialized = 0, 2263 ixgbe_eeprom_spi, 2264 ixgbe_flash, 2265 ixgbe_eeprom_none /* No NVM support */ 2266}; 2267 2268enum ixgbe_mac_type { 2269 ixgbe_mac_unknown = 0, 2270 ixgbe_mac_82598EB, 2271 ixgbe_mac_82599EB, 2272 ixgbe_num_macs 2273}; 2274 2275enum ixgbe_phy_type { 2276 ixgbe_phy_unknown = 0, 2277 ixgbe_phy_none, 2278 ixgbe_phy_tn, 2279 ixgbe_phy_aq, 2280 ixgbe_phy_cu_unknown, 2281 ixgbe_phy_qt, 2282 ixgbe_phy_xaui, 2283 ixgbe_phy_nl, 2284 ixgbe_phy_tw_tyco, 2285 ixgbe_phy_tw_unknown, 2286 ixgbe_phy_sfp_avago, 2287 ixgbe_phy_sfp_ftl, 2288 ixgbe_phy_sfp_unknown, 2289 ixgbe_phy_sfp_intel, 2290 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ 2291 ixgbe_phy_generic 2292}; 2293 2294/* 2295 * SFP+ module type IDs: 2296 * 2297 * ID Module Type 2298 * ============= 2299 * 0 SFP_DA_CU 2300 * 1 SFP_SR 2301 * 2 SFP_LR 2302 * 3 SFP_DA_CU_CORE0 - 82599-specific 2303 * 4 SFP_DA_CU_CORE1 - 82599-specific 2304 * 5 SFP_SR/LR_CORE0 - 82599-specific 2305 * 6 SFP_SR/LR_CORE1 - 82599-specific 2306 */ 2307enum ixgbe_sfp_type { 2308 ixgbe_sfp_type_da_cu = 0, 2309 ixgbe_sfp_type_sr = 1, 2310 ixgbe_sfp_type_lr = 2, 2311 ixgbe_sfp_type_da_cu_core0 = 3, 2312 ixgbe_sfp_type_da_cu_core1 = 4, 2313 ixgbe_sfp_type_srlr_core0 = 5, 2314 ixgbe_sfp_type_srlr_core1 = 6, 2315 ixgbe_sfp_type_not_present = 0xFFFE, 2316 ixgbe_sfp_type_unknown = 0xFFFF 2317}; 2318 2319enum ixgbe_media_type { 2320 ixgbe_media_type_unknown = 0, 2321 ixgbe_media_type_fiber, 2322 ixgbe_media_type_copper, 2323 ixgbe_media_type_backplane, 2324 ixgbe_media_type_cx4, 2325 ixgbe_media_type_virtual 2326}; 2327 2328/* Flow Control Settings */ 2329enum ixgbe_fc_mode { 2330 ixgbe_fc_none = 0, 2331 ixgbe_fc_rx_pause, 2332 ixgbe_fc_tx_pause, 2333 ixgbe_fc_full, 2334 ixgbe_fc_default 2335}; 2336 2337/* Smart Speed Settings */ 2338#define IXGBE_SMARTSPEED_MAX_RETRIES 3 2339enum ixgbe_smart_speed { 2340 ixgbe_smart_speed_auto = 0, 2341 ixgbe_smart_speed_on, 2342 ixgbe_smart_speed_off 2343}; 2344 2345/* PCI bus types */ 2346enum ixgbe_bus_type { 2347 ixgbe_bus_type_unknown = 0, 2348 ixgbe_bus_type_pci, 2349 ixgbe_bus_type_pcix, 2350 ixgbe_bus_type_pci_express, 2351 ixgbe_bus_type_reserved 2352}; 2353 2354/* PCI bus speeds */ 2355enum ixgbe_bus_speed { 2356 ixgbe_bus_speed_unknown = 0, 2357 ixgbe_bus_speed_33, 2358 ixgbe_bus_speed_66, 2359 ixgbe_bus_speed_100, 2360 ixgbe_bus_speed_120, 2361 ixgbe_bus_speed_133, 2362 ixgbe_bus_speed_2500, 2363 ixgbe_bus_speed_5000, 2364 ixgbe_bus_speed_reserved 2365}; 2366 2367/* PCI bus widths */ 2368enum ixgbe_bus_width { 2369 ixgbe_bus_width_unknown = 0, 2370 ixgbe_bus_width_pcie_x1, 2371 ixgbe_bus_width_pcie_x2, 2372 ixgbe_bus_width_pcie_x4 = 4, 2373 ixgbe_bus_width_pcie_x8 = 8, 2374 ixgbe_bus_width_32, 2375 ixgbe_bus_width_64, 2376 ixgbe_bus_width_reserved 2377}; 2378 2379struct ixgbe_addr_filter_info { 2380 u32 num_mc_addrs; 2381 u32 rar_used_count; 2382 u32 mta_in_use; 2383 u32 overflow_promisc; 2384 bool user_set_promisc; 2385}; 2386 2387/* Bus parameters */ 2388struct ixgbe_bus_info { 2389 enum ixgbe_bus_speed speed; 2390 enum ixgbe_bus_width width; 2391 enum ixgbe_bus_type type; 2392 2393 u16 func; 2394 u16 lan_id; 2395}; 2396 2397/* Flow control parameters */ 2398struct ixgbe_fc_info { 2399 u32 high_water; /* Flow Control High-water */ 2400 u32 low_water; /* Flow Control Low-water */ 2401 u16 pause_time; /* Flow Control Pause timer */ 2402 bool send_xon; /* Flow control send XON */ 2403 bool strict_ieee; /* Strict IEEE mode */ 2404 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 2405 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 2406 enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 2407 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 2408}; 2409 2410/* Statistics counters collected by the MAC */ 2411struct ixgbe_hw_stats { 2412 u64 crcerrs; 2413 u64 illerrc; 2414 u64 errbc; 2415 u64 mspdc; 2416 u64 mpctotal; 2417 u64 mpc[8]; 2418 u64 mlfc; 2419 u64 mrfc; 2420 u64 rlec; 2421 u64 lxontxc; 2422 u64 lxonrxc; 2423 u64 lxofftxc; 2424 u64 lxoffrxc; 2425 u64 pxontxc[8]; 2426 u64 pxonrxc[8]; 2427 u64 pxofftxc[8]; 2428 u64 pxoffrxc[8]; 2429 u64 prc64; 2430 u64 prc127; 2431 u64 prc255; 2432 u64 prc511; 2433 u64 prc1023; 2434 u64 prc1522; 2435 u64 gprc; 2436 u64 bprc; 2437 u64 mprc; 2438 u64 gptc; 2439 u64 gorc; 2440 u64 gotc; 2441 u64 rnbc[8]; 2442 u64 ruc; 2443 u64 rfc; 2444 u64 roc; 2445 u64 rjc; 2446 u64 mngprc; 2447 u64 mngpdc; 2448 u64 mngptc; 2449 u64 tor; 2450 u64 tpr; 2451 u64 tpt; 2452 u64 ptc64; 2453 u64 ptc127; 2454 u64 ptc255; 2455 u64 ptc511; 2456 u64 ptc1023; 2457 u64 ptc1522; 2458 u64 mptc; 2459 u64 bptc; 2460 u64 xec; 2461 u64 rqsmr[16]; 2462 u64 tqsmr[8]; 2463 u64 qprc[16]; 2464 u64 qptc[16]; 2465 u64 qbrc[16]; 2466 u64 qbtc[16]; 2467 u64 qprdc[16]; 2468 u64 pxon2offc[8]; 2469 u64 fdirustat_add; 2470 u64 fdirustat_remove; 2471 u64 fdirfstat_fadd; 2472 u64 fdirfstat_fremove; 2473 u64 fdirmatch; 2474 u64 fdirmiss; 2475 u64 fccrc; 2476 u64 fclast; 2477 u64 fcoerpdc; 2478 u64 fcoeprc; 2479 u64 fcoeptc; 2480 u64 fcoedwrc; 2481 u64 fcoedwtc; 2482}; 2483 2484/* forward declaration */ 2485struct ixgbe_hw; 2486 2487/* iterator type for walking multicast address lists */ 2488typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 2489 u32 *vmdq); 2490 2491/* Function pointer table */ 2492struct ixgbe_eeprom_operations { 2493 s32 (*init_params)(struct ixgbe_hw *); 2494 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 2495 s32 (*write)(struct ixgbe_hw *, u16, u16); 2496 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 2497 s32 (*update_checksum)(struct ixgbe_hw *); 2498 u16 (*calc_checksum)(struct ixgbe_hw *); 2499}; 2500 2501struct ixgbe_mac_operations { 2502 s32 (*init_hw)(struct ixgbe_hw *); 2503 s32 (*reset_hw)(struct ixgbe_hw *); 2504 s32 (*start_hw)(struct ixgbe_hw *); 2505 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 2506 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 2507 u32 (*get_supported_physical_layer)(struct ixgbe_hw *); 2508 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 2509 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 2510 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); 2511 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 2512 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 2513 s32 (*stop_adapter)(struct ixgbe_hw *); 2514 s32 (*get_bus_info)(struct ixgbe_hw *); 2515 void (*set_lan_id)(struct ixgbe_hw *); 2516 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 2517 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 2518 s32 (*setup_sfp)(struct ixgbe_hw *); 2519 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 2520 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16); 2521 void (*release_swfw_sync)(struct ixgbe_hw *, u16); 2522 2523 /* Link */ 2524 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool); 2525 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 2526 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 2527 bool *); 2528 2529 /* LED */ 2530 s32 (*led_on)(struct ixgbe_hw *, u32); 2531 s32 (*led_off)(struct ixgbe_hw *, u32); 2532 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 2533 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 2534 2535 /* RAR, Multicast, VLAN */ 2536 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 2537 s32 (*clear_rar)(struct ixgbe_hw *, u32); 2538 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); 2539 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 2540 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 2541 s32 (*init_rx_addrs)(struct ixgbe_hw *); 2542 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 2543 ixgbe_mc_addr_itr); 2544 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 2545 ixgbe_mc_addr_itr); 2546 s32 (*enable_mc)(struct ixgbe_hw *); 2547 s32 (*disable_mc)(struct ixgbe_hw *); 2548 s32 (*clear_vfta)(struct ixgbe_hw *); 2549 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 2550 s32 (*init_uta_tables)(struct ixgbe_hw *); 2551 2552 /* Flow Control */ 2553 s32 (*fc_enable)(struct ixgbe_hw *, s32); 2554}; 2555 2556struct ixgbe_phy_operations { 2557 s32 (*identify)(struct ixgbe_hw *); 2558 s32 (*identify_sfp)(struct ixgbe_hw *); 2559 s32 (*init)(struct ixgbe_hw *); 2560 s32 (*reset)(struct ixgbe_hw *); 2561 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 2562 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 2563 s32 (*setup_link)(struct ixgbe_hw *); 2564 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, 2565 bool); 2566 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 2567 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 2568 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 2569 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 2570 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 2571 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 2572 void (*i2c_bus_clear)(struct ixgbe_hw *); 2573}; 2574 2575struct ixgbe_eeprom_info { 2576 struct ixgbe_eeprom_operations ops; 2577 enum ixgbe_eeprom_type type; 2578 u32 semaphore_delay; 2579 u16 word_size; 2580 u16 address_bits; 2581}; 2582 2583struct ixgbe_mac_info { 2584 struct ixgbe_mac_operations ops; 2585 enum ixgbe_mac_type type; 2586 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 2587 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 2588 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 2589 /* prefix for World Wide Node Name (WWNN) */ 2590 u16 wwnn_prefix; 2591 /* prefix for World Wide Port Name (WWPN) */ 2592 u16 wwpn_prefix; 2593 s32 mc_filter_type; 2594 u32 mcft_size; 2595 u32 vft_size; 2596 u32 num_rar_entries; 2597 u32 rar_highwater; 2598 u32 max_tx_queues; 2599 u32 max_rx_queues; 2600 u32 max_msix_vectors; 2601 bool msix_vectors_from_pcie; 2602 u32 orig_autoc; 2603 u32 orig_autoc2; 2604 bool orig_link_settings_stored; 2605 bool autotry_restart; 2606}; 2607 2608struct ixgbe_phy_info { 2609 struct ixgbe_phy_operations ops; 2610 enum ixgbe_phy_type type; 2611 u32 addr; 2612 u32 id; 2613 enum ixgbe_sfp_type sfp_type; 2614 bool sfp_setup_needed; 2615 u32 revision; 2616 enum ixgbe_media_type media_type; 2617 bool reset_disable; 2618 ixgbe_autoneg_advertised autoneg_advertised; 2619 enum ixgbe_smart_speed smart_speed; 2620 bool smart_speed_active; 2621 bool multispeed_fiber; 2622}; 2623 2624struct ixgbe_hw { 2625 u8 *hw_addr; 2626 void *back; 2627 struct ixgbe_mac_info mac; 2628 struct ixgbe_addr_filter_info addr_ctrl; 2629 struct ixgbe_fc_info fc; 2630 struct ixgbe_phy_info phy; 2631 struct ixgbe_eeprom_info eeprom; 2632 struct ixgbe_bus_info bus; 2633 u16 device_id; 2634 u16 vendor_id; 2635 u16 subsystem_device_id; 2636 u16 subsystem_vendor_id; 2637 u8 revision_id; 2638 bool adapter_stopped; 2639}; 2640 2641#define ixgbe_call_func(hw, func, params, error) \ 2642 (func != NULL) ? func params : error 2643 2644 2645/* Error Codes */ 2646#define IXGBE_SUCCESS 0 2647#define IXGBE_ERR_EEPROM -1 2648#define IXGBE_ERR_EEPROM_CHECKSUM -2 2649#define IXGBE_ERR_PHY -3 2650#define IXGBE_ERR_CONFIG -4 2651#define IXGBE_ERR_PARAM -5 2652#define IXGBE_ERR_MAC_TYPE -6 2653#define IXGBE_ERR_UNKNOWN_PHY -7 2654#define IXGBE_ERR_LINK_SETUP -8 2655#define IXGBE_ERR_ADAPTER_STOPPED -9 2656#define IXGBE_ERR_INVALID_MAC_ADDR -10 2657#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 2658#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 2659#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 2660#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 2661#define IXGBE_ERR_RESET_FAILED -15 2662#define IXGBE_ERR_SWFW_SYNC -16 2663#define IXGBE_ERR_PHY_ADDR_INVALID -17 2664#define IXGBE_ERR_I2C -18 2665#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 2666#define IXGBE_ERR_SFP_NOT_PRESENT -20 2667#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 2668#define IXGBE_ERR_NO_SAN_ADDR_PTR -22 2669#define IXGBE_ERR_FDIR_REINIT_FAILED -23 2670#define IXGBE_ERR_EEPROM_VERSION -24 2671#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 2672 2673 2674#endif /* _IXGBE_TYPE_H_ */ 2675