ixgbe_type.h revision 181003
1210678Srpaulo/****************************************************************************** 2210678Srpaulo 3210678Srpaulo Copyright (c) 2001-2008, Intel Corporation 4210678Srpaulo All rights reserved. 5210678Srpaulo 6210678Srpaulo Redistribution and use in source and binary forms, with or without 7210678Srpaulo modification, are permitted provided that the following conditions are met: 8210678Srpaulo 9210678Srpaulo 1. Redistributions of source code must retain the above copyright notice, 10210678Srpaulo this list of conditions and the following disclaimer. 11210678Srpaulo 12210678Srpaulo 2. Redistributions in binary form must reproduce the above copyright 13210678Srpaulo notice, this list of conditions and the following disclaimer in the 14210678Srpaulo documentation and/or other materials provided with the distribution. 15210678Srpaulo 16210678Srpaulo 3. Neither the name of the Intel Corporation nor the names of its 17210678Srpaulo contributors may be used to endorse or promote products derived from 18210678Srpaulo this software without specific prior written permission. 19210678Srpaulo 20210678Srpaulo THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21210678Srpaulo AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22210678Srpaulo IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23210678Srpaulo ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24210678Srpaulo LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25210678Srpaulo CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26210678Srpaulo SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27210678Srpaulo INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28210678Srpaulo CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29210678Srpaulo ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30210678Srpaulo POSSIBILITY OF SUCH DAMAGE. 31210678Srpaulo 32210678Srpaulo******************************************************************************/ 33210678Srpaulo/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 181003 2008-07-30 18:15:18Z jfv $*/ 34210678Srpaulo 35210678Srpaulo#ifndef _IXGBE_TYPE_H_ 36210678Srpaulo#define _IXGBE_TYPE_H_ 37210678Srpaulo 38210678Srpaulo#include "ixgbe_osdep.h" 39210678Srpaulo 40210678Srpaulo/* Vendor ID */ 41210678Srpaulo#define IXGBE_INTEL_VENDOR_ID 0x8086 42210678Srpaulo 43210678Srpaulo/* Device IDs */ 44210678Srpaulo#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 45210678Srpaulo#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 46210678Srpaulo#define IXGBE_DEV_ID_82598AT 0x10C8 47210678Srpaulo#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10D7 48210678Srpaulo#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 49210678Srpaulo#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 50210678Srpaulo#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 51210678Srpaulo 52210678Srpaulo/* General Registers */ 53210678Srpaulo#define IXGBE_CTRL 0x00000 54269720Smarkj#define IXGBE_STATUS 0x00008 55269720Smarkj#define IXGBE_CTRL_EXT 0x00018 56269720Smarkj#define IXGBE_ESDP 0x00020 57210678Srpaulo#define IXGBE_EODSDP 0x00028 58210678Srpaulo#define IXGBE_LEDCTL 0x00200 59210678Srpaulo#define IXGBE_FRTIMER 0x00048 60210678Srpaulo#define IXGBE_TCPTIMER 0x0004C 61210678Srpaulo 62210678Srpaulo/* NVM Registers */ 63210678Srpaulo#define IXGBE_EEC 0x10010 64210678Srpaulo#define IXGBE_EERD 0x10014 65210678Srpaulo#define IXGBE_FLA 0x1001C 66210678Srpaulo#define IXGBE_EEMNGCTL 0x10110 67210678Srpaulo#define IXGBE_EEMNGDATA 0x10114 68210678Srpaulo#define IXGBE_FLMNGCTL 0x10118 69210678Srpaulo#define IXGBE_FLMNGDATA 0x1011C 70210678Srpaulo#define IXGBE_FLMNGCNT 0x10120 71210678Srpaulo#define IXGBE_FLOP 0x1013C 72210678Srpaulo#define IXGBE_GRC 0x10200 73210678Srpaulo 74210678Srpaulo/* Interrupt Registers */ 75210678Srpaulo#define IXGBE_EICR 0x00800 76210678Srpaulo#define IXGBE_EICS 0x00808 77210678Srpaulo#define IXGBE_EIMS 0x00880 78210678Srpaulo#define IXGBE_EIMC 0x00888 79210678Srpaulo#define IXGBE_EIAC 0x00810 80210678Srpaulo#define IXGBE_EIAM 0x00890 81210678Srpaulo#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4))) 82210678Srpaulo#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 83210678Srpaulo#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 84210678Srpaulo#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 85210678Srpaulo#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 86210678Srpaulo#define IXGBE_GPIE 0x00898 87210678Srpaulo 88210678Srpaulo/* Flow Control Registers */ 89210678Srpaulo#define IXGBE_PFCTOP 0x03008 90210678Srpaulo#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 91210678Srpaulo#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 92210678Srpaulo#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 93210678Srpaulo#define IXGBE_FCRTV 0x032A0 94210678Srpaulo#define IXGBE_TFCS 0x0CE00 95210678Srpaulo 96210678Srpaulo/* Receive DMA Registers */ 97210678Srpaulo#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40))) 98210678Srpaulo#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40))) 99210678Srpaulo#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40))) 100210678Srpaulo#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40))) 101210678Srpaulo#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40))) 102210678Srpaulo#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40))) 103210678Srpaulo/* 104210678Srpaulo * Split and Replication Receive Control Registers 105210678Srpaulo * 00-15 : 0x02100 + n*4 106210678Srpaulo * 16-64 : 0x01014 + n*0x40 107210678Srpaulo * 64-127: 0x0D014 + (n-64)*0x40 108210678Srpaulo */ 109210678Srpaulo#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 110210678Srpaulo (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 111210678Srpaulo (0x0D014 + ((_i - 64) * 0x40)))) 112210678Srpaulo/* 113210678Srpaulo * Rx DCA Control Register: 114210678Srpaulo * 00-15 : 0x02200 + n*4 115210678Srpaulo * 16-64 : 0x0100C + n*0x40 116210678Srpaulo * 64-127: 0x0D00C + (n-64)*0x40 117210678Srpaulo */ 118210678Srpaulo#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 119210678Srpaulo (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 120210678Srpaulo (0x0D00C + ((_i - 64) * 0x40)))) 121210678Srpaulo#define IXGBE_RDRXCTL 0x02F00 122210678Srpaulo#define IXGBE_RDRXCTRL_RSC_PUSH 0x80 123210678Srpaulo#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 124210678Srpaulo /* 8 of these 0x03C00 - 0x03C1C */ 125210678Srpaulo#define IXGBE_RXCTRL 0x03000 126210678Srpaulo#define IXGBE_DROPEN 0x03D04 127210678Srpaulo#define IXGBE_RXPBSIZE_SHIFT 10 128210678Srpaulo 129210678Srpaulo/* Receive Registers */ 130210678Srpaulo#define IXGBE_RXCSUM 0x05000 131210678Srpaulo#define IXGBE_RFCTL 0x05008 132210678Srpaulo/* Multicast Table Array - 128 entries */ 133210678Srpaulo#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 134210678Srpaulo#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8))) 135210678Srpaulo#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8))) 136210678Srpaulo/* Packet split receive type */ 137210678Srpaulo#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4))) 138210678Srpaulo/* array of 4096 1-bit vlan filters */ 139210678Srpaulo#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 140210678Srpaulo/*array of 4096 4-bit vlan vmdq indices */ 141210678Srpaulo#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 142210678Srpaulo#define IXGBE_FCTRL 0x05080 143210678Srpaulo#define IXGBE_VLNCTRL 0x05088 144210678Srpaulo#define IXGBE_MCSTCTRL 0x05090 145210678Srpaulo#define IXGBE_MRQC 0x05818 146210678Srpaulo#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 147210678Srpaulo#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 148210678Srpaulo#define IXGBE_IMIRVP 0x05AC0 149210678Srpaulo#define IXGBE_VMD_CTL 0x0581C 150210678Srpaulo#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 151210678Srpaulo#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 152210678Srpaulo 153 154/* Transmit DMA registers */ 155#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ 156#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 157#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 158#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 159#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 160#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 161#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 162#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 163#define IXGBE_DTXCTL 0x07E00 164 165#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ 166#define IXGBE_TIPG 0x0CB00 167#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) /* 8 of these */ 168#define IXGBE_MNGTXMAP 0x0CD10 169#define IXGBE_TIPG_FIBER_DEFAULT 3 170#define IXGBE_TXPBSIZE_SHIFT 10 171 172/* Wake up registers */ 173#define IXGBE_WUC 0x05800 174#define IXGBE_WUFC 0x05808 175#define IXGBE_WUS 0x05810 176#define IXGBE_IPAV 0x05838 177#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 178#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 179#define IXGBE_WUPL 0x05900 180#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 181#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ 182 183/* Music registers */ 184#define IXGBE_RMCS 0x03D00 185#define IXGBE_DPMCS 0x07F40 186#define IXGBE_PDPMCS 0x0CD00 187#define IXGBE_RUPPBMR 0x050A0 188#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 189#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 190#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 191#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 192#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 193#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 194 195/* LinkSec (MacSec) Registers */ 196#define IXGBE_LSECTXCTRL 0x08A04 197#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 198#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 199#define IXGBE_LSECTXSA 0x08A10 200#define IXGBE_LSECTXPN0 0x08A14 201#define IXGBE_LSECTXPN1 0x08A18 202#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 203#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 204#define IXGBE_LSECRXCTRL 0x08F04 205#define IXGBE_LSECRXSCL 0x08F08 206#define IXGBE_LSECRXSCH 0x08F0C 207#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 208#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 209#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 210 211/* IpSec Registers */ 212#define IXGBE_IPSTXIDX 0x08900 213#define IXGBE_IPSTXSALT 0x08904 214#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 215#define IXGBE_IPSRXIDX 0x08E00 216#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 217#define IXGBE_IPSRXSPI 0x08E14 218#define IXGBE_IPSRXIPIDX 0x08E18 219#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 220#define IXGBE_IPSRXSALT 0x08E2C 221#define IXGBE_IPSRXMOD 0x08E30 222 223 224/* Stats registers */ 225#define IXGBE_CRCERRS 0x04000 226#define IXGBE_ILLERRC 0x04004 227#define IXGBE_ERRBC 0x04008 228#define IXGBE_MSPDC 0x04010 229#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 230#define IXGBE_MLFC 0x04034 231#define IXGBE_MRFC 0x04038 232#define IXGBE_RLEC 0x04040 233#define IXGBE_LXONTXC 0x03F60 234#define IXGBE_LXONRXC 0x0CF60 235#define IXGBE_LXOFFTXC 0x03F68 236#define IXGBE_LXOFFRXC 0x0CF68 237#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 238#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 239#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 240#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 241#define IXGBE_PRC64 0x0405C 242#define IXGBE_PRC127 0x04060 243#define IXGBE_PRC255 0x04064 244#define IXGBE_PRC511 0x04068 245#define IXGBE_PRC1023 0x0406C 246#define IXGBE_PRC1522 0x04070 247#define IXGBE_GPRC 0x04074 248#define IXGBE_BPRC 0x04078 249#define IXGBE_MPRC 0x0407C 250#define IXGBE_GPTC 0x04080 251#define IXGBE_GORCL 0x04088 252#define IXGBE_GORCH 0x0408C 253#define IXGBE_GOTCL 0x04090 254#define IXGBE_GOTCH 0x04094 255#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 256#define IXGBE_RUC 0x040A4 257#define IXGBE_RFC 0x040A8 258#define IXGBE_ROC 0x040AC 259#define IXGBE_RJC 0x040B0 260#define IXGBE_MNGPRC 0x040B4 261#define IXGBE_MNGPDC 0x040B8 262#define IXGBE_MNGPTC 0x0CF90 263#define IXGBE_TORL 0x040C0 264#define IXGBE_TORH 0x040C4 265#define IXGBE_TPR 0x040D0 266#define IXGBE_TPT 0x040D4 267#define IXGBE_PTC64 0x040D8 268#define IXGBE_PTC127 0x040DC 269#define IXGBE_PTC255 0x040E0 270#define IXGBE_PTC511 0x040E4 271#define IXGBE_PTC1023 0x040E8 272#define IXGBE_PTC1522 0x040EC 273#define IXGBE_MPTC 0x040F0 274#define IXGBE_BPTC 0x040F4 275#define IXGBE_XEC 0x04120 276 277#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ 278#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4))) 279 280#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 281#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 282#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 283#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 284 285/* Management */ 286#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 287#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 288#define IXGBE_MANC 0x05820 289#define IXGBE_MFVAL 0x05824 290#define IXGBE_MANC2H 0x05860 291#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 292#define IXGBE_MIPAF 0x058B0 293#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 294#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 295#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 296 297/* ARC Subsystem registers */ 298#define IXGBE_HICR 0x15F00 299#define IXGBE_FWSTS 0x15F0C 300#define IXGBE_HSMC0R 0x15F04 301#define IXGBE_HSMC1R 0x15F08 302#define IXGBE_SWSR 0x15F10 303#define IXGBE_HFDR 0x15FE8 304#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 305 306/* PCI-E registers */ 307#define IXGBE_GCR 0x11000 308#define IXGBE_GTV 0x11004 309#define IXGBE_FUNCTAG 0x11008 310#define IXGBE_GLT 0x1100C 311#define IXGBE_GSCL_1 0x11010 312#define IXGBE_GSCL_2 0x11014 313#define IXGBE_GSCL_3 0x11018 314#define IXGBE_GSCL_4 0x1101C 315#define IXGBE_GSCN_0 0x11020 316#define IXGBE_GSCN_1 0x11024 317#define IXGBE_GSCN_2 0x11028 318#define IXGBE_GSCN_3 0x1102C 319#define IXGBE_FACTPS 0x10150 320#define IXGBE_PCIEANACTL 0x11040 321#define IXGBE_SWSM 0x10140 322#define IXGBE_FWSM 0x10148 323#define IXGBE_GSSR 0x10160 324#define IXGBE_MREVID 0x11064 325#define IXGBE_DCA_ID 0x11070 326#define IXGBE_DCA_CTRL 0x11074 327 328/* Diagnostic Registers */ 329#define IXGBE_RDSTATCTL 0x02C20 330#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 331#define IXGBE_RDHMPN 0x02F08 332#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 333#define IXGBE_RDPROBE 0x02F20 334#define IXGBE_TDSTATCTL 0x07C20 335#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 336#define IXGBE_TDHMPN 0x07F08 337#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 338#define IXGBE_TDPROBE 0x07F20 339#define IXGBE_TXBUFCTRL 0x0C600 340#define IXGBE_TXBUFDATA0 0x0C610 341#define IXGBE_TXBUFDATA1 0x0C614 342#define IXGBE_TXBUFDATA2 0x0C618 343#define IXGBE_TXBUFDATA3 0x0C61C 344#define IXGBE_RXBUFCTRL 0x03600 345#define IXGBE_RXBUFDATA0 0x03610 346#define IXGBE_RXBUFDATA1 0x03614 347#define IXGBE_RXBUFDATA2 0x03618 348#define IXGBE_RXBUFDATA3 0x0361C 349#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 350#define IXGBE_RFVAL 0x050A4 351#define IXGBE_MDFTC1 0x042B8 352#define IXGBE_MDFTC2 0x042C0 353#define IXGBE_MDFTFIFO1 0x042C4 354#define IXGBE_MDFTFIFO2 0x042C8 355#define IXGBE_MDFTS 0x042CC 356#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 357#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 358#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 359#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 360#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 361#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 362#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 363#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 364#define IXGBE_PCIEECCCTL 0x1106C 365#define IXGBE_PBTXECC 0x0C300 366#define IXGBE_PBRXECC 0x03300 367#define IXGBE_GHECCR 0x110B0 368 369/* MAC Registers */ 370#define IXGBE_PCS1GCFIG 0x04200 371#define IXGBE_PCS1GLCTL 0x04208 372#define IXGBE_PCS1GLSTA 0x0420C 373#define IXGBE_PCS1GDBG0 0x04210 374#define IXGBE_PCS1GDBG1 0x04214 375#define IXGBE_PCS1GANA 0x04218 376#define IXGBE_PCS1GANLP 0x0421C 377#define IXGBE_PCS1GANNP 0x04220 378#define IXGBE_PCS1GANLPNP 0x04224 379#define IXGBE_HLREG0 0x04240 380#define IXGBE_HLREG1 0x04244 381#define IXGBE_PAP 0x04248 382#define IXGBE_MACA 0x0424C 383#define IXGBE_APAE 0x04250 384#define IXGBE_ARD 0x04254 385#define IXGBE_AIS 0x04258 386#define IXGBE_MSCA 0x0425C 387#define IXGBE_MSRWD 0x04260 388#define IXGBE_MLADD 0x04264 389#define IXGBE_MHADD 0x04268 390#define IXGBE_TREG 0x0426C 391#define IXGBE_PCSS1 0x04288 392#define IXGBE_PCSS2 0x0428C 393#define IXGBE_XPCSS 0x04290 394#define IXGBE_SERDESC 0x04298 395#define IXGBE_MACS 0x0429C 396#define IXGBE_AUTOC 0x042A0 397#define IXGBE_LINKS 0x042A4 398#define IXGBE_AUTOC2 0x042A8 399#define IXGBE_AUTOC3 0x042AC 400#define IXGBE_ANLP1 0x042B0 401#define IXGBE_ANLP2 0x042B4 402#define IXGBE_ATLASCTL 0x04800 403 404/* RDRXCTL Bit Masks */ 405#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ 406#define IXGBE_RDRXCTL_MVMEN 0x00000020 407#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 408 409/* CTRL Bit Masks */ 410#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 411#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 412#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 413 414/* FACTPS */ 415#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 416 417/* MHADD Bit Masks */ 418#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 419#define IXGBE_MHADD_MFS_SHIFT 16 420 421/* Extended Device Control */ 422#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 423#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 424#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 425 426/* Direct Cache Access (DCA) definitions */ 427#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 428#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 429 430#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 431#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 432 433#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 434#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 435#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 436#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 437 438#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 439#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 440#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 441#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 442 443/* MSCA Bit Masks */ 444#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 445#define IXGBE_MSCA_NP_ADDR_SHIFT 0 446#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 447#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 448#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 449#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 450#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 451#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 452#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 453#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 454#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */ 455#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/ 456#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 457#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 458#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 459#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 460#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 461#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 462 463/* MSRWD bit masks */ 464#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 465#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 466#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 467#define IXGBE_MSRWD_READ_DATA_SHIFT 16 468 469/* Atlas registers */ 470#define IXGBE_ATLAS_PDN_LPBK 0x24 471#define IXGBE_ATLAS_PDN_10G 0xB 472#define IXGBE_ATLAS_PDN_1G 0xC 473#define IXGBE_ATLAS_PDN_AN 0xD 474 475/* Atlas bit masks */ 476#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 477#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 478#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 479#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 480#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 481 482/* Device Type definitions for new protocol MDIO commands */ 483#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 484#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 485#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 486#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 487#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 488 489#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 490 491#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ 492#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 493#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 494#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 495#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 496#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 497 498#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 499#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 500#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 501#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 502#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 503#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 504#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 505#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 506#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 507 508/* MII clause 22/28 definitions */ 509#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 510 511#define IXGBE_MII_SPEED_SELECTION_REG 0x10 512#define IXGBE_MII_RESTART 0x200 513#define IXGBE_MII_AUTONEG_COMPLETE 0x20 514#define IXGBE_MII_AUTONEG_REG 0x0 515 516#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 517#define IXGBE_MAX_PHY_ADDR 32 518 519/* PHY IDs*/ 520#define TN1010_PHY_ID 0x00A19410 521#define TNX_FW_REV 0xB 522#define QT2022_PHY_ID 0x0043A400 523 524/* PHY Types */ 525#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 526 527/* General purpose Interrupt Enable */ 528#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 529#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 530#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 531#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 532#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 533#define IXGBE_GPIE_EIAME 0x40000000 534#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 535 536/* Transmit Flow Control status */ 537#define IXGBE_TFCS_TXOFF 0x00000001 538#define IXGBE_TFCS_TXOFF0 0x00000100 539#define IXGBE_TFCS_TXOFF1 0x00000200 540#define IXGBE_TFCS_TXOFF2 0x00000400 541#define IXGBE_TFCS_TXOFF3 0x00000800 542#define IXGBE_TFCS_TXOFF4 0x00001000 543#define IXGBE_TFCS_TXOFF5 0x00002000 544#define IXGBE_TFCS_TXOFF6 0x00004000 545#define IXGBE_TFCS_TXOFF7 0x00008000 546 547/* TCP Timer */ 548#define IXGBE_TCPTIMER_KS 0x00000100 549#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 550#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 551#define IXGBE_TCPTIMER_LOOP 0x00000800 552#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 553 554/* HLREG0 Bit Masks */ 555#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 556#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 557#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 558#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 559#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 560#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 561#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 562#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 563#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 564#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 565#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 566#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 567#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 568#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 569#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 570 571/* VMD_CTL bitmasks */ 572#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 573#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 574 575/* RDHMPN and TDHMPN bitmasks */ 576#define IXGBE_RDHMPN_RDICADDR 0x007FF800 577#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 578#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 579#define IXGBE_TDHMPN_TDICADDR 0x003FF800 580#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 581#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 582 583/* Receive Checksum Control */ 584#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 585#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 586 587/* FCRTL Bit Masks */ 588#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */ 589#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */ 590 591/* PAP bit masks*/ 592#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 593 594/* RMCS Bit Masks */ 595#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 596/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 597#define IXGBE_RMCS_RAC 0x00000004 598#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 599#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */ 600#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ 601#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 602 603 604/* Interrupt register bitmasks */ 605 606/* Extended Interrupt Cause Read */ 607#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 608#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 609#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 610#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 611#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 612#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 613#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 614#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 615#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 616 617/* Extended Interrupt Cause Set */ 618#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 619#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 620#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 621#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 622#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 623#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 624#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 625#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 626#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 627 628/* Extended Interrupt Mask Set */ 629#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 630#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 631#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 632#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 633#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 634#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 635#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 636#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 637#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 638 639/* Extended Interrupt Mask Clear */ 640#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 641#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 642#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 643#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 644#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 645#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 646#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 647#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 648#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 649 650#define IXGBE_EIMS_ENABLE_MASK ( \ 651 IXGBE_EIMS_RTX_QUEUE | \ 652 IXGBE_EIMS_LSC | \ 653 IXGBE_EIMS_TCP_TIMER | \ 654 IXGBE_EIMS_OTHER) 655 656/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 657#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 658#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 659#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 660#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 661#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 662#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 663#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 664#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 665#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 666#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 667 668/* Interrupt clear mask */ 669#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 670 671/* Interrupt Vector Allocation Registers */ 672#define IXGBE_IVAR_REG_NUM 25 673#define IXGBE_IVAR_TXRX_ENTRY 96 674#define IXGBE_IVAR_RX_ENTRY 64 675#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 676#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 677#define IXGBE_IVAR_TX_ENTRY 32 678 679#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 680#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 681 682#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 683 684#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 685 686/* VLAN Control Bit Masks */ 687#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 688#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 689#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 690#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 691#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 692 693 694#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 695 696/* STATUS Bit Masks */ 697#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 698#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 699 700#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 701#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 702 703/* ESDP Bit Masks */ 704#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */ 705#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */ 706#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 707#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */ 708 709/* LEDCTL Bit Masks */ 710#define IXGBE_LED_IVRT_BASE 0x00000040 711#define IXGBE_LED_BLINK_BASE 0x00000080 712#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 713#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 714#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 715#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 716#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 717#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 718 719/* LED modes */ 720#define IXGBE_LED_LINK_UP 0x0 721#define IXGBE_LED_LINK_10G 0x1 722#define IXGBE_LED_MAC 0x2 723#define IXGBE_LED_FILTER 0x3 724#define IXGBE_LED_LINK_ACTIVE 0x4 725#define IXGBE_LED_LINK_1G 0x5 726#define IXGBE_LED_ON 0xE 727#define IXGBE_LED_OFF 0xF 728 729/* AUTOC Bit Masks */ 730#define IXGBE_AUTOC_KX4_SUPP 0x80000000 731#define IXGBE_AUTOC_KX_SUPP 0x40000000 732#define IXGBE_AUTOC_PAUSE 0x30000000 733#define IXGBE_AUTOC_RF 0x08000000 734#define IXGBE_AUTOC_PD_TMR 0x06000000 735#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 736#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 737#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 738#define IXGBE_AUTOC_AN_RESTART 0x00001000 739#define IXGBE_AUTOC_FLU 0x00000001 740#define IXGBE_AUTOC_LMS_SHIFT 13 741#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 742#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 743#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 744#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 745#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 746#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 747#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 748 749#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 750#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 751#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 752#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 753#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 754#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 755#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 756#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 757#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 758 759/* LINKS Bit Masks */ 760#define IXGBE_LINKS_KX_AN_COMP 0x80000000 761#define IXGBE_LINKS_UP 0x40000000 762#define IXGBE_LINKS_SPEED 0x20000000 763#define IXGBE_LINKS_MODE 0x18000000 764#define IXGBE_LINKS_RX_MODE 0x06000000 765#define IXGBE_LINKS_TX_MODE 0x01800000 766#define IXGBE_LINKS_XGXS_EN 0x00400000 767#define IXGBE_LINKS_PCS_1G_EN 0x00200000 768#define IXGBE_LINKS_1G_AN_EN 0x00100000 769#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 770#define IXGBE_LINKS_1G_SYNC 0x00040000 771#define IXGBE_LINKS_10G_ALIGN 0x00020000 772#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 773#define IXGBE_LINKS_TL_FAULT 0x00001000 774#define IXGBE_LINKS_SIGNAL 0x00000F00 775 776#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 777#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 778 779#define FIBER_LINK_UP_LIMIT 50 780 781/* PCS1GLSTA Bit Masks */ 782#define IXGBE_PCS1GLSTA_LINK_OK 1 783#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 784#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 785#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 786#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 787#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 788#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 789 790#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 791#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 792 793/* PCS1GLCTL Bit Masks */ 794#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 795#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 796#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 797#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 798#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 799#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 800 801/* SW Semaphore Register bitmasks */ 802#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 803#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 804#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 805 806/* GSSR definitions */ 807#define IXGBE_GSSR_EEP_SM 0x0001 808#define IXGBE_GSSR_PHY0_SM 0x0002 809#define IXGBE_GSSR_PHY1_SM 0x0004 810#define IXGBE_GSSR_MAC_CSR_SM 0x0008 811#define IXGBE_GSSR_FLASH_SM 0x0010 812 813/* EEC Register */ 814#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 815#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 816#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 817#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 818#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 819#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 820#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 821#define IXGBE_EEC_FWE_SHIFT 4 822#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 823#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 824#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 825#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 826/* EEPROM Addressing bits based on type (0-small, 1-large) */ 827#define IXGBE_EEC_ADDR_SIZE 0x00000400 828#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 829 830#define IXGBE_EEC_SIZE_SHIFT 11 831#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 832#define IXGBE_EEPROM_OPCODE_BITS 8 833 834/* Checksum and EEPROM pointers */ 835#define IXGBE_EEPROM_CHECKSUM 0x3F 836#define IXGBE_EEPROM_SUM 0xBABA 837#define IXGBE_PCIE_ANALOG_PTR 0x03 838#define IXGBE_ATLAS0_CONFIG_PTR 0x04 839#define IXGBE_ATLAS1_CONFIG_PTR 0x05 840#define IXGBE_PCIE_GENERAL_PTR 0x06 841#define IXGBE_PCIE_CONFIG0_PTR 0x07 842#define IXGBE_PCIE_CONFIG1_PTR 0x08 843#define IXGBE_CORE0_PTR 0x09 844#define IXGBE_CORE1_PTR 0x0A 845#define IXGBE_MAC0_PTR 0x0B 846#define IXGBE_MAC1_PTR 0x0C 847#define IXGBE_CSR0_CONFIG_PTR 0x0D 848#define IXGBE_CSR1_CONFIG_PTR 0x0E 849#define IXGBE_FW_PTR 0x0F 850#define IXGBE_PBANUM0_PTR 0x15 851#define IXGBE_PBANUM1_PTR 0x16 852 853/* Legacy EEPROM word offsets */ 854#define IXGBE_ISCSI_BOOT_CAPS 0x0033 855#define IXGBE_ISCSI_SETUP_PORT_0 0x0030 856#define IXGBE_ISCSI_SETUP_PORT_1 0x0034 857 858/* EEPROM Commands - SPI */ 859#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 860#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 861#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 862#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 863#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 864#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 865/* EEPROM reset Write Enable latch */ 866#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 867#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 868#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 869#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 870#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 871#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 872 873/* EEPROM Read Register */ 874#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */ 875#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */ 876#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */ 877#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */ 878 879#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 880 881#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 882#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 883#endif 884 885#ifndef IXGBE_EERD_ATTEMPTS 886/* Number of 5 microseconds we wait for EERD read to complete */ 887#define IXGBE_EERD_ATTEMPTS 100000 888#endif 889 890/* PCI Bus Info */ 891#define IXGBE_PCI_LINK_STATUS 0xB2 892#define IXGBE_PCI_LINK_WIDTH 0x3F0 893#define IXGBE_PCI_LINK_WIDTH_1 0x10 894#define IXGBE_PCI_LINK_WIDTH_2 0x20 895#define IXGBE_PCI_LINK_WIDTH_4 0x40 896#define IXGBE_PCI_LINK_WIDTH_8 0x80 897#define IXGBE_PCI_LINK_SPEED 0xF 898#define IXGBE_PCI_LINK_SPEED_2500 0x1 899#define IXGBE_PCI_LINK_SPEED_5000 0x2 900#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 901#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 902 903/* Number of 100 microseconds we wait for PCI Express master disable */ 904#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 905 906/* Check whether address is multicast. This is little-endian specific check.*/ 907#define IXGBE_IS_MULTICAST(Address) \ 908 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 909 910/* Check whether an address is broadcast. */ 911#define IXGBE_IS_BROADCAST(Address) \ 912 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 913 (((u8 *)(Address))[1] == ((u8)0xff))) 914 915/* RAH */ 916#define IXGBE_RAH_VIND_MASK 0x003C0000 917#define IXGBE_RAH_VIND_SHIFT 18 918#define IXGBE_RAH_AV 0x80000000 919#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 920 921/* Header split receive */ 922#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 923#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 924#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 925#define IXGBE_RFCTL_NFSW_DIS 0x00000040 926#define IXGBE_RFCTL_NFSR_DIS 0x00000080 927#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 928#define IXGBE_RFCTL_NFS_VER_SHIFT 8 929#define IXGBE_RFCTL_NFS_VER_2 0 930#define IXGBE_RFCTL_NFS_VER_3 1 931#define IXGBE_RFCTL_NFS_VER_4 2 932#define IXGBE_RFCTL_IPV6_DIS 0x00000400 933#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 934#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 935#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 936#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 937 938/* Transmit Config masks */ 939#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 940#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 941/* Enable short packet padding to 64 bytes */ 942#define IXGBE_TX_PAD_ENABLE 0x00000400 943#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 944/* This allows for 16K packets + 4k for vlan */ 945#define IXGBE_MAX_FRAME_SZ 0x40040000 946 947#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 948#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 949 950/* Receive Config masks */ 951#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 952#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 953#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 954 955#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 956#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 957#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 958#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 959#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 960#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 961/* Receive Priority Flow Control Enable */ 962#define IXGBE_FCTRL_RPFCE 0x00004000 963#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 964 965/* Multiple Receive Queue Control */ 966#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 967#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 968#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 969#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 970#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 971#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 972#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 973#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 974#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 975#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 976#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 977 978#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 979#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 980#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 981#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 982#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 983#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 984#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 985#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 986#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 987 988/* Receive Descriptor bit definitions */ 989#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 990#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 991#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 992#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 993#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 994#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 995#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 996#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 997#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 998#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 999#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 1000#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 1001#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 1002#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 1003#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 1004#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 1005#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 1006#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 1007#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 1008#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 1009#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 1010#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 1011#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 1012#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 1013#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 1014#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 1015#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 1016#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 1017#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 1018#define IXGBE_RXD_PRI_SHIFT 13 1019#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 1020#define IXGBE_RXD_CFI_SHIFT 12 1021 1022/* SRRCTL bit definitions */ 1023#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 1024#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 1025#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 1026#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 1027#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 1028#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 1029#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 1030#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 1031#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 1032 1033#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 1034#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 1035 1036#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 1037#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 1038#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 1039#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 1040#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 1041#define IXGBE_RXDADV_SPH 0x8000 1042 1043/* RSS Hash results */ 1044#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 1045#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 1046#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 1047#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 1048#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 1049#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 1050#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 1051#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 1052#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 1053#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 1054 1055/* RSS Packet Types as indicated in the receive descriptor. */ 1056#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 1057#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 1058#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 1059#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 1060#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 1061#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 1062#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 1063#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 1064#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 1065 1066/* Masks to determine if packets should be dropped due to frame errors */ 1067#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 1068 IXGBE_RXD_ERR_CE | \ 1069 IXGBE_RXD_ERR_LE | \ 1070 IXGBE_RXD_ERR_PE | \ 1071 IXGBE_RXD_ERR_OSE | \ 1072 IXGBE_RXD_ERR_USE) 1073 1074#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 1075 IXGBE_RXDADV_ERR_CE | \ 1076 IXGBE_RXDADV_ERR_LE | \ 1077 IXGBE_RXDADV_ERR_PE | \ 1078 IXGBE_RXDADV_ERR_OSE | \ 1079 IXGBE_RXDADV_ERR_USE) 1080 1081/* Multicast bit mask */ 1082#define IXGBE_MCSTCTRL_MFE 0x4 1083 1084/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 1085#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 1086#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 1087#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 1088 1089/* Vlan-specific macros */ 1090#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 1091#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 1092#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 1093#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 1094 1095#ifndef __le16 1096/* Little Endian defines */ 1097#define __le8 u8 1098#define __le16 u16 1099#define __le32 u32 1100#define __le64 u64 1101 1102#endif 1103 1104 1105/* Transmit Descriptor - Legacy */ 1106struct ixgbe_legacy_tx_desc { 1107 u64 buffer_addr; /* Address of the descriptor's data buffer */ 1108 union { 1109 __le32 data; 1110 struct { 1111 __le16 length; /* Data buffer length */ 1112 __le8 cso; /* Checksum offset */ 1113 __le8 cmd; /* Descriptor control */ 1114 } flags; 1115 } lower; 1116 union { 1117 __le32 data; 1118 struct { 1119 __le8 status; /* Descriptor status */ 1120 __le8 css; /* Checksum start */ 1121 __le16 vlan; 1122 } fields; 1123 } upper; 1124}; 1125 1126/* Transmit Descriptor - Advanced */ 1127union ixgbe_adv_tx_desc { 1128 struct { 1129 __le64 buffer_addr; /* Address of descriptor's data buf */ 1130 __le32 cmd_type_len; 1131 __le32 olinfo_status; 1132 } read; 1133 struct { 1134 __le64 rsvd; /* Reserved */ 1135 __le32 nxtseq_seed; 1136 __le32 status; 1137 } wb; 1138}; 1139 1140/* Receive Descriptor - Legacy */ 1141struct ixgbe_legacy_rx_desc { 1142 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 1143 __le16 length; /* Length of data DMAed into data buffer */ 1144 __le16 csum; /* Packet checksum */ 1145 __le8 status; /* Descriptor status */ 1146 __le8 errors; /* Descriptor Errors */ 1147 __le16 vlan; 1148}; 1149 1150/* Receive Descriptor - Advanced */ 1151union ixgbe_adv_rx_desc { 1152 struct { 1153 __le64 pkt_addr; /* Packet buffer address */ 1154 __le64 hdr_addr; /* Header buffer address */ 1155 } read; 1156 struct { 1157 struct { 1158 union { 1159 __le32 data; 1160 struct { 1161 __le16 pkt_info; /* RSS, Pkt type */ 1162 __le16 hdr_info; /* Splithdr, hdrlen */ 1163 } hs_rss; 1164 } lo_dword; 1165 union { 1166 __le32 rss; /* RSS Hash */ 1167 struct { 1168 __le16 ip_id; /* IP id */ 1169 __le16 csum; /* Packet Checksum */ 1170 } csum_ip; 1171 } hi_dword; 1172 } lower; 1173 struct { 1174 __le32 status_error; /* ext status/error */ 1175 __le16 length; /* Packet length */ 1176 __le16 vlan; /* VLAN tag */ 1177 } upper; 1178 } wb; /* writeback */ 1179}; 1180 1181/* Context descriptors */ 1182struct ixgbe_adv_tx_context_desc { 1183 __le32 vlan_macip_lens; 1184 __le32 seqnum_seed; 1185 __le32 type_tucmd_mlhl; 1186 __le32 mss_l4len_idx; 1187}; 1188 1189/* Adv Transmit Descriptor Config Masks */ 1190#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 1191#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 1192#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 1193#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 1194#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 1195#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 1196#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 1197#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 1198#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 1199#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 1200#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 1201#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 1202#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 1203#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 1204#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 1205#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 1206#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 1207#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 1208 IXGBE_ADVTXD_POPTS_SHIFT) 1209#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 1210 IXGBE_ADVTXD_POPTS_SHIFT) 1211#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 1212#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 1213#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 1214#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ 1215#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 1216#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 1217#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 1218#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 1219#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 1220#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 1221#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 1222#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 1223#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 1224#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ 1225#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 1226#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 1227 1228/* Autonegotiation advertised speeds */ 1229typedef u32 ixgbe_autoneg_advertised; 1230/* Link speed */ 1231typedef u32 ixgbe_link_speed; 1232#define IXGBE_LINK_SPEED_UNKNOWN 0 1233#define IXGBE_LINK_SPEED_100_FULL 0x0008 1234#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 1235#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 1236#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 1237 IXGBE_LINK_SPEED_10GB_FULL) 1238 1239enum ixgbe_eeprom_type { 1240 ixgbe_eeprom_uninitialized = 0, 1241 ixgbe_eeprom_spi, 1242 ixgbe_eeprom_none /* No NVM support */ 1243}; 1244 1245enum ixgbe_mac_type { 1246 ixgbe_mac_unknown = 0, 1247 ixgbe_mac_82598EB, 1248 ixgbe_num_macs 1249}; 1250 1251enum ixgbe_phy_type { 1252 ixgbe_phy_unknown = 0, 1253 ixgbe_phy_tn, 1254 ixgbe_phy_qt, 1255 ixgbe_phy_xaui, 1256 ixgbe_phy_generic 1257}; 1258 1259enum ixgbe_media_type { 1260 ixgbe_media_type_unknown = 0, 1261 ixgbe_media_type_fiber, 1262 ixgbe_media_type_copper, 1263 ixgbe_media_type_backplane, 1264 ixgbe_media_type_virtual 1265}; 1266 1267/* Flow Control Settings */ 1268enum ixgbe_fc_type { 1269 ixgbe_fc_none = 0, 1270 ixgbe_fc_rx_pause, 1271 ixgbe_fc_tx_pause, 1272 ixgbe_fc_full, 1273 ixgbe_fc_default 1274}; 1275 1276/* PCI bus types */ 1277enum ixgbe_bus_type { 1278 ixgbe_bus_type_unknown = 0, 1279 ixgbe_bus_type_pci, 1280 ixgbe_bus_type_pcix, 1281 ixgbe_bus_type_pci_express, 1282 ixgbe_bus_type_reserved 1283}; 1284 1285/* PCI bus speeds */ 1286enum ixgbe_bus_speed { 1287 ixgbe_bus_speed_unknown = 0, 1288 ixgbe_bus_speed_33, 1289 ixgbe_bus_speed_66, 1290 ixgbe_bus_speed_100, 1291 ixgbe_bus_speed_120, 1292 ixgbe_bus_speed_133, 1293 ixgbe_bus_speed_2500, 1294 ixgbe_bus_speed_5000, 1295 ixgbe_bus_speed_reserved 1296}; 1297 1298/* PCI bus widths */ 1299enum ixgbe_bus_width { 1300 ixgbe_bus_width_unknown = 0, 1301 ixgbe_bus_width_pcie_x1, 1302 ixgbe_bus_width_pcie_x2, 1303 ixgbe_bus_width_pcie_x4 = 4, 1304 ixgbe_bus_width_pcie_x8 = 8, 1305 ixgbe_bus_width_32, 1306 ixgbe_bus_width_64, 1307 ixgbe_bus_width_reserved 1308}; 1309 1310struct ixgbe_addr_filter_info { 1311 u32 num_mc_addrs; 1312 u32 rar_used_count; 1313 u32 mc_addr_in_rar_count; 1314 u32 mta_in_use; 1315 u32 overflow_promisc; 1316 bool user_set_promisc; 1317}; 1318 1319/* Bus parameters */ 1320struct ixgbe_bus_info { 1321 enum ixgbe_bus_speed speed; 1322 enum ixgbe_bus_width width; 1323 enum ixgbe_bus_type type; 1324}; 1325 1326/* Flow control parameters */ 1327struct ixgbe_fc_info { 1328 u32 high_water; /* Flow Control High-water */ 1329 u32 low_water; /* Flow Control Low-water */ 1330 u16 pause_time; /* Flow Control Pause timer */ 1331 bool send_xon; /* Flow control send XON */ 1332 bool strict_ieee; /* Strict IEEE mode */ 1333 enum ixgbe_fc_type type; /* Type of flow control */ 1334 enum ixgbe_fc_type original_type; 1335}; 1336 1337/* Statistics counters collected by the MAC */ 1338struct ixgbe_hw_stats { 1339 u64 crcerrs; 1340 u64 illerrc; 1341 u64 errbc; 1342 u64 mspdc; 1343 u64 mpctotal; 1344 u64 mpc[8]; 1345 u64 mlfc; 1346 u64 mrfc; 1347 u64 rlec; 1348 u64 lxontxc; 1349 u64 lxonrxc; 1350 u64 lxofftxc; 1351 u64 lxoffrxc; 1352 u64 pxontxc[8]; 1353 u64 pxonrxc[8]; 1354 u64 pxofftxc[8]; 1355 u64 pxoffrxc[8]; 1356 u64 prc64; 1357 u64 prc127; 1358 u64 prc255; 1359 u64 prc511; 1360 u64 prc1023; 1361 u64 prc1522; 1362 u64 gprc; 1363 u64 bprc; 1364 u64 mprc; 1365 u64 gptc; 1366 u64 gorc; 1367 u64 gotc; 1368 u64 rnbc[8]; 1369 u64 ruc; 1370 u64 rfc; 1371 u64 roc; 1372 u64 rjc; 1373 u64 mngprc; 1374 u64 mngpdc; 1375 u64 mngptc; 1376 u64 tor; 1377 u64 tpr; 1378 u64 tpt; 1379 u64 ptc64; 1380 u64 ptc127; 1381 u64 ptc255; 1382 u64 ptc511; 1383 u64 ptc1023; 1384 u64 ptc1522; 1385 u64 mptc; 1386 u64 bptc; 1387 u64 xec; 1388 u64 rqsmr[16]; 1389 u64 tqsmr[8]; 1390 u64 qprc[16]; 1391 u64 qptc[16]; 1392 u64 qbrc[16]; 1393 u64 qbtc[16]; 1394}; 1395 1396/* forward declaration */ 1397struct ixgbe_hw; 1398 1399/* iterator type for walking multicast address lists */ 1400typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 1401 u32 *vmdq); 1402 1403/* Function pointer table */ 1404struct ixgbe_eeprom_operations { 1405 s32 (*init_params)(struct ixgbe_hw *); 1406 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 1407 s32 (*write)(struct ixgbe_hw *, u16, u16); 1408 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 1409 s32 (*update_checksum)(struct ixgbe_hw *); 1410}; 1411 1412struct ixgbe_mac_operations { 1413 s32 (*init_hw)(struct ixgbe_hw *); 1414 s32 (*reset_hw)(struct ixgbe_hw *); 1415 s32 (*start_hw)(struct ixgbe_hw *); 1416 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 1417 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 1418 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 1419 s32 (*stop_adapter)(struct ixgbe_hw *); 1420 s32 (*get_bus_info)(struct ixgbe_hw *); 1421 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 1422 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 1423 1424 /* Link */ 1425 s32 (*setup_link)(struct ixgbe_hw *); 1426 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, 1427 bool); 1428 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 1429 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 1430 bool *); 1431 1432 /* LED */ 1433 s32 (*led_on)(struct ixgbe_hw *, u32); 1434 s32 (*led_off)(struct ixgbe_hw *, u32); 1435 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 1436 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 1437 1438 /* RAR, Multicast, VLAN */ 1439 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 1440 s32 (*clear_rar)(struct ixgbe_hw *, u32); 1441 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 1442 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 1443 s32 (*init_rx_addrs)(struct ixgbe_hw *); 1444 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 1445 ixgbe_mc_addr_itr); 1446 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 1447 ixgbe_mc_addr_itr); 1448 s32 (*enable_mc)(struct ixgbe_hw *); 1449 s32 (*disable_mc)(struct ixgbe_hw *); 1450 s32 (*clear_vfta)(struct ixgbe_hw *); 1451 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 1452 s32 (*init_uta_tables)(struct ixgbe_hw *); 1453 1454 /* Flow Control */ 1455 s32 (*setup_fc)(struct ixgbe_hw *, s32); 1456}; 1457 1458struct ixgbe_phy_operations { 1459 s32 (*identify)(struct ixgbe_hw *); 1460 s32 (*reset)(struct ixgbe_hw *); 1461 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 1462 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 1463 s32 (*setup_link)(struct ixgbe_hw *); 1464 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, 1465 bool); 1466 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 1467 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 1468}; 1469 1470struct ixgbe_eeprom_info { 1471 struct ixgbe_eeprom_operations ops; 1472 enum ixgbe_eeprom_type type; 1473 u32 semaphore_delay; 1474 u16 word_size; 1475 u16 address_bits; 1476}; 1477 1478struct ixgbe_mac_info { 1479 struct ixgbe_mac_operations ops; 1480 enum ixgbe_mac_type type; 1481 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1482 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1483 s32 mc_filter_type; 1484 u32 mcft_size; 1485 u32 vft_size; 1486 u32 num_rar_entries; 1487 u32 max_tx_queues; 1488 u32 max_rx_queues; 1489 u32 link_attach_type; 1490 u32 link_mode_select; 1491 bool link_settings_loaded; 1492 bool autoneg; 1493 bool autoneg_failed; 1494}; 1495 1496struct ixgbe_phy_info { 1497 struct ixgbe_phy_operations ops; 1498 enum ixgbe_phy_type type; 1499 u32 addr; 1500 u32 id; 1501 u32 revision; 1502 enum ixgbe_media_type media_type; 1503 bool reset_disable; 1504 ixgbe_autoneg_advertised autoneg_advertised; 1505 bool autoneg_wait_to_complete; 1506}; 1507 1508struct ixgbe_hw { 1509 u8 *hw_addr; 1510 void *back; 1511 struct ixgbe_mac_info mac; 1512 struct ixgbe_addr_filter_info addr_ctrl; 1513 struct ixgbe_fc_info fc; 1514 struct ixgbe_phy_info phy; 1515 struct ixgbe_eeprom_info eeprom; 1516 struct ixgbe_bus_info bus; 1517 u16 device_id; 1518 u16 vendor_id; 1519 u16 subsystem_device_id; 1520 u16 subsystem_vendor_id; 1521 u8 revision_id; 1522 bool adapter_stopped; 1523}; 1524 1525#define ixgbe_call_func(hw, func, params, error) \ 1526 (func != NULL) ? func params: error 1527 1528/* Error Codes */ 1529#define IXGBE_SUCCESS 0 1530#define IXGBE_ERR_EEPROM -1 1531#define IXGBE_ERR_EEPROM_CHECKSUM -2 1532#define IXGBE_ERR_PHY -3 1533#define IXGBE_ERR_CONFIG -4 1534#define IXGBE_ERR_PARAM -5 1535#define IXGBE_ERR_MAC_TYPE -6 1536#define IXGBE_ERR_UNKNOWN_PHY -7 1537#define IXGBE_ERR_LINK_SETUP -8 1538#define IXGBE_ERR_ADAPTER_STOPPED -9 1539#define IXGBE_ERR_INVALID_MAC_ADDR -10 1540#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 1541#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 1542#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 1543#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 1544#define IXGBE_ERR_RESET_FAILED -15 1545#define IXGBE_ERR_SWFW_SYNC -16 1546#define IXGBE_ERR_PHY_ADDR_INVALID -17 1547#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 1548 1549#define UNREFERENCED_PARAMETER(_p) 1550 1551#endif /* _IXGBE_TYPE_H_ */ 1552