ixgbe_type.h revision 179055
1161246Spjd/****************************************************************************** 2161246Spjd 3161246Spjd Copyright (c) 2001-2008, Intel Corporation 4161246Spjd All rights reserved. 5161246Spjd 6161246Spjd Redistribution and use in source and binary forms, with or without 7161246Spjd modification, are permitted provided that the following conditions are met: 8161246Spjd 9161246Spjd 1. Redistributions of source code must retain the above copyright notice, 10161246Spjd this list of conditions and the following disclaimer. 11161246Spjd 12161246Spjd 2. Redistributions in binary form must reproduce the above copyright 13161246Spjd notice, this list of conditions and the following disclaimer in the 14161246Spjd documentation and/or other materials provided with the distribution. 15161246Spjd 16161246Spjd 3. Neither the name of the Intel Corporation nor the names of its 17161246Spjd contributors may be used to endorse or promote products derived from 18161246Spjd this software without specific prior written permission. 19161246Spjd 20161246Spjd THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21161246Spjd AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22161246Spjd IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23161246Spjd ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24161246Spjd LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25161246Spjd CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26161246Spjd SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27161246Spjd INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28161246Spjd CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29161246Spjd ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30161246Spjd POSSIBILITY OF SUCH DAMAGE. 31161246Spjd 32161246Spjd******************************************************************************/ 33161246Spjd/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 179055 2008-05-16 18:46:30Z jfv $*/ 34161246Spjd 35161246Spjd#ifndef _IXGBE_TYPE_H_ 36161246Spjd#define _IXGBE_TYPE_H_ 37161246Spjd 38161246Spjd#include "ixgbe_osdep.h" 39161246Spjd 40161246Spjd/* Vendor ID */ 41162834Spjd#define IXGBE_INTEL_VENDOR_ID 0x8086 42161246Spjd 43161246Spjd/* Device IDs */ 44161246Spjd#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 45161246Spjd#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 46161246Spjd#define IXGBE_DEV_ID_82598AT 0x10C8 47161246Spjd#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10D7 48161246Spjd#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 49161246Spjd#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 50161246Spjd#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 51161246Spjd#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 52161246Spjd#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 53161246Spjd 54161246Spjd/* General Registers */ 55161246Spjd#define IXGBE_CTRL 0x00000 56161246Spjd#define IXGBE_STATUS 0x00008 57161246Spjd#define IXGBE_CTRL_EXT 0x00018 58161246Spjd#define IXGBE_ESDP 0x00020 59161246Spjd#define IXGBE_EODSDP 0x00028 60161246Spjd#define IXGBE_LEDCTL 0x00200 61161246Spjd#define IXGBE_FRTIMER 0x00048 62161246Spjd#define IXGBE_TCPTIMER 0x0004C 63161246Spjd 64161246Spjd/* NVM Registers */ 65161246Spjd#define IXGBE_EEC 0x10010 66161246Spjd#define IXGBE_EERD 0x10014 67161246Spjd#define IXGBE_FLA 0x1001C 68161246Spjd#define IXGBE_EEMNGCTL 0x10110 69161246Spjd#define IXGBE_EEMNGDATA 0x10114 70161246Spjd#define IXGBE_FLMNGCTL 0x10118 71161246Spjd#define IXGBE_FLMNGDATA 0x1011C 72161246Spjd#define IXGBE_FLMNGCNT 0x10120 73161246Spjd#define IXGBE_FLOP 0x1013C 74161246Spjd#define IXGBE_GRC 0x10200 75161246Spjd 76161246Spjd/* Interrupt Registers */ 77162834Spjd#define IXGBE_EICR 0x00800 78161246Spjd#define IXGBE_EICS 0x00808 79161246Spjd#define IXGBE_EIMS 0x00880 80161246Spjd#define IXGBE_EIMC 0x00888 81161246Spjd#define IXGBE_EIAC 0x00810 82161246Spjd#define IXGBE_EIAM 0x00890 83161246Spjd#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4))) 84161246Spjd#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 85161246Spjd#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 86161246Spjd#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 87161246Spjd#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 88161246Spjd#define IXGBE_GPIE 0x00898 89161246Spjd 90161246Spjd/* Flow Control Registers */ 91161246Spjd#define IXGBE_PFCTOP 0x03008 92161246Spjd#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 93161246Spjd#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 94161246Spjd#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 95161246Spjd#define IXGBE_FCRTV 0x032A0 96161246Spjd#define IXGBE_TFCS 0x0CE00 97161246Spjd 98161246Spjd/* Receive DMA Registers */ 99161246Spjd#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40))) 100161246Spjd#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40))) 101161246Spjd#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40))) 102161246Spjd#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40))) 103161246Spjd#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40))) 104161246Spjd#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40))) 105161246Spjd/* 106161246Spjd * Split and Replication Receive Control Registers 107161246Spjd * 00-15 : 0x02100 + n*4 108161246Spjd * 16-64 : 0x01014 + n*0x40 109161246Spjd * 64-127: 0x0D014 + (n-64)*0x40 110161246Spjd */ 111161246Spjd#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 112161246Spjd (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 113162834Spjd (0x0D014 + ((_i - 64) * 0x40)))) 114161246Spjd/* 115161246Spjd * Rx DCA Control Register: 116161246Spjd * 00-15 : 0x02200 + n*4 117161246Spjd * 16-64 : 0x0100C + n*0x40 118161246Spjd * 64-127: 0x0D00C + (n-64)*0x40 119161246Spjd */ 120161246Spjd#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 121161246Spjd (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 122161246Spjd (0x0D00C + ((_i - 64) * 0x40)))) 123161246Spjd#define IXGBE_RDRXCTL 0x02F00 124161246Spjd#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 125161246Spjd /* 8 of these 0x03C00 - 0x03C1C */ 126161246Spjd#define IXGBE_RXCTRL 0x03000 127161246Spjd#define IXGBE_DROPEN 0x03D04 128161246Spjd#define IXGBE_RXPBSIZE_SHIFT 10 129161246Spjd 130161246Spjd/* Receive Registers */ 131161246Spjd#define IXGBE_RXCSUM 0x05000 132161246Spjd#define IXGBE_RFCTL 0x05008 133161246Spjd/* Multicast Table Array - 128 entries */ 134161246Spjd#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 135161246Spjd#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8))) 136161246Spjd#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8))) 137161246Spjd/* Packet split receive type */ 138161246Spjd#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4))) 139161246Spjd/* array of 4096 1-bit vlan filters */ 140161246Spjd#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 141/*array of 4096 4-bit vlan vmdq indices */ 142#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 143#define IXGBE_FCTRL 0x05080 144#define IXGBE_VLNCTRL 0x05088 145#define IXGBE_MCSTCTRL 0x05090 146#define IXGBE_MRQC 0x05818 147#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 148#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 149#define IXGBE_IMIRVP 0x05AC0 150#define IXGBE_VMD_CTL 0x0581C 151#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 152#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 153 154 155/* Transmit DMA registers */ 156#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ 157#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 158#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 159#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 160#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 161#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 162#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 163#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 164#define IXGBE_DTXCTL 0x07E00 165 166#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ 167#define IXGBE_TIPG 0x0CB00 168#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) /* 8 of these */ 169#define IXGBE_MNGTXMAP 0x0CD10 170#define IXGBE_TIPG_FIBER_DEFAULT 3 171#define IXGBE_TXPBSIZE_SHIFT 10 172 173/* Wake up registers */ 174#define IXGBE_WUC 0x05800 175#define IXGBE_WUFC 0x05808 176#define IXGBE_WUS 0x05810 177#define IXGBE_IPAV 0x05838 178#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 179#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 180#define IXGBE_WUPL 0x05900 181#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 182#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ 183 184/* Music registers */ 185#define IXGBE_RMCS 0x03D00 186#define IXGBE_DPMCS 0x07F40 187#define IXGBE_PDPMCS 0x0CD00 188#define IXGBE_RUPPBMR 0x050A0 189#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 190#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 191#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 192#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 193#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 194#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 195 196/* LinkSec (MacSec) Registers */ 197#define IXGBE_LSECTXCTRL 0x08A04 198#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 199#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 200#define IXGBE_LSECTXSA 0x08A10 201#define IXGBE_LSECTXPN0 0x08A14 202#define IXGBE_LSECTXPN1 0x08A18 203#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 204#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 205#define IXGBE_LSECRXCTRL 0x08F04 206#define IXGBE_LSECRXSCL 0x08F08 207#define IXGBE_LSECRXSCH 0x08F0C 208#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 209#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 210#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 211 212/* IpSec Registers */ 213#define IXGBE_IPSTXIDX 0x08900 214#define IXGBE_IPSTXSALT 0x08904 215#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 216#define IXGBE_IPSRXIDX 0x08E00 217#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 218#define IXGBE_IPSRXSPI 0x08E14 219#define IXGBE_IPSRXIPIDX 0x08E18 220#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 221#define IXGBE_IPSRXSALT 0x08E2C 222#define IXGBE_IPSRXMOD 0x08E30 223 224 225/* Stats registers */ 226#define IXGBE_CRCERRS 0x04000 227#define IXGBE_ILLERRC 0x04004 228#define IXGBE_ERRBC 0x04008 229#define IXGBE_MSPDC 0x04010 230#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 231#define IXGBE_MLFC 0x04034 232#define IXGBE_MRFC 0x04038 233#define IXGBE_RLEC 0x04040 234#define IXGBE_LXONTXC 0x03F60 235#define IXGBE_LXONRXC 0x0CF60 236#define IXGBE_LXOFFTXC 0x03F68 237#define IXGBE_LXOFFRXC 0x0CF68 238#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 239#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 240#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 241#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 242#define IXGBE_PRC64 0x0405C 243#define IXGBE_PRC127 0x04060 244#define IXGBE_PRC255 0x04064 245#define IXGBE_PRC511 0x04068 246#define IXGBE_PRC1023 0x0406C 247#define IXGBE_PRC1522 0x04070 248#define IXGBE_GPRC 0x04074 249#define IXGBE_BPRC 0x04078 250#define IXGBE_MPRC 0x0407C 251#define IXGBE_GPTC 0x04080 252#define IXGBE_GORCL 0x04088 253#define IXGBE_GORCH 0x0408C 254#define IXGBE_GOTCL 0x04090 255#define IXGBE_GOTCH 0x04094 256#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 257#define IXGBE_RUC 0x040A4 258#define IXGBE_RFC 0x040A8 259#define IXGBE_ROC 0x040AC 260#define IXGBE_RJC 0x040B0 261#define IXGBE_MNGPRC 0x040B4 262#define IXGBE_MNGPDC 0x040B8 263#define IXGBE_MNGPTC 0x0CF90 264#define IXGBE_TORL 0x040C0 265#define IXGBE_TORH 0x040C4 266#define IXGBE_TPR 0x040D0 267#define IXGBE_TPT 0x040D4 268#define IXGBE_PTC64 0x040D8 269#define IXGBE_PTC127 0x040DC 270#define IXGBE_PTC255 0x040E0 271#define IXGBE_PTC511 0x040E4 272#define IXGBE_PTC1023 0x040E8 273#define IXGBE_PTC1522 0x040EC 274#define IXGBE_MPTC 0x040F0 275#define IXGBE_BPTC 0x040F4 276#define IXGBE_XEC 0x04120 277 278#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ 279#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4))) 280 281#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 282#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 283#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 284#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 285 286/* Management */ 287#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 288#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 289#define IXGBE_MANC 0x05820 290#define IXGBE_MFVAL 0x05824 291#define IXGBE_MANC2H 0x05860 292#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 293#define IXGBE_MIPAF 0x058B0 294#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 295#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 296#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 297 298/* ARC Subsystem registers */ 299#define IXGBE_HICR 0x15F00 300#define IXGBE_FWSTS 0x15F0C 301#define IXGBE_HSMC0R 0x15F04 302#define IXGBE_HSMC1R 0x15F08 303#define IXGBE_SWSR 0x15F10 304#define IXGBE_HFDR 0x15FE8 305#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 306 307/* PCI-E registers */ 308#define IXGBE_GCR 0x11000 309#define IXGBE_GTV 0x11004 310#define IXGBE_FUNCTAG 0x11008 311#define IXGBE_GLT 0x1100C 312#define IXGBE_GSCL_1 0x11010 313#define IXGBE_GSCL_2 0x11014 314#define IXGBE_GSCL_3 0x11018 315#define IXGBE_GSCL_4 0x1101C 316#define IXGBE_GSCN_0 0x11020 317#define IXGBE_GSCN_1 0x11024 318#define IXGBE_GSCN_2 0x11028 319#define IXGBE_GSCN_3 0x1102C 320#define IXGBE_FACTPS 0x10150 321#define IXGBE_PCIEANACTL 0x11040 322#define IXGBE_SWSM 0x10140 323#define IXGBE_FWSM 0x10148 324#define IXGBE_GSSR 0x10160 325#define IXGBE_MREVID 0x11064 326#define IXGBE_DCA_ID 0x11070 327#define IXGBE_DCA_CTRL 0x11074 328 329/* Diagnostic Registers */ 330#define IXGBE_RDSTATCTL 0x02C20 331#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 332#define IXGBE_RDHMPN 0x02F08 333#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 334#define IXGBE_RDPROBE 0x02F20 335#define IXGBE_TDSTATCTL 0x07C20 336#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 337#define IXGBE_TDHMPN 0x07F08 338#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 339#define IXGBE_TDPROBE 0x07F20 340#define IXGBE_TXBUFCTRL 0x0C600 341#define IXGBE_TXBUFDATA0 0x0C610 342#define IXGBE_TXBUFDATA1 0x0C614 343#define IXGBE_TXBUFDATA2 0x0C618 344#define IXGBE_TXBUFDATA3 0x0C61C 345#define IXGBE_RXBUFCTRL 0x03600 346#define IXGBE_RXBUFDATA0 0x03610 347#define IXGBE_RXBUFDATA1 0x03614 348#define IXGBE_RXBUFDATA2 0x03618 349#define IXGBE_RXBUFDATA3 0x0361C 350#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 351#define IXGBE_RFVAL 0x050A4 352#define IXGBE_MDFTC1 0x042B8 353#define IXGBE_MDFTC2 0x042C0 354#define IXGBE_MDFTFIFO1 0x042C4 355#define IXGBE_MDFTFIFO2 0x042C8 356#define IXGBE_MDFTS 0x042CC 357#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 358#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 359#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 360#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 361#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 362#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 363#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 364#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 365#define IXGBE_PCIEECCCTL 0x1106C 366#define IXGBE_PBTXECC 0x0C300 367#define IXGBE_PBRXECC 0x03300 368#define IXGBE_GHECCR 0x110B0 369 370/* MAC Registers */ 371#define IXGBE_PCS1GCFIG 0x04200 372#define IXGBE_PCS1GLCTL 0x04208 373#define IXGBE_PCS1GLSTA 0x0420C 374#define IXGBE_PCS1GDBG0 0x04210 375#define IXGBE_PCS1GDBG1 0x04214 376#define IXGBE_PCS1GANA 0x04218 377#define IXGBE_PCS1GANLP 0x0421C 378#define IXGBE_PCS1GANNP 0x04220 379#define IXGBE_PCS1GANLPNP 0x04224 380#define IXGBE_HLREG0 0x04240 381#define IXGBE_HLREG1 0x04244 382#define IXGBE_PAP 0x04248 383#define IXGBE_MACA 0x0424C 384#define IXGBE_APAE 0x04250 385#define IXGBE_ARD 0x04254 386#define IXGBE_AIS 0x04258 387#define IXGBE_MSCA 0x0425C 388#define IXGBE_MSRWD 0x04260 389#define IXGBE_MLADD 0x04264 390#define IXGBE_MHADD 0x04268 391#define IXGBE_TREG 0x0426C 392#define IXGBE_PCSS1 0x04288 393#define IXGBE_PCSS2 0x0428C 394#define IXGBE_XPCSS 0x04290 395#define IXGBE_SERDESC 0x04298 396#define IXGBE_MACS 0x0429C 397#define IXGBE_AUTOC 0x042A0 398#define IXGBE_LINKS 0x042A4 399#define IXGBE_AUTOC2 0x042A8 400#define IXGBE_AUTOC3 0x042AC 401#define IXGBE_ANLP1 0x042B0 402#define IXGBE_ANLP2 0x042B4 403#define IXGBE_ATLASCTL 0x04800 404 405 406/* CTRL Bit Masks */ 407#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 408#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 409#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 410 411/* FACTPS */ 412#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 413 414/* MHADD Bit Masks */ 415#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 416#define IXGBE_MHADD_MFS_SHIFT 16 417 418/* Extended Device Control */ 419#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 420#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 421#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 422 423/* Direct Cache Access (DCA) definitions */ 424#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 425#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 426 427#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 428#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 429 430#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 431#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 432#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 433#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 434 435#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 436#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 437#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 438#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 439 440/* MSCA Bit Masks */ 441#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 442#define IXGBE_MSCA_NP_ADDR_SHIFT 0 443#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 444#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 445#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 446#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 447#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 448#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 449#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 450#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 451#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */ 452#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/ 453#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 454#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 455#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 456#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 457#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 458#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 459 460/* MSRWD bit masks */ 461#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 462#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 463#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 464#define IXGBE_MSRWD_READ_DATA_SHIFT 16 465 466/* Atlas registers */ 467#define IXGBE_ATLAS_PDN_LPBK 0x24 468#define IXGBE_ATLAS_PDN_10G 0xB 469#define IXGBE_ATLAS_PDN_1G 0xC 470#define IXGBE_ATLAS_PDN_AN 0xD 471 472/* Atlas bit masks */ 473#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 474#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 475#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 476#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 477#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 478 479/* Device Type definitions for new protocol MDIO commands */ 480#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 481#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 482#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 483#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 484#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 485#define IXGBE_TWINAX_DEV 1 486 487#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 488 489#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ 490#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 491#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 492#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 493#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 494#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 495 496#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 497#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 498#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 499#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 500#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 501#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 502#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 503#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 504#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 505 506/* MII clause 22/28 definitions */ 507#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 508 509#define IXGBE_MII_SPEED_SELECTION_REG 0x10 510#define IXGBE_MII_RESTART 0x200 511#define IXGBE_MII_AUTONEG_COMPLETE 0x20 512#define IXGBE_MII_AUTONEG_REG 0x0 513 514#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 515#define IXGBE_MAX_PHY_ADDR 32 516 517/* PHY IDs*/ 518#define TN1010_PHY_ID 0x00A19410 519#define TNX_FW_REV 0xB 520#define QT2022_PHY_ID 0x0043A400 521#define ATH_PHY_ID 0x03429050 522 523/* PHY Types */ 524#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 525 526/* Special PHY Init Routine */ 527#define IXGBE_PHY_INIT_OFFSET_NL 0x002B 528#define IXGBE_CONTROL_MASK_NL 0xF000 529#define IXGBE_DATA_MASK_NL 0x0FFF 530#define IXGBE_CONTROL_SHIFT_NL 12 531#define IXGBE_DELAY_NL 0 532#define IXGBE_DATA_NL 1 533#define IXGBE_CONTROL_NL 0x000F 534#define IXGBE_CONTROL_EOL_NL 0x0FFF 535#define IXGBE_CONTROL_SOL_NL 0x0000 536 537/* General purpose Interrupt Enable */ 538#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 539#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 540#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 541#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 542#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 543#define IXGBE_GPIE_EIAME 0x40000000 544#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 545 546/* Transmit Flow Control status */ 547#define IXGBE_TFCS_TXOFF 0x00000001 548#define IXGBE_TFCS_TXOFF0 0x00000100 549#define IXGBE_TFCS_TXOFF1 0x00000200 550#define IXGBE_TFCS_TXOFF2 0x00000400 551#define IXGBE_TFCS_TXOFF3 0x00000800 552#define IXGBE_TFCS_TXOFF4 0x00001000 553#define IXGBE_TFCS_TXOFF5 0x00002000 554#define IXGBE_TFCS_TXOFF6 0x00004000 555#define IXGBE_TFCS_TXOFF7 0x00008000 556 557/* TCP Timer */ 558#define IXGBE_TCPTIMER_KS 0x00000100 559#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 560#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 561#define IXGBE_TCPTIMER_LOOP 0x00000800 562#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 563 564/* HLREG0 Bit Masks */ 565#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 566#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 567#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 568#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 569#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 570#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 571#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 572#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 573#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 574#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 575#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 576#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 577#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 578#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 579#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 580 581/* VMD_CTL bitmasks */ 582#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 583#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 584 585/* RDHMPN and TDHMPN bitmasks */ 586#define IXGBE_RDHMPN_RDICADDR 0x007FF800 587#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 588#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 589#define IXGBE_TDHMPN_TDICADDR 0x003FF800 590#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 591#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 592 593/* Receive Checksum Control */ 594#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 595#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 596 597/* FCRTL Bit Masks */ 598#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */ 599#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */ 600 601/* PAP bit masks*/ 602#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 603 604/* RMCS Bit Masks */ 605#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 606/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 607#define IXGBE_RMCS_RAC 0x00000004 608#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 609#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */ 610#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ 611#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 612 613 614/* Interrupt register bitmasks */ 615 616/* Extended Interrupt Cause Read */ 617#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 618#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 619#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 620#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 621#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 622#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 623#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 624#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 625#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 626 627/* Extended Interrupt Cause Set */ 628#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 629#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* Gen Purpose Interrupt on SDP0 */ 630#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* Gen Purpose Interrupt on SDP1 */ 631#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 632#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 633#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 634#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 635#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 636#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 637 638/* Extended Interrupt Mask Set */ 639#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 640#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* Gen Purpose Interrupt on SDP0 */ 641#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* Gen Purpose Interrupt on SDP1 */ 642#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 643#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 644#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 645#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 646#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 647#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 648 649/* Extended Interrupt Mask Clear */ 650#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 651#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* Gen Purpose Interrupt on SDP0 */ 652#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* Gen Purpose Interrupt on SDP1 */ 653#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 654#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 655#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 656#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 657#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 658#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 659 660#define IXGBE_EIMS_ENABLE_MASK ( \ 661 IXGBE_EIMS_RTX_QUEUE | \ 662 IXGBE_EIMS_LSC | \ 663 IXGBE_EIMS_TCP_TIMER | \ 664 IXGBE_EIMS_OTHER) 665 666/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 667#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 668#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 669#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 670#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 671#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 672#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 673#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 674#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 675#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 676#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 677 678/* Interrupt clear mask */ 679#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 680 681/* Interrupt Vector Allocation Registers */ 682#define IXGBE_IVAR_REG_NUM 25 683#define IXGBE_IVAR_TXRX_ENTRY 96 684#define IXGBE_IVAR_RX_ENTRY 64 685#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 686#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 687#define IXGBE_IVAR_TX_ENTRY 32 688 689#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 690#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 691 692#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 693 694#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 695 696/* VLAN Control Bit Masks */ 697#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 698#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 699#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 700#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 701#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 702 703 704#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 705 706/* STATUS Bit Masks */ 707#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 708#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 709 710#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 711#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 712 713/* ESDP Bit Masks */ 714#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */ 715#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */ 716#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 717#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */ 718 719/* LEDCTL Bit Masks */ 720#define IXGBE_LED_IVRT_BASE 0x00000040 721#define IXGBE_LED_BLINK_BASE 0x00000080 722#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 723#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 724#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 725#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 726#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 727#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 728 729/* LED modes */ 730#define IXGBE_LED_LINK_UP 0x0 731#define IXGBE_LED_LINK_10G 0x1 732#define IXGBE_LED_MAC 0x2 733#define IXGBE_LED_FILTER 0x3 734#define IXGBE_LED_LINK_ACTIVE 0x4 735#define IXGBE_LED_LINK_1G 0x5 736#define IXGBE_LED_ON 0xE 737#define IXGBE_LED_OFF 0xF 738 739/* AUTOC Bit Masks */ 740#define IXGBE_AUTOC_KX4_SUPP 0x80000000 741#define IXGBE_AUTOC_KX_SUPP 0x40000000 742#define IXGBE_AUTOC_PAUSE 0x30000000 743#define IXGBE_AUTOC_RF 0x08000000 744#define IXGBE_AUTOC_PD_TMR 0x06000000 745#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 746#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 747#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 748#define IXGBE_AUTOC_AN_RESTART 0x00001000 749#define IXGBE_AUTOC_FLU 0x00000001 750#define IXGBE_AUTOC_LMS_SHIFT 13 751#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 752#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 753#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 754#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 755#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 756#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 757#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 758 759#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 760#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 761#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 762#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 763#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 764#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 765#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 766#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 767#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 768 769/* LINKS Bit Masks */ 770#define IXGBE_LINKS_KX_AN_COMP 0x80000000 771#define IXGBE_LINKS_UP 0x40000000 772#define IXGBE_LINKS_SPEED 0x20000000 773#define IXGBE_LINKS_MODE 0x18000000 774#define IXGBE_LINKS_RX_MODE 0x06000000 775#define IXGBE_LINKS_TX_MODE 0x01800000 776#define IXGBE_LINKS_XGXS_EN 0x00400000 777#define IXGBE_LINKS_PCS_1G_EN 0x00200000 778#define IXGBE_LINKS_1G_AN_EN 0x00100000 779#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 780#define IXGBE_LINKS_1G_SYNC 0x00040000 781#define IXGBE_LINKS_10G_ALIGN 0x00020000 782#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 783#define IXGBE_LINKS_TL_FAULT 0x00001000 784#define IXGBE_LINKS_SIGNAL 0x00000F00 785 786#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 787#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 788 789#define FIBER_LINK_UP_LIMIT 50 790 791/* PCS1GLSTA Bit Masks */ 792#define IXGBE_PCS1GLSTA_LINK_OK 1 793#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 794#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 795#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 796#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 797#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 798#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 799 800#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 801#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 802 803/* PCS1GLCTL Bit Masks */ 804#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg timeout enable (bit 18) */ 805#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 806#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 807#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 808#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 809#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 810 811/* SW Semaphore Register bitmasks */ 812#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 813#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 814#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 815 816/* GSSR definitions */ 817#define IXGBE_GSSR_EEP_SM 0x0001 818#define IXGBE_GSSR_PHY0_SM 0x0002 819#define IXGBE_GSSR_PHY1_SM 0x0004 820#define IXGBE_GSSR_MAC_CSR_SM 0x0008 821#define IXGBE_GSSR_FLASH_SM 0x0010 822 823/* EEC Register */ 824#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 825#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 826#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 827#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 828#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 829#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 830#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 831#define IXGBE_EEC_FWE_SHIFT 4 832#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 833#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 834#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 835#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 836/* EEPROM Addressing bits based on type (0-small, 1-large) */ 837#define IXGBE_EEC_ADDR_SIZE 0x00000400 838#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 839 840#define IXGBE_EEC_SIZE_SHIFT 11 841#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 842#define IXGBE_EEPROM_OPCODE_BITS 8 843 844/* Checksum and EEPROM pointers */ 845#define IXGBE_EEPROM_CHECKSUM 0x3F 846#define IXGBE_EEPROM_SUM 0xBABA 847#define IXGBE_PCIE_ANALOG_PTR 0x03 848#define IXGBE_ATLAS0_CONFIG_PTR 0x04 849#define IXGBE_ATLAS1_CONFIG_PTR 0x05 850#define IXGBE_PCIE_GENERAL_PTR 0x06 851#define IXGBE_PCIE_CONFIG0_PTR 0x07 852#define IXGBE_PCIE_CONFIG1_PTR 0x08 853#define IXGBE_CORE0_PTR 0x09 854#define IXGBE_CORE1_PTR 0x0A 855#define IXGBE_MAC0_PTR 0x0B 856#define IXGBE_MAC1_PTR 0x0C 857#define IXGBE_CSR0_CONFIG_PTR 0x0D 858#define IXGBE_CSR1_CONFIG_PTR 0x0E 859#define IXGBE_FW_PTR 0x0F 860#define IXGBE_PBANUM0_PTR 0x15 861#define IXGBE_PBANUM1_PTR 0x16 862 863/* Legacy EEPROM word offsets */ 864#define IXGBE_ISCSI_BOOT_CAPS 0x0033 865#define IXGBE_ISCSI_SETUP_PORT_0 0x0030 866#define IXGBE_ISCSI_SETUP_PORT_1 0x0034 867 868/* EEPROM Commands - SPI */ 869#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 870#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 871#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 872#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 873#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 874#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 875/* EEPROM reset Write Enable latch */ 876#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 877#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 878#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 879#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 880#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 881#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 882 883/* EEPROM Read Register */ 884#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */ 885#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */ 886#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */ 887#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */ 888 889#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 890 891#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 892#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 893#endif 894 895#ifndef IXGBE_EERD_ATTEMPTS 896/* Number of 5 microseconds we wait for EERD read to complete */ 897#define IXGBE_EERD_ATTEMPTS 100000 898#endif 899 900/* PCI Bus Info */ 901#define IXGBE_PCI_LINK_STATUS 0xB2 902#define IXGBE_PCI_LINK_WIDTH 0x3F0 903#define IXGBE_PCI_LINK_WIDTH_1 0x10 904#define IXGBE_PCI_LINK_WIDTH_2 0x20 905#define IXGBE_PCI_LINK_WIDTH_4 0x40 906#define IXGBE_PCI_LINK_WIDTH_8 0x80 907#define IXGBE_PCI_LINK_SPEED 0xF 908#define IXGBE_PCI_LINK_SPEED_2500 0x1 909#define IXGBE_PCI_LINK_SPEED_5000 0x2 910#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 911#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 912 913/* Number of 100 microseconds we wait for PCI Express master disable */ 914#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 915 916/* Check whether address is multicast. This is little-endian specific check.*/ 917#define IXGBE_IS_MULTICAST(Address) \ 918 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 919 920/* Check whether an address is broadcast. */ 921#define IXGBE_IS_BROADCAST(Address) \ 922 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 923 (((u8 *)(Address))[1] == ((u8)0xff))) 924 925/* RAH */ 926#define IXGBE_RAH_VIND_MASK 0x003C0000 927#define IXGBE_RAH_VIND_SHIFT 18 928#define IXGBE_RAH_AV 0x80000000 929 930/* Header split receive */ 931#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 932#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 933#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 934#define IXGBE_RFCTL_NFSW_DIS 0x00000040 935#define IXGBE_RFCTL_NFSR_DIS 0x00000080 936#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 937#define IXGBE_RFCTL_NFS_VER_SHIFT 8 938#define IXGBE_RFCTL_NFS_VER_2 0 939#define IXGBE_RFCTL_NFS_VER_3 1 940#define IXGBE_RFCTL_NFS_VER_4 2 941#define IXGBE_RFCTL_IPV6_DIS 0x00000400 942#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 943#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 944#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 945#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 946 947/* Transmit Config masks */ 948#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 949#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 950/* Enable short packet padding to 64 bytes */ 951#define IXGBE_TX_PAD_ENABLE 0x00000400 952#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 953/* This allows for 16K packets + 4k for vlan */ 954#define IXGBE_MAX_FRAME_SZ 0x40040000 955 956#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 957#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq. # write-back enable */ 958 959/* Receive Config masks */ 960#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 961#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 962#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 963 964#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 965#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 966#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 967#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 968#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 969#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 970/* Receive Priority Flow Control Enable */ 971#define IXGBE_FCTRL_RPFCE 0x00004000 972#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 973 974/* Multiple Receive Queue Control */ 975#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 976#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 977#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 978#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 979#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 980#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 981#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 982#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 983#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 984#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 985#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 986 987#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 988#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 989#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 990#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 991#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 992#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 993#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 994#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 995#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 996 997/* Receive Descriptor bit definitions */ 998#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 999#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 1000#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 1001#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 1002#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 1003#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 1004#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 1005#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 1006#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 1007#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 1008#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 1009#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 1010#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 1011#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 1012#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 1013#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 1014#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 1015#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 1016#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 1017#define IXGBE_RXDADV_HBO 0x00800000 1018#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 1019#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 1020#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 1021#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 1022#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 1023#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 1024#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 1025#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 1026#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 1027#define IXGBE_RXD_PRI_SHIFT 13 1028#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 1029#define IXGBE_RXD_CFI_SHIFT 12 1030 1031/* SRRCTL bit definitions */ 1032#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 1033#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 1034#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 1035#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 1036#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 1037#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 1038#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 1039#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 1040#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 1041 1042#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 1043#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 1044 1045#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 1046#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 1047#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 1048#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 1049#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 1050#define IXGBE_RXDADV_SPH 0x8000 1051 1052/* RSS Hash results */ 1053#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 1054#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 1055#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 1056#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 1057#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 1058#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 1059#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 1060#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 1061#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 1062#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 1063 1064/* RSS Packet Types as indicated in the receive descriptor. */ 1065#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 1066#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 1067#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 1068#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 1069#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 1070#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 1071#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 1072#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 1073#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 1074 1075/* Masks to determine if packets should be dropped due to frame errors */ 1076#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 1077 IXGBE_RXD_ERR_CE | \ 1078 IXGBE_RXD_ERR_LE | \ 1079 IXGBE_RXD_ERR_PE | \ 1080 IXGBE_RXD_ERR_OSE | \ 1081 IXGBE_RXD_ERR_USE) 1082 1083#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 1084 IXGBE_RXDADV_ERR_CE | \ 1085 IXGBE_RXDADV_ERR_LE | \ 1086 IXGBE_RXDADV_ERR_PE | \ 1087 IXGBE_RXDADV_ERR_OSE | \ 1088 IXGBE_RXDADV_ERR_USE) 1089 1090/* Multicast bit mask */ 1091#define IXGBE_MCSTCTRL_MFE 0x4 1092 1093/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 1094#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 1095#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 1096#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 1097 1098/* Vlan-specific macros */ 1099#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 1100#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 1101#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 1102#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 1103 1104#ifndef __le16 1105/* Little Endian defines */ 1106#define __le8 u8 1107#define __le16 u16 1108#define __le32 u32 1109#define __le64 u64 1110 1111#endif 1112 1113 1114/* Transmit Descriptor - Legacy */ 1115struct ixgbe_legacy_tx_desc { 1116 u64 buffer_addr; /* Address of the descriptor's data buffer */ 1117 union { 1118 __le32 data; 1119 struct { 1120 __le16 length; /* Data buffer length */ 1121 __le8 cso; /* Checksum offset */ 1122 __le8 cmd; /* Descriptor control */ 1123 } flags; 1124 } lower; 1125 union { 1126 __le32 data; 1127 struct { 1128 __le8 status; /* Descriptor status */ 1129 __le8 css; /* Checksum start */ 1130 __le16 vlan; 1131 } fields; 1132 } upper; 1133}; 1134 1135/* Transmit Descriptor - Advanced */ 1136union ixgbe_adv_tx_desc { 1137 struct { 1138 __le64 buffer_addr; /* Address of descriptor's data buf */ 1139 __le32 cmd_type_len; 1140 __le32 olinfo_status; 1141 } read; 1142 struct { 1143 __le64 rsvd; /* Reserved */ 1144 __le32 nxtseq_seed; 1145 __le32 status; 1146 } wb; 1147}; 1148 1149/* Receive Descriptor - Legacy */ 1150struct ixgbe_legacy_rx_desc { 1151 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 1152 __le16 length; /* Length of data DMAed into data buffer */ 1153 __le16 csum; /* Packet checksum */ 1154 __le8 status; /* Descriptor status */ 1155 __le8 errors; /* Descriptor Errors */ 1156 __le16 vlan; 1157}; 1158 1159/* Receive Descriptor - Advanced */ 1160union ixgbe_adv_rx_desc { 1161 struct { 1162 __le64 pkt_addr; /* Packet buffer address */ 1163 __le64 hdr_addr; /* Header buffer address */ 1164 } read; 1165 struct { 1166 struct { 1167 union { 1168 __le32 data; 1169 struct { 1170 __le16 pkt_info; /* RSS type, Packet type */ 1171 __le16 hdr_info; /* Split Header, header len */ 1172 } hs_rss; 1173 } lo_dword; 1174 union { 1175 __le32 rss; /* RSS Hash */ 1176 struct { 1177 __le16 ip_id; /* IP id */ 1178 __le16 csum; /* Packet Checksum */ 1179 } csum_ip; 1180 } hi_dword; 1181 } lower; 1182 struct { 1183 __le32 status_error; /* ext status/error */ 1184 __le16 length; /* Packet length */ 1185 __le16 vlan; /* VLAN tag */ 1186 } upper; 1187 } wb; /* writeback */ 1188}; 1189 1190/* Context descriptors */ 1191struct ixgbe_adv_tx_context_desc { 1192 __le32 vlan_macip_lens; 1193 __le32 seqnum_seed; 1194 __le32 type_tucmd_mlhl; 1195 __le32 mss_l4len_idx; 1196}; 1197 1198/* Adv Transmit Descriptor Config Masks */ 1199#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */ 1200#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 1201#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 1202#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 1203#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 1204#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 1205#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 1206#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 1207#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 1208#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 1209#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 1210#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 1211#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ 1212#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 1213#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 1214#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 1215#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 1216#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 1217 IXGBE_ADVTXD_POPTS_SHIFT) 1218#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 1219 IXGBE_ADVTXD_POPTS_SHIFT) 1220#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 1221#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 1222#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 1223#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ 1224#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 1225#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 1226#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 1227#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 1228#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 1229#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 1230#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 1231#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 1232#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 1233#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ 1234#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 1235#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 1236 1237/* Autonegotiation advertised speeds */ 1238typedef u32 ixgbe_autoneg_advertised; 1239/* Link speed */ 1240typedef u32 ixgbe_link_speed; 1241#define IXGBE_LINK_SPEED_UNKNOWN 0 1242#define IXGBE_LINK_SPEED_100_FULL 0x0008 1243#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 1244#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 1245#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 1246 IXGBE_LINK_SPEED_10GB_FULL) 1247 1248enum ixgbe_eeprom_type { 1249 ixgbe_eeprom_uninitialized = 0, 1250 ixgbe_eeprom_spi, 1251 ixgbe_eeprom_none /* No NVM support */ 1252}; 1253 1254enum ixgbe_mac_type { 1255 ixgbe_mac_unknown = 0, 1256 ixgbe_mac_82598EB, 1257 ixgbe_num_macs 1258}; 1259 1260enum ixgbe_phy_type { 1261 ixgbe_phy_unknown = 0, 1262 ixgbe_phy_tn, 1263 ixgbe_phy_qt, 1264 ixgbe_phy_xaui, 1265 ixgbe_phy_nl, 1266 ixgbe_phy_generic 1267}; 1268 1269enum ixgbe_media_type { 1270 ixgbe_media_type_unknown = 0, 1271 ixgbe_media_type_fiber, 1272 ixgbe_media_type_copper, 1273 ixgbe_media_type_backplane, 1274 ixgbe_media_type_virtual 1275}; 1276 1277/* Flow Control Settings */ 1278enum ixgbe_fc_type { 1279 ixgbe_fc_none = 0, 1280 ixgbe_fc_rx_pause, 1281 ixgbe_fc_tx_pause, 1282 ixgbe_fc_full, 1283 ixgbe_fc_default 1284}; 1285 1286/* PCI bus types */ 1287enum ixgbe_bus_type { 1288 ixgbe_bus_type_unknown = 0, 1289 ixgbe_bus_type_pci, 1290 ixgbe_bus_type_pcix, 1291 ixgbe_bus_type_pci_express, 1292 ixgbe_bus_type_reserved 1293}; 1294 1295/* PCI bus speeds */ 1296enum ixgbe_bus_speed { 1297 ixgbe_bus_speed_unknown = 0, 1298 ixgbe_bus_speed_33, 1299 ixgbe_bus_speed_66, 1300 ixgbe_bus_speed_100, 1301 ixgbe_bus_speed_120, 1302 ixgbe_bus_speed_133, 1303 ixgbe_bus_speed_2500, 1304 ixgbe_bus_speed_5000, 1305 ixgbe_bus_speed_reserved 1306}; 1307 1308/* PCI bus widths */ 1309enum ixgbe_bus_width { 1310 ixgbe_bus_width_unknown = 0, 1311 ixgbe_bus_width_pcie_x1, 1312 ixgbe_bus_width_pcie_x2, 1313 ixgbe_bus_width_pcie_x4 = 4, 1314 ixgbe_bus_width_pcie_x8 = 8, 1315 ixgbe_bus_width_32, 1316 ixgbe_bus_width_64, 1317 ixgbe_bus_width_reserved 1318}; 1319 1320struct ixgbe_addr_filter_info { 1321 u32 num_mc_addrs; 1322 u32 rar_used_count; 1323 u32 mc_addr_in_rar_count; 1324 u32 mta_in_use; 1325 u32 overflow_promisc; 1326 bool user_set_promisc; 1327}; 1328 1329/* Bus parameters */ 1330struct ixgbe_bus_info { 1331 enum ixgbe_bus_speed speed; 1332 enum ixgbe_bus_width width; 1333 enum ixgbe_bus_type type; 1334}; 1335 1336/* Flow control parameters */ 1337struct ixgbe_fc_info { 1338 u32 high_water; /* Flow Control High-water */ 1339 u32 low_water; /* Flow Control Low-water */ 1340 u16 pause_time; /* Flow Control Pause timer */ 1341 bool send_xon; /* Flow control send XON */ 1342 bool strict_ieee; /* Strict IEEE mode */ 1343 enum ixgbe_fc_type type; /* Type of flow control */ 1344 enum ixgbe_fc_type original_type; 1345}; 1346 1347/* Statistics counters collected by the MAC */ 1348struct ixgbe_hw_stats { 1349 u64 crcerrs; 1350 u64 illerrc; 1351 u64 errbc; 1352 u64 mspdc; 1353 u64 mpctotal; 1354 u64 mpc[8]; 1355 u64 mlfc; 1356 u64 mrfc; 1357 u64 rlec; 1358 u64 lxontxc; 1359 u64 lxonrxc; 1360 u64 lxofftxc; 1361 u64 lxoffrxc; 1362 u64 pxontxc[8]; 1363 u64 pxonrxc[8]; 1364 u64 pxofftxc[8]; 1365 u64 pxoffrxc[8]; 1366 u64 prc64; 1367 u64 prc127; 1368 u64 prc255; 1369 u64 prc511; 1370 u64 prc1023; 1371 u64 prc1522; 1372 u64 gprc; 1373 u64 bprc; 1374 u64 mprc; 1375 u64 gptc; 1376 u64 gorc; 1377 u64 gotc; 1378 u64 rnbc[8]; 1379 u64 ruc; 1380 u64 rfc; 1381 u64 roc; 1382 u64 rjc; 1383 u64 mngprc; 1384 u64 mngpdc; 1385 u64 mngptc; 1386 u64 tor; 1387 u64 tpr; 1388 u64 tpt; 1389 u64 ptc64; 1390 u64 ptc127; 1391 u64 ptc255; 1392 u64 ptc511; 1393 u64 ptc1023; 1394 u64 ptc1522; 1395 u64 mptc; 1396 u64 bptc; 1397 u64 xec; 1398 u64 rqsmr[16]; 1399 u64 tqsmr[8]; 1400 u64 qprc[16]; 1401 u64 qptc[16]; 1402 u64 qbrc[16]; 1403 u64 qbtc[16]; 1404}; 1405 1406/* forward declaration */ 1407struct ixgbe_hw; 1408 1409/* iterator type for walking multicast address lists */ 1410typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 1411 u32 *vmdq); 1412 1413/* Function pointer table */ 1414struct ixgbe_eeprom_operations { 1415 s32 (*init_params)(struct ixgbe_hw *); 1416 s32 (*read)(struct ixgbe_hw *, u16, u16 *); 1417 s32 (*write)(struct ixgbe_hw *, u16, u16); 1418 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 1419 s32 (*update_checksum)(struct ixgbe_hw *); 1420}; 1421 1422struct ixgbe_mac_operations { 1423 s32 (*init_hw)(struct ixgbe_hw *); 1424 s32 (*reset_hw)(struct ixgbe_hw *); 1425 s32 (*start_hw)(struct ixgbe_hw *); 1426 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 1427 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 1428 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 1429 s32 (*stop_adapter)(struct ixgbe_hw *); 1430 s32 (*get_bus_info)(struct ixgbe_hw *); 1431 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 1432 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 1433 1434 /* Link */ 1435 s32 (*setup_link)(struct ixgbe_hw *); 1436 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, 1437 bool); 1438 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 1439 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 1440 bool *); 1441 1442 /* LED */ 1443 s32 (*led_on)(struct ixgbe_hw *, u32); 1444 s32 (*led_off)(struct ixgbe_hw *, u32); 1445 s32 (*blink_led_start)(struct ixgbe_hw *, u32); 1446 s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 1447 1448 /* RAR, Multicast, VLAN */ 1449 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 1450 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 1451 s32 (*init_rx_addrs)(struct ixgbe_hw *); 1452 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 1453 ixgbe_mc_addr_itr); 1454 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 1455 ixgbe_mc_addr_itr); 1456 s32 (*enable_mc)(struct ixgbe_hw *); 1457 s32 (*disable_mc)(struct ixgbe_hw *); 1458 s32 (*clear_vfta)(struct ixgbe_hw *); 1459 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool); 1460 1461 /* Flow Control */ 1462 s32 (*setup_fc)(struct ixgbe_hw *, s32); 1463}; 1464 1465struct ixgbe_phy_operations { 1466 s32 (*identify)(struct ixgbe_hw *); 1467 s32 (*reset)(struct ixgbe_hw *); 1468 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 1469 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 1470 s32 (*setup_link)(struct ixgbe_hw *); 1471 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool, 1472 bool); 1473 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 1474 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 1475}; 1476 1477struct ixgbe_eeprom_info { 1478 struct ixgbe_eeprom_operations ops; 1479 enum ixgbe_eeprom_type type; 1480 u16 word_size; 1481 u16 address_bits; 1482}; 1483 1484struct ixgbe_mac_info { 1485 struct ixgbe_mac_operations ops; 1486 enum ixgbe_mac_type type; 1487 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1488 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1489 s32 mc_filter_type; 1490 u32 mcft_size; 1491 u32 vft_size; 1492 u32 num_rar_entries; 1493 u32 max_tx_queues; 1494 u32 max_rx_queues; 1495 u32 link_attach_type; 1496 u32 link_mode_select; 1497 bool link_settings_loaded; 1498 bool autoneg; 1499 bool autoneg_failed; 1500}; 1501 1502struct ixgbe_phy_info { 1503 struct ixgbe_phy_operations ops; 1504 enum ixgbe_phy_type type; 1505 u32 addr; 1506 u32 id; 1507 u32 revision; 1508 enum ixgbe_media_type media_type; 1509 bool reset_disable; 1510 ixgbe_autoneg_advertised autoneg_advertised; 1511 bool autoneg_wait_to_complete; 1512}; 1513 1514struct ixgbe_hw { 1515 u8 *hw_addr; 1516 void *back; 1517 struct ixgbe_mac_info mac; 1518 struct ixgbe_addr_filter_info addr_ctrl; 1519 struct ixgbe_fc_info fc; 1520 struct ixgbe_phy_info phy; 1521 struct ixgbe_eeprom_info eeprom; 1522 struct ixgbe_bus_info bus; 1523 u16 device_id; 1524 u16 vendor_id; 1525 u16 subsystem_device_id; 1526 u16 subsystem_vendor_id; 1527 u8 revision_id; 1528 bool adapter_stopped; 1529}; 1530 1531#define ixgbe_call_func(hw, func, params, error) \ 1532 (func != NULL) ? func params: error 1533 1534/* Error Codes */ 1535#define IXGBE_SUCCESS 0 1536#define IXGBE_ERR_EEPROM -1 1537#define IXGBE_ERR_EEPROM_CHECKSUM -2 1538#define IXGBE_ERR_PHY -3 1539#define IXGBE_ERR_CONFIG -4 1540#define IXGBE_ERR_PARAM -5 1541#define IXGBE_ERR_MAC_TYPE -6 1542#define IXGBE_ERR_UNKNOWN_PHY -7 1543#define IXGBE_ERR_LINK_SETUP -8 1544#define IXGBE_ERR_ADAPTER_STOPPED -9 1545#define IXGBE_ERR_INVALID_MAC_ADDR -10 1546#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 1547#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 1548#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 1549#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 1550#define IXGBE_ERR_RESET_FAILED -15 1551#define IXGBE_ERR_SWFW_SYNC -16 1552#define IXGBE_ERR_PHY_ADDR_INVALID -17 1553#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 1554 1555#define UNREFERENCED_PARAMETER(_p) 1556 1557#endif /* _IXGBE_TYPE_H_ */ 1558