ixgbe_type.h revision 171411
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33/* $FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 171384 2007-07-11 23:03:16Z jfv $ */ 34 35#ifndef _IXGBE_TYPE_H_ 36#define _IXGBE_TYPE_H_ 37 38#include "ixgbe_osdep.h" 39 40/* Vendor ID */ 41#define IXGBE_INTEL_VENDOR_ID 0x8086 42 43/* Device IDs */ 44#define IXGBE_DEV_ID_82598 0x10B6 45#define IXGBE_DEV_ID_82598_FPGA 0xF0C0 46#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 47#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 48#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8 49 50/* General Registers */ 51#define IXGBE_CTRL 0x00000 52#define IXGBE_STATUS 0x00008 53#define IXGBE_CTRL_EXT 0x00018 54#define IXGBE_ESDP 0x00020 55#define IXGBE_EODSDP 0x00028 56#define IXGBE_LEDCTL 0x00200 57#define IXGBE_FRTIMER 0x00048 58#define IXGBE_TCPTIMER 0x0004C 59 60/* NVM Registers */ 61#define IXGBE_EEC 0x10010 62#define IXGBE_EERD 0x10014 63#define IXGBE_FLA 0x1001C 64#define IXGBE_EEMNGCTL 0x10110 65#define IXGBE_EEMNGDATA 0x10114 66#define IXGBE_FLMNGCTL 0x10118 67#define IXGBE_FLMNGDATA 0x1011C 68#define IXGBE_FLMNGCNT 0x10120 69#define IXGBE_FLOP 0x1013C 70#define IXGBE_GRC 0x10200 71 72/* Interrupt Registers */ 73#define IXGBE_EICR 0x00800 74#define IXGBE_EICS 0x00808 75#define IXGBE_EIMS 0x00880 76#define IXGBE_EIMC 0x00888 77#define IXGBE_EIAC 0x00810 78#define IXGBE_EIAM 0x00890 79#define IXGBE_EITR(_i) (0x00820 + ((_i) * 4)) /* 0x820-0x86c */ 80#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 81#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 82#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 83#define IXGBE_PBACL 0x11068 84#define IXGBE_GPIE 0x00898 85 86/* Flow Control Registers */ 87#define IXGBE_PFCTOP 0x03008 88#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 89#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 90#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 91#define IXGBE_FCRTV 0x032A0 92#define IXGBE_TFCS 0x0CE00 93 94/* Receive DMA Registers */ 95#define IXGBE_RDBAL(_i) (0x01000 + ((_i) * 0x40)) /* 64 of each (0-63)*/ 96#define IXGBE_RDBAH(_i) (0x01004 + ((_i) * 0x40)) 97#define IXGBE_RDLEN(_i) (0x01008 + ((_i) * 0x40)) 98#define IXGBE_RDH(_i) (0x01010 + ((_i) * 0x40)) 99#define IXGBE_RDT(_i) (0x01018 + ((_i) * 0x40)) 100#define IXGBE_RXDCTL(_i) (0x01028 + ((_i) * 0x40)) 101#define IXGBE_SRRCTL(_i) (0x02100 + ((_i) * 4)) 102 /* array of 16 (0x02100-0x0213C) */ 103#define IXGBE_DCA_RXCTRL(_i) (0x02200 + ((_i) * 4)) 104 /* array of 16 (0x02200-0x0223C) */ 105#define IXGBE_RDRXCTL 0x02F00 106#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 107 /* 8 of these 0x03C00 - 0x03C1C */ 108#define IXGBE_RXCTRL 0x03000 109#define IXGBE_DROPEN 0x03D04 110#define IXGBE_RXPBSIZE_SHIFT 10 111 112/* Receive Registers */ 113#define IXGBE_RXCSUM 0x05000 114#define IXGBE_RFCTL 0x05008 115#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 116 /* Multicast Table Array - 128 entries */ 117#define IXGBE_RAL(_i) (0x05400 + ((_i) * 8)) /* 16 of these (0-15) */ 118#define IXGBE_RAH(_i) (0x05404 + ((_i) * 8)) /* 16 of these (0-15) */ 119#define IXGBE_PSRTYPE 0x05480 120 /* 0x5480-0x54BC Packet split receive type */ 121#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 122 /* array of 4096 1-bit vlan filters */ 123#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 124 /*array of 4096 4-bit vlan vmdq indicies */ 125#define IXGBE_FCTRL 0x05080 126#define IXGBE_VLNCTRL 0x05088 127#define IXGBE_MCSTCTRL 0x05090 128#define IXGBE_MRQC 0x05818 129#define IXGBE_VMD_CTL 0x0581C 130#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 131#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 132#define IXGBE_IMIRVP 0x05AC0 133#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 134#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 135 136/* Transmit DMA registers */ 137#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))/* 32 of these (0-31)*/ 138#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 139#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 140#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 141#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 142#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 143#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 144#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 145#define IXGBE_DTXCTL 0x07E00 146#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 147 /* there are 16 of these (0-15) */ 148#define IXGBE_TIPG 0x0CB00 149#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) 150 /* there are 8 of these */ 151#define IXGBE_MNGTXMAP 0x0CD10 152#define IXGBE_TIPG_FIBER_DEFAULT 3 153#define IXGBE_TXPBSIZE_SHIFT 10 154 155/* Wake up registers */ 156#define IXGBE_WUC 0x05800 157#define IXGBE_WUFC 0x05808 158#define IXGBE_WUS 0x05810 159#define IXGBE_IPAV 0x05838 160#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 161#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 162#define IXGBE_WUPL 0x05900 163#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 164#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ 165 166/* Music registers */ 167#define IXGBE_RMCS 0x03D00 168#define IXGBE_DPMCS 0x07F40 169#define IXGBE_PDPMCS 0x0CD00 170#define IXGBE_RUPPBMR 0x050A0 171#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 172#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 173#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 174#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 175#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 176#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 177 178/* Stats registers */ 179#define IXGBE_CRCERRS 0x04000 180#define IXGBE_ILLERRC 0x04004 181#define IXGBE_ERRBC 0x04008 182#define IXGBE_MSPDC 0x04010 183#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 184#define IXGBE_MLFC 0x04034 185#define IXGBE_MRFC 0x04038 186#define IXGBE_RLEC 0x04040 187#define IXGBE_LXONTXC 0x03F60 188#define IXGBE_LXONRXC 0x0CF60 189#define IXGBE_LXOFFTXC 0x03F68 190#define IXGBE_LXOFFRXC 0x0CF68 191#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 192#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 193#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 194#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 195#define IXGBE_PRC64 0x0405C 196#define IXGBE_PRC127 0x04060 197#define IXGBE_PRC255 0x04064 198#define IXGBE_PRC511 0x04068 199#define IXGBE_PRC1023 0x0406C 200#define IXGBE_PRC1522 0x04070 201#define IXGBE_GPRC 0x04074 202#define IXGBE_BPRC 0x04078 203#define IXGBE_MPRC 0x0407C 204#define IXGBE_GPTC 0x04080 205#define IXGBE_GORCL 0x04088 206#define IXGBE_GORCH 0x0408C 207#define IXGBE_GOTCL 0x04090 208#define IXGBE_GOTCH 0x04094 209#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 210#define IXGBE_RUC 0x040A4 211#define IXGBE_RFC 0x040A8 212#define IXGBE_ROC 0x040AC 213#define IXGBE_RJC 0x040B0 214#define IXGBE_MNGPRC 0x040B4 215#define IXGBE_MNGPDC 0x040B8 216#define IXGBE_MNGPTC 0x0CF90 217#define IXGBE_TORL 0x040C0 218#define IXGBE_TORH 0x040C4 219#define IXGBE_TPR 0x040D0 220#define IXGBE_TPT 0x040D4 221#define IXGBE_PTC64 0x040D8 222#define IXGBE_PTC127 0x040DC 223#define IXGBE_PTC255 0x040E0 224#define IXGBE_PTC511 0x040E4 225#define IXGBE_PTC1023 0x040E8 226#define IXGBE_PTC1522 0x040EC 227#define IXGBE_MPTC 0x040F0 228#define IXGBE_BPTC 0x040F4 229#define IXGBE_XEC 0x04120 230 231#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ 232#define IXGBE_TQSMR(_i) (0x07300 + ((_i) * 4)) /* 8 of these */ 233 234#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 235#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 236#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 237#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 238 239/* Management */ 240#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 241#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 242#define IXGBE_MANC 0x05820 243#define IXGBE_MFVAL 0x05824 244#define IXGBE_MANC2H 0x05860 245#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 246#define IXGBE_MIPAF 0x058B0 247#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 248#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 249#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 250 251/* ARC Subsystem registers */ 252#define IXGBE_HICR 0x15F00 253#define IXGBE_FWSTS 0x15F0C 254#define IXGBE_HSMC0R 0x15F04 255#define IXGBE_HSMC1R 0x15F08 256#define IXGBE_SWSR 0x15F10 257#define IXGBE_HFDR 0x15FE8 258#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 259 260/* PCI-E registers */ 261#define IXGBE_GCR 0x11000 262#define IXGBE_GTV 0x11004 263#define IXGBE_FUNCTAG 0x11008 264#define IXGBE_GLT 0x1100C 265#define IXGBE_GSCL_1 0x11010 266#define IXGBE_GSCL_2 0x11014 267#define IXGBE_GSCL_3 0x11018 268#define IXGBE_GSCL_4 0x1101C 269#define IXGBE_GSCN_0 0x11020 270#define IXGBE_GSCN_1 0x11024 271#define IXGBE_GSCN_2 0x11028 272#define IXGBE_GSCN_3 0x1102C 273#define IXGBE_FACTPS 0x10150 274#define IXGBE_PCIEANACTL 0x11040 275#define IXGBE_SWSM 0x10140 276#define IXGBE_FWSM 0x10148 277#define IXGBE_GSSR 0x10160 278#define IXGBE_MREVID 0x11064 279#define IXGBE_DCA_ID 0x11070 280#define IXGBE_DCA_CTRL 0x11074 281 282/* Diagnostic Registers */ 283#define IXGBE_RDSTATCTL 0x02C20 284#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 285#define IXGBE_RDHMPN 0x02F08 286#define IXGBE_RIC_DW0 0x02F10 287#define IXGBE_RIC_DW1 0x02F14 288#define IXGBE_RIC_DW2 0x02F18 289#define IXGBE_RIC_DW3 0x02F1C 290#define IXGBE_RDPROBE 0x02F20 291#define IXGBE_TDSTATCTL 0x07C20 292#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 293#define IXGBE_TDHMPN 0x07F08 294#define IXGBE_TIC_DW0 0x07F10 295#define IXGBE_TIC_DW1 0x07F14 296#define IXGBE_TIC_DW2 0x07F18 297#define IXGBE_TIC_DW3 0x07F1C 298#define IXGBE_TDPROBE 0x07F20 299#define IXGBE_TXBUFCTRL 0x0C600 300#define IXGBE_TXBUFDATA0 0x0C610 301#define IXGBE_TXBUFDATA1 0x0C614 302#define IXGBE_TXBUFDATA2 0x0C618 303#define IXGBE_TXBUFDATA3 0x0C61C 304#define IXGBE_RXBUFCTRL 0x03600 305#define IXGBE_RXBUFDATA0 0x03610 306#define IXGBE_RXBUFDATA1 0x03614 307#define IXGBE_RXBUFDATA2 0x03618 308#define IXGBE_RXBUFDATA3 0x0361C 309#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 310#define IXGBE_RFVAL 0x050A4 311#define IXGBE_MDFTC1 0x042B8 312#define IXGBE_MDFTC2 0x042C0 313#define IXGBE_MDFTFIFO1 0x042C4 314#define IXGBE_MDFTFIFO2 0x042C8 315#define IXGBE_MDFTS 0x042CC 316#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 317#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 318#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 319#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 320#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 321#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 322#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 323#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 324#define IXGBE_PCIEECCCTL 0x1106C 325#define IXGBE_PBTXECC 0x0C300 326#define IXGBE_PBRXECC 0x03300 327#define IXGBE_GHECCR 0x110B0 328 329/* MAC Registers */ 330#define IXGBE_PCS1GCFIG 0x04200 331#define IXGBE_PCS1GLCTL 0x04208 332#define IXGBE_PCS1GLSTA 0x0420C 333#define IXGBE_PCS1GDBG0 0x04210 334#define IXGBE_PCS1GDBG1 0x04214 335#define IXGBE_PCS1GANA 0x04218 336#define IXGBE_PCS1GANLP 0x0421C 337#define IXGBE_PCS1GANNP 0x04220 338#define IXGBE_PCS1GANLPNP 0x04224 339#define IXGBE_HLREG0 0x04240 340#define IXGBE_HLREG1 0x04244 341#define IXGBE_PAP 0x04248 342#define IXGBE_MACA 0x0424C 343#define IXGBE_APAE 0x04250 344#define IXGBE_ARD 0x04254 345#define IXGBE_AIS 0x04258 346#define IXGBE_MSCA 0x0425C 347#define IXGBE_MSRWD 0x04260 348#define IXGBE_MLADD 0x04264 349#define IXGBE_MHADD 0x04268 350#define IXGBE_TREG 0x0426C 351#define IXGBE_PCSS1 0x04288 352#define IXGBE_PCSS2 0x0428C 353#define IXGBE_XPCSS 0x04290 354#define IXGBE_SERDESC 0x04298 355#define IXGBE_MACS 0x0429C 356#define IXGBE_AUTOC 0x042A0 357#define IXGBE_LINKS 0x042A4 358#define IXGBE_AUTOC2 0x042A8 359#define IXGBE_AUTOC3 0x042AC 360#define IXGBE_ANLP1 0x042B0 361#define IXGBE_ANLP2 0x042B4 362#define IXGBE_ATLASCTL 0x04800 363 364 365/* CTRL Bit Masks */ 366#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 367#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 368#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 369 370/* FACTPS */ 371#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 372 373/* MHADD Bit Masks */ 374#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 375#define IXGBE_MHADD_MFS_SHIFT 16 376 377/* Extended Device Control */ 378#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 379#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 380#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 381 382/* Direct Cache Access (DCA) definitions */ 383#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 384#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 385 386#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 387#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 388 389#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 390#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 391#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 392#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 393 394#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 395#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 396 397/* MSCA Bit Masks */ 398#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 399#define IXGBE_MSCA_NP_ADDR_SHIFT 0 400#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 401#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 402#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 403#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 404#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 405#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 406#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 407#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 408#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */ 409#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/ 410#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 411#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 412#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 413#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 414#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 415#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 416 417/* MSRWD bit masks */ 418#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 419#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 420#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 421#define IXGBE_MSRWD_READ_DATA_SHIFT 16 422 423/* Device Type definitions for new protocol MDIO commands */ 424#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 425#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 426#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 427#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 428#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 429 430#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ 431#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 432#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 433#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 434#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 435#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 436 437#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 438#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 439#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 440#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 441#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 442#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 443#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Abilty Reg */ 444#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 445#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 446 447#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 448#define IXGBE_MAX_PHY_ADDR 32 449 450/* PHY IDs*/ 451#define TN1010_PHY_ID 0x00A19410 452#define QT2022_PHY_ID 0x0043A400 453 454/* General purpose Interrupt Enable */ 455#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 456#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 457#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 458#define IXGBE_GPIE_EIAME 0x40000000 459#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 460 461/* Transmit Flow Control status */ 462#define IXGBE_TFCS_TXOFF 0x00000001 463#define IXGBE_TFCS_TXOFF0 0x00000100 464#define IXGBE_TFCS_TXOFF1 0x00000200 465#define IXGBE_TFCS_TXOFF2 0x00000400 466#define IXGBE_TFCS_TXOFF3 0x00000800 467#define IXGBE_TFCS_TXOFF4 0x00001000 468#define IXGBE_TFCS_TXOFF5 0x00002000 469#define IXGBE_TFCS_TXOFF6 0x00004000 470#define IXGBE_TFCS_TXOFF7 0x00008000 471 472/* TCP Timer */ 473#define IXGBE_TCPTIMER_KS 0x00000100 474#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 475#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 476#define IXGBE_TCPTIMER_LOOP 0x00000800 477#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 478 479/* HLREG0 Bit Masks */ 480#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 481#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 482#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 483#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 484#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 485#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 486#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 487#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 488#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 489#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 490#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 491#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 492#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 493#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 494#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 495 496/* VMD_CTL bitmasks */ 497#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 498#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 499 500/* RDHMPN and TDHMPN bitmasks */ 501#define IXGBE_RDHMPN_RDICADDR 0x007FF800 502#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 503#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 504#define IXGBE_TDHMPN_TDICADDR 0x003FF800 505#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 506#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 507 508/* Receive Checksum Control */ 509#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 510#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 511 512/* FCRTL Bit Masks */ 513#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */ 514#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */ 515 516/* PAP bit masks*/ 517#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 518 519/* RMCS Bit Masks */ 520#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recylce Mode enable */ 521/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 522#define IXGBE_RMCS_RAC 0x00000004 523#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 524#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */ 525#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ 526#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 527 528/* Interrupt register bitmasks */ 529 530/* Extended Interrupt Cause Read */ 531#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 532#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 533#define IXGBE_EICR_MNG 0x00400000 /* Managability Event Interrupt */ 534#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 535#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 536#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 537#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 538 539/* Extended Interrupt Cause Set */ 540#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 541#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 542#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 543#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 544#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 545#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 546#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 547#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 548 549/* Extended Interrupt Mask Set */ 550#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 551#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 552#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 553#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 554#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 555#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 556#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 557 558/* Extended Interrupt Mask Clear */ 559#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 560#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 561#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 562#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 563#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 564#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 565#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 566 567#define IXGBE_EIMS_ENABLE_MASK ( \ 568 IXGBE_EIMS_RTX_QUEUE | \ 569 IXGBE_EIMS_LSC | \ 570 IXGBE_EIMS_TCP_TIMER | \ 571 IXGBE_EIMS_OTHER) 572 573/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */ 574#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 575#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 576#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 577#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 578#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 579#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 580#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 581#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 582#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 583#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 584 585/* Interrupt clear mask */ 586#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 587 588/* Interrupt Vector Allocation Registers */ 589#define IXGBE_IVAR_REG_NUM 25 590#define IXGBE_IVAR_TXRX_ENTRY 96 591#define IXGBE_IVAR_RX_ENTRY 64 592#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 593#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 594#define IXGBE_IVAR_TX_ENTRY 32 595 596#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 597#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 598 599#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 600 601#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 602 603/* VLAN Control Bit Masks */ 604#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 605#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 606#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 607#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 608#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 609 610#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 611 612/* STATUS Bit Masks */ 613#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 614#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 615 616#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 617#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 618 619/* ESDP Bit Masks */ 620#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */ 621#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */ 622#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 623#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */ 624 625/* LEDCTL Bit Masks */ 626#define IXGBE_LED_IVRT_BASE 0x00000040 627#define IXGBE_LED_BLINK_BASE 0x00000080 628#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 629#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 630#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 631#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 632#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 633#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 634 635/* LED modes */ 636#define IXGBE_LED_LINK_UP 0x0 637#define IXGBE_LED_LINK_10G 0x1 638#define IXGBE_LED_MAC 0x2 639#define IXGBE_LED_FILTER 0x3 640#define IXGBE_LED_LINK_ACTIVE 0x4 641#define IXGBE_LED_LINK_1G 0x5 642#define IXGBE_LED_ON 0xE 643#define IXGBE_LED_OFF 0xF 644 645/* AUTOC Bit Masks */ 646#define IXGBE_AUTOC_KX4_SUPP 0x80000000 647#define IXGBE_AUTOC_KX_SUPP 0x40000000 648#define IXGBE_AUTOC_PAUSE 0x30000000 649#define IXGBE_AUTOC_RF 0x08000000 650#define IXGBE_AUTOC_PD_TMR 0x06000000 651#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 652#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 653#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 654#define IXGBE_AUTOC_AN_RESTART 0x00001000 655#define IXGBE_AUTOC_FLU 0x00000001 656#define IXGBE_AUTOC_LMS_SHIFT 13 657#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 658#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 659#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 660#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 661#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 662#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 663#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 664 665#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 666#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 667#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 668#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 669#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 670#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 671#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 672#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 673#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 674 675/* LINKS Bit Masks */ 676#define IXGBE_LINKS_KX_AN_COMP 0x80000000 677#define IXGBE_LINKS_UP 0x40000000 678#define IXGBE_LINKS_SPEED 0x20000000 679#define IXGBE_LINKS_MODE 0x18000000 680#define IXGBE_LINKS_RX_MODE 0x06000000 681#define IXGBE_LINKS_TX_MODE 0x01800000 682#define IXGBE_LINKS_XGXS_EN 0x00400000 683#define IXGBE_LINKS_PCS_1G_EN 0x00200000 684#define IXGBE_LINKS_1G_AN_EN 0x00100000 685#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 686#define IXGBE_LINKS_1G_SYNC 0x00040000 687#define IXGBE_LINKS_10G_ALIGN 0x00020000 688#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 689#define IXGBE_LINKS_TL_FAULT 0x00001000 690#define IXGBE_LINKS_SIGNAL 0x00000F00 691 692#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 693 694/* SW Semaphore Register bitmasks */ 695#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 696#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 697#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 698 699/* GSSR definitions */ 700#define IXGBE_GSSR_EEP_SM 0x0001 701#define IXGBE_GSSR_PHY0_SM 0x0002 702#define IXGBE_GSSR_PHY1_SM 0x0004 703#define IXGBE_GSSR_MAC_CSR_SM 0x0008 704#define IXGBE_GSSR_FLASH_SM 0x0010 705 706/* EEC Register */ 707#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 708#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 709#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 710#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 711#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 712#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 713#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 714#define IXGBE_EEC_FWE_SHIFT 4 715#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 716#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 717#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 718#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 719/* EEPROM Addressing bits based on type (0-small, 1-large) */ 720#define IXGBE_EEC_ADDR_SIZE 0x00000400 721#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 722 723#define IXGBE_EEC_SIZE_SHIFT 11 724#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 725#define IXGBE_EEPROM_OPCODE_BITS 8 726 727/* Checksum and EEPROM pointers */ 728#define IXGBE_EEPROM_CHECKSUM 0x3F 729#define IXGBE_EEPROM_SUM 0xBABA 730#define IXGBE_PCIE_ANALOG_PTR 0x03 731#define IXGBE_ATLAS0_CONFIG_PTR 0x04 732#define IXGBE_ATLAS1_CONFIG_PTR 0x05 733#define IXGBE_PCIE_GENERAL_PTR 0x06 734#define IXGBE_PCIE_CONFIG0_PTR 0x07 735#define IXGBE_PCIE_CONFIG1_PTR 0x08 736#define IXGBE_CORE0_PTR 0x09 737#define IXGBE_CORE1_PTR 0x0A 738#define IXGBE_MAC0_PTR 0x0B 739#define IXGBE_MAC1_PTR 0x0C 740#define IXGBE_CSR0_CONFIG_PTR 0x0D 741#define IXGBE_CSR1_CONFIG_PTR 0x0E 742#define IXGBE_FW_PTR 0x0F 743 744/* EEPROM Commands - SPI */ 745#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 746#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 747#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 748#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 749#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 750#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 751/* EEPROM reset Write Enbale latch */ 752#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 753#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 754#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 755#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 756#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 757#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 758 759/* EEPROM Read Register */ 760#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */ 761#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */ 762#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */ 763#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */ 764 765#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 766 767#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 768#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 769#endif 770 771#ifndef IXGBE_EERD_ATTEMPTS 772/* Number of 5 microseconds we wait for EERD read to complete */ 773#define IXGBE_EERD_ATTEMPTS 100000 774#endif 775 776/* PCI Bus Info */ 777#define IXGBE_PCI_LINK_STATUS 0xB2 778#define IXGBE_PCI_LINK_WIDTH 0x3F0 779#define IXGBE_PCI_LINK_WIDTH_1 0x10 780#define IXGBE_PCI_LINK_WIDTH_2 0x20 781#define IXGBE_PCI_LINK_WIDTH_4 0x40 782#define IXGBE_PCI_LINK_WIDTH_8 0x80 783#define IXGBE_PCI_LINK_SPEED 0xF 784#define IXGBE_PCI_LINK_SPEED_2500 0x1 785#define IXGBE_PCI_LINK_SPEED_5000 0x2 786 787/* Number of 100 microseconds we wait for PCI Express master disable */ 788#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 789 790/* PHY Types */ 791#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 792 793/* Check whether address is multicast. This is little-endian specific check.*/ 794#define IXGBE_IS_MULTICAST(Address) \ 795 (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 796 797/* Check whether an address is broadcast. */ 798#define IXGBE_IS_BROADCAST(Address) \ 799 ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 800 (((u8 *)(Address))[1] == ((u8)0xff))) 801 802/* RAH */ 803#define IXGBE_RAH_VIND_MASK 0x003C0000 804#define IXGBE_RAH_VIND_SHIFT 18 805#define IXGBE_RAH_AV 0x80000000 806 807/* Filters */ 808#define IXGBE_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 809#define IXGBE_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 810 811/* Header split receive */ 812#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 813#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 814#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 815#define IXGBE_RFCTL_NFSW_DIS 0x00000040 816#define IXGBE_RFCTL_NFSR_DIS 0x00000080 817#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 818#define IXGBE_RFCTL_NFS_VER_SHIFT 8 819#define IXGBE_RFCTL_NFS_VER_2 0 820#define IXGBE_RFCTL_NFS_VER_3 1 821#define IXGBE_RFCTL_NFS_VER_4 2 822#define IXGBE_RFCTL_IPV6_DIS 0x00000400 823#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 824#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 825#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 826#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 827 828/* Transmit Config masks */ 829#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 830#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 831/* Enable short packet padding to 64 bytes */ 832#define IXGBE_TX_PAD_ENABLE 0x00000400 833#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 834/* This allows for 16K packets + 4k for vlan */ 835#define IXGBE_MAX_FRAME_SZ 0x40040000 836 837#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 838#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq. # write-back enable */ 839 840/* Receive Config masks */ 841#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 842#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 843#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 844 845#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 846#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 847#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 848#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 849#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 850#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 851/* Receive Priority Flow Control Enbale */ 852#define IXGBE_FCTRL_RPFCE 0x00004000 853#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 854 855/* Multiple Receive Queue Control */ 856#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 857#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 858#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 859#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 860#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 861#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 862#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 863#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 864#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 865#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 866#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 867 868#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 869#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 870#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 871#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 872#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 873#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 874#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 875#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 876#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 877 878/* Receive Descriptor bit definitions */ 879#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 880#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 881#define IXGBE_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 882#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 883#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 884#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 885#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 886#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 887#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 888#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 889#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 890#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 891#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 892#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 893#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 894#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 895#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 896#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 897#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 898#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 899#define IXGBE_RXDADV_HBO 0x00800000 900#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 901#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 902#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 903#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 904#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 905#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 906#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 907#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 908#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 909#define IXGBE_RXD_PRI_SHIFT 13 910#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 911#define IXGBE_RXD_CFI_SHIFT 12 912 913/* SRRCTL bit definitions */ 914#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 915#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 916#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 917#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 918#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 919#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 920#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 921#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 922 923#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 924#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 925 926#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 927#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 928#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 929#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 930#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 931#define IXGBE_RXDADV_SPH 0x8000 932 933/* RSS Hash results */ 934#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 935#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 936#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 937#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 938#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 939#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 940#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 941#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 942#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 943#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 944 945/* RSS Packet Types as indicated in the receive descriptor. */ 946#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 947#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 948#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 949#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 950#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 951#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 952#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 953#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 954#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 955 956/* Masks to determine if packets should be dropped due to frame errors */ 957#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 958 IXGBE_RXD_ERR_CE | \ 959 IXGBE_RXD_ERR_LE | \ 960 IXGBE_RXD_ERR_PE | \ 961 IXGBE_RXD_ERR_OSE | \ 962 IXGBE_RXD_ERR_USE) 963 964#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 965 IXGBE_RXDADV_ERR_CE | \ 966 IXGBE_RXDADV_ERR_LE | \ 967 IXGBE_RXDADV_ERR_PE | \ 968 IXGBE_RXDADV_ERR_OSE | \ 969 IXGBE_RXDADV_ERR_USE) 970 971/* Multicast bit mask */ 972#define IXGBE_MCSTCTRL_MFE 0x4 973 974/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 975#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 976#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 977#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 978 979/* Vlan-specific macros */ 980#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 981#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 982#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 983#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 984 985/* Transmit Descriptor - Legacy */ 986struct ixgbe_legacy_tx_desc { 987 u64 buffer_addr; /* Address of the descriptor's data buffer */ 988 union { 989 u32 data; 990 struct { 991 u16 length; /* Data buffer length */ 992 u8 cso; /* Checksum offset */ 993 u8 cmd; /* Descriptor control */ 994 } flags; 995 } lower; 996 union { 997 u32 data; 998 struct { 999 u8 status; /* Descriptor status */ 1000 u8 css; /* Checksum start */ 1001 u16 vlan; 1002 } fields; 1003 } upper; 1004}; 1005 1006/* Transmit Descriptor - Advanced */ 1007union ixgbe_adv_tx_desc { 1008 struct { 1009 u64 buffer_addr; /* Address of descriptor's data buf */ 1010 u32 cmd_type_len; 1011 u32 olinfo_status; 1012 } read; 1013 struct { 1014 u64 rsvd; /* Reserved */ 1015 u32 nxtseq_seed; 1016 u32 status; 1017 } wb; 1018}; 1019 1020/* Receive Descriptor - Legacy */ 1021struct ixgbe_legacy_rx_desc { 1022 u64 buffer_addr; /* Address of the descriptor's data buffer */ 1023 u16 length; /* Length of data DMAed into data buffer */ 1024 u16 csum; /* Packet checksum */ 1025 u8 status; /* Descriptor status */ 1026 u8 errors; /* Descriptor Errors */ 1027 u16 vlan; 1028}; 1029 1030/* Receive Descriptor - Advanced */ 1031union ixgbe_adv_rx_desc { 1032 struct { 1033 u64 pkt_addr; /* Packet buffer address */ 1034 u64 hdr_addr; /* Header buffer address */ 1035 } read; 1036 struct { 1037 struct { 1038 struct { 1039 u16 pkt_info; /* RSS type, Packet type */ 1040 u16 hdr_info; /* Split Header, header len */ 1041 } lo_dword; 1042 union { 1043 u32 rss; /* RSS Hash */ 1044 struct { 1045 u16 ip_id; /* IP id */ 1046 u16 csum; /* Packet Checksum */ 1047 } csum_ip; 1048 } hi_dword; 1049 } lower; 1050 struct { 1051 u32 status_error; /* ext status/error */ 1052 u16 length; /* Packet length */ 1053 u16 vlan; /* VLAN tag */ 1054 } upper; 1055 } wb; /* writeback */ 1056}; 1057 1058/* Context descriptors */ 1059struct ixgbe_adv_tx_context_desc { 1060 u32 vlan_macip_lens; 1061 u32 seqnum_seed; 1062 u32 type_tucmd_mlhl; 1063 u32 mss_l4len_idx; 1064}; 1065 1066/* Adv Transmit Descriptor Config Masks */ 1067#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */ 1068#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 1069#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 1070#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 1071#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 1072#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 1073#define IXGBE_ADVTXD_DCMD_RDMA 0x04000000 /* RDMA */ 1074#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 1075#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 1076#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 1077#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 1078#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 1079#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 1080#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ 1081#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 1082#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 1083#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 1084#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 1085 IXGBE_ADVTXD_POPTS_SHIFT) 1086#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 1087 IXGBE_ADVTXD_POPTS_SHIFT) 1088#define IXGBE_ADVTXD_POPTS_EOM 0x00000400 /* Enable L bit-RDMA DDP hdr */ 1089#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 1090#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 1091#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 1092#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/ 1093#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 1094#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 1095#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 1096#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 1097#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 1098#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 1099#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 1100#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 1101#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ 1102#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 1103#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 1104 1105/* Autonegotiation advertised speeds */ 1106typedef u32 ixgbe_autoneg_advertised; 1107/* Link speed */ 1108typedef u32 ixgbe_link_speed; 1109#define IXGBE_LINK_SPEED_UNKNOWN 0 1110#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 1111#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 1112 1113 1114enum ixgbe_eeprom_type { 1115 ixgbe_eeprom_uninitialized = 0, 1116 ixgbe_eeprom_spi, 1117 ixgbe_eeprom_none /* No NVM support */ 1118}; 1119 1120enum ixgbe_mac_type { 1121 ixgbe_mac_unknown = 0, 1122 ixgbe_mac_82598EB, 1123 ixgbe_num_macs 1124}; 1125 1126enum ixgbe_phy_type { 1127 ixgbe_phy_unknown = 0, 1128 ixgbe_phy_tn, 1129 ixgbe_phy_qt, 1130 ixgbe_phy_xaui 1131}; 1132 1133enum ixgbe_media_type { 1134 ixgbe_media_type_unknown = 0, 1135 ixgbe_media_type_fiber, 1136 ixgbe_media_type_copper, 1137 ixgbe_media_type_backplane 1138}; 1139 1140/* Flow Control Settings */ 1141enum ixgbe_fc_type { 1142 ixgbe_fc_none = 0, 1143 ixgbe_fc_rx_pause, 1144 ixgbe_fc_tx_pause, 1145 ixgbe_fc_full, 1146 ixgbe_fc_default 1147}; 1148 1149/* PCI bus types */ 1150enum ixgbe_bus_type { 1151 ixgbe_bus_type_unknown = 0, 1152 ixgbe_bus_type_pci, 1153 ixgbe_bus_type_pcix, 1154 ixgbe_bus_type_pci_express, 1155 ixgbe_bus_type_reserved 1156}; 1157 1158/* PCI bus speeds */ 1159enum ixgbe_bus_speed { 1160 ixgbe_bus_speed_unknown = 0, 1161 ixgbe_bus_speed_33, 1162 ixgbe_bus_speed_66, 1163 ixgbe_bus_speed_100, 1164 ixgbe_bus_speed_120, 1165 ixgbe_bus_speed_133, 1166 ixgbe_bus_speed_2500, 1167 ixgbe_bus_speed_5000, 1168 ixgbe_bus_speed_reserved 1169}; 1170 1171/* PCI bus widths */ 1172enum ixgbe_bus_width { 1173 ixgbe_bus_width_unknown = 0, 1174 ixgbe_bus_width_pcie_x1, 1175 ixgbe_bus_width_pcie_x2, 1176 ixgbe_bus_width_pcie_x4, 1177 ixgbe_bus_width_pcie_x8, 1178 ixgbe_bus_width_32, 1179 ixgbe_bus_width_64, 1180 ixgbe_bus_width_reserved 1181}; 1182 1183struct ixgbe_eeprom_info { 1184 enum ixgbe_eeprom_type type; 1185 u16 word_size; 1186 u16 address_bits; 1187}; 1188 1189struct ixgbe_addr_filter_info { 1190 u32 num_mc_addrs; 1191 u32 rar_used_count; 1192 u32 mc_addr_in_rar_count; 1193 u32 mta_in_use; 1194}; 1195 1196/* Bus parameters */ 1197struct ixgbe_bus_info { 1198 enum ixgbe_bus_speed speed; 1199 enum ixgbe_bus_width width; 1200 enum ixgbe_bus_type type; 1201}; 1202 1203/* Flow control parameters */ 1204struct ixgbe_fc_info { 1205 u32 high_water; /* Flow Control High-water */ 1206 u32 low_water; /* Flow Control Low-water */ 1207 u16 pause_time; /* Flow Control Pause timer */ 1208 bool send_xon; /* Flow control send XON */ 1209 bool strict_ieee; /* Strict IEEE mode */ 1210 enum ixgbe_fc_type type; /* Type of flow control */ 1211 enum ixgbe_fc_type original_type; 1212}; 1213 1214/* Statistics counters collected by the MAC */ 1215struct ixgbe_hw_stats { 1216 u64 crcerrs; 1217 u64 illerrc; 1218 u64 errbc; 1219 u64 mspdc; 1220 u64 mpctotal; 1221 u64 mpc[8]; 1222 u64 mlfc; 1223 u64 mrfc; 1224 u64 rlec; 1225 u64 lxontxc; 1226 u64 lxonrxc; 1227 u64 lxofftxc; 1228 u64 lxoffrxc; 1229 u64 pxontxc[8]; 1230 u64 pxonrxc[8]; 1231 u64 pxofftxc[8]; 1232 u64 pxoffrxc[8]; 1233 u64 prc64; 1234 u64 prc127; 1235 u64 prc255; 1236 u64 prc511; 1237 u64 prc1023; 1238 u64 prc1522; 1239 u64 gprc; 1240 u64 bprc; 1241 u64 mprc; 1242 u64 gptc; 1243 u64 gorc; 1244 u64 gotc; 1245 u64 rnbc[8]; 1246 u64 ruc; 1247 u64 rfc; 1248 u64 roc; 1249 u64 rjc; 1250 u64 mngprc; 1251 u64 mngpdc; 1252 u64 mngptc; 1253 u64 tor; 1254 u64 tpr; 1255 u64 tpt; 1256 u64 ptc64; 1257 u64 ptc127; 1258 u64 ptc255; 1259 u64 ptc511; 1260 u64 ptc1023; 1261 u64 ptc1522; 1262 u64 mptc; 1263 u64 bptc; 1264 u64 xec; 1265 u64 rqsmr[16]; 1266 u64 tqsmr[8]; 1267 u64 qprc[16]; 1268 u64 qptc[16]; 1269 u64 qbrc[16]; 1270 u64 qbtc[16]; 1271}; 1272 1273 1274/* forward declaration */ 1275struct ixgbe_hw; 1276 1277/* Function pointer table */ 1278struct ixgbe_functions 1279{ 1280 s32 (*ixgbe_func_init_hw)(struct ixgbe_hw *); 1281 s32 (*ixgbe_func_reset_hw)(struct ixgbe_hw *); 1282 s32 (*ixgbe_func_start_hw)(struct ixgbe_hw *); 1283 s32 (*ixgbe_func_clear_hw_cntrs)(struct ixgbe_hw *); 1284 enum ixgbe_media_type (*ixgbe_func_get_media_type)(struct ixgbe_hw *); 1285 s32 (*ixgbe_func_get_mac_addr)(struct ixgbe_hw *, u8 *); 1286 u32 (*ixgbe_func_get_num_of_tx_queues)(struct ixgbe_hw *); 1287 u32 (*ixgbe_func_get_num_of_rx_queues)(struct ixgbe_hw *); 1288 s32 (*ixgbe_func_stop_adapter)(struct ixgbe_hw *); 1289 s32 (*ixgbe_func_get_bus_info)(struct ixgbe_hw *); 1290 1291 1292 /* PHY */ 1293 s32 (*ixgbe_func_identify_phy)(struct ixgbe_hw *); 1294 s32 (*ixgbe_func_reset_phy)(struct ixgbe_hw *); 1295 s32 (*ixgbe_func_read_phy_reg)(struct ixgbe_hw *, u32, u32, u16 *); 1296 s32 (*ixgbe_func_write_phy_reg)(struct ixgbe_hw *, u32, u32, u16); 1297 s32 (*ixgbe_func_setup_phy_link)(struct ixgbe_hw *); 1298 s32 (*ixgbe_func_setup_phy_link_speed)(struct ixgbe_hw *, 1299 ixgbe_link_speed, 1300 bool, bool); 1301 s32 (*ixgbe_func_check_phy_link)(struct ixgbe_hw *, ixgbe_link_speed *, 1302 bool *); 1303 1304 /* Link */ 1305 s32 (*ixgbe_func_setup_link)(struct ixgbe_hw *); 1306 s32 (*ixgbe_func_setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, 1307 bool, bool); 1308 s32 (*ixgbe_func_check_link)(struct ixgbe_hw *, ixgbe_link_speed *, 1309 bool *); 1310 s32 (*ixgbe_func_get_link_settings)(struct ixgbe_hw *, 1311 ixgbe_link_speed *, 1312 bool *); 1313 1314 /* LED */ 1315 s32 (*ixgbe_func_led_on)(struct ixgbe_hw *, u32); 1316 s32 (*ixgbe_func_led_off)(struct ixgbe_hw *, u32); 1317 s32 (*ixgbe_func_blink_led_start)(struct ixgbe_hw *, u32); 1318 s32 (*ixgbe_func_blink_led_stop)(struct ixgbe_hw *, u32); 1319 1320 /* EEPROM */ 1321 s32 (*ixgbe_func_init_eeprom_params)(struct ixgbe_hw *); 1322 s32 (*ixgbe_func_read_eeprom)(struct ixgbe_hw *, u16, u16 *); 1323 s32 (*ixgbe_func_write_eeprom)(struct ixgbe_hw *, u16, u16); 1324 s32 (*ixgbe_func_validate_eeprom_checksum)(struct ixgbe_hw *, u16 *); 1325 s32 (*ixgbe_func_update_eeprom_checksum)(struct ixgbe_hw *); 1326 1327 /* RAR, Multicast, VLAN */ 1328 s32 (*ixgbe_func_set_rar)(struct ixgbe_hw *, u32, u8 *, u32 , u32); 1329 s32 (*ixgbe_func_init_rx_addrs)(struct ixgbe_hw *); 1330 u32 (*ixgbe_func_get_num_rx_addrs)(struct ixgbe_hw *); 1331 s32 (*ixgbe_func_update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 1332 u32); 1333 s32 (*ixgbe_func_enable_mc)(struct ixgbe_hw *); 1334 s32 (*ixgbe_func_disable_mc)(struct ixgbe_hw *); 1335 s32 (*ixgbe_func_clear_vfta)(struct ixgbe_hw *); 1336 s32 (*ixgbe_func_set_vfta)(struct ixgbe_hw *, u32, u32, bool); 1337 1338 /* Flow Control */ 1339 s32 (*ixgbe_func_setup_fc)(struct ixgbe_hw *, s32); 1340}; 1341 1342struct ixgbe_mac_info { 1343 enum ixgbe_mac_type type; 1344 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1345 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1346 s32 mc_filter_type; 1347 u32 link_attach_type; 1348 u32 link_mode_select; 1349 bool link_settings_loaded; 1350}; 1351 1352struct ixgbe_phy_info { 1353 enum ixgbe_phy_type type; 1354 u32 addr; 1355 u32 id; 1356 u32 revision; 1357 enum ixgbe_media_type media_type; 1358 ixgbe_autoneg_advertised autoneg_advertised; 1359 bool autoneg_wait_to_complete; 1360}; 1361 1362struct ixgbe_hw { 1363 u8 *hw_addr; 1364 void *back; 1365 struct ixgbe_functions func; 1366 struct ixgbe_mac_info mac; 1367 struct ixgbe_addr_filter_info addr_ctrl; 1368 struct ixgbe_fc_info fc; 1369 struct ixgbe_phy_info phy; 1370 struct ixgbe_eeprom_info eeprom; 1371 struct ixgbe_bus_info bus; 1372 u16 device_id; 1373 u16 vendor_id; 1374 u16 subsystem_device_id; 1375 u16 subsystem_vendor_id; 1376 u8 revision_id; 1377 bool adapter_stopped; 1378}; 1379 1380 1381#define ixgbe_func_from_hw_struct(hw, _func) hw->func._func 1382 1383#define ixgbe_call_func(hw, func, params, error) \ 1384 (ixgbe_func_from_hw_struct(hw, func) != NULL) ? \ 1385 ixgbe_func_from_hw_struct(hw, func) params: error 1386 1387/* Error Codes */ 1388#define IXGBE_SUCCESS 0 1389#define IXGBE_ERR_EEPROM -1 1390#define IXGBE_ERR_EEPROM_CHECKSUM -2 1391#define IXGBE_ERR_PHY -3 1392#define IXGBE_ERR_CONFIG -4 1393#define IXGBE_ERR_PARAM -5 1394#define IXGBE_ERR_MAC_TYPE -6 1395#define IXGBE_ERR_UNKNOWN_PHY -7 1396#define IXGBE_ERR_LINK_SETUP -8 1397#define IXGBE_ERR_ADAPTER_STOPPED -9 1398#define IXGBE_ERR_INVALID_MAC_ADDR -10 1399#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 1400#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 1401#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 1402#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 1403#define IXGBE_ERR_RESET_FAILED -15 1404#define IXGBE_ERR_SWFW_SYNC -16 1405#define IXGBE_ERR_PHY_ADDR_INVALID -17 1406#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 1407 1408#ifndef UNREFERENCED_PARAMETER 1409#define UNREFERENCED_PARAMETER(_p) 1410#endif 1411 1412#endif /* _IXGBE_TYPE_H_ */ 1413