ixgbe_type.h revision 171384
1214571Sdim/******************************************************************************* 2214571Sdim 3214571Sdim Copyright (c) 2001-2007, Intel Corporation 4214571Sdim All rights reserved. 5214571Sdim 6214571Sdim Redistribution and use in source and binary forms, with or without 7214571Sdim modification, are permitted provided that the following conditions are met: 8214571Sdim 9214571Sdim 1. Redistributions of source code must retain the above copyright notice, 10214571Sdim this list of conditions and the following disclaimer. 11214571Sdim 12214571Sdim 2. Redistributions in binary form must reproduce the above copyright 13214571Sdim notice, this list of conditions and the following disclaimer in the 14214571Sdim documentation and/or other materials provided with the distribution. 15214571Sdim 16214571Sdim 3. Neither the name of the Intel Corporation nor the names of its 17214571Sdim contributors may be used to endorse or promote products derived from 18214571Sdim this software without specific prior written permission. 19214571Sdim 20214571Sdim THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21214571Sdim AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22214571Sdim IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23214571Sdim ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24214571Sdim LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25214571Sdim CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26214571Sdim SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27214571Sdim INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28214571Sdim CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29214571Sdim ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30214571Sdim POSSIBILITY OF SUCH DAMAGE. 31214571Sdim 32214571Sdim*******************************************************************************/ 33214571Sdim/* $FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 171384 2007-07-11 23:03:16Z jfv $ */ 34214571Sdim 35214571Sdim#ifndef _IXGBE_TYPE_H_ 36214571Sdim#define _IXGBE_TYPE_H_ 37214571Sdim 38214571Sdim#include "ixgbe_osdep.h" 39214571Sdim 40214571Sdim/* Vendor ID */ 41214571Sdim#define IXGBE_INTEL_VENDOR_ID 0x8086 42214571Sdim 43214571Sdim/* Device IDs */ 44214571Sdim#define IXGBE_DEV_ID_82598 0x10B6 45214571Sdim#define IXGBE_DEV_ID_82598_FPGA 0xF0C0 46214571Sdim#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 47214571Sdim#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 48214571Sdim#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8 49214571Sdim 50214571Sdim/* General Registers */ 51214571Sdim#define IXGBE_CTRL 0x00000 52214571Sdim#define IXGBE_STATUS 0x00008 53214571Sdim#define IXGBE_CTRL_EXT 0x00018 54214571Sdim#define IXGBE_ESDP 0x00020 55214571Sdim#define IXGBE_EODSDP 0x00028 56214571Sdim#define IXGBE_LEDCTL 0x00200 57214571Sdim#define IXGBE_FRTIMER 0x00048 58214571Sdim#define IXGBE_TCPTIMER 0x0004C 59214571Sdim 60214571Sdim/* NVM Registers */ 61214571Sdim#define IXGBE_EEC 0x10010 62214571Sdim#define IXGBE_EERD 0x10014 63214571Sdim#define IXGBE_FLA 0x1001C 64214571Sdim#define IXGBE_EEMNGCTL 0x10110 65214571Sdim#define IXGBE_EEMNGDATA 0x10114 66214571Sdim#define IXGBE_FLMNGCTL 0x10118 67214571Sdim#define IXGBE_FLMNGDATA 0x1011C 68214571Sdim#define IXGBE_FLMNGCNT 0x10120 69214571Sdim#define IXGBE_FLOP 0x1013C 70214571Sdim#define IXGBE_GRC 0x10200 71214571Sdim 72214571Sdim/* Interrupt Registers */ 73214571Sdim#define IXGBE_EICR 0x00800 74214571Sdim#define IXGBE_EICS 0x00808 75214571Sdim#define IXGBE_EIMS 0x00880 76214571Sdim#define IXGBE_EIMC 0x00888 77214571Sdim#define IXGBE_EIAC 0x00810 78214571Sdim#define IXGBE_EIAM 0x00890 79214571Sdim#define IXGBE_EITR(_i) (0x00820 + ((_i) * 4)) /* 0x820-0x86c */ 80214571Sdim#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 81214571Sdim#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 82214571Sdim#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 83214571Sdim#define IXGBE_PBACL 0x11068 84214571Sdim#define IXGBE_GPIE 0x00898 85214571Sdim 86214571Sdim/* Flow Control Registers */ 87214571Sdim#define IXGBE_PFCTOP 0x03008 88214571Sdim#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 89214571Sdim#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 90214571Sdim#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 91214571Sdim#define IXGBE_FCRTV 0x032A0 92214571Sdim#define IXGBE_TFCS 0x0CE00 93214571Sdim 94214571Sdim/* Receive DMA Registers */ 95214571Sdim#define IXGBE_RDBAL(_i) (0x01000 + ((_i) * 0x40)) /* 64 of each (0-63)*/ 96214571Sdim#define IXGBE_RDBAH(_i) (0x01004 + ((_i) * 0x40)) 97214571Sdim#define IXGBE_RDLEN(_i) (0x01008 + ((_i) * 0x40)) 98214571Sdim#define IXGBE_RDH(_i) (0x01010 + ((_i) * 0x40)) 99214571Sdim#define IXGBE_RDT(_i) (0x01018 + ((_i) * 0x40)) 100214571Sdim#define IXGBE_RXDCTL(_i) (0x01028 + ((_i) * 0x40)) 101214571Sdim#define IXGBE_SRRCTL(_i) (0x02100 + ((_i) * 4)) 102214571Sdim /* array of 16 (0x02100-0x0213C) */ 103214571Sdim#define IXGBE_DCA_RXCTRL(_i) (0x02200 + ((_i) * 4)) 104214571Sdim /* array of 16 (0x02200-0x0223C) */ 105214571Sdim#define IXGBE_RDRXCTL 0x02F00 106214571Sdim#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 107214571Sdim /* 8 of these 0x03C00 - 0x03C1C */ 108214571Sdim#define IXGBE_RXCTRL 0x03000 109214571Sdim#define IXGBE_DROPEN 0x03D04 110214571Sdim#define IXGBE_RXPBSIZE_SHIFT 10 111214571Sdim 112214571Sdim/* Receive Registers */ 113214571Sdim#define IXGBE_RXCSUM 0x05000 114214571Sdim#define IXGBE_RFCTL 0x05008 115214571Sdim#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 116214571Sdim /* Multicast Table Array - 128 entries */ 117214571Sdim#define IXGBE_RAL(_i) (0x05400 + ((_i) * 8)) /* 16 of these (0-15) */ 118214571Sdim#define IXGBE_RAH(_i) (0x05404 + ((_i) * 8)) /* 16 of these (0-15) */ 119214571Sdim#define IXGBE_PSRTYPE 0x05480 120214571Sdim /* 0x5480-0x54BC Packet split receive type */ 121214571Sdim#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 122214571Sdim /* array of 4096 1-bit vlan filters */ 123214571Sdim#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 124214571Sdim /*array of 4096 4-bit vlan vmdq indicies */ 125214571Sdim#define IXGBE_FCTRL 0x05080 126214571Sdim#define IXGBE_VLNCTRL 0x05088 127214571Sdim#define IXGBE_MCSTCTRL 0x05090 128214571Sdim#define IXGBE_MRQC 0x05818 129214571Sdim#define IXGBE_VMD_CTL 0x0581C 130214571Sdim#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 131214571Sdim#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 132214571Sdim#define IXGBE_IMIRVP 0x05AC0 133214571Sdim#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 134214571Sdim#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 135214571Sdim 136214571Sdim/* Transmit DMA registers */ 137214571Sdim#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))/* 32 of these (0-31)*/ 138214571Sdim#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 139214571Sdim#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 140214571Sdim#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 141214571Sdim#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 142214571Sdim#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 143214571Sdim#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 144214571Sdim#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 145214571Sdim#define IXGBE_DTXCTL 0x07E00 146214571Sdim#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 147214571Sdim /* there are 16 of these (0-15) */ 148214571Sdim#define IXGBE_TIPG 0x0CB00 149214571Sdim#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) 150214571Sdim /* there are 8 of these */ 151214571Sdim#define IXGBE_MNGTXMAP 0x0CD10 152214571Sdim#define IXGBE_TIPG_FIBER_DEFAULT 3 153214571Sdim#define IXGBE_TXPBSIZE_SHIFT 10 154214571Sdim 155214571Sdim/* Wake up registers */ 156214571Sdim#define IXGBE_WUC 0x05800 157214571Sdim#define IXGBE_WUFC 0x05808 158214571Sdim#define IXGBE_WUS 0x05810 159214571Sdim#define IXGBE_IPAV 0x05838 160214571Sdim#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 161214571Sdim#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 162214571Sdim#define IXGBE_WUPL 0x05900 163214571Sdim#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 164214571Sdim#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ 165214571Sdim 166214571Sdim/* Music registers */ 167214571Sdim#define IXGBE_RMCS 0x03D00 168214571Sdim#define IXGBE_DPMCS 0x07F40 169214571Sdim#define IXGBE_PDPMCS 0x0CD00 170214571Sdim#define IXGBE_RUPPBMR 0x050A0 171214571Sdim#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 172214571Sdim#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 173214571Sdim#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 174214571Sdim#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 175214571Sdim#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 176214571Sdim#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 177214571Sdim 178214571Sdim/* Stats registers */ 179214571Sdim#define IXGBE_CRCERRS 0x04000 180214571Sdim#define IXGBE_ILLERRC 0x04004 181214571Sdim#define IXGBE_ERRBC 0x04008 182214571Sdim#define IXGBE_MSPDC 0x04010 183214571Sdim#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 184214571Sdim#define IXGBE_MLFC 0x04034 185214571Sdim#define IXGBE_MRFC 0x04038 186214571Sdim#define IXGBE_RLEC 0x04040 187214571Sdim#define IXGBE_LXONTXC 0x03F60 188214571Sdim#define IXGBE_LXONRXC 0x0CF60 189214571Sdim#define IXGBE_LXOFFTXC 0x03F68 190214571Sdim#define IXGBE_LXOFFRXC 0x0CF68 191214571Sdim#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 192214571Sdim#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 193214571Sdim#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 194214571Sdim#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 195214571Sdim#define IXGBE_PRC64 0x0405C 196214571Sdim#define IXGBE_PRC127 0x04060 197214571Sdim#define IXGBE_PRC255 0x04064 198214571Sdim#define IXGBE_PRC511 0x04068 199214571Sdim#define IXGBE_PRC1023 0x0406C 200214571Sdim#define IXGBE_PRC1522 0x04070 201214571Sdim#define IXGBE_GPRC 0x04074 202214571Sdim#define IXGBE_BPRC 0x04078 203214571Sdim#define IXGBE_MPRC 0x0407C 204214571Sdim#define IXGBE_GPTC 0x04080 205214571Sdim#define IXGBE_GORCL 0x04088 206214571Sdim#define IXGBE_GORCH 0x0408C 207214571Sdim#define IXGBE_GOTCL 0x04090 208214571Sdim#define IXGBE_GOTCH 0x04094 209214571Sdim#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 210214571Sdim#define IXGBE_RUC 0x040A4 211214571Sdim#define IXGBE_RFC 0x040A8 212214571Sdim#define IXGBE_ROC 0x040AC 213214571Sdim#define IXGBE_RJC 0x040B0 214214571Sdim#define IXGBE_MNGPRC 0x040B4 215214571Sdim#define IXGBE_MNGPDC 0x040B8 216214571Sdim#define IXGBE_MNGPTC 0x0CF90 217214571Sdim#define IXGBE_TORL 0x040C0 218214571Sdim#define IXGBE_TORH 0x040C4 219214571Sdim#define IXGBE_TPR 0x040D0 220214571Sdim#define IXGBE_TPT 0x040D4 221214571Sdim#define IXGBE_PTC64 0x040D8 222214571Sdim#define IXGBE_PTC127 0x040DC 223214571Sdim#define IXGBE_PTC255 0x040E0 224214571Sdim#define IXGBE_PTC511 0x040E4 225214571Sdim#define IXGBE_PTC1023 0x040E8 226214571Sdim#define IXGBE_PTC1522 0x040EC 227214571Sdim#define IXGBE_MPTC 0x040F0 228214571Sdim#define IXGBE_BPTC 0x040F4 229214571Sdim#define IXGBE_XEC 0x04120 230214571Sdim 231214571Sdim#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ 232214571Sdim#define IXGBE_TQSMR(_i) (0x07300 + ((_i) * 4)) /* 8 of these */ 233214571Sdim 234214571Sdim#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 235214571Sdim#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 236214571Sdim#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 237214571Sdim#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 238214571Sdim 239214571Sdim/* Management */ 240214571Sdim#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 241214571Sdim#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 242214571Sdim#define IXGBE_MANC 0x05820 243214571Sdim#define IXGBE_MFVAL 0x05824 244214571Sdim#define IXGBE_MANC2H 0x05860 245214571Sdim#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 246214571Sdim#define IXGBE_MIPAF 0x058B0 247214571Sdim#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 248214571Sdim#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 249214571Sdim#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 250214571Sdim 251214571Sdim/* ARC Subsystem registers */ 252214571Sdim#define IXGBE_HICR 0x15F00 253214571Sdim#define IXGBE_FWSTS 0x15F0C 254214571Sdim#define IXGBE_HSMC0R 0x15F04 255214571Sdim#define IXGBE_HSMC1R 0x15F08 256214571Sdim#define IXGBE_SWSR 0x15F10 257214571Sdim#define IXGBE_HFDR 0x15FE8 258214571Sdim#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 259214571Sdim 260214571Sdim/* PCI-E registers */ 261214571Sdim#define IXGBE_GCR 0x11000 262214571Sdim#define IXGBE_GTV 0x11004 263214571Sdim#define IXGBE_FUNCTAG 0x11008 264214571Sdim#define IXGBE_GLT 0x1100C 265214571Sdim#define IXGBE_GSCL_1 0x11010 266214571Sdim#define IXGBE_GSCL_2 0x11014 267214571Sdim#define IXGBE_GSCL_3 0x11018 268214571Sdim#define IXGBE_GSCL_4 0x1101C 269214571Sdim#define IXGBE_GSCN_0 0x11020 270214571Sdim#define IXGBE_GSCN_1 0x11024 271214571Sdim#define IXGBE_GSCN_2 0x11028 272214571Sdim#define IXGBE_GSCN_3 0x1102C 273214571Sdim#define IXGBE_FACTPS 0x10150 274214571Sdim#define IXGBE_PCIEANACTL 0x11040 275214571Sdim#define IXGBE_SWSM 0x10140 276214571Sdim#define IXGBE_FWSM 0x10148 277214571Sdim#define IXGBE_GSSR 0x10160 278214571Sdim#define IXGBE_MREVID 0x11064 279214571Sdim#define IXGBE_DCA_ID 0x11070 280214571Sdim#define IXGBE_DCA_CTRL 0x11074 281214571Sdim 282214571Sdim/* Diagnostic Registers */ 283214571Sdim#define IXGBE_RDSTATCTL 0x02C20 284214571Sdim#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 285214571Sdim#define IXGBE_RDHMPN 0x02F08 286214571Sdim#define IXGBE_RIC_DW0 0x02F10 287214571Sdim#define IXGBE_RIC_DW1 0x02F14 288214571Sdim#define IXGBE_RIC_DW2 0x02F18 289214571Sdim#define IXGBE_RIC_DW3 0x02F1C 290214571Sdim#define IXGBE_RDPROBE 0x02F20 291214571Sdim#define IXGBE_TDSTATCTL 0x07C20 292214571Sdim#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 293214571Sdim#define IXGBE_TDHMPN 0x07F08 294214571Sdim#define IXGBE_TIC_DW0 0x07F10 295214571Sdim#define IXGBE_TIC_DW1 0x07F14 296214571Sdim#define IXGBE_TIC_DW2 0x07F18 297214571Sdim#define IXGBE_TIC_DW3 0x07F1C 298214571Sdim#define IXGBE_TDPROBE 0x07F20 299214571Sdim#define IXGBE_TXBUFCTRL 0x0C600 300214571Sdim#define IXGBE_TXBUFDATA0 0x0C610 301214571Sdim#define IXGBE_TXBUFDATA1 0x0C614 302214571Sdim#define IXGBE_TXBUFDATA2 0x0C618 303214571Sdim#define IXGBE_TXBUFDATA3 0x0C61C 304214571Sdim#define IXGBE_RXBUFCTRL 0x03600 305214571Sdim#define IXGBE_RXBUFDATA0 0x03610 306214571Sdim#define IXGBE_RXBUFDATA1 0x03614 307214571Sdim#define IXGBE_RXBUFDATA2 0x03618 308214571Sdim#define IXGBE_RXBUFDATA3 0x0361C 309214571Sdim#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 310214571Sdim#define IXGBE_RFVAL 0x050A4 311214571Sdim#define IXGBE_MDFTC1 0x042B8 312214571Sdim#define IXGBE_MDFTC2 0x042C0 313214571Sdim#define IXGBE_MDFTFIFO1 0x042C4 314214571Sdim#define IXGBE_MDFTFIFO2 0x042C8 315214571Sdim#define IXGBE_MDFTS 0x042CC 316214571Sdim#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 317214571Sdim#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 318214571Sdim#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 319214571Sdim#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 320214571Sdim#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 321214571Sdim#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 322214571Sdim#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 323214571Sdim#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 324214571Sdim#define IXGBE_PCIEECCCTL 0x1106C 325214571Sdim#define IXGBE_PBTXECC 0x0C300 326214571Sdim#define IXGBE_PBRXECC 0x03300 327214571Sdim#define IXGBE_GHECCR 0x110B0 328214571Sdim 329214571Sdim/* MAC Registers */ 330214571Sdim#define IXGBE_PCS1GCFIG 0x04200 331214571Sdim#define IXGBE_PCS1GLCTL 0x04208 332214571Sdim#define IXGBE_PCS1GLSTA 0x0420C 333214571Sdim#define IXGBE_PCS1GDBG0 0x04210 334214571Sdim#define IXGBE_PCS1GDBG1 0x04214 335214571Sdim#define IXGBE_PCS1GANA 0x04218 336214571Sdim#define IXGBE_PCS1GANLP 0x0421C 337214571Sdim#define IXGBE_PCS1GANNP 0x04220 338214571Sdim#define IXGBE_PCS1GANLPNP 0x04224 339214571Sdim#define IXGBE_HLREG0 0x04240 340214571Sdim#define IXGBE_HLREG1 0x04244 341214571Sdim#define IXGBE_PAP 0x04248 342214571Sdim#define IXGBE_MACA 0x0424C 343214571Sdim#define IXGBE_APAE 0x04250 344214571Sdim#define IXGBE_ARD 0x04254 345214571Sdim#define IXGBE_AIS 0x04258 346214571Sdim#define IXGBE_MSCA 0x0425C 347214571Sdim#define IXGBE_MSRWD 0x04260 348214571Sdim#define IXGBE_MLADD 0x04264 349214571Sdim#define IXGBE_MHADD 0x04268 350214571Sdim#define IXGBE_TREG 0x0426C 351214571Sdim#define IXGBE_PCSS1 0x04288 352214571Sdim#define IXGBE_PCSS2 0x0428C 353214571Sdim#define IXGBE_XPCSS 0x04290 354214571Sdim#define IXGBE_SERDESC 0x04298 355214571Sdim#define IXGBE_MACS 0x0429C 356214571Sdim#define IXGBE_AUTOC 0x042A0 357214571Sdim#define IXGBE_LINKS 0x042A4 358214571Sdim#define IXGBE_AUTOC2 0x042A8 359214571Sdim#define IXGBE_AUTOC3 0x042AC 360214571Sdim#define IXGBE_ANLP1 0x042B0 361214571Sdim#define IXGBE_ANLP2 0x042B4 362214571Sdim#define IXGBE_ATLASCTL 0x04800 363214571Sdim 364214571Sdim 365214571Sdim/* CTRL Bit Masks */ 366214571Sdim#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 367214571Sdim#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 368214571Sdim#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 369214571Sdim 370214571Sdim/* FACTPS */ 371214571Sdim#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 372214571Sdim 373214571Sdim/* MHADD Bit Masks */ 374214571Sdim#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 375214571Sdim#define IXGBE_MHADD_MFS_SHIFT 16 376214571Sdim 377214571Sdim/* Extended Device Control */ 378214571Sdim#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 379214571Sdim#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 380214571Sdim#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 381214571Sdim 382214571Sdim/* Direct Cache Access (DCA) definitions */ 383214571Sdim#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 384214571Sdim#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 385214571Sdim 386214571Sdim#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 387214571Sdim#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 388214571Sdim 389214571Sdim#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 390214571Sdim#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 391214571Sdim#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 392214571Sdim#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 393214571Sdim 394214571Sdim#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 395214571Sdim#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 396214571Sdim 397214571Sdim/* MSCA Bit Masks */ 398214571Sdim#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 399214571Sdim#define IXGBE_MSCA_NP_ADDR_SHIFT 0 400214571Sdim#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 401214571Sdim#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 402214571Sdim#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 403214571Sdim#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 404214571Sdim#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 405214571Sdim#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 406214571Sdim#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 407214571Sdim#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 408214571Sdim#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */ 409214571Sdim#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/ 410214571Sdim#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 411214571Sdim#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 412214571Sdim#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 413214571Sdim#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 414214571Sdim#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 415214571Sdim#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 416214571Sdim 417214571Sdim/* MSRWD bit masks */ 418214571Sdim#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 419214571Sdim#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 420214571Sdim#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 421214571Sdim#define IXGBE_MSRWD_READ_DATA_SHIFT 16 422214571Sdim 423214571Sdim/* Device Type definitions for new protocol MDIO commands */ 424214571Sdim#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 425214571Sdim#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 426214571Sdim#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 427214571Sdim#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 428214571Sdim#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 429214571Sdim 430214571Sdim#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ 431214571Sdim#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 432214571Sdim#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 433214571Sdim#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 434214571Sdim#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 435214571Sdim#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 436214571Sdim 437214571Sdim#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 438214571Sdim#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 439214571Sdim#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 440214571Sdim#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 441214571Sdim#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 442214571Sdim#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 443214571Sdim#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Abilty Reg */ 444214571Sdim#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 445214571Sdim#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 446214571Sdim 447214571Sdim#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 448214571Sdim#define IXGBE_MAX_PHY_ADDR 32 449214571Sdim 450214571Sdim/* PHY IDs*/ 451214571Sdim#define TN1010_PHY_ID 0x00A19410 452214571Sdim#define QT2022_PHY_ID 0x0043A400 453214571Sdim 454214571Sdim/* General purpose Interrupt Enable */ 455214571Sdim#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 456214571Sdim#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 457214571Sdim#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 458214571Sdim#define IXGBE_GPIE_EIAME 0x40000000 459214571Sdim#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 460214571Sdim 461214571Sdim/* Transmit Flow Control status */ 462214571Sdim#define IXGBE_TFCS_TXOFF 0x00000001 463214571Sdim#define IXGBE_TFCS_TXOFF0 0x00000100 464214571Sdim#define IXGBE_TFCS_TXOFF1 0x00000200 465214571Sdim#define IXGBE_TFCS_TXOFF2 0x00000400 466214571Sdim#define IXGBE_TFCS_TXOFF3 0x00000800 467214571Sdim#define IXGBE_TFCS_TXOFF4 0x00001000 468214571Sdim#define IXGBE_TFCS_TXOFF5 0x00002000 469214571Sdim#define IXGBE_TFCS_TXOFF6 0x00004000 470214571Sdim#define IXGBE_TFCS_TXOFF7 0x00008000 471214571Sdim 472214571Sdim/* TCP Timer */ 473214571Sdim#define IXGBE_TCPTIMER_KS 0x00000100 474214571Sdim#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 475214571Sdim#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 476214571Sdim#define IXGBE_TCPTIMER_LOOP 0x00000800 477214571Sdim#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 478214571Sdim 479214571Sdim/* HLREG0 Bit Masks */ 480214571Sdim#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 481214571Sdim#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 482214571Sdim#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 483214571Sdim#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 484214571Sdim#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 485214571Sdim#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 486214571Sdim#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 487214571Sdim#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 488214571Sdim#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 489214571Sdim#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 490214571Sdim#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 491214571Sdim#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 492214571Sdim#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 493214571Sdim#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 494214571Sdim#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 495214571Sdim 496214571Sdim/* VMD_CTL bitmasks */ 497214571Sdim#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 498214571Sdim#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 499214571Sdim 500214571Sdim/* RDHMPN and TDHMPN bitmasks */ 501214571Sdim#define IXGBE_RDHMPN_RDICADDR 0x007FF800 502214571Sdim#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 503214571Sdim#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 504214571Sdim#define IXGBE_TDHMPN_TDICADDR 0x003FF800 505214571Sdim#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 506214571Sdim#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 507214571Sdim 508214571Sdim/* Receive Checksum Control */ 509214571Sdim#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 510214571Sdim#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 511214571Sdim 512214571Sdim/* FCRTL Bit Masks */ 513214571Sdim#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */ 514214571Sdim#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */ 515214571Sdim 516214571Sdim/* PAP bit masks*/ 517214571Sdim#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 518214571Sdim 519214571Sdim/* RMCS Bit Masks */ 520214571Sdim#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recylce Mode enable */ 521214571Sdim/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 522214571Sdim#define IXGBE_RMCS_RAC 0x00000004 523214571Sdim#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 524214571Sdim#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */ 525214571Sdim#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ 526214571Sdim#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 527214571Sdim 528214571Sdim/* Interrupt register bitmasks */ 529214571Sdim 530214571Sdim/* Extended Interrupt Cause Read */ 531214571Sdim#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 532214571Sdim#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 533214571Sdim#define IXGBE_EICR_MNG 0x00400000 /* Managability Event Interrupt */ 534214571Sdim#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 535214571Sdim#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 536214571Sdim#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 537214571Sdim#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 538214571Sdim 539214571Sdim/* Extended Interrupt Cause Set */ 540214571Sdim#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 541214571Sdim#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 542214571Sdim#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 543214571Sdim#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 544214571Sdim#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 545214571Sdim#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 546214571Sdim#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 547214571Sdim#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 548214571Sdim 549214571Sdim/* Extended Interrupt Mask Set */ 550214571Sdim#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 551214571Sdim#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 552214571Sdim#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 553214571Sdim#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 554214571Sdim#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 555214571Sdim#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 556214571Sdim#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 557214571Sdim 558214571Sdim/* Extended Interrupt Mask Clear */ 559214571Sdim#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 560214571Sdim#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 561214571Sdim#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 562214571Sdim#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */ 563214571Sdim#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 564214571Sdim#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 565214571Sdim#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 566214571Sdim 567214571Sdim#define IXGBE_EIMS_ENABLE_MASK ( \ 568214571Sdim IXGBE_EIMS_RTX_QUEUE | \ 569214571Sdim IXGBE_EIMS_LSC | \ 570214571Sdim IXGBE_EIMS_TCP_TIMER | \ 571214571Sdim IXGBE_EIMS_OTHER) 572214571Sdim 573214571Sdim/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */ 574214571Sdim#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 575214571Sdim#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 576214571Sdim#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 577214571Sdim#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 578214571Sdim#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 579214571Sdim#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 580214571Sdim#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 581214571Sdim#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 582214571Sdim#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 583214571Sdim#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 584214571Sdim 585214571Sdim/* Interrupt clear mask */ 586214571Sdim#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 587214571Sdim 588214571Sdim/* Interrupt Vector Allocation Registers */ 589214571Sdim#define IXGBE_IVAR_REG_NUM 25 590214571Sdim#define IXGBE_IVAR_TXRX_ENTRY 96 591214571Sdim#define IXGBE_IVAR_RX_ENTRY 64 592214571Sdim#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 593214571Sdim#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 594214571Sdim#define IXGBE_IVAR_TX_ENTRY 32 595214571Sdim 596214571Sdim#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 597214571Sdim#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 598214571Sdim 599214571Sdim#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 600214571Sdim 601214571Sdim#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 602214571Sdim 603214571Sdim/* VLAN Control Bit Masks */ 604214571Sdim#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 605214571Sdim#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 606214571Sdim#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 607214571Sdim#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 608214571Sdim#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 609214571Sdim 610214571Sdim#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 611214571Sdim 612214571Sdim/* STATUS Bit Masks */ 613214571Sdim#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 614214571Sdim#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 615214571Sdim 616214571Sdim#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 617214571Sdim#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 618214571Sdim 619214571Sdim/* ESDP Bit Masks */ 620214571Sdim#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */ 621214571Sdim#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */ 622214571Sdim#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 623214571Sdim#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */ 624214571Sdim 625214571Sdim/* LEDCTL Bit Masks */ 626214571Sdim#define IXGBE_LED_IVRT_BASE 0x00000040 627214571Sdim#define IXGBE_LED_BLINK_BASE 0x00000080 628214571Sdim#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 629214571Sdim#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 630214571Sdim#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 631214571Sdim#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 632214571Sdim#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 633214571Sdim#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 634214571Sdim 635214571Sdim/* LED modes */ 636214571Sdim#define IXGBE_LED_LINK_UP 0x0 637214571Sdim#define IXGBE_LED_LINK_10G 0x1 638214571Sdim#define IXGBE_LED_MAC 0x2 639214571Sdim#define IXGBE_LED_FILTER 0x3 640214571Sdim#define IXGBE_LED_LINK_ACTIVE 0x4 641214571Sdim#define IXGBE_LED_LINK_1G 0x5 642214571Sdim#define IXGBE_LED_ON 0xE 643214571Sdim#define IXGBE_LED_OFF 0xF 644214571Sdim 645214571Sdim/* AUTOC Bit Masks */ 646214571Sdim#define IXGBE_AUTOC_KX4_SUPP 0x80000000 647214571Sdim#define IXGBE_AUTOC_KX_SUPP 0x40000000 648214571Sdim#define IXGBE_AUTOC_PAUSE 0x30000000 649214571Sdim#define IXGBE_AUTOC_RF 0x08000000 650214571Sdim#define IXGBE_AUTOC_PD_TMR 0x06000000 651214571Sdim#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 652214571Sdim#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 653214571Sdim#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 654214571Sdim#define IXGBE_AUTOC_AN_RESTART 0x00001000 655214571Sdim#define IXGBE_AUTOC_FLU 0x00000001 656214571Sdim#define IXGBE_AUTOC_LMS_SHIFT 13 657214571Sdim#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 658214571Sdim#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 659214571Sdim#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 660214571Sdim#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 661214571Sdim#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 662214571Sdim#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 663214571Sdim#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 664214571Sdim 665214571Sdim#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 666214571Sdim#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 667214571Sdim#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 668214571Sdim#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 669214571Sdim#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 670214571Sdim#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 671214571Sdim#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 672214571Sdim#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 673214571Sdim#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 674214571Sdim 675214571Sdim/* LINKS Bit Masks */ 676214571Sdim#define IXGBE_LINKS_KX_AN_COMP 0x80000000 677214571Sdim#define IXGBE_LINKS_UP 0x40000000 678214571Sdim#define IXGBE_LINKS_SPEED 0x20000000 679214571Sdim#define IXGBE_LINKS_MODE 0x18000000 680214571Sdim#define IXGBE_LINKS_RX_MODE 0x06000000 681214571Sdim#define IXGBE_LINKS_TX_MODE 0x01800000 682214571Sdim#define IXGBE_LINKS_XGXS_EN 0x00400000 683214571Sdim#define IXGBE_LINKS_PCS_1G_EN 0x00200000 684214571Sdim#define IXGBE_LINKS_1G_AN_EN 0x00100000 685214571Sdim#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 686214571Sdim#define IXGBE_LINKS_1G_SYNC 0x00040000 687214571Sdim#define IXGBE_LINKS_10G_ALIGN 0x00020000 688214571Sdim#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 689214571Sdim#define IXGBE_LINKS_TL_FAULT 0x00001000 690214571Sdim#define IXGBE_LINKS_SIGNAL 0x00000F00 691214571Sdim 692214571Sdim#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 693214571Sdim 694214571Sdim/* SW Semaphore Register bitmasks */ 695214571Sdim#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 696214571Sdim#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 697214571Sdim#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 698214571Sdim 699214571Sdim/* GSSR definitions */ 700214571Sdim#define IXGBE_GSSR_EEP_SM 0x0001 701214571Sdim#define IXGBE_GSSR_PHY0_SM 0x0002 702214571Sdim#define IXGBE_GSSR_PHY1_SM 0x0004 703214571Sdim#define IXGBE_GSSR_MAC_CSR_SM 0x0008 704214571Sdim#define IXGBE_GSSR_FLASH_SM 0x0010 705214571Sdim 706214571Sdim/* EEC Register */ 707214571Sdim#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 708214571Sdim#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 709214571Sdim#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 710214571Sdim#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 711214571Sdim#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 712214571Sdim#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 713214571Sdim#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 714214571Sdim#define IXGBE_EEC_FWE_SHIFT 4 715214571Sdim#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 716214571Sdim#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 717214571Sdim#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 718214571Sdim#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 719214571Sdim/* EEPROM Addressing bits based on type (0-small, 1-large) */ 720214571Sdim#define IXGBE_EEC_ADDR_SIZE 0x00000400 721214571Sdim#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 722214571Sdim 723214571Sdim#define IXGBE_EEC_SIZE_SHIFT 11 724214571Sdim#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 725214571Sdim#define IXGBE_EEPROM_OPCODE_BITS 8 726214571Sdim 727214571Sdim/* Checksum and EEPROM pointers */ 728214571Sdim#define IXGBE_EEPROM_CHECKSUM 0x3F 729214571Sdim#define IXGBE_EEPROM_SUM 0xBABA 730214571Sdim#define IXGBE_PCIE_ANALOG_PTR 0x03 731214571Sdim#define IXGBE_ATLAS0_CONFIG_PTR 0x04 732214571Sdim#define IXGBE_ATLAS1_CONFIG_PTR 0x05 733214571Sdim#define IXGBE_PCIE_GENERAL_PTR 0x06 734214571Sdim#define IXGBE_PCIE_CONFIG0_PTR 0x07 735214571Sdim#define IXGBE_PCIE_CONFIG1_PTR 0x08 736214571Sdim#define IXGBE_CORE0_PTR 0x09 737214571Sdim#define IXGBE_CORE1_PTR 0x0A 738214571Sdim#define IXGBE_MAC0_PTR 0x0B 739214571Sdim#define IXGBE_MAC1_PTR 0x0C 740214571Sdim#define IXGBE_CSR0_CONFIG_PTR 0x0D 741214571Sdim#define IXGBE_CSR1_CONFIG_PTR 0x0E 742214571Sdim#define IXGBE_FW_PTR 0x0F 743214571Sdim 744214571Sdim/* EEPROM Commands - SPI */ 745214571Sdim#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 746214571Sdim#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 747214571Sdim#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 748214571Sdim#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 749214571Sdim#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 750214571Sdim#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 751214571Sdim/* EEPROM reset Write Enbale latch */ 752214571Sdim#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 753214571Sdim#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 754214571Sdim#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 755214571Sdim#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 756214571Sdim#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 757214571Sdim#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 758214571Sdim 759214571Sdim/* EEPROM Read Register */ 760214571Sdim#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */ 761214571Sdim#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */ 762214571Sdim#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */ 763214571Sdim#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */ 764214571Sdim 765214571Sdim#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 766214571Sdim 767214571Sdim#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 768214571Sdim#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 769214571Sdim#endif 770214571Sdim 771214571Sdim#ifndef IXGBE_EERD_ATTEMPTS 772214571Sdim/* Number of 5 microseconds we wait for EERD read to complete */ 773214571Sdim#define IXGBE_EERD_ATTEMPTS 100000 774214571Sdim#endif 775214571Sdim 776214571Sdim/* PCI Bus Info */ 777214571Sdim#define IXGBE_PCI_LINK_STATUS 0xB2 778214571Sdim#define IXGBE_PCI_LINK_WIDTH 0x3F0 779214571Sdim#define IXGBE_PCI_LINK_WIDTH_1 0x10 780214571Sdim#define IXGBE_PCI_LINK_WIDTH_2 0x20 781214571Sdim#define IXGBE_PCI_LINK_WIDTH_4 0x40 782214571Sdim#define IXGBE_PCI_LINK_WIDTH_8 0x80 783214571Sdim#define IXGBE_PCI_LINK_SPEED 0xF 784214571Sdim#define IXGBE_PCI_LINK_SPEED_2500 0x1 785214571Sdim#define IXGBE_PCI_LINK_SPEED_5000 0x2 786214571Sdim 787214571Sdim/* Number of 100 microseconds we wait for PCI Express master disable */ 788214571Sdim#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 789214571Sdim 790214571Sdim/* PHY Types */ 791214571Sdim#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 792214571Sdim 793214571Sdim/* Check whether address is multicast. This is little-endian specific check.*/ 794214571Sdim#define IXGBE_IS_MULTICAST(Address) \ 795214571Sdim (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 796214571Sdim 797214571Sdim/* Check whether an address is broadcast. */ 798214571Sdim#define IXGBE_IS_BROADCAST(Address) \ 799214571Sdim ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 800214571Sdim (((u8 *)(Address))[1] == ((u8)0xff))) 801214571Sdim 802214571Sdim/* RAH */ 803214571Sdim#define IXGBE_RAH_VIND_MASK 0x003C0000 804214571Sdim#define IXGBE_RAH_VIND_SHIFT 18 805214571Sdim#define IXGBE_RAH_AV 0x80000000 806214571Sdim 807214571Sdim/* Filters */ 808214571Sdim#define IXGBE_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 809214571Sdim#define IXGBE_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 810214571Sdim 811214571Sdim/* Header split receive */ 812214571Sdim#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 813214571Sdim#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 814214571Sdim#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 815214571Sdim#define IXGBE_RFCTL_NFSW_DIS 0x00000040 816214571Sdim#define IXGBE_RFCTL_NFSR_DIS 0x00000080 817214571Sdim#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 818214571Sdim#define IXGBE_RFCTL_NFS_VER_SHIFT 8 819214571Sdim#define IXGBE_RFCTL_NFS_VER_2 0 820214571Sdim#define IXGBE_RFCTL_NFS_VER_3 1 821214571Sdim#define IXGBE_RFCTL_NFS_VER_4 2 822214571Sdim#define IXGBE_RFCTL_IPV6_DIS 0x00000400 823214571Sdim#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 824214571Sdim#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 825214571Sdim#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 826214571Sdim#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 827214571Sdim 828214571Sdim/* Transmit Config masks */ 829214571Sdim#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 830214571Sdim#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 831214571Sdim/* Enable short packet padding to 64 bytes */ 832214571Sdim#define IXGBE_TX_PAD_ENABLE 0x00000400 833214571Sdim#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 834214571Sdim/* This allows for 16K packets + 4k for vlan */ 835214571Sdim#define IXGBE_MAX_FRAME_SZ 0x40040000 836214571Sdim 837214571Sdim#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 838214571Sdim#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq. # write-back enable */ 839214571Sdim 840214571Sdim/* Receive Config masks */ 841214571Sdim#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 842214571Sdim#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 843214571Sdim#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 844214571Sdim 845214571Sdim#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 846214571Sdim#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 847214571Sdim#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 848214571Sdim#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 849214571Sdim#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 850214571Sdim#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 851214571Sdim/* Receive Priority Flow Control Enbale */ 852214571Sdim#define IXGBE_FCTRL_RPFCE 0x00004000 853214571Sdim#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 854214571Sdim 855214571Sdim/* Multiple Receive Queue Control */ 856214571Sdim#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 857214571Sdim#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 858214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 859214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 860214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 861214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 862214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 863214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 864214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 865214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 866214571Sdim#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 867214571Sdim 868214571Sdim#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 869214571Sdim#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 870214571Sdim#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 871214571Sdim#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 872214571Sdim#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 873214571Sdim#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 874214571Sdim#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 875214571Sdim#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 876214571Sdim#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 877214571Sdim 878214571Sdim/* Receive Descriptor bit definitions */ 879214571Sdim#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 880214571Sdim#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 881214571Sdim#define IXGBE_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 882214571Sdim#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 883214571Sdim#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 884214571Sdim#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 885214571Sdim#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 886214571Sdim#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 887214571Sdim#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 888214571Sdim#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 889214571Sdim#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 890214571Sdim#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 891214571Sdim#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 892214571Sdim#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 893214571Sdim#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 894214571Sdim#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 895214571Sdim#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 896214571Sdim#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 897214571Sdim#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 898214571Sdim#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 899214571Sdim#define IXGBE_RXDADV_HBO 0x00800000 900214571Sdim#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 901214571Sdim#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 902214571Sdim#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 903214571Sdim#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 904214571Sdim#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 905214571Sdim#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 906214571Sdim#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 907214571Sdim#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 908214571Sdim#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 909214571Sdim#define IXGBE_RXD_PRI_SHIFT 13 910214571Sdim#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 911214571Sdim#define IXGBE_RXD_CFI_SHIFT 12 912214571Sdim 913214571Sdim/* SRRCTL bit definitions */ 914214571Sdim#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 915214571Sdim#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 916214571Sdim#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 917214571Sdim#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 918214571Sdim#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 919214571Sdim#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 920214571Sdim#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 921214571Sdim#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 922214571Sdim 923214571Sdim#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 924214571Sdim#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 925214571Sdim 926214571Sdim#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 927214571Sdim#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 928214571Sdim#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 929214571Sdim#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 930214571Sdim#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 931214571Sdim#define IXGBE_RXDADV_SPH 0x8000 932214571Sdim 933214571Sdim/* RSS Hash results */ 934214571Sdim#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 935214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 936214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 937214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 938214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 939214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 940214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 941214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 942214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 943214571Sdim#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 944214571Sdim 945214571Sdim/* RSS Packet Types as indicated in the receive descriptor. */ 946214571Sdim#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 947214571Sdim#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 948214571Sdim#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 949214571Sdim#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 950214571Sdim#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 951214571Sdim#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 952214571Sdim#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 953214571Sdim#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 954214571Sdim#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 955214571Sdim 956214571Sdim/* Masks to determine if packets should be dropped due to frame errors */ 957214571Sdim#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 958214571Sdim IXGBE_RXD_ERR_CE | \ 959214571Sdim IXGBE_RXD_ERR_LE | \ 960214571Sdim IXGBE_RXD_ERR_PE | \ 961214571Sdim IXGBE_RXD_ERR_OSE | \ 962214571Sdim IXGBE_RXD_ERR_USE) 963214571Sdim 964214571Sdim#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 965214571Sdim IXGBE_RXDADV_ERR_CE | \ 966214571Sdim IXGBE_RXDADV_ERR_LE | \ 967214571Sdim IXGBE_RXDADV_ERR_PE | \ 968214571Sdim IXGBE_RXDADV_ERR_OSE | \ 969214571Sdim IXGBE_RXDADV_ERR_USE) 970214571Sdim 971214571Sdim/* Multicast bit mask */ 972214571Sdim#define IXGBE_MCSTCTRL_MFE 0x4 973214571Sdim 974214571Sdim/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 975214571Sdim#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 976214571Sdim#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 977214571Sdim#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 978214571Sdim 979214571Sdim/* Vlan-specific macros */ 980214571Sdim#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 981214571Sdim#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 982214571Sdim#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 983214571Sdim#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 984214571Sdim 985214571Sdim/* Transmit Descriptor - Legacy */ 986214571Sdimstruct ixgbe_legacy_tx_desc { 987214571Sdim u64 buffer_addr; /* Address of the descriptor's data buffer */ 988214571Sdim union { 989214571Sdim u32 data; 990214571Sdim struct { 991214571Sdim u16 length; /* Data buffer length */ 992214571Sdim u8 cso; /* Checksum offset */ 993214571Sdim u8 cmd; /* Descriptor control */ 994214571Sdim } flags; 995214571Sdim } lower; 996214571Sdim union { 997214571Sdim u32 data; 998214571Sdim struct { 999214571Sdim u8 status; /* Descriptor status */ 1000214571Sdim u8 css; /* Checksum start */ 1001214571Sdim u16 vlan; 1002214571Sdim } fields; 1003214571Sdim } upper; 1004214571Sdim}; 1005214571Sdim 1006214571Sdim/* Transmit Descriptor - Advanced */ 1007214571Sdimunion ixgbe_adv_tx_desc { 1008214571Sdim struct { 1009214571Sdim u64 buffer_addr; /* Address of descriptor's data buf */ 1010214571Sdim u32 cmd_type_len; 1011214571Sdim u32 olinfo_status; 1012214571Sdim } read; 1013214571Sdim struct { 1014214571Sdim u64 rsvd; /* Reserved */ 1015214571Sdim u32 nxtseq_seed; 1016214571Sdim u32 status; 1017214571Sdim } wb; 1018214571Sdim}; 1019214571Sdim 1020214571Sdim/* Receive Descriptor - Legacy */ 1021214571Sdimstruct ixgbe_legacy_rx_desc { 1022214571Sdim u64 buffer_addr; /* Address of the descriptor's data buffer */ 1023214571Sdim u16 length; /* Length of data DMAed into data buffer */ 1024214571Sdim u16 csum; /* Packet checksum */ 1025214571Sdim u8 status; /* Descriptor status */ 1026214571Sdim u8 errors; /* Descriptor Errors */ 1027214571Sdim u16 vlan; 1028214571Sdim}; 1029214571Sdim 1030214571Sdim/* Receive Descriptor - Advanced */ 1031214571Sdimunion ixgbe_adv_rx_desc { 1032214571Sdim struct { 1033214571Sdim u64 pkt_addr; /* Packet buffer address */ 1034214571Sdim u64 hdr_addr; /* Header buffer address */ 1035214571Sdim } read; 1036214571Sdim struct { 1037214571Sdim struct { 1038214571Sdim struct { 1039214571Sdim u16 pkt_info; /* RSS type, Packet type */ 1040214571Sdim u16 hdr_info; /* Split Header, header len */ 1041214571Sdim } lo_dword; 1042214571Sdim union { 1043214571Sdim u32 rss; /* RSS Hash */ 1044214571Sdim struct { 1045214571Sdim u16 ip_id; /* IP id */ 1046214571Sdim u16 csum; /* Packet Checksum */ 1047214571Sdim } csum_ip; 1048214571Sdim } hi_dword; 1049214571Sdim } lower; 1050214571Sdim struct { 1051214571Sdim u32 status_error; /* ext status/error */ 1052214571Sdim u16 length; /* Packet length */ 1053214571Sdim u16 vlan; /* VLAN tag */ 1054214571Sdim } upper; 1055214571Sdim } wb; /* writeback */ 1056214571Sdim}; 1057214571Sdim 1058214571Sdim/* Context descriptors */ 1059214571Sdimstruct ixgbe_adv_tx_context_desc { 1060214571Sdim u32 vlan_macip_lens; 1061214571Sdim u32 seqnum_seed; 1062214571Sdim u32 type_tucmd_mlhl; 1063214571Sdim u32 mss_l4len_idx; 1064214571Sdim}; 1065214571Sdim 1066214571Sdim/* Adv Transmit Descriptor Config Masks */ 1067214571Sdim#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */ 1068214571Sdim#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 1069214571Sdim#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 1070214571Sdim#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 1071214571Sdim#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 1072214571Sdim#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 1073214571Sdim#define IXGBE_ADVTXD_DCMD_RDMA 0x04000000 /* RDMA */ 1074214571Sdim#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 1075214571Sdim#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 1076214571Sdim#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 1077214571Sdim#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 1078214571Sdim#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 1079214571Sdim#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 1080214571Sdim#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */ 1081214571Sdim#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 1082214571Sdim#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 1083214571Sdim#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 1084214571Sdim#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 1085214571Sdim IXGBE_ADVTXD_POPTS_SHIFT) 1086214571Sdim#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 1087214571Sdim IXGBE_ADVTXD_POPTS_SHIFT) 1088214571Sdim#define IXGBE_ADVTXD_POPTS_EOM 0x00000400 /* Enable L bit-RDMA DDP hdr */ 1089214571Sdim#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 1090214571Sdim#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 1091214571Sdim#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 1092214571Sdim#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/ 1093214571Sdim#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 1094214571Sdim#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 1095214571Sdim#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 1096214571Sdim#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 1097214571Sdim#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 1098214571Sdim#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 1099214571Sdim#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 1100214571Sdim#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 1101214571Sdim#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */ 1102214571Sdim#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 1103214571Sdim#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 1104214571Sdim 1105214571Sdim/* Autonegotiation advertised speeds */ 1106214571Sdimtypedef u32 ixgbe_autoneg_advertised; 1107214571Sdim/* Link speed */ 1108214571Sdimtypedef u32 ixgbe_link_speed; 1109214571Sdim#define IXGBE_LINK_SPEED_UNKNOWN 0 1110214571Sdim#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 1111214571Sdim#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 1112214571Sdim 1113214571Sdim 1114214571Sdimenum ixgbe_eeprom_type { 1115214571Sdim ixgbe_eeprom_uninitialized = 0, 1116214571Sdim ixgbe_eeprom_spi, 1117214571Sdim ixgbe_eeprom_none /* No NVM support */ 1118214571Sdim}; 1119214571Sdim 1120214571Sdimenum ixgbe_mac_type { 1121214571Sdim ixgbe_mac_unknown = 0, 1122214571Sdim ixgbe_mac_82598EB, 1123214571Sdim ixgbe_num_macs 1124214571Sdim}; 1125214571Sdim 1126214571Sdimenum ixgbe_phy_type { 1127214571Sdim ixgbe_phy_unknown = 0, 1128214571Sdim ixgbe_phy_tn, 1129214571Sdim ixgbe_phy_qt, 1130214571Sdim ixgbe_phy_xaui 1131214571Sdim}; 1132214571Sdim 1133214571Sdimenum ixgbe_media_type { 1134214571Sdim ixgbe_media_type_unknown = 0, 1135214571Sdim ixgbe_media_type_fiber, 1136214571Sdim ixgbe_media_type_copper, 1137214571Sdim ixgbe_media_type_backplane 1138214571Sdim}; 1139214571Sdim 1140214571Sdim/* Flow Control Settings */ 1141214571Sdimenum ixgbe_fc_type { 1142214571Sdim ixgbe_fc_none = 0, 1143214571Sdim ixgbe_fc_rx_pause, 1144214571Sdim ixgbe_fc_tx_pause, 1145214571Sdim ixgbe_fc_full, 1146214571Sdim ixgbe_fc_default 1147214571Sdim}; 1148214571Sdim 1149214571Sdim/* PCI bus types */ 1150214571Sdimenum ixgbe_bus_type { 1151214571Sdim ixgbe_bus_type_unknown = 0, 1152214571Sdim ixgbe_bus_type_pci, 1153214571Sdim ixgbe_bus_type_pcix, 1154214571Sdim ixgbe_bus_type_pci_express, 1155214571Sdim ixgbe_bus_type_reserved 1156214571Sdim}; 1157214571Sdim 1158214571Sdim/* PCI bus speeds */ 1159214571Sdimenum ixgbe_bus_speed { 1160214571Sdim ixgbe_bus_speed_unknown = 0, 1161214571Sdim ixgbe_bus_speed_33, 1162214571Sdim ixgbe_bus_speed_66, 1163214571Sdim ixgbe_bus_speed_100, 1164214571Sdim ixgbe_bus_speed_120, 1165214571Sdim ixgbe_bus_speed_133, 1166214571Sdim ixgbe_bus_speed_2500, 1167214571Sdim ixgbe_bus_speed_5000, 1168214571Sdim ixgbe_bus_speed_reserved 1169214571Sdim}; 1170214571Sdim 1171214571Sdim/* PCI bus widths */ 1172214571Sdimenum ixgbe_bus_width { 1173214571Sdim ixgbe_bus_width_unknown = 0, 1174214571Sdim ixgbe_bus_width_pcie_x1, 1175214571Sdim ixgbe_bus_width_pcie_x2, 1176214571Sdim ixgbe_bus_width_pcie_x4, 1177214571Sdim ixgbe_bus_width_pcie_x8, 1178214571Sdim ixgbe_bus_width_32, 1179214571Sdim ixgbe_bus_width_64, 1180214571Sdim ixgbe_bus_width_reserved 1181214571Sdim}; 1182214571Sdim 1183214571Sdimstruct ixgbe_eeprom_info { 1184214571Sdim enum ixgbe_eeprom_type type; 1185214571Sdim u16 word_size; 1186214571Sdim u16 address_bits; 1187214571Sdim}; 1188214571Sdim 1189214571Sdimstruct ixgbe_addr_filter_info { 1190214571Sdim u32 num_mc_addrs; 1191214571Sdim u32 rar_used_count; 1192214571Sdim u32 mc_addr_in_rar_count; 1193214571Sdim u32 mta_in_use; 1194214571Sdim}; 1195214571Sdim 1196214571Sdim/* Bus parameters */ 1197214571Sdimstruct ixgbe_bus_info { 1198 enum ixgbe_bus_speed speed; 1199 enum ixgbe_bus_width width; 1200 enum ixgbe_bus_type type; 1201}; 1202 1203/* Flow control parameters */ 1204struct ixgbe_fc_info { 1205 u32 high_water; /* Flow Control High-water */ 1206 u32 low_water; /* Flow Control Low-water */ 1207 u16 pause_time; /* Flow Control Pause timer */ 1208 bool send_xon; /* Flow control send XON */ 1209 bool strict_ieee; /* Strict IEEE mode */ 1210 enum ixgbe_fc_type type; /* Type of flow control */ 1211 enum ixgbe_fc_type original_type; 1212}; 1213 1214/* Statistics counters collected by the MAC */ 1215struct ixgbe_hw_stats { 1216 u64 crcerrs; 1217 u64 illerrc; 1218 u64 errbc; 1219 u64 mspdc; 1220 u64 mpctotal; 1221 u64 mpc[8]; 1222 u64 mlfc; 1223 u64 mrfc; 1224 u64 rlec; 1225 u64 lxontxc; 1226 u64 lxonrxc; 1227 u64 lxofftxc; 1228 u64 lxoffrxc; 1229 u64 pxontxc[8]; 1230 u64 pxonrxc[8]; 1231 u64 pxofftxc[8]; 1232 u64 pxoffrxc[8]; 1233 u64 prc64; 1234 u64 prc127; 1235 u64 prc255; 1236 u64 prc511; 1237 u64 prc1023; 1238 u64 prc1522; 1239 u64 gprc; 1240 u64 bprc; 1241 u64 mprc; 1242 u64 gptc; 1243 u64 gorc; 1244 u64 gotc; 1245 u64 rnbc[8]; 1246 u64 ruc; 1247 u64 rfc; 1248 u64 roc; 1249 u64 rjc; 1250 u64 mngprc; 1251 u64 mngpdc; 1252 u64 mngptc; 1253 u64 tor; 1254 u64 tpr; 1255 u64 tpt; 1256 u64 ptc64; 1257 u64 ptc127; 1258 u64 ptc255; 1259 u64 ptc511; 1260 u64 ptc1023; 1261 u64 ptc1522; 1262 u64 mptc; 1263 u64 bptc; 1264 u64 xec; 1265 u64 rqsmr[16]; 1266 u64 tqsmr[8]; 1267 u64 qprc[16]; 1268 u64 qptc[16]; 1269 u64 qbrc[16]; 1270 u64 qbtc[16]; 1271}; 1272 1273 1274/* forward declaration */ 1275struct ixgbe_hw; 1276 1277/* Function pointer table */ 1278struct ixgbe_functions 1279{ 1280 s32 (*ixgbe_func_init_hw)(struct ixgbe_hw *); 1281 s32 (*ixgbe_func_reset_hw)(struct ixgbe_hw *); 1282 s32 (*ixgbe_func_start_hw)(struct ixgbe_hw *); 1283 s32 (*ixgbe_func_clear_hw_cntrs)(struct ixgbe_hw *); 1284 enum ixgbe_media_type (*ixgbe_func_get_media_type)(struct ixgbe_hw *); 1285 s32 (*ixgbe_func_get_mac_addr)(struct ixgbe_hw *, u8 *); 1286 u32 (*ixgbe_func_get_num_of_tx_queues)(struct ixgbe_hw *); 1287 u32 (*ixgbe_func_get_num_of_rx_queues)(struct ixgbe_hw *); 1288 s32 (*ixgbe_func_stop_adapter)(struct ixgbe_hw *); 1289 s32 (*ixgbe_func_get_bus_info)(struct ixgbe_hw *); 1290 1291 1292 /* PHY */ 1293 s32 (*ixgbe_func_identify_phy)(struct ixgbe_hw *); 1294 s32 (*ixgbe_func_reset_phy)(struct ixgbe_hw *); 1295 s32 (*ixgbe_func_read_phy_reg)(struct ixgbe_hw *, u32, u32, u16 *); 1296 s32 (*ixgbe_func_write_phy_reg)(struct ixgbe_hw *, u32, u32, u16); 1297 s32 (*ixgbe_func_setup_phy_link)(struct ixgbe_hw *); 1298 s32 (*ixgbe_func_setup_phy_link_speed)(struct ixgbe_hw *, 1299 ixgbe_link_speed, 1300 bool, bool); 1301 s32 (*ixgbe_func_check_phy_link)(struct ixgbe_hw *, ixgbe_link_speed *, 1302 bool *); 1303 1304 /* Link */ 1305 s32 (*ixgbe_func_setup_link)(struct ixgbe_hw *); 1306 s32 (*ixgbe_func_setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, 1307 bool, bool); 1308 s32 (*ixgbe_func_check_link)(struct ixgbe_hw *, ixgbe_link_speed *, 1309 bool *); 1310 s32 (*ixgbe_func_get_link_settings)(struct ixgbe_hw *, 1311 ixgbe_link_speed *, 1312 bool *); 1313 1314 /* LED */ 1315 s32 (*ixgbe_func_led_on)(struct ixgbe_hw *, u32); 1316 s32 (*ixgbe_func_led_off)(struct ixgbe_hw *, u32); 1317 s32 (*ixgbe_func_blink_led_start)(struct ixgbe_hw *, u32); 1318 s32 (*ixgbe_func_blink_led_stop)(struct ixgbe_hw *, u32); 1319 1320 /* EEPROM */ 1321 s32 (*ixgbe_func_init_eeprom_params)(struct ixgbe_hw *); 1322 s32 (*ixgbe_func_read_eeprom)(struct ixgbe_hw *, u16, u16 *); 1323 s32 (*ixgbe_func_write_eeprom)(struct ixgbe_hw *, u16, u16); 1324 s32 (*ixgbe_func_validate_eeprom_checksum)(struct ixgbe_hw *, u16 *); 1325 s32 (*ixgbe_func_update_eeprom_checksum)(struct ixgbe_hw *); 1326 1327 /* RAR, Multicast, VLAN */ 1328 s32 (*ixgbe_func_set_rar)(struct ixgbe_hw *, u32, u8 *, u32 , u32); 1329 s32 (*ixgbe_func_init_rx_addrs)(struct ixgbe_hw *); 1330 u32 (*ixgbe_func_get_num_rx_addrs)(struct ixgbe_hw *); 1331 s32 (*ixgbe_func_update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 1332 u32); 1333 s32 (*ixgbe_func_enable_mc)(struct ixgbe_hw *); 1334 s32 (*ixgbe_func_disable_mc)(struct ixgbe_hw *); 1335 s32 (*ixgbe_func_clear_vfta)(struct ixgbe_hw *); 1336 s32 (*ixgbe_func_set_vfta)(struct ixgbe_hw *, u32, u32, bool); 1337 1338 /* Flow Control */ 1339 s32 (*ixgbe_func_setup_fc)(struct ixgbe_hw *, s32); 1340}; 1341 1342struct ixgbe_mac_info { 1343 enum ixgbe_mac_type type; 1344 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1345 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 1346 s32 mc_filter_type; 1347 u32 link_attach_type; 1348 u32 link_mode_select; 1349 bool link_settings_loaded; 1350}; 1351 1352struct ixgbe_phy_info { 1353 enum ixgbe_phy_type type; 1354 u32 addr; 1355 u32 id; 1356 u32 revision; 1357 enum ixgbe_media_type media_type; 1358 ixgbe_autoneg_advertised autoneg_advertised; 1359 bool autoneg_wait_to_complete; 1360}; 1361 1362struct ixgbe_hw { 1363 u8 *hw_addr; 1364 void *back; 1365 struct ixgbe_functions func; 1366 struct ixgbe_mac_info mac; 1367 struct ixgbe_addr_filter_info addr_ctrl; 1368 struct ixgbe_fc_info fc; 1369 struct ixgbe_phy_info phy; 1370 struct ixgbe_eeprom_info eeprom; 1371 struct ixgbe_bus_info bus; 1372 u16 device_id; 1373 u16 vendor_id; 1374 u16 subsystem_device_id; 1375 u16 subsystem_vendor_id; 1376 u8 revision_id; 1377 bool adapter_stopped; 1378}; 1379 1380 1381#define ixgbe_func_from_hw_struct(hw, _func) hw->func._func 1382 1383#define ixgbe_call_func(hw, func, params, error) \ 1384 (ixgbe_func_from_hw_struct(hw, func) != NULL) ? \ 1385 ixgbe_func_from_hw_struct(hw, func) params: error 1386 1387/* Error Codes */ 1388#define IXGBE_SUCCESS 0 1389#define IXGBE_ERR_EEPROM -1 1390#define IXGBE_ERR_EEPROM_CHECKSUM -2 1391#define IXGBE_ERR_PHY -3 1392#define IXGBE_ERR_CONFIG -4 1393#define IXGBE_ERR_PARAM -5 1394#define IXGBE_ERR_MAC_TYPE -6 1395#define IXGBE_ERR_UNKNOWN_PHY -7 1396#define IXGBE_ERR_LINK_SETUP -8 1397#define IXGBE_ERR_ADAPTER_STOPPED -9 1398#define IXGBE_ERR_INVALID_MAC_ADDR -10 1399#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 1400#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 1401#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 1402#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 1403#define IXGBE_ERR_RESET_FAILED -15 1404#define IXGBE_ERR_SWFW_SYNC -16 1405#define IXGBE_ERR_PHY_ADDR_INVALID -17 1406#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 1407 1408#ifndef UNREFERENCED_PARAMETER 1409#define UNREFERENCED_PARAMETER(_p) 1410#endif 1411 1412#endif /* _IXGBE_TYPE_H_ */ 1413