1251964Sjfv/****************************************************************************** 2251964Sjfv 3251964Sjfv Copyright (c) 2001-2013, Intel Corporation 4251964Sjfv All rights reserved. 5251964Sjfv 6251964Sjfv Redistribution and use in source and binary forms, with or without 7251964Sjfv modification, are permitted provided that the following conditions are met: 8251964Sjfv 9251964Sjfv 1. Redistributions of source code must retain the above copyright notice, 10251964Sjfv this list of conditions and the following disclaimer. 11251964Sjfv 12251964Sjfv 2. Redistributions in binary form must reproduce the above copyright 13251964Sjfv notice, this list of conditions and the following disclaimer in the 14251964Sjfv documentation and/or other materials provided with the distribution. 15251964Sjfv 16251964Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17251964Sjfv contributors may be used to endorse or promote products derived from 18251964Sjfv this software without specific prior written permission. 19251964Sjfv 20251964Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21251964Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22251964Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23251964Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24251964Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25251964Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26251964Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27251964Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28251964Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29251964Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30251964Sjfv POSSIBILITY OF SUCH DAMAGE. 31251964Sjfv 32251964Sjfv******************************************************************************/ 33251964Sjfv/*$FreeBSD$*/ 34251964Sjfv 35251964Sjfv#ifndef _IXGBE_DCB_82599_H_ 36251964Sjfv#define _IXGBE_DCB_82599_H_ 37251964Sjfv 38251964Sjfv/* DCB register definitions */ 39251964Sjfv#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin, 40251964Sjfv * 1 WSP - Weighted Strict Priority 41251964Sjfv */ 42251964Sjfv#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin, 43251964Sjfv * 1 WRR - Weighted Round Robin 44251964Sjfv */ 45251964Sjfv#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */ 46251964Sjfv#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */ 47251964Sjfv#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must 48251964Sjfv * clear! 49251964Sjfv */ 50251964Sjfv#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */ 51251964Sjfv 52251964Sjfv/* Receive UP2TC mapping */ 53251964Sjfv#define IXGBE_RTRUP2TC_UP_SHIFT 3 54251964Sjfv#define IXGBE_RTRUP2TC_UP_MASK 7 55251964Sjfv/* Transmit UP2TC mapping */ 56251964Sjfv#define IXGBE_RTTUP2TC_UP_SHIFT 3 57251964Sjfv 58251964Sjfv#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 59251964Sjfv#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */ 60251964Sjfv#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */ 61251964Sjfv#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */ 62251964Sjfv 63251964Sjfv#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 64251964Sjfv * buffers enable 65251964Sjfv */ 66251964Sjfv#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 67251964Sjfv * (RSS) enable 68251964Sjfv */ 69251964Sjfv 70251964Sjfv/* RTRPCS Bit Masks */ 71251964Sjfv#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 72251964Sjfv/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 73251964Sjfv#define IXGBE_RTRPCS_RAC 0x00000004 74251964Sjfv#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 75251964Sjfv 76251964Sjfv/* RTTDT2C Bit Masks */ 77251964Sjfv#define IXGBE_RTTDT2C_MCL_SHIFT 12 78251964Sjfv#define IXGBE_RTTDT2C_BWG_SHIFT 9 79251964Sjfv#define IXGBE_RTTDT2C_GSP 0x40000000 80251964Sjfv#define IXGBE_RTTDT2C_LSP 0x80000000 81251964Sjfv 82251964Sjfv#define IXGBE_RTTPT2C_MCL_SHIFT 12 83251964Sjfv#define IXGBE_RTTPT2C_BWG_SHIFT 9 84251964Sjfv#define IXGBE_RTTPT2C_GSP 0x40000000 85251964Sjfv#define IXGBE_RTTPT2C_LSP 0x80000000 86251964Sjfv 87251964Sjfv/* RTTPCS Bit Masks */ 88251964Sjfv#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin, 89251964Sjfv * 1 SP - Strict Priority 90251964Sjfv */ 91251964Sjfv#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */ 92251964Sjfv#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */ 93251964Sjfv#define IXGBE_RTTPCS_ARBD_SHIFT 22 94251964Sjfv#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */ 95251964Sjfv 96251964Sjfv#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ 97251964Sjfv 98251964Sjfv/* SECTXMINIFG DCB */ 99251964Sjfv#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */ 100251964Sjfv 101251964Sjfv/* BCN register definitions */ 102251964Sjfv#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 103251964Sjfv#define IXGBE_RTTBCNRC_RS_ENA 0x80000000 104251964Sjfv 105251964Sjfv#define IXGBE_RTTBCNCR_MNG_CMTGI 0x00000001 106251964Sjfv#define IXGBE_RTTBCNCR_MGN_BCNA_MODE 0x00000002 107251964Sjfv#define IXGBE_RTTBCNCR_RSV7_11_SHIFT 5 108251964Sjfv#define IXGBE_RTTBCNCR_G 0x00000400 109251964Sjfv#define IXGBE_RTTBCNCR_I 0x00000800 110251964Sjfv#define IXGBE_RTTBCNCR_H 0x00001000 111251964Sjfv#define IXGBE_RTTBCNCR_VER_SHIFT 14 112251964Sjfv#define IXGBE_RTTBCNCR_CMT_ETH_SHIFT 16 113251964Sjfv 114251964Sjfv#define IXGBE_RTTBCNACL_SMAC_L_SHIFT 16 115251964Sjfv 116251964Sjfv#define IXGBE_RTTBCNTG_BCNA_MODE 0x80000000 117251964Sjfv 118251964Sjfv#define IXGBE_RTTBCNRTT_TS_SHIFT 3 119251964Sjfv#define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT 16 120251964Sjfv 121251964Sjfv#define IXGBE_RTTBCNRD_BCN_CLEAR_ALL 0x00000002 122251964Sjfv#define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT 2 123251964Sjfv#define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT 16 124251964Sjfv#define IXGBE_RTTBCNRD_DRIFT_ENA 0x80000000 125251964Sjfv 126251964Sjfv 127251964Sjfv/* DCB driver APIs */ 128251964Sjfv 129251964Sjfv/* DCB PFC */ 130251964Sjfvs32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *); 131251964Sjfv 132251964Sjfv/* DCB stats */ 133251964Sjfvs32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *, 134251964Sjfv struct ixgbe_dcb_config *); 135251964Sjfvs32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *, 136251964Sjfv struct ixgbe_hw_stats *, u8); 137251964Sjfvs32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *, 138251964Sjfv struct ixgbe_hw_stats *, u8); 139251964Sjfv 140251964Sjfv/* DCB config arbiters */ 141251964Sjfvs32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 142251964Sjfv u8 *, u8 *); 143251964Sjfvs32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, 144251964Sjfv u8 *, u8 *, u8 *); 145251964Sjfvs32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *, 146251964Sjfv u8 *, u8 *); 147251964Sjfv 148251964Sjfv/* DCB initialization */ 149251964Sjfvs32 ixgbe_dcb_config_82599(struct ixgbe_hw *, 150251964Sjfv struct ixgbe_dcb_config *); 151251964Sjfv 152251964Sjfvs32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, 153251964Sjfv u8 *, u8 *); 154251964Sjfv#endif /* _IXGBE_DCB_82959_H_ */ 155