1141398Sphk/*- 2141398Sphk * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3202870Sjoerg * Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org> 4141398Sphk * All rights reserved. 5141398Sphk * 6141398Sphk * Redistribution and use in source and binary forms, with or without 7141398Sphk * modification, are permitted provided that the following conditions 8141398Sphk * are met: 9141398Sphk * 1. Redistributions of source code must retain the above copyright 10141398Sphk * notice, this list of conditions and the following disclaimer. 11141398Sphk * 2. Redistributions in binary form must reproduce the above copyright 12141398Sphk * notice, this list of conditions and the following disclaimer in the 13141398Sphk * documentation and/or other materials provided with the distribution. 14141398Sphk * 15141398Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16141398Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17141398Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18141398Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19141398Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20141398Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21141398Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22141398Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23141398Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24141398Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25141398Sphk * SUCH DAMAGE. 26141398Sphk * 27141398Sphk * $FreeBSD$ 28141398Sphk * 29141398Sphk * Locating an actual �PD7210 data book has proven quite impossible for me. 30141398Sphk * There are a fair number of newer chips which are supersets of the �PD7210 31141398Sphk * but they are particular eager to comprehensively mark what the extensions 32141398Sphk * are and what is in the base set. Some even give the registers and their 33141398Sphk * bits new names. 34141398Sphk * 35141398Sphk * The following information is based on a description of the �PD7210 found 36141398Sphk * in an old manual for a VME board which used the chip. 37141398Sphk */ 38141398Sphk 39141747Sphk#ifndef _DEV_IEEE488_UPD7210_H_ 40141747Sphk#define _DEV_IEEE488_UPD7210_H_ 41141747Sphk#ifdef _KERNEL 42141398Sphk 43141398Sphkstruct upd7210; 44141398Sphkstruct ibfoo; 45141398Sphk 46141747Sphk/* upd7210 interface definitions for HW drivers */ 47141398Sphk 48141747Sphktypedef int upd7210_irq_t(struct upd7210 *, int); 49141398Sphk 50141398Sphkstruct upd7210 { 51150525Sphk struct resource *reg_res[8]; 52202870Sjoerg struct resource *irq_clear_res; 53202898Sjoerg u_int reg_offset[8]; 54141777Sphk int dmachan; 55150153Sphk int unit; 56203360Sjoerg int use_fifo; 57141398Sphk 58141398Sphk /* private stuff */ 59141398Sphk struct mtx mutex; 60141398Sphk uint8_t rreg[8]; 61141398Sphk uint8_t wreg[8 + 8]; 62141398Sphk 63141398Sphk upd7210_irq_t *irq; 64141398Sphk 65141398Sphk int busy; 66141398Sphk u_char *buf; 67141398Sphk size_t bufsize; 68141398Sphk u_int buf_wp; 69141398Sphk u_int buf_rp; 70141398Sphk struct cdev *cdev; 71141398Sphk 72141398Sphk struct ibfoo *ibfoo; 73141398Sphk}; 74141398Sphk 75141747Sphk#ifdef UPD7210_HW_DRIVER 76141747Sphkvoid upd7210intr(void *); 77141747Sphkvoid upd7210attach(struct upd7210 *); 78150153Sphkvoid upd7210detach(struct upd7210 *); 79141747Sphk#endif 80141747Sphk 81141747Sphk#ifdef UPD7210_SW_DRIVER 82141747Sphk 83141398Sphk/* upd7210 hardware definitions. */ 84141398Sphk 85141398Sphk/* Write registers */ 86141398Sphkenum upd7210_wreg { 87141398Sphk CDOR = 0, /* Command/Data Out Register */ 88141398Sphk IMR1 = 1, /* Interrupt Mask Register 1 */ 89141398Sphk IMR2 = 2, /* Interrupt Mask Register 2 */ 90141398Sphk SPMR = 3, /* Serial Poll Mode Register */ 91141398Sphk ADMR = 4, /* ADdress Mode Register */ 92141398Sphk AUXMR = 5, /* AUXilliary Mode Register */ 93141398Sphk ICR = 5, /* Internal Counter Register */ 94141398Sphk PPR = 5, /* Parallel Poll Register */ 95141398Sphk AUXRA = 5, /* AUXilliary Register A */ 96141398Sphk AUXRB = 5, /* AUXilliary Register B */ 97141398Sphk AUXRE = 5, /* AUXilliary Register E */ 98141398Sphk ADR = 6, /* ADdress Register */ 99141398Sphk EOSR = 7, /* End-Of-String Register */ 100141398Sphk}; 101141398Sphk 102141398Sphk/* Read registers */ 103141398Sphkenum upd7210_rreg { 104141398Sphk DIR = 0, /* Data In Register */ 105141398Sphk ISR1 = 1, /* Interrupt Status Register 1 */ 106141398Sphk ISR2 = 2, /* Interrupt Status Register 2 */ 107141398Sphk SPSR = 3, /* Serial Poll Status Register */ 108141398Sphk ADSR = 4, /* ADdress Status Register */ 109141398Sphk CPTR = 5, /* Command Pass Though Register */ 110141398Sphk ADR0 = 6, /* ADdress Register 0 */ 111141398Sphk ADR1 = 7, /* ADdress Register 1 */ 112141398Sphk}; 113141398Sphk 114141398Sphk/* Bits for ISR1 and IMR1 */ 115141398Sphk#define IXR1_DI (1 << 0) /* Data In */ 116141398Sphk#define IXR1_DO (1 << 1) /* Data Out */ 117141398Sphk#define IXR1_ERR (1 << 2) /* Error */ 118141398Sphk#define IXR1_DEC (1 << 3) /* Device Clear */ 119141398Sphk#define IXR1_ENDRX (1 << 4) /* End Received */ 120141398Sphk#define IXR1_DET (1 << 5) /* Device Execute Trigger */ 121141398Sphk#define IXR1_APT (1 << 6) /* Address Pass-Through */ 122141398Sphk#define IXR1_CPT (1 << 7) /* Command Pass-Through */ 123141398Sphk 124141398Sphk/* Bits for ISR2 and IMR2 */ 125141398Sphk#define IXR2_ADSC (1 << 0) /* Addressed Status Change */ 126141398Sphk#define IXR2_REMC (1 << 1) /* Remote Change */ 127141398Sphk#define IXR2_LOKC (1 << 2) /* Lockout Change */ 128141398Sphk#define IXR2_CO (1 << 3) /* Command Out */ 129141398Sphk#define ISR2_REM (1 << 4) /* Remove */ 130141398Sphk#define IMR2_DMAI (1 << 4) /* DMA In Enable */ 131141398Sphk#define ISR2_LOK (1 << 5) /* Lockout */ 132141398Sphk#define IMR2_DMAO (1 << 5) /* DMA Out Enable */ 133141398Sphk#define IXR2_SRQI (1 << 6) /* Service Request Input */ 134141398Sphk#define ISR2_INT (1 << 7) /* Interrupt */ 135141398Sphk 136141398Sphk#define SPSR_PEND (1 << 6) /* Pending */ 137141398Sphk#define SPMR_RSV (1 << 6) /* Request SerVice */ 138141398Sphk 139141398Sphk#define ADSR_MJMN (1 << 0) /* MaJor MiNor */ 140141398Sphk#define ADSR_TA (1 << 1) /* Talker Active */ 141141398Sphk#define ADSR_LA (1 << 2) /* Listener Active */ 142141398Sphk#define ADSR_TPAS (1 << 3) /* Talker Primary Addr. State */ 143141398Sphk#define ADSR_LPAS (1 << 4) /* Listener Primary Addr. State */ 144141398Sphk#define ADSR_SPMS (1 << 5) /* Serial Poll Mode State */ 145141398Sphk#define ADSR_ATN (1 << 6) /* Attention */ 146141398Sphk#define ADSR_CIC (1 << 7) /* Controller In Charge */ 147141398Sphk 148141398Sphk#define ADMR_ADM0 (1 << 0) /* Address Mode 0 */ 149141398Sphk#define ADMR_ADM1 (1 << 1) /* Address Mode 1 */ 150141398Sphk#define ADMR_TRM0 (1 << 4) /* Transmit/Receive Mode 0 */ 151141398Sphk#define ADMR_TRM1 (1 << 5) /* Transmit/Receive Mode 1 */ 152141398Sphk#define ADMR_LON (1 << 6) /* Listen Only */ 153141398Sphk#define ADMR_TON (1 << 7) /* Talk Only */ 154141398Sphk 155141398Sphk/* Constant part of overloaded write registers */ 156141398Sphk#define C_ICR 0x20 157141398Sphk#define C_PPR 0x60 158141398Sphk#define C_AUXA 0x80 159141398Sphk#define C_AUXB 0xa0 160141398Sphk#define C_AUXE 0xc0 161141398Sphk 162141398Sphk#define AUXMR_PON 0x00 /* Immediate Execute pon */ 163141398Sphk#define AUXMR_CPP 0x01 /* Clear Parallel Poll */ 164141398Sphk#define AUXMR_CRST 0x02 /* Chip Reset */ 165141398Sphk#define AUXMR_RFD 0x03 /* Finish Handshake */ 166141398Sphk#define AUXMR_TRIG 0x04 /* Trigger */ 167141398Sphk#define AUXMR_RTL 0x05 /* Return to local */ 168141398Sphk#define AUXMR_SEOI 0x06 /* Send EOI */ 169141398Sphk#define AUXMR_NVSA 0x07 /* Non-Valid Secondary cmd/addr */ 170141398Sphk /* 0x08 undefined/unknown */ 171141398Sphk#define AUXMR_SPP 0x09 /* Set Parallel Poll */ 172141398Sphk /* 0x0a undefined/unknown */ 173141398Sphk /* 0x0b undefined/unknown */ 174141398Sphk /* 0x0c undefined/unknown */ 175141398Sphk /* 0x0d undefined/unknown */ 176141398Sphk /* 0x0e undefined/unknown */ 177141398Sphk#define AUXMR_VSA 0x0f /* Valid Secondary cmd/addr */ 178141398Sphk#define AUXMR_GTS 0x10 /* Go to Standby */ 179141398Sphk#define AUXMR_TCA 0x11 /* Take Control Async (pulsed) */ 180141398Sphk#define AUXMR_TCS 0x12 /* Take Control Synchronously */ 181141398Sphk#define AUXMR_LISTEN 0x13 /* Listen */ 182141398Sphk#define AUXMR_DSC 0x14 /* Disable System Control */ 183141398Sphk /* 0x15 undefined/unknown */ 184141398Sphk#define AUXMR_SIFC 0x16 /* Set IFC */ 185141398Sphk#define AUXMR_CREN 0x17 /* Clear REN */ 186141398Sphk /* 0x18 undefined/unknown */ 187141398Sphk /* 0x19 undefined/unknown */ 188141398Sphk#define AUXMR_TCSE 0x1a /* Take Control Sync on End */ 189141398Sphk#define AUXMR_LCM 0x1b /* Listen Continuously Mode */ 190141398Sphk#define AUXMR_LUNL 0x1c /* Local Unlisten */ 191141398Sphk#define AUXMR_EPP 0x1d /* Execute Parallel Poll */ 192141398Sphk#define AUXMR_CIFC 0x1e /* Clear IFC */ 193141398Sphk#define AUXMR_SREN 0x1f /* Set REN */ 194141398Sphk 195141398Sphk#define PPR_U (1 << 4) /* Unconfigure */ 196141398Sphk#define PPR_S (1 << 3) /* Status Polarity */ 197141398Sphk 198141398Sphk#define AUXA_HLDA (1 << 0) /* Holdoff on All */ 199141398Sphk#define AUXA_HLDE (1 << 1) /* Holdoff on END */ 200141398Sphk#define AUXA_REOS (1 << 2) /* End on EOS received */ 201141398Sphk#define AUXA_XEOS (1 << 3) /* Transmit END with EOS */ 202141398Sphk#define AUXA_BIN (1 << 4) /* Binary */ 203141398Sphk 204141398Sphk#define AUXB_CPTE (1 << 0) /* Cmd Pass Through Enable */ 205141398Sphk#define AUXB_SPEOI (1 << 1) /* Send Serial Poll EOI */ 206141398Sphk#define AUXB_TRI (1 << 2) /* Three-State Timing */ 207141398Sphk#define AUXB_INV (1 << 3) /* Invert */ 208141398Sphk#define AUXB_ISS (1 << 4) /* Individual Status Select */ 209141398Sphk 210141398Sphk#define AUXE_DHDT (1 << 0) /* DAC Holdoff on DTAS */ 211141398Sphk#define AUXE_DHDC (1 << 1) /* DAC Holdoff on DCAS */ 212141398Sphk 213141398Sphk#define ADR0_DL0 (1 << 5) /* Disable Listener 0 */ 214141398Sphk#define ADR0_DT0 (1 << 6) /* Disable Talker 0 */ 215141398Sphk 216141398Sphk#define ADR_DL (1 << 5) /* Disable Listener */ 217141398Sphk#define ADR_DT (1 << 6) /* Disable Talker */ 218141398Sphk#define ADR_ARS (1 << 7) /* Address Register Select */ 219141398Sphk 220141398Sphk#define ADR1_DL1 (1 << 5) /* Disable Listener 1 */ 221141398Sphk#define ADR1_DT1 (1 << 6) /* Disable Talker 1 */ 222141398Sphk#define ADR1_EOI (1 << 7) /* End or Identify */ 223141398Sphk 224141747Sphk/* Stuff from software drivers */ 225141747Sphkextern struct cdevsw gpib_ib_cdevsw; 226141747Sphk 227141747Sphk/* Stuff from upd7210.c */ 228141747Sphkvoid upd7210_print_isr(u_int isr1, u_int isr2); 229141747Sphku_int upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg); 230141747Sphkvoid upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val); 231141747Sphkint upd7210_take_ctrl_async(struct upd7210 *u); 232141747Sphkint upd7210_goto_standby(struct upd7210 *u); 233141747Sphk 234141747Sphk#endif /* UPD7210_SW_DRIVER */ 235141747Sphk 236141747Sphk#endif /* _KERNEL */ 237141747Sphk#endif /* _DEV_IEEE488_UPD7210_H_ */ 238