177962Snyan/*-
277962Snyan * Copyright (c) 1991 The Regents of the University of California.
377962Snyan * All rights reserved.
477962Snyan *
577962Snyan * Redistribution and use in source and binary forms, with or without
677962Snyan * modification, are permitted provided that the following conditions
777962Snyan * are met:
877962Snyan * 1. Redistributions of source code must retain the above copyright
977962Snyan *    notice, this list of conditions and the following disclaimer.
1077962Snyan * 2. Redistributions in binary form must reproduce the above copyright
1177962Snyan *    notice, this list of conditions and the following disclaimer in the
1277962Snyan *    documentation and/or other materials provided with the distribution.
1377962Snyan * 4. Neither the name of the University nor the names of its contributors
1477962Snyan *    may be used to endorse or promote products derived from this software
1577962Snyan *    without specific prior written permission.
1677962Snyan *
1777962Snyan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
1877962Snyan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1977962Snyan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2077962Snyan * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
2177962Snyan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2277962Snyan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2377962Snyan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2477962Snyan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2577962Snyan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2677962Snyan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2777962Snyan * SUCH DAMAGE.
2877962Snyan *
2977962Snyan * $FreeBSD$
3077962Snyan */
3177962Snyan
3277962Snyan/*
3377962Snyan * modified for PC9801 by M.Ishii
3477962Snyan *			Kyoto University Microcomputer Club (KMC)
35182835Snyan *
3677962Snyan * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
3777962Snyan */
3877962Snyan
39182835Snyan/* i8251 mode register */
40182835Snyan#define	MOD8251_5BITS	0x00
41182835Snyan#define	MOD8251_6BITS	0x04
42182835Snyan#define	MOD8251_7BITS	0x08
43182835Snyan#define	MOD8251_8BITS	0x0c
44182835Snyan#define	MOD8251_PENAB	0x10	/* parity enable */
45182835Snyan#define	MOD8251_PEVEN	0x20	/* parity even */
46182835Snyan#define	MOD8251_STOP1	0x40	/* 1 stop bit */
47182835Snyan#define	MOD8251_STOP15	0x80	/* 1.5 stop bit */
48182835Snyan#define	MOD8251_STOP2	0xc0	/* 2 stop bit */
49182835Snyan#define	MOD8251_CLKx1	0x01	/* x1 */
50182835Snyan#define	MOD8251_CLKx16	0x02	/* x16 */
51182835Snyan#define	MOD8251_CLKx64	0x03	/* x64 */
52182835Snyan
53182835Snyan/* i8251 command register */
5477962Snyan#define	CMD8251_TxEN	0x01	/* transmit enable */
5577962Snyan#define	CMD8251_DTR	0x02	/* assert DTR */
5677962Snyan#define	CMD8251_RxEN	0x04	/* receive enable */
5777962Snyan#define	CMD8251_SBRK	0x08	/* send break */
5877962Snyan#define	CMD8251_ER	0x10	/* error reset */
5977962Snyan#define	CMD8251_RTS	0x20	/* assert RTS */
6077962Snyan#define	CMD8251_RESET	0x40	/* internal reset */
61182835Snyan#define	CMD8251_EH	0x80	/* enter hunt mode */
6277962Snyan
63182835Snyan/* i8251 status register */
6477962Snyan#define	STS8251_TxRDY	0x01	/* transmit READY */
6577962Snyan#define	STS8251_RxRDY	0x02	/* data exists in receive buffer */
6677962Snyan#define	STS8251_TxEMP	0x04	/* transmit buffer EMPTY */
6777962Snyan#define	STS8251_PE	0x08	/* perity error */
6877962Snyan#define	STS8251_OE	0x10	/* overrun error */
6977962Snyan#define	STS8251_FE	0x20	/* framing error */
70182835Snyan#define	STS8251_BI	0x40	/* break detect */
7177962Snyan#define	STS8251_DSR	0x80	/* DSR is asserted */
7277962Snyan
73182835Snyan/* i8251F line status register */
74182835Snyan#define	FLSR_TxEMP	0x01	/* transmit buffer EMPTY */
75182835Snyan#define	FLSR_TxRDY	0x02	/* transmit READY */
76182835Snyan#define	FLSR_RxRDY	0x04	/* data exists in receive buffer */
77182835Snyan#define	FLSR_OE		0x10	/* overrun error */
78182835Snyan#define	FLSR_PE		0x20	/* perity error */
79182835Snyan#define	FLSR_BI		0x80	/* break detect */
8077962Snyan
81182835Snyan/* i8251F modem status register */
82182835Snyan#define	MSR_DCD		0x80	/* Current Data Carrier Detect */
83182835Snyan#define	MSR_RI		0x40	/* Current Ring Indicator */
84182835Snyan#define	MSR_DSR		0x20	/* Current Data Set Ready */
85182835Snyan#define	MSR_CTS		0x10	/* Current Clear to Send */
86182835Snyan#define	MSR_DDCD	0x08	/* DCD has changed state */
87182835Snyan#define	MSR_TERI	0x04	/* RI has toggled low to high */
88182835Snyan#define	MSR_DDSR	0x02	/* DSR has changed state */
89182835Snyan#define	MSR_DCTS	0x01	/* CTS has changed state */
9077962Snyan
91182835Snyan/* i8251F interrupt identification register */
92182835Snyan#define	IIR_FIFO_CK1	0x40
93182835Snyan#define	IIR_FIFO_CK2	0x20
94182835Snyan#define	IIR_IMASK	0x0f
95182835Snyan#define	IIR_RXTOUT	0x0c	/* Receiver timeout */
96182835Snyan#define	IIR_RLS		0x06	/* Line status change */
97182835Snyan#define	IIR_RXRDY	0x04	/* Receiver ready */
98182835Snyan#define	IIR_TXRDY	0x02	/* Transmitter ready */
99182835Snyan#define	IIR_NOPEND	0x01	/* Transmitter ready */
100182835Snyan#define	IIR_MLSC	0x00	/* Modem status */
10177962Snyan
102182835Snyan/* i8251F fifo control register */
103182835Snyan#define	FIFO_ENABLE	0x01	/* Turn the FIFO on */
104182835Snyan#define	FIFO_RCV_RST	0x02	/* Reset RX FIFO */
105182835Snyan#define	FIFO_XMT_RST	0x04	/* Reset TX FIFO */
106182835Snyan#define	FIFO_LSR_EN	0x08
107182835Snyan#define	FIFO_MSR_EN	0x10
108182835Snyan#define	FIFO_TRIGGER_1	0x00	/* Trigger RXRDY intr on 1 character */
109182835Snyan#define	FIFO_TRIGGER_4	0x40	/* ibid 4 */
110182835Snyan#define	FIFO_TRIGGER_8	0x80	/* ibid 8 */
111182835Snyan#define	FIFO_TRIGGER_14	0xc0	/* ibid 14 */
112