1147191Sjkoshy/*- 2147191Sjkoshy * Copyright (c) 2005, Joseph Koshy 3147191Sjkoshy * All rights reserved. 4147191Sjkoshy * 5147191Sjkoshy * Redistribution and use in source and binary forms, with or without 6147191Sjkoshy * modification, are permitted provided that the following conditions 7147191Sjkoshy * are met: 8147191Sjkoshy * 1. Redistributions of source code must retain the above copyright 9147191Sjkoshy * notice, this list of conditions and the following disclaimer. 10147191Sjkoshy * 2. Redistributions in binary form must reproduce the above copyright 11147191Sjkoshy * notice, this list of conditions and the following disclaimer in the 12147191Sjkoshy * documentation and/or other materials provided with the distribution. 13147191Sjkoshy * 14147191Sjkoshy * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15147191Sjkoshy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16147191Sjkoshy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17147191Sjkoshy * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18147191Sjkoshy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19147191Sjkoshy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20147191Sjkoshy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21147191Sjkoshy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22147191Sjkoshy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23147191Sjkoshy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24147191Sjkoshy * SUCH DAMAGE. 25147191Sjkoshy * 26147191Sjkoshy * $FreeBSD$ 27147191Sjkoshy */ 28147191Sjkoshy 29147191Sjkoshy/* Machine dependent interfaces */ 30147191Sjkoshy 31147191Sjkoshy#ifndef _DEV_HWPMC_PIV_H_ 32147191Sjkoshy#define _DEV_HWPMC_PIV_H_ 1 33147191Sjkoshy 34147191Sjkoshy/* Intel P4 PMCs */ 35147191Sjkoshy 36184802Sjkoshy#define P4_NPMCS 18 37147191Sjkoshy#define P4_NESCR 45 38147191Sjkoshy#define P4_INVALID_PMC_INDEX -1 39147191Sjkoshy#define P4_MAX_ESCR_PER_EVENT 2 40147191Sjkoshy#define P4_MAX_PMC_PER_ESCR 3 41147191Sjkoshy 42147191Sjkoshy#define P4_CCCR_OVF (1 << 31) 43147191Sjkoshy#define P4_CCCR_CASCADE (1 << 30) 44147191Sjkoshy#define P4_CCCR_OVF_PMI_T1 (1 << 27) 45147191Sjkoshy#define P4_CCCR_OVF_PMI_T0 (1 << 26) 46147191Sjkoshy#define P4_CCCR_FORCE_OVF (1 << 25) 47147191Sjkoshy#define P4_CCCR_EDGE (1 << 24) 48147191Sjkoshy#define P4_CCCR_THRESHOLD_SHIFT 20 49147191Sjkoshy#define P4_CCCR_THRESHOLD_MASK 0x00F00000 50147191Sjkoshy#define P4_CCCR_TO_THRESHOLD(C) (((C) << P4_CCCR_THRESHOLD_SHIFT) & \ 51147191Sjkoshy P4_CCCR_THRESHOLD_MASK) 52147191Sjkoshy#define P4_CCCR_COMPLEMENT (1 << 19) 53147191Sjkoshy#define P4_CCCR_COMPARE (1 << 18) 54147191Sjkoshy#define P4_CCCR_ACTIVE_THREAD_SHIFT 16 55147191Sjkoshy#define P4_CCCR_ACTIVE_THREAD_MASK 0x00030000 56147191Sjkoshy#define P4_CCCR_TO_ACTIVE_THREAD(T) (((T) << P4_CCCR_ACTIVE_THREAD_SHIFT) & \ 57147191Sjkoshy P4_CCCR_ACTIVE_THREAD_MASK) 58147191Sjkoshy#define P4_CCCR_ESCR_SELECT_SHIFT 13 59147191Sjkoshy#define P4_CCCR_ESCR_SELECT_MASK 0x0000E000 60147191Sjkoshy#define P4_CCCR_TO_ESCR_SELECT(E) (((E) << P4_CCCR_ESCR_SELECT_SHIFT) & \ 61147191Sjkoshy P4_CCCR_ESCR_SELECT_MASK) 62147191Sjkoshy#define P4_CCCR_ENABLE (1 << 12) 63147191Sjkoshy#define P4_CCCR_VALID_BITS (P4_CCCR_OVF | P4_CCCR_CASCADE | \ 64147191Sjkoshy P4_CCCR_OVF_PMI_T1 | P4_CCCR_OVF_PMI_T0 | P4_CCCR_FORCE_OVF | \ 65147191Sjkoshy P4_CCCR_EDGE | P4_CCCR_THRESHOLD_MASK | P4_CCCR_COMPLEMENT | \ 66147191Sjkoshy P4_CCCR_COMPARE | P4_CCCR_ESCR_SELECT_MASK | P4_CCCR_ENABLE) 67147191Sjkoshy 68147191Sjkoshy#define P4_ESCR_EVENT_SELECT_SHIFT 25 69147191Sjkoshy#define P4_ESCR_EVENT_SELECT_MASK 0x7E000000 70147191Sjkoshy#define P4_ESCR_TO_EVENT_SELECT(E) (((E) << P4_ESCR_EVENT_SELECT_SHIFT) & \ 71147191Sjkoshy P4_ESCR_EVENT_SELECT_MASK) 72147191Sjkoshy#define P4_ESCR_EVENT_MASK_SHIFT 9 73147191Sjkoshy#define P4_ESCR_EVENT_MASK_MASK 0x01FFFE00 74147191Sjkoshy#define P4_ESCR_TO_EVENT_MASK(M) (((M) << P4_ESCR_EVENT_MASK_SHIFT) & \ 75147191Sjkoshy P4_ESCR_EVENT_MASK_MASK) 76147191Sjkoshy#define P4_ESCR_TAG_VALUE_SHIFT 5 77147191Sjkoshy#define P4_ESCR_TAG_VALUE_MASK 0x000001E0 78147191Sjkoshy#define P4_ESCR_TO_TAG_VALUE(T) (((T) << P4_ESCR_TAG_VALUE_SHIFT) & \ 79147191Sjkoshy P4_ESCR_TAG_VALUE_MASK) 80147191Sjkoshy#define P4_ESCR_TAG_ENABLE 0x00000010 81147191Sjkoshy#define P4_ESCR_T0_OS 0x00000008 82147191Sjkoshy#define P4_ESCR_T0_USR 0x00000004 83147191Sjkoshy#define P4_ESCR_T1_OS 0x00000002 84147191Sjkoshy#define P4_ESCR_T1_USR 0x00000001 85147191Sjkoshy#define P4_ESCR_OS P4_ESCR_T0_OS 86147191Sjkoshy#define P4_ESCR_USR P4_ESCR_T0_USR 87147191Sjkoshy#define P4_ESCR_VALID_BITS (P4_ESCR_EVENT_SELECT_MASK | \ 88147191Sjkoshy P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | \ 89147191Sjkoshy P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \ 90147191Sjkoshy P4_ESCR_T1_USR) 91147191Sjkoshy 92147191Sjkoshy#define P4_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */ 93147191Sjkoshy#define P4_PERFCTR_OVERFLOWED(PMC) ((rdpmc(PMC) & (1LL << 39)) == 0) 94147191Sjkoshy 95147191Sjkoshy#define P4_CCCR_MSR_FIRST 0x360 /* MSR_BPU_CCCR0 */ 96147191Sjkoshy#define P4_PERFCTR_MSR_FIRST 0x300 /* MSR_BPU_COUNTER0 */ 97147191Sjkoshy 98147191Sjkoshy#define P4_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (1 - (V)) 99147191Sjkoshy#define P4_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (1 - (P)) 100147191Sjkoshy 101147191Sjkoshystruct pmc_md_p4_op_pmcallocate { 102147191Sjkoshy uint32_t pm_p4_cccrconfig; 103147191Sjkoshy uint32_t pm_p4_escrconfig; 104147191Sjkoshy}; 105147191Sjkoshy 106147191Sjkoshy#ifdef _KERNEL 107147191Sjkoshy 108147191Sjkoshy/* MD extension for 'struct pmc' */ 109147191Sjkoshystruct pmc_md_p4_pmc { 110147191Sjkoshy uint32_t pm_p4_cccrvalue; 111147191Sjkoshy uint32_t pm_p4_escrvalue; 112147191Sjkoshy uint32_t pm_p4_escr; 113147191Sjkoshy uint32_t pm_p4_escrmsr; 114147191Sjkoshy}; 115147191Sjkoshy 116147191Sjkoshy 117147191Sjkoshy/* 118147191Sjkoshy * Prototypes 119147191Sjkoshy */ 120147191Sjkoshy 121184802Sjkoshyint pmc_p4_initialize(struct pmc_mdep *_md, int _ncpus); 122184802Sjkoshyvoid pmc_p4_finalize(struct pmc_mdep *md); 123147191Sjkoshy 124147191Sjkoshy#endif /* _KERNEL */ 125184802Sjkoshy#endif /* _DEV_HWPMC_PIV_H_ */ 126