12116Sjkh/*- 22116Sjkh * Copyright (c) 2005, Joseph Koshy 32116Sjkh * All rights reserved. 42116Sjkh * 52116Sjkh * Redistribution and use in source and binary forms, with or without 62116Sjkh * modification, are permitted provided that the following conditions 72116Sjkh * are met: 88870Srgrimes * 1. Redistributions of source code must retain the above copyright 92116Sjkh * notice, this list of conditions and the following disclaimer. 102116Sjkh * 2. Redistributions in binary form must reproduce the above copyright 112116Sjkh * notice, this list of conditions and the following disclaimer in the 122116Sjkh * documentation and/or other materials provided with the distribution. 13176305Sbde * 14176305Sbde * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 152116Sjkh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 162116Sjkh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 172116Sjkh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 182116Sjkh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 192116Sjkh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 202116Sjkh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 212116Sjkh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 222116Sjkh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 232116Sjkh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 242116Sjkh * SUCH DAMAGE. 25176305Sbde * 26176305Sbde * $FreeBSD$ 272116Sjkh */ 282116Sjkh 292116Sjkh/* Machine dependent interfaces */ 302116Sjkh 312116Sjkh#ifndef _DEV_HWPMC_AMD_H_ 3297413Salfred#define _DEV_HWPMC_AMD_H_ 1 33117912Speter 342116Sjkh/* AMD K7 and K8 PMCs */ 352116Sjkh 362116Sjkh#define AMD_PMC_EVSEL_0 0xC0010000 372116Sjkh#define AMD_PMC_EVSEL_1 0xC0010001 382116Sjkh#define AMD_PMC_EVSEL_2 0xC0010002 392116Sjkh#define AMD_PMC_EVSEL_3 0xC0010003 402116Sjkh 412116Sjkh#define AMD_PMC_PERFCTR_0 0xC0010004 428870Srgrimes#define AMD_PMC_PERFCTR_1 0xC0010005 432116Sjkh#define AMD_PMC_PERFCTR_2 0xC0010006 442116Sjkh#define AMD_PMC_PERFCTR_3 0xC0010007 452116Sjkh 462116Sjkh 472116Sjkh#define AMD_NPMCS 4 482116Sjkh 492116Sjkh#define AMD_PMC_COUNTERMASK 0xFF000000 502116Sjkh#define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) 512116Sjkh#define AMD_PMC_INVERT (1 << 23) 522116Sjkh#define AMD_PMC_ENABLE (1 << 22) 532116Sjkh#define AMD_PMC_INT (1 << 20) 542116Sjkh#define AMD_PMC_PC (1 << 19) 552116Sjkh#define AMD_PMC_EDGE (1 << 18) 562116Sjkh#define AMD_PMC_OS (1 << 17) 572116Sjkh#define AMD_PMC_USR (1 << 16) 582116Sjkh 592116Sjkh#define AMD_PMC_UNITMASK_M 0x10 602116Sjkh#define AMD_PMC_UNITMASK_O 0x08 618870Srgrimes#define AMD_PMC_UNITMASK_E 0x04 622116Sjkh#define AMD_PMC_UNITMASK_S 0x02 632116Sjkh#define AMD_PMC_UNITMASK_I 0x01 642116Sjkh#define AMD_PMC_UNITMASK_MOESI 0x1F 652116Sjkh 662116Sjkh#define AMD_PMC_UNITMASK 0xFF00 672116Sjkh#define AMD_PMC_EVENTMASK 0x00FF 682116Sjkh 692116Sjkh#define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 702116Sjkh#define AMD_PMC_TO_EVENTMASK(x) ((x) & 0xFF) 712116Sjkh#define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ 722116Sjkh AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ 732116Sjkh AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) 74176280Sbde 75176280Sbde#define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ 76176280Sbde PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ 77176280Sbde PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) 78 79#define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) 80#define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) 81 82#define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) 83#define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) 84 85struct pmc_md_amd_op_pmcallocate { 86 uint32_t pm_amd_config; 87}; 88 89#ifdef _KERNEL 90 91/* MD extension for 'struct pmc' */ 92struct pmc_md_amd_pmc { 93 uint32_t pm_amd_evsel; 94}; 95 96#endif /* _KERNEL */ 97#endif /* _DEV_HWPMC_AMD_H_ */ 98