1145256Sjkoshy/*- 2183266Sjkoshy * Copyright (c) 2003-2008 Joseph Koshy 3174395Sjkoshy * Copyright (c) 2007 The FreeBSD Foundation 4145256Sjkoshy * All rights reserved. 5145256Sjkoshy * 6174395Sjkoshy * Portions of this software were developed by A. Joseph Koshy under 7174395Sjkoshy * sponsorship from the FreeBSD Foundation and Google, Inc. 8174395Sjkoshy * 9145256Sjkoshy * Redistribution and use in source and binary forms, with or without 10145256Sjkoshy * modification, are permitted provided that the following conditions 11145256Sjkoshy * are met: 12145256Sjkoshy * 1. Redistributions of source code must retain the above copyright 13145256Sjkoshy * notice, this list of conditions and the following disclaimer. 14145256Sjkoshy * 2. Redistributions in binary form must reproduce the above copyright 15145256Sjkoshy * notice, this list of conditions and the following disclaimer in the 16145256Sjkoshy * documentation and/or other materials provided with the distribution. 17145256Sjkoshy * 18145256Sjkoshy * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19145256Sjkoshy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20145256Sjkoshy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21145256Sjkoshy * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22145256Sjkoshy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23145256Sjkoshy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24145256Sjkoshy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25145256Sjkoshy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26145256Sjkoshy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27145256Sjkoshy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28145256Sjkoshy * SUCH DAMAGE. 29145256Sjkoshy */ 30145256Sjkoshy 31145256Sjkoshy#include <sys/cdefs.h> 32145256Sjkoshy__FBSDID("$FreeBSD$"); 33145256Sjkoshy 34145256Sjkoshy/* Support for the AMD K7 and later processors */ 35145256Sjkoshy 36145256Sjkoshy#include <sys/param.h> 37145256Sjkoshy#include <sys/lock.h> 38145256Sjkoshy#include <sys/malloc.h> 39145256Sjkoshy#include <sys/mutex.h> 40145338Smarcel#include <sys/pmc.h> 41183266Sjkoshy#include <sys/pmckern.h> 42145256Sjkoshy#include <sys/smp.h> 43145256Sjkoshy#include <sys/systm.h> 44145256Sjkoshy 45174395Sjkoshy#include <machine/cpu.h> 46147191Sjkoshy#include <machine/cpufunc.h> 47145256Sjkoshy#include <machine/md_var.h> 48147191Sjkoshy#include <machine/specialreg.h> 49145256Sjkoshy 50153110Sru#ifdef DEBUG 51147191Sjkoshyenum pmc_class amd_pmc_class; 52145256Sjkoshy#endif 53145256Sjkoshy 54145256Sjkoshy/* AMD K7 & K8 PMCs */ 55145256Sjkoshystruct amd_descr { 56145256Sjkoshy struct pmc_descr pm_descr; /* "base class" */ 57145256Sjkoshy uint32_t pm_evsel; /* address of EVSEL register */ 58145256Sjkoshy uint32_t pm_perfctr; /* address of PERFCTR register */ 59145256Sjkoshy}; 60145256Sjkoshy 61147191Sjkoshystatic struct amd_descr amd_pmcdesc[AMD_NPMCS] = 62145256Sjkoshy{ 63145256Sjkoshy { 64145256Sjkoshy .pm_descr = 65145256Sjkoshy { 66147191Sjkoshy .pd_name = "", 67147191Sjkoshy .pd_class = -1, 68145256Sjkoshy .pd_caps = AMD_PMC_CAPS, 69145256Sjkoshy .pd_width = 48 70145256Sjkoshy }, 71145256Sjkoshy .pm_evsel = AMD_PMC_EVSEL_0, 72145256Sjkoshy .pm_perfctr = AMD_PMC_PERFCTR_0 73145256Sjkoshy }, 74145256Sjkoshy { 75145256Sjkoshy .pm_descr = 76145256Sjkoshy { 77147191Sjkoshy .pd_name = "", 78147191Sjkoshy .pd_class = -1, 79145256Sjkoshy .pd_caps = AMD_PMC_CAPS, 80145256Sjkoshy .pd_width = 48 81145256Sjkoshy }, 82145256Sjkoshy .pm_evsel = AMD_PMC_EVSEL_1, 83145256Sjkoshy .pm_perfctr = AMD_PMC_PERFCTR_1 84145256Sjkoshy }, 85145256Sjkoshy { 86145256Sjkoshy .pm_descr = 87145256Sjkoshy { 88147191Sjkoshy .pd_name = "", 89147191Sjkoshy .pd_class = -1, 90145256Sjkoshy .pd_caps = AMD_PMC_CAPS, 91145256Sjkoshy .pd_width = 48 92145256Sjkoshy }, 93145256Sjkoshy .pm_evsel = AMD_PMC_EVSEL_2, 94145256Sjkoshy .pm_perfctr = AMD_PMC_PERFCTR_2 95145256Sjkoshy }, 96145256Sjkoshy { 97145256Sjkoshy .pm_descr = 98145256Sjkoshy { 99147191Sjkoshy .pd_name = "", 100147191Sjkoshy .pd_class = -1, 101145256Sjkoshy .pd_caps = AMD_PMC_CAPS, 102145256Sjkoshy .pd_width = 48 103145256Sjkoshy }, 104145256Sjkoshy .pm_evsel = AMD_PMC_EVSEL_3, 105145256Sjkoshy .pm_perfctr = AMD_PMC_PERFCTR_3 106145256Sjkoshy } 107145256Sjkoshy}; 108145256Sjkoshy 109145256Sjkoshystruct amd_event_code_map { 110145256Sjkoshy enum pmc_event pe_ev; /* enum value */ 111145256Sjkoshy uint8_t pe_code; /* encoded event mask */ 112145256Sjkoshy uint8_t pe_mask; /* bits allowed in unit mask */ 113145256Sjkoshy}; 114145256Sjkoshy 115145256Sjkoshyconst struct amd_event_code_map amd_event_codes[] = { 116147191Sjkoshy#if defined(__i386__) /* 32 bit Athlon (K7) only */ 117145256Sjkoshy { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, 118145256Sjkoshy { PMC_EV_K7_DC_MISSES, 0x41, 0 }, 119147191Sjkoshy { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, 120147191Sjkoshy { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, 121147191Sjkoshy { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, 122145256Sjkoshy { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, 123145256Sjkoshy { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, 124145256Sjkoshy { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, 125145256Sjkoshy 126145256Sjkoshy { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, 127145256Sjkoshy { PMC_EV_K7_IC_MISSES, 0x81, 0 }, 128145256Sjkoshy 129145256Sjkoshy { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, 130145256Sjkoshy { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, 131145256Sjkoshy 132145256Sjkoshy { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, 133145256Sjkoshy { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, 134145256Sjkoshy { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, 135145256Sjkoshy { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, 136145256Sjkoshy { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, 137145256Sjkoshy { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, 138145256Sjkoshy { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, 139145256Sjkoshy { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, 140145256Sjkoshy { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, 141145256Sjkoshy { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, 142147191Sjkoshy { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, 143145256Sjkoshy#endif 144145256Sjkoshy 145145256Sjkoshy { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, 146145256Sjkoshy { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, 147145256Sjkoshy { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, 148145256Sjkoshy 149145256Sjkoshy { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, 150145256Sjkoshy { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 151145256Sjkoshy 0x21, 0x00 }, 152145256Sjkoshy { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, 153145256Sjkoshy { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, 154145256Sjkoshy { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, 155145256Sjkoshy { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, 156145256Sjkoshy { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, 157145256Sjkoshy { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, 158145256Sjkoshy 159145256Sjkoshy { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, 160145256Sjkoshy { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, 161145256Sjkoshy { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, 162145256Sjkoshy { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, 163145256Sjkoshy { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, 164145256Sjkoshy { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, 165145256Sjkoshy { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, 166145256Sjkoshy { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, 167145256Sjkoshy { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, 168145256Sjkoshy { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, 169145256Sjkoshy { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, 170145256Sjkoshy { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, 171145256Sjkoshy { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, 172145256Sjkoshy 173145256Sjkoshy { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, 174145256Sjkoshy { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, 175145256Sjkoshy { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, 176145256Sjkoshy { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, 177145256Sjkoshy 178145256Sjkoshy { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, 179145256Sjkoshy { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, 180145256Sjkoshy { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, 181145256Sjkoshy { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, 182145256Sjkoshy { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, 183145256Sjkoshy { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, 184145256Sjkoshy { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, 185145256Sjkoshy { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, 186145256Sjkoshy { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, 187145256Sjkoshy { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, 188145256Sjkoshy 189145256Sjkoshy { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, 190145256Sjkoshy { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, 191145256Sjkoshy { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, 192145256Sjkoshy { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, 193145256Sjkoshy { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, 194145256Sjkoshy { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, 195145256Sjkoshy { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, 196145256Sjkoshy { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, 197145256Sjkoshy { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, 198145256Sjkoshy { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, 199145256Sjkoshy { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 200145256Sjkoshy 0xCA, 0x00 }, 201145256Sjkoshy { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, 202145256Sjkoshy { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 203145256Sjkoshy 0xCC, 0x07 }, 204145256Sjkoshy { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, 205145256Sjkoshy { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, 206145256Sjkoshy { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, 207145256Sjkoshy 208145256Sjkoshy { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, 209145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, 210145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 211145256Sjkoshy 0xD2, 0x00 }, 212145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, 213145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, 214145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 215145256Sjkoshy 0xD5, 0x00 }, 216145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 217145256Sjkoshy 0xD6, 0x00 }, 218145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, 219145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, 220145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 221145256Sjkoshy 0xD9, 0x00 }, 222145256Sjkoshy { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 223145256Sjkoshy 0xDA, 0x00 }, 224145256Sjkoshy { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, 225145256Sjkoshy { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, 226145256Sjkoshy { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, 227145256Sjkoshy { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, 228145256Sjkoshy { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, 229145256Sjkoshy 230145256Sjkoshy { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, 231145256Sjkoshy { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, 232145256Sjkoshy { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 233145256Sjkoshy 0xE2, 0x00 }, 234145256Sjkoshy { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, 235145256Sjkoshy { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, 236145256Sjkoshy { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, 237145256Sjkoshy { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, 238145256Sjkoshy { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, 239145256Sjkoshy { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, 240145256Sjkoshy { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } 241145256Sjkoshy 242145256Sjkoshy}; 243145256Sjkoshy 244145256Sjkoshyconst int amd_event_codes_size = 245145256Sjkoshy sizeof(amd_event_codes) / sizeof(amd_event_codes[0]); 246145256Sjkoshy 247145256Sjkoshy/* 248184802Sjkoshy * Per-processor information 249184802Sjkoshy */ 250184802Sjkoshy 251184802Sjkoshystruct amd_cpu { 252184802Sjkoshy struct pmc_hw pc_amdpmcs[AMD_NPMCS]; 253184802Sjkoshy}; 254184802Sjkoshy 255184802Sjkoshystatic struct amd_cpu **amd_pcpu; 256184802Sjkoshy 257184802Sjkoshy/* 258145256Sjkoshy * read a pmc register 259145256Sjkoshy */ 260145256Sjkoshy 261145256Sjkoshystatic int 262145256Sjkoshyamd_read_pmc(int cpu, int ri, pmc_value_t *v) 263145256Sjkoshy{ 264145256Sjkoshy enum pmc_mode mode; 265145256Sjkoshy const struct amd_descr *pd; 266145256Sjkoshy struct pmc *pm; 267145256Sjkoshy pmc_value_t tmp; 268145256Sjkoshy 269183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 270145256Sjkoshy ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 271145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 272145256Sjkoshy ("[amd,%d] illegal row-index %d", __LINE__, ri)); 273184802Sjkoshy KASSERT(amd_pcpu[cpu], 274184802Sjkoshy ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu)); 275145256Sjkoshy 276184802Sjkoshy pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 277184802Sjkoshy pd = &amd_pmcdesc[ri]; 278145256Sjkoshy 279145256Sjkoshy KASSERT(pm != NULL, 280145256Sjkoshy ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, 281145256Sjkoshy cpu, ri)); 282145256Sjkoshy 283145774Sjkoshy mode = PMC_TO_MODE(pm); 284145256Sjkoshy 285145256Sjkoshy PMCDBG(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); 286145256Sjkoshy 287153110Sru#ifdef DEBUG 288147191Sjkoshy KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 289145256Sjkoshy ("[amd,%d] unknown PMC class (%d)", __LINE__, 290145256Sjkoshy pd->pm_descr.pd_class)); 291147191Sjkoshy#endif 292145256Sjkoshy 293145256Sjkoshy tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ 294177344Sadrian PMCDBG(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp); 295177344Sadrian if (PMC_IS_SAMPLING_MODE(mode)) { 296177344Sadrian /* Sign extend 48 bit value to 64 bits. */ 297177344Sadrian tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16); 298177344Sadrian tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 299177344Sadrian } 300177344Sadrian *v = tmp; 301145256Sjkoshy 302177344Sadrian PMCDBG(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v); 303145256Sjkoshy 304145256Sjkoshy return 0; 305145256Sjkoshy} 306145256Sjkoshy 307145256Sjkoshy/* 308145256Sjkoshy * Write a PMC MSR. 309145256Sjkoshy */ 310145256Sjkoshy 311145256Sjkoshystatic int 312145256Sjkoshyamd_write_pmc(int cpu, int ri, pmc_value_t v) 313145256Sjkoshy{ 314145256Sjkoshy const struct amd_descr *pd; 315184802Sjkoshy enum pmc_mode mode; 316145256Sjkoshy struct pmc *pm; 317145256Sjkoshy 318183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 319145256Sjkoshy ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 320145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 321145256Sjkoshy ("[amd,%d] illegal row-index %d", __LINE__, ri)); 322145256Sjkoshy 323184802Sjkoshy pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 324184802Sjkoshy pd = &amd_pmcdesc[ri]; 325145256Sjkoshy 326145256Sjkoshy KASSERT(pm != NULL, 327145256Sjkoshy ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__, 328145256Sjkoshy cpu, ri)); 329145256Sjkoshy 330145774Sjkoshy mode = PMC_TO_MODE(pm); 331145256Sjkoshy 332153110Sru#ifdef DEBUG 333147191Sjkoshy KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 334145256Sjkoshy ("[amd,%d] unknown PMC class (%d)", __LINE__, 335145256Sjkoshy pd->pm_descr.pd_class)); 336147191Sjkoshy#endif 337145256Sjkoshy 338145256Sjkoshy /* use 2's complement of the count for sampling mode PMCs */ 339145256Sjkoshy if (PMC_IS_SAMPLING_MODE(mode)) 340147191Sjkoshy v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 341145256Sjkoshy 342145256Sjkoshy PMCDBG(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); 343145256Sjkoshy 344145256Sjkoshy /* write the PMC value */ 345145256Sjkoshy wrmsr(pd->pm_perfctr, v); 346145256Sjkoshy return 0; 347145256Sjkoshy} 348145256Sjkoshy 349145256Sjkoshy/* 350145256Sjkoshy * configure hardware pmc according to the configuration recorded in 351145256Sjkoshy * pmc 'pm'. 352145256Sjkoshy */ 353145256Sjkoshy 354145256Sjkoshystatic int 355145256Sjkoshyamd_config_pmc(int cpu, int ri, struct pmc *pm) 356145256Sjkoshy{ 357145256Sjkoshy struct pmc_hw *phw; 358145256Sjkoshy 359145615Sjkoshy PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 360145615Sjkoshy 361183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 362145256Sjkoshy ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 363145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 364145256Sjkoshy ("[amd,%d] illegal row-index %d", __LINE__, ri)); 365145256Sjkoshy 366184802Sjkoshy phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 367145256Sjkoshy 368145256Sjkoshy KASSERT(pm == NULL || phw->phw_pmc == NULL, 369145615Sjkoshy ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 370145615Sjkoshy __LINE__, pm, phw->phw_pmc)); 371145256Sjkoshy 372145256Sjkoshy phw->phw_pmc = pm; 373145256Sjkoshy return 0; 374145256Sjkoshy} 375145256Sjkoshy 376145256Sjkoshy/* 377145774Sjkoshy * Retrieve a configured PMC pointer from hardware state. 378145774Sjkoshy */ 379145774Sjkoshy 380145774Sjkoshystatic int 381145774Sjkoshyamd_get_config(int cpu, int ri, struct pmc **ppm) 382145774Sjkoshy{ 383184802Sjkoshy *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 384145774Sjkoshy 385145774Sjkoshy return 0; 386145774Sjkoshy} 387145774Sjkoshy 388145774Sjkoshy/* 389145256Sjkoshy * Machine dependent actions taken during the context switch in of a 390145256Sjkoshy * thread. 391145256Sjkoshy */ 392145256Sjkoshy 393145256Sjkoshystatic int 394145615Sjkoshyamd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 395145256Sjkoshy{ 396145256Sjkoshy (void) pc; 397145256Sjkoshy 398145615Sjkoshy PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 399145774Sjkoshy (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); 400145615Sjkoshy 401145615Sjkoshy /* enable the RDPMC instruction if needed */ 402145774Sjkoshy if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 403145615Sjkoshy load_cr4(rcr4() | CR4_PCE); 404145615Sjkoshy 405145256Sjkoshy return 0; 406145256Sjkoshy} 407145256Sjkoshy 408145256Sjkoshy/* 409145256Sjkoshy * Machine dependent actions taken during the context switch out of a 410145256Sjkoshy * thread. 411145256Sjkoshy */ 412145256Sjkoshy 413145256Sjkoshystatic int 414145615Sjkoshyamd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 415145256Sjkoshy{ 416145256Sjkoshy (void) pc; 417145615Sjkoshy (void) pp; /* can be NULL */ 418145256Sjkoshy 419145615Sjkoshy PMCDBG(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? 420145774Sjkoshy (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); 421145615Sjkoshy 422145615Sjkoshy /* always turn off the RDPMC instruction */ 423145256Sjkoshy load_cr4(rcr4() & ~CR4_PCE); 424145615Sjkoshy 425145256Sjkoshy return 0; 426145256Sjkoshy} 427145256Sjkoshy 428145256Sjkoshy/* 429145256Sjkoshy * Check if a given allocation is feasible. 430145256Sjkoshy */ 431145256Sjkoshy 432145256Sjkoshystatic int 433145256Sjkoshyamd_allocate_pmc(int cpu, int ri, struct pmc *pm, 434145256Sjkoshy const struct pmc_op_pmcallocate *a) 435145256Sjkoshy{ 436145256Sjkoshy int i; 437145256Sjkoshy uint32_t allowed_unitmask, caps, config, unitmask; 438145256Sjkoshy enum pmc_event pe; 439145256Sjkoshy const struct pmc_descr *pd; 440145256Sjkoshy 441145256Sjkoshy (void) cpu; 442145256Sjkoshy 443183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 444145256Sjkoshy ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 445145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 446145256Sjkoshy ("[amd,%d] illegal row index %d", __LINE__, ri)); 447145256Sjkoshy 448145256Sjkoshy pd = &amd_pmcdesc[ri].pm_descr; 449145256Sjkoshy 450145256Sjkoshy /* check class match */ 451145774Sjkoshy if (pd->pd_class != a->pm_class) 452145256Sjkoshy return EINVAL; 453145256Sjkoshy 454145256Sjkoshy caps = pm->pm_caps; 455145256Sjkoshy 456145256Sjkoshy PMCDBG(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); 457145256Sjkoshy 458145256Sjkoshy if ((pd->pd_caps & caps) != caps) 459145256Sjkoshy return EPERM; 460145256Sjkoshy 461145256Sjkoshy pe = a->pm_ev; 462145256Sjkoshy 463145256Sjkoshy /* map ev to the correct event mask code */ 464145256Sjkoshy config = allowed_unitmask = 0; 465145256Sjkoshy for (i = 0; i < amd_event_codes_size; i++) 466145256Sjkoshy if (amd_event_codes[i].pe_ev == pe) { 467145256Sjkoshy config = 468145256Sjkoshy AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); 469145256Sjkoshy allowed_unitmask = 470145256Sjkoshy AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); 471145256Sjkoshy break; 472145256Sjkoshy } 473145256Sjkoshy if (i == amd_event_codes_size) 474145256Sjkoshy return EINVAL; 475145256Sjkoshy 476147191Sjkoshy unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; 477145256Sjkoshy if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ 478145256Sjkoshy return EINVAL; 479145256Sjkoshy 480145256Sjkoshy if (unitmask && (caps & PMC_CAP_QUALIFIER)) 481145256Sjkoshy config |= unitmask; 482145256Sjkoshy 483145256Sjkoshy if (caps & PMC_CAP_THRESHOLD) 484147191Sjkoshy config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; 485145256Sjkoshy 486145256Sjkoshy /* set at least one of the 'usr' or 'os' caps */ 487145256Sjkoshy if (caps & PMC_CAP_USER) 488145256Sjkoshy config |= AMD_PMC_USR; 489145256Sjkoshy if (caps & PMC_CAP_SYSTEM) 490145256Sjkoshy config |= AMD_PMC_OS; 491145256Sjkoshy if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) 492145256Sjkoshy config |= (AMD_PMC_USR|AMD_PMC_OS); 493145256Sjkoshy 494145256Sjkoshy if (caps & PMC_CAP_EDGE) 495145256Sjkoshy config |= AMD_PMC_EDGE; 496145256Sjkoshy if (caps & PMC_CAP_INVERT) 497145256Sjkoshy config |= AMD_PMC_INVERT; 498145256Sjkoshy if (caps & PMC_CAP_INTERRUPT) 499145256Sjkoshy config |= AMD_PMC_INT; 500145256Sjkoshy 501145256Sjkoshy pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ 502145256Sjkoshy 503145256Sjkoshy PMCDBG(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); 504145256Sjkoshy 505145256Sjkoshy return 0; 506145256Sjkoshy} 507145256Sjkoshy 508145256Sjkoshy/* 509145256Sjkoshy * Release machine dependent state associated with a PMC. This is a 510145256Sjkoshy * no-op on this architecture. 511145256Sjkoshy * 512145256Sjkoshy */ 513145256Sjkoshy 514145256Sjkoshy/* ARGSUSED0 */ 515145256Sjkoshystatic int 516145256Sjkoshyamd_release_pmc(int cpu, int ri, struct pmc *pmc) 517145256Sjkoshy{ 518153110Sru#ifdef DEBUG 519145256Sjkoshy const struct amd_descr *pd; 520145256Sjkoshy#endif 521145256Sjkoshy struct pmc_hw *phw; 522145256Sjkoshy 523145256Sjkoshy (void) pmc; 524145256Sjkoshy 525183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 526145256Sjkoshy ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 527145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 528145256Sjkoshy ("[amd,%d] illegal row-index %d", __LINE__, ri)); 529145256Sjkoshy 530184802Sjkoshy phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 531145256Sjkoshy 532145256Sjkoshy KASSERT(phw->phw_pmc == NULL, 533145256Sjkoshy ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 534145256Sjkoshy 535153110Sru#ifdef DEBUG 536145256Sjkoshy pd = &amd_pmcdesc[ri]; 537147191Sjkoshy if (pd->pm_descr.pd_class == amd_pmc_class) 538145256Sjkoshy KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 539145256Sjkoshy ("[amd,%d] PMC %d released while active", __LINE__, ri)); 540145256Sjkoshy#endif 541145256Sjkoshy 542145256Sjkoshy return 0; 543145256Sjkoshy} 544145256Sjkoshy 545145256Sjkoshy/* 546145256Sjkoshy * start a PMC. 547145256Sjkoshy */ 548145256Sjkoshy 549145256Sjkoshystatic int 550145256Sjkoshyamd_start_pmc(int cpu, int ri) 551145256Sjkoshy{ 552145256Sjkoshy uint32_t config; 553145256Sjkoshy struct pmc *pm; 554145256Sjkoshy struct pmc_hw *phw; 555145256Sjkoshy const struct amd_descr *pd; 556145256Sjkoshy 557183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 558145256Sjkoshy ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 559145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 560145256Sjkoshy ("[amd,%d] illegal row-index %d", __LINE__, ri)); 561145256Sjkoshy 562184802Sjkoshy phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 563145256Sjkoshy pm = phw->phw_pmc; 564145256Sjkoshy pd = &amd_pmcdesc[ri]; 565145256Sjkoshy 566145256Sjkoshy KASSERT(pm != NULL, 567145256Sjkoshy ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__, 568145256Sjkoshy cpu, ri)); 569145256Sjkoshy 570145256Sjkoshy PMCDBG(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); 571145256Sjkoshy 572145256Sjkoshy KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 573145256Sjkoshy ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, 574145256Sjkoshy ri, cpu, pd->pm_descr.pd_name)); 575145256Sjkoshy 576145256Sjkoshy /* turn on the PMC ENABLE bit */ 577145256Sjkoshy config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; 578145256Sjkoshy 579145256Sjkoshy PMCDBG(MDP,STA,2,"amd-start config=0x%x", config); 580145256Sjkoshy 581145256Sjkoshy wrmsr(pd->pm_evsel, config); 582145256Sjkoshy return 0; 583145256Sjkoshy} 584145256Sjkoshy 585145256Sjkoshy/* 586145256Sjkoshy * Stop a PMC. 587145256Sjkoshy */ 588145256Sjkoshy 589145256Sjkoshystatic int 590145256Sjkoshyamd_stop_pmc(int cpu, int ri) 591145256Sjkoshy{ 592145256Sjkoshy struct pmc *pm; 593145256Sjkoshy struct pmc_hw *phw; 594145256Sjkoshy const struct amd_descr *pd; 595145256Sjkoshy uint64_t config; 596145256Sjkoshy 597183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 598145256Sjkoshy ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 599145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 600145256Sjkoshy ("[amd,%d] illegal row-index %d", __LINE__, ri)); 601145256Sjkoshy 602184802Sjkoshy phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 603145256Sjkoshy pm = phw->phw_pmc; 604145256Sjkoshy pd = &amd_pmcdesc[ri]; 605145256Sjkoshy 606145256Sjkoshy KASSERT(pm != NULL, 607145256Sjkoshy ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__, 608145256Sjkoshy cpu, ri)); 609145256Sjkoshy KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), 610145256Sjkoshy ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", 611145256Sjkoshy __LINE__, ri, cpu, pd->pm_descr.pd_name)); 612145256Sjkoshy 613145256Sjkoshy PMCDBG(MDP,STO,1,"amd-stop ri=%d", ri); 614145256Sjkoshy 615145256Sjkoshy /* turn off the PMC ENABLE bit */ 616145256Sjkoshy config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; 617145256Sjkoshy wrmsr(pd->pm_evsel, config); 618145256Sjkoshy return 0; 619145256Sjkoshy} 620145256Sjkoshy 621145256Sjkoshy/* 622145256Sjkoshy * Interrupt handler. This function needs to return '1' if the 623145256Sjkoshy * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed 624145256Sjkoshy * to sleep or do anything a 'fast' interrupt handler is not allowed 625145256Sjkoshy * to do. 626145256Sjkoshy */ 627145256Sjkoshy 628145256Sjkoshystatic int 629174395Sjkoshyamd_intr(int cpu, struct trapframe *tf) 630145256Sjkoshy{ 631184802Sjkoshy int i, error, retval; 632147191Sjkoshy uint32_t config, evsel, perfctr; 633145256Sjkoshy struct pmc *pm; 634184802Sjkoshy struct amd_cpu *pac; 635147191Sjkoshy pmc_value_t v; 636145256Sjkoshy 637183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 638145256Sjkoshy ("[amd,%d] out of range CPU %d", __LINE__, cpu)); 639145256Sjkoshy 640177343Sadrian PMCDBG(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf, 641174395Sjkoshy TRAPF_USERMODE(tf)); 642147191Sjkoshy 643145256Sjkoshy retval = 0; 644145256Sjkoshy 645184802Sjkoshy pac = amd_pcpu[cpu]; 646145256Sjkoshy 647145256Sjkoshy /* 648145256Sjkoshy * look for all PMCs that have interrupted: 649147191Sjkoshy * - look for a running, sampling PMC which has overflowed 650147191Sjkoshy * and which has a valid 'struct pmc' association 651147191Sjkoshy * 652147191Sjkoshy * If found, we call a helper to process the interrupt. 653150050Sjkoshy * 654150050Sjkoshy * If multiple PMCs interrupt at the same time, the AMD64 655150050Sjkoshy * processor appears to deliver as many NMIs as there are 656174395Sjkoshy * outstanding PMC interrupts. So we process only one NMI 657174395Sjkoshy * interrupt at a time. 658145256Sjkoshy */ 659145256Sjkoshy 660184802Sjkoshy for (i = 0; retval == 0 && i < AMD_NPMCS; i++) { 661145256Sjkoshy 662185555Sjkoshy if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL || 663185555Sjkoshy !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 664185555Sjkoshy continue; 665185555Sjkoshy } 666185555Sjkoshy 667147191Sjkoshy if (!AMD_PMC_HAS_OVERFLOWED(i)) 668147191Sjkoshy continue; 669147191Sjkoshy 670185555Sjkoshy retval = 1; /* Found an interrupting PMC. */ 671147191Sjkoshy 672185555Sjkoshy if (pm->pm_state != PMC_STATE_RUNNING) 673145256Sjkoshy continue; 674145256Sjkoshy 675174395Sjkoshy /* Stop the PMC, reload count. */ 676147191Sjkoshy evsel = AMD_PMC_EVSEL_0 + i; 677147191Sjkoshy perfctr = AMD_PMC_PERFCTR_0 + i; 678147191Sjkoshy v = pm->pm_sc.pm_reloadcount; 679147191Sjkoshy config = rdmsr(evsel); 680147191Sjkoshy 681147191Sjkoshy KASSERT((config & ~AMD_PMC_ENABLE) == 682147191Sjkoshy (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), 683147191Sjkoshy ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__, 684147191Sjkoshy config, pm->pm_md.pm_amd.pm_amd_evsel)); 685147191Sjkoshy 686147191Sjkoshy wrmsr(evsel, config & ~AMD_PMC_ENABLE); 687147191Sjkoshy wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); 688147191Sjkoshy 689174395Sjkoshy /* Restart the counter if logging succeeded. */ 690236238Sfabient error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 691236238Sfabient TRAPF_USERMODE(tf)); 692147191Sjkoshy if (error == 0) 693147191Sjkoshy wrmsr(evsel, config | AMD_PMC_ENABLE); 694145256Sjkoshy } 695147191Sjkoshy 696147867Sjkoshy atomic_add_int(retval ? &pmc_stats.pm_intr_processed : 697147867Sjkoshy &pmc_stats.pm_intr_ignored, 1); 698147867Sjkoshy 699174395Sjkoshy return (retval); 700145256Sjkoshy} 701145256Sjkoshy 702145256Sjkoshy/* 703145256Sjkoshy * describe a PMC 704145256Sjkoshy */ 705145256Sjkoshystatic int 706145256Sjkoshyamd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 707145256Sjkoshy{ 708145256Sjkoshy int error; 709145256Sjkoshy size_t copied; 710145256Sjkoshy const struct amd_descr *pd; 711145256Sjkoshy struct pmc_hw *phw; 712145256Sjkoshy 713183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 714145256Sjkoshy ("[amd,%d] illegal CPU %d", __LINE__, cpu)); 715145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 716145256Sjkoshy ("[amd,%d] row-index %d out of range", __LINE__, ri)); 717145256Sjkoshy 718184802Sjkoshy phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 719145256Sjkoshy pd = &amd_pmcdesc[ri]; 720145256Sjkoshy 721145256Sjkoshy if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, 722145256Sjkoshy PMC_NAME_MAX, &copied)) != 0) 723145256Sjkoshy return error; 724145256Sjkoshy 725145256Sjkoshy pi->pm_class = pd->pm_descr.pd_class; 726145256Sjkoshy 727145256Sjkoshy if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 728145256Sjkoshy pi->pm_enabled = TRUE; 729145256Sjkoshy *ppmc = phw->phw_pmc; 730145256Sjkoshy } else { 731145256Sjkoshy pi->pm_enabled = FALSE; 732145256Sjkoshy *ppmc = NULL; 733145256Sjkoshy } 734145256Sjkoshy 735145256Sjkoshy return 0; 736145256Sjkoshy} 737145256Sjkoshy 738145256Sjkoshy/* 739145256Sjkoshy * i386 specific entry points 740145256Sjkoshy */ 741145256Sjkoshy 742145256Sjkoshy/* 743145256Sjkoshy * return the MSR address of the given PMC. 744145256Sjkoshy */ 745145256Sjkoshy 746145256Sjkoshystatic int 747145256Sjkoshyamd_get_msr(int ri, uint32_t *msr) 748145256Sjkoshy{ 749145256Sjkoshy KASSERT(ri >= 0 && ri < AMD_NPMCS, 750145256Sjkoshy ("[amd,%d] ri %d out of range", __LINE__, ri)); 751145256Sjkoshy 752145615Sjkoshy *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; 753184802Sjkoshy 754184802Sjkoshy return (0); 755145256Sjkoshy} 756145256Sjkoshy 757145256Sjkoshy/* 758145256Sjkoshy * processor dependent initialization. 759145256Sjkoshy */ 760145256Sjkoshy 761145256Sjkoshystatic int 762184802Sjkoshyamd_pcpu_init(struct pmc_mdep *md, int cpu) 763145256Sjkoshy{ 764184802Sjkoshy int classindex, first_ri, n; 765184802Sjkoshy struct pmc_cpu *pc; 766184802Sjkoshy struct amd_cpu *pac; 767145256Sjkoshy struct pmc_hw *phw; 768145256Sjkoshy 769183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 770145256Sjkoshy ("[amd,%d] insane cpu number %d", __LINE__, cpu)); 771145256Sjkoshy 772145256Sjkoshy PMCDBG(MDP,INI,1,"amd-init cpu=%d", cpu); 773145256Sjkoshy 774184802Sjkoshy amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC, 775145256Sjkoshy M_WAITOK|M_ZERO); 776145256Sjkoshy 777145256Sjkoshy /* 778184802Sjkoshy * Set the content of the hardware descriptors to a known 779184802Sjkoshy * state and initialize pointers in the MI per-cpu descriptor. 780145256Sjkoshy */ 781184802Sjkoshy pc = pmc_pcpu[cpu]; 782184802Sjkoshy#if defined(__amd64__) 783184802Sjkoshy classindex = PMC_MDEP_CLASS_INDEX_K8; 784184802Sjkoshy#elif defined(__i386__) 785184802Sjkoshy classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? 786184802Sjkoshy PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; 787184802Sjkoshy#endif 788184802Sjkoshy first_ri = md->pmd_classdep[classindex].pcd_ri; 789145256Sjkoshy 790184802Sjkoshy KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__)); 791184802Sjkoshy 792184802Sjkoshy for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) { 793145256Sjkoshy phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 794145256Sjkoshy PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); 795145256Sjkoshy phw->phw_pmc = NULL; 796184802Sjkoshy pc->pc_hwpmcs[n + first_ri] = phw; 797145256Sjkoshy } 798145256Sjkoshy 799184802Sjkoshy return (0); 800145256Sjkoshy} 801145256Sjkoshy 802145256Sjkoshy 803145256Sjkoshy/* 804145256Sjkoshy * processor dependent cleanup prior to the KLD 805145256Sjkoshy * being unloaded 806145256Sjkoshy */ 807145256Sjkoshy 808145256Sjkoshystatic int 809184802Sjkoshyamd_pcpu_fini(struct pmc_mdep *md, int cpu) 810145256Sjkoshy{ 811184802Sjkoshy int classindex, first_ri, i; 812145256Sjkoshy uint32_t evsel; 813184802Sjkoshy struct pmc_cpu *pc; 814184802Sjkoshy struct amd_cpu *pac; 815145256Sjkoshy 816183266Sjkoshy KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 817145256Sjkoshy ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); 818145256Sjkoshy 819145256Sjkoshy PMCDBG(MDP,INI,1,"amd-cleanup cpu=%d", cpu); 820145256Sjkoshy 821145256Sjkoshy /* 822145256Sjkoshy * First, turn off all PMCs on this CPU. 823145256Sjkoshy */ 824145256Sjkoshy for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ 825145256Sjkoshy evsel = rdmsr(AMD_PMC_EVSEL_0 + i); 826145256Sjkoshy evsel &= ~AMD_PMC_ENABLE; 827145256Sjkoshy wrmsr(AMD_PMC_EVSEL_0 + i, evsel); 828145256Sjkoshy } 829145256Sjkoshy 830145256Sjkoshy /* 831145256Sjkoshy * Next, free up allocated space. 832145256Sjkoshy */ 833184802Sjkoshy if ((pac = amd_pcpu[cpu]) == NULL) 834184802Sjkoshy return (0); 835145256Sjkoshy 836184802Sjkoshy amd_pcpu[cpu] = NULL; 837145256Sjkoshy 838153110Sru#ifdef DEBUG 839184802Sjkoshy for (i = 0; i < AMD_NPMCS; i++) { 840184802Sjkoshy KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL, 841145256Sjkoshy ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); 842241272Savg KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i), 843145256Sjkoshy ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); 844145256Sjkoshy } 845145256Sjkoshy#endif 846145256Sjkoshy 847184802Sjkoshy pc = pmc_pcpu[cpu]; 848184802Sjkoshy KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__)); 849184802Sjkoshy 850184802Sjkoshy#if defined(__amd64__) 851184802Sjkoshy classindex = PMC_MDEP_CLASS_INDEX_K8; 852184802Sjkoshy#elif defined(__i386__) 853184802Sjkoshy classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : 854184802Sjkoshy PMC_MDEP_CLASS_INDEX_K7; 855184802Sjkoshy#endif 856184802Sjkoshy first_ri = md->pmd_classdep[classindex].pcd_ri; 857184802Sjkoshy 858184802Sjkoshy /* 859184802Sjkoshy * Reset pointers in the MI 'per-cpu' state. 860184802Sjkoshy */ 861184802Sjkoshy for (i = 0; i < AMD_NPMCS; i++) { 862184802Sjkoshy pc->pc_hwpmcs[i + first_ri] = NULL; 863184802Sjkoshy } 864184802Sjkoshy 865184802Sjkoshy 866184802Sjkoshy free(pac, M_PMC); 867184802Sjkoshy 868184802Sjkoshy return (0); 869145256Sjkoshy} 870145256Sjkoshy 871145256Sjkoshy/* 872145256Sjkoshy * Initialize ourselves. 873145256Sjkoshy */ 874145256Sjkoshy 875145256Sjkoshystruct pmc_mdep * 876145256Sjkoshypmc_amd_initialize(void) 877145256Sjkoshy{ 878236238Sfabient int classindex, error, i, ncpus; 879184802Sjkoshy struct pmc_classdep *pcd; 880147191Sjkoshy enum pmc_cputype cputype; 881184802Sjkoshy struct pmc_mdep *pmc_mdep; 882147191Sjkoshy enum pmc_class class; 883147191Sjkoshy char *name; 884145256Sjkoshy 885147191Sjkoshy /* 886147191Sjkoshy * The presence of hardware performance counters on the AMD 887147191Sjkoshy * Athlon, Duron or later processors, is _not_ indicated by 888147191Sjkoshy * any of the processor feature flags set by the 'CPUID' 889147191Sjkoshy * instruction, so we only check the 'instruction family' 890147191Sjkoshy * field returned by CPUID for instruction family >= 6. 891147191Sjkoshy */ 892145256Sjkoshy 893147510Sjkoshy name = NULL; 894147191Sjkoshy switch (cpu_id & 0xF00) { 895184802Sjkoshy#if defined(__i386__) 896147191Sjkoshy case 0x600: /* Athlon(tm) processor */ 897184802Sjkoshy classindex = PMC_MDEP_CLASS_INDEX_K7; 898147191Sjkoshy cputype = PMC_CPU_AMD_K7; 899147191Sjkoshy class = PMC_CLASS_K7; 900147191Sjkoshy name = "K7"; 901147191Sjkoshy break; 902184802Sjkoshy#endif 903147191Sjkoshy case 0xF00: /* Athlon64/Opteron processor */ 904184802Sjkoshy classindex = PMC_MDEP_CLASS_INDEX_K8; 905147191Sjkoshy cputype = PMC_CPU_AMD_K8; 906147191Sjkoshy class = PMC_CLASS_K8; 907147191Sjkoshy name = "K8"; 908147191Sjkoshy break; 909147191Sjkoshy 910229776Sdim default: 911147191Sjkoshy (void) printf("pmc: Unknown AMD CPU.\n"); 912145256Sjkoshy return NULL; 913147191Sjkoshy } 914145256Sjkoshy 915153110Sru#ifdef DEBUG 916147191Sjkoshy amd_pmc_class = class; 917147191Sjkoshy#endif 918147191Sjkoshy 919184802Sjkoshy /* 920184802Sjkoshy * Allocate space for pointers to PMC HW descriptors and for 921184802Sjkoshy * the MDEP structure used by MI code. 922184802Sjkoshy */ 923184802Sjkoshy amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC, 924184802Sjkoshy M_WAITOK|M_ZERO); 925184802Sjkoshy 926184802Sjkoshy /* 927184802Sjkoshy * These processors have two classes of PMCs: the TSC and 928184802Sjkoshy * programmable PMCs. 929184802Sjkoshy */ 930236238Sfabient pmc_mdep = pmc_mdep_alloc(2); 931145256Sjkoshy 932184802Sjkoshy pmc_mdep->pmd_cputype = cputype; 933145256Sjkoshy 934184802Sjkoshy ncpus = pmc_cpu_max(); 935145774Sjkoshy 936184802Sjkoshy /* Initialize the TSC. */ 937184802Sjkoshy error = pmc_tsc_initialize(pmc_mdep, ncpus); 938184802Sjkoshy if (error) 939184802Sjkoshy goto error; 940145774Sjkoshy 941184802Sjkoshy /* Initialize AMD K7 and K8 PMC handling. */ 942184802Sjkoshy pcd = &pmc_mdep->pmd_classdep[classindex]; 943145774Sjkoshy 944184802Sjkoshy pcd->pcd_caps = AMD_PMC_CAPS; 945184802Sjkoshy pcd->pcd_class = class; 946184802Sjkoshy pcd->pcd_num = AMD_NPMCS; 947184802Sjkoshy pcd->pcd_ri = pmc_mdep->pmd_npmc; 948184802Sjkoshy pcd->pcd_width = 48; 949145256Sjkoshy 950147191Sjkoshy /* fill in the correct pmc name and class */ 951184802Sjkoshy for (i = 0; i < AMD_NPMCS; i++) { 952147191Sjkoshy (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, 953147191Sjkoshy sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", 954184992Sjkoshy name, i); 955147191Sjkoshy amd_pmcdesc[i].pm_descr.pd_class = class; 956147191Sjkoshy } 957147191Sjkoshy 958184802Sjkoshy pcd->pcd_allocate_pmc = amd_allocate_pmc; 959184802Sjkoshy pcd->pcd_config_pmc = amd_config_pmc; 960184802Sjkoshy pcd->pcd_describe = amd_describe; 961184802Sjkoshy pcd->pcd_get_config = amd_get_config; 962184802Sjkoshy pcd->pcd_get_msr = amd_get_msr; 963184802Sjkoshy pcd->pcd_pcpu_fini = amd_pcpu_fini; 964184802Sjkoshy pcd->pcd_pcpu_init = amd_pcpu_init; 965184802Sjkoshy pcd->pcd_read_pmc = amd_read_pmc; 966184802Sjkoshy pcd->pcd_release_pmc = amd_release_pmc; 967184802Sjkoshy pcd->pcd_start_pmc = amd_start_pmc; 968184802Sjkoshy pcd->pcd_stop_pmc = amd_stop_pmc; 969184802Sjkoshy pcd->pcd_write_pmc = amd_write_pmc; 970145256Sjkoshy 971184802Sjkoshy pmc_mdep->pmd_pcpu_init = NULL; 972184802Sjkoshy pmc_mdep->pmd_pcpu_fini = NULL; 973184802Sjkoshy pmc_mdep->pmd_intr = amd_intr; 974184802Sjkoshy pmc_mdep->pmd_switch_in = amd_switch_in; 975184802Sjkoshy pmc_mdep->pmd_switch_out = amd_switch_out; 976184802Sjkoshy 977184802Sjkoshy pmc_mdep->pmd_npmc += AMD_NPMCS; 978184802Sjkoshy 979145256Sjkoshy PMCDBG(MDP,INI,0,"%s","amd-initialize"); 980145256Sjkoshy 981184802Sjkoshy return (pmc_mdep); 982184802Sjkoshy 983184802Sjkoshy error: 984184802Sjkoshy if (error) { 985184802Sjkoshy free(pmc_mdep, M_PMC); 986184802Sjkoshy pmc_mdep = NULL; 987184802Sjkoshy } 988184802Sjkoshy 989184802Sjkoshy return (NULL); 990145256Sjkoshy} 991184802Sjkoshy 992184802Sjkoshy/* 993184802Sjkoshy * Finalization code for AMD CPUs. 994184802Sjkoshy */ 995184802Sjkoshy 996184802Sjkoshyvoid 997184802Sjkoshypmc_amd_finalize(struct pmc_mdep *md) 998184802Sjkoshy{ 999184802Sjkoshy#if defined(INVARIANTS) 1000184802Sjkoshy int classindex, i, ncpus, pmcclass; 1001184802Sjkoshy#endif 1002184802Sjkoshy 1003184802Sjkoshy pmc_tsc_finalize(md); 1004184802Sjkoshy 1005184802Sjkoshy KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer", 1006184802Sjkoshy __LINE__)); 1007184802Sjkoshy 1008184802Sjkoshy#if defined(INVARIANTS) 1009184802Sjkoshy switch (md->pmd_cputype) { 1010184802Sjkoshy#if defined(__i386__) 1011184802Sjkoshy case PMC_CPU_AMD_K7: 1012184802Sjkoshy classindex = PMC_MDEP_CLASS_INDEX_K7; 1013184802Sjkoshy pmcclass = PMC_CLASS_K7; 1014184802Sjkoshy break; 1015184802Sjkoshy#endif 1016184802Sjkoshy default: 1017184802Sjkoshy classindex = PMC_MDEP_CLASS_INDEX_K8; 1018184802Sjkoshy pmcclass = PMC_CLASS_K8; 1019184802Sjkoshy } 1020184802Sjkoshy 1021184802Sjkoshy KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass, 1022184802Sjkoshy ("[amd,%d] pmc class mismatch", __LINE__)); 1023184802Sjkoshy 1024184802Sjkoshy ncpus = pmc_cpu_max(); 1025184802Sjkoshy 1026184802Sjkoshy for (i = 0; i < ncpus; i++) 1027184802Sjkoshy KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu", 1028184802Sjkoshy __LINE__)); 1029184802Sjkoshy#endif 1030184802Sjkoshy 1031184802Sjkoshy free(amd_pcpu, M_PMC); 1032184802Sjkoshy amd_pcpu = NULL; 1033184802Sjkoshy} 1034