1228940Sdelphij/*-
2228940Sdelphij * Copyright (c) 2011 HighPoint Technologies, Inc.
3228940Sdelphij * All rights reserved.
4228940Sdelphij *
5228940Sdelphij * Redistribution and use in source and binary forms, with or without
6228940Sdelphij * modification, are permitted provided that the following conditions
7228940Sdelphij * are met:
8228940Sdelphij * 1. Redistributions of source code must retain the above copyright
9228940Sdelphij *    notice, this list of conditions and the following disclaimer.
10228940Sdelphij * 2. Redistributions in binary form must reproduce the above copyright
11228940Sdelphij *    notice, this list of conditions and the following disclaimer in the
12228940Sdelphij *    documentation and/or other materials provided with the distribution.
13228940Sdelphij *
14228940Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15228940Sdelphij * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16228940Sdelphij * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17228940Sdelphij * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18228940Sdelphij * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19228940Sdelphij * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20228940Sdelphij * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21228940Sdelphij * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22228940Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23228940Sdelphij * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24228940Sdelphij * SUCH DAMAGE.
25228940Sdelphij *
26228940Sdelphij * $FreeBSD$
27228940Sdelphij */
28228940Sdelphij
29228940Sdelphij#include <dev/hpt27xx/hpt27xx_config.h>
30228940Sdelphij
31228940Sdelphij#ifndef HPT_INTF_H
32228940Sdelphij#define HPT_INTF_H
33228940Sdelphij
34228940Sdelphij#if defined(__BIG_ENDIAN__)&&!defined(__BIG_ENDIAN_BITFIELD)
35228940Sdelphij#define __BIG_ENDIAN_BITFIELD
36228940Sdelphij#endif
37228940Sdelphij
38228940Sdelphij#ifdef __cplusplus
39228940Sdelphijextern "C" {
40228940Sdelphij#endif
41228940Sdelphij
42228940Sdelphij#ifndef __GNUC__
43228940Sdelphij#define __attribute__(x)
44228940Sdelphij#endif
45228940Sdelphij
46228940Sdelphij#pragma pack(1)
47228940Sdelphij
48228940Sdelphij/*
49228940Sdelphij * Version of this interface.
50228940Sdelphij * The user mode application must first issue a hpt_get_version() call to
51228940Sdelphij * check HPT_INTERFACE_VERSION. When an utility using newer version interface
52228940Sdelphij * is used with old version drivers, it must call only the functions that
53228940Sdelphij * driver supported.
54228940Sdelphij * A new version interface should only add ioctl functions; it should implement
55228940Sdelphij * all old version functions without change their definition.
56228940Sdelphij */
57228940Sdelphij#define __this_HPT_INTERFACE_VERSION 0x02010000
58228940Sdelphij
59228940Sdelphij#ifndef HPT_INTERFACE_VERSION
60228940Sdelphij#error "You must define HPT_INTERFACE_VERSION you implemented"
61228940Sdelphij#endif
62228940Sdelphij
63228940Sdelphij#if HPT_INTERFACE_VERSION > __this_HPT_INTERFACE_VERSION
64228940Sdelphij#error "HPT_INTERFACE_VERSION is invalid"
65228940Sdelphij#endif
66228940Sdelphij
67228940Sdelphij/*
68228940Sdelphij * DEFINITION
69228940Sdelphij *   Logical device  --- a device that can be accessed by OS.
70228940Sdelphij *   Physical device --- device attached to the controller.
71228940Sdelphij *  A logical device can be simply a physical device.
72228940Sdelphij *
73228940Sdelphij * Each logical and physical device has a 32bit ID. GUI will use this ID
74228940Sdelphij * to identify devices.
75228940Sdelphij *   1. The ID must be unique.
76228940Sdelphij *   2. The ID must be immutable. Once an ID is assigned to a device, it
77228940Sdelphij * must not change when system is running and the device exists.
78228940Sdelphij *   3. The ID of logical device must be NOT reusable. If a device is
79228940Sdelphij * removed, other newly created logical device must not use the same ID.
80228940Sdelphij *   4. The ID must not be zero or 0xFFFFFFFF.
81228940Sdelphij */
82228940Sdelphijtypedef HPT_U32 DEVICEID;
83228940Sdelphij
84228940Sdelphij/*
85228940Sdelphij * logical device type.
86228940Sdelphij * Identify array (logical device) and physical device.
87228940Sdelphij */
88228940Sdelphij#define LDT_ARRAY   1
89228940Sdelphij#define LDT_DEVICE  2
90228940Sdelphij
91228940Sdelphij/*
92228940Sdelphij * Array types
93228940Sdelphij * GUI will treat all array as 1-level RAID. No RAID0/1 or RAID1/0.
94228940Sdelphij * A RAID0/1 device is type AT_RAID1. A RAID1/0 device is type AT_RAID0.
95228940Sdelphij * Their members may be another array of type RAID0 or RAID1.
96228940Sdelphij */
97228940Sdelphij#define AT_UNKNOWN  0
98228940Sdelphij#define AT_RAID0    1
99228940Sdelphij#define AT_RAID1    2
100228940Sdelphij#define AT_RAID5    3
101228940Sdelphij#define AT_RAID6    4
102228940Sdelphij#define AT_RAID3    5
103228940Sdelphij#define AT_RAID4    6
104228940Sdelphij#define AT_JBOD     7
105228940Sdelphij#define AT_RAID1E   8
106228940Sdelphij
107228940Sdelphij/*
108228940Sdelphij * physical device type
109228940Sdelphij */
110228940Sdelphij#define PDT_UNKNOWN     0
111228940Sdelphij#define PDT_HARDDISK    1
112228940Sdelphij#define PDT_CDROM       2
113228940Sdelphij#define PDT_TAPE        3
114228940Sdelphij
115228940Sdelphij/*
116228940Sdelphij * Some constants.
117228940Sdelphij */
118228940Sdelphij#define MAX_NAME_LENGTH     36
119228940Sdelphij#define MAX_ARRAYNAME_LEN   16
120228940Sdelphij
121228940Sdelphij#define MAX_ARRAY_MEMBERS_V1 8
122228940Sdelphij
123228940Sdelphij#ifndef MAX_ARRAY_MEMBERS_V2
124228940Sdelphij#define MAX_ARRAY_MEMBERS_V2 16
125228940Sdelphij#endif
126228940Sdelphij
127228940Sdelphij#ifndef MAX_ARRAY_MEMBERS_V3
128228940Sdelphij#define MAX_ARRAY_MEMBERS_V3 64
129228940Sdelphij#endif
130228940Sdelphij
131228940Sdelphij/* keep definition for source code compatiblity */
132228940Sdelphij#define MAX_ARRAY_MEMBERS MAX_ARRAY_MEMBERS_V1
133228940Sdelphij
134228940Sdelphij/*
135228940Sdelphij * io commands
136228940Sdelphij * GUI use these commands to do IO on logical/physical devices.
137228940Sdelphij */
138228940Sdelphij#define IO_COMMAND_READ     1
139228940Sdelphij#define IO_COMMAND_WRITE    2
140228940Sdelphij
141228940Sdelphij
142228940Sdelphij
143228940Sdelphij/*
144228940Sdelphij * array flags
145228940Sdelphij */
146228940Sdelphij#define ARRAY_FLAG_DISABLED         0x00000001 /* The array is disabled */
147228940Sdelphij#define ARRAY_FLAG_NEEDBUILDING     0x00000002 /* array data need to be rebuilt */
148228940Sdelphij#define ARRAY_FLAG_REBUILDING       0x00000004 /* array is in rebuilding process */
149228940Sdelphij#define ARRAY_FLAG_BROKEN           0x00000008 /* broken but may still working */
150228940Sdelphij#define ARRAY_FLAG_BOOTDISK         0x00000010 /* array has a active partition */
151228940Sdelphij
152228940Sdelphij#define ARRAY_FLAG_BOOTMARK         0x00000040 /* array has boot mark set */
153228940Sdelphij#define ARRAY_FLAG_NEED_AUTOREBUILD 0x00000080 /* auto-rebuild should start */
154228940Sdelphij#define ARRAY_FLAG_VERIFYING        0x00000100 /* is being verified */
155228940Sdelphij#define ARRAY_FLAG_INITIALIZING     0x00000200 /* is being initialized */
156228940Sdelphij#define ARRAY_FLAG_TRANSFORMING     0x00000400 /* tranform in progress */
157228940Sdelphij#define ARRAY_FLAG_NEEDTRANSFORM    0x00000800 /* array need tranform */
158228940Sdelphij#define ARRAY_FLAG_NEEDINITIALIZING 0x00001000 /* the array's initialization hasn't finished*/
159228940Sdelphij#define ARRAY_FLAG_BROKEN_REDUNDANT 0x00002000 /* broken but redundant (raid6) */
160228940Sdelphij#define ARRAY_FLAG_RAID15PLUS       0x80000000 /* display this RAID 1 as RAID 1.5 */
161228940Sdelphij/*
162228940Sdelphij * device flags
163228940Sdelphij */
164228940Sdelphij#define DEVICE_FLAG_DISABLED        0x00000001 /* device is disabled */
165228940Sdelphij#define DEVICE_FLAG_BOOTDISK        0x00000002 /* disk has a active partition */
166228940Sdelphij#define DEVICE_FLAG_BOOTMARK        0x00000004 /* disk has boot mark set */
167228940Sdelphij#define DEVICE_FLAG_WITH_601        0x00000008 /* has HPT601 connected */
168228940Sdelphij#define DEVICE_FLAG_SATA            0x00000010 /* SATA or SAS device */
169228940Sdelphij#define DEVICE_FLAG_ON_PM_PORT      0x00000020 /* PM port */
170228940Sdelphij#define DEVICE_FLAG_SAS             0x00000040 /* SAS device */
171228940Sdelphij#define DEVICE_FLAG_IN_ENCLOSURE    0x00000080 /* PathId is enclosure# */
172228940Sdelphij#define DEVICE_FLAG_UNINITIALIZED   0x00010000 /* device is not initialized, can't be used to create array */
173228940Sdelphij#define DEVICE_FLAG_LEGACY          0x00020000 /* single disk & mbr contains at least one partition */
174228940Sdelphij
175228940Sdelphij#define DEVICE_FLAG_IS_SPARE        0x80000000 /* is a spare disk */
176228940Sdelphij
177228940Sdelphij/*
178228940Sdelphij * array states used by hpt_set_array_state()
179228940Sdelphij */
180228940Sdelphij/* old defines */
181228940Sdelphij#define MIRROR_REBUILD_START    1
182228940Sdelphij#define MIRROR_REBUILD_ABORT    2
183228940Sdelphij#define MIRROR_REBUILD_COMPLETE 3
184228940Sdelphij/* new defines */
185228940Sdelphij#define AS_REBUILD_START 1
186228940Sdelphij#define AS_REBUILD_ABORT 2
187228940Sdelphij#define AS_REBUILD_PAUSE AS_REBUILD_ABORT
188228940Sdelphij#define AS_REBUILD_COMPLETE 3
189228940Sdelphij#define AS_VERIFY_START 4
190228940Sdelphij#define AS_VERIFY_ABORT 5
191228940Sdelphij#define AS_VERIFY_COMPLETE 6
192228940Sdelphij#define AS_INITIALIZE_START 7
193228940Sdelphij#define AS_INITIALIZE_ABORT 8
194228940Sdelphij#define AS_INITIALIZE_COMPLETE 9
195228940Sdelphij#define AS_VERIFY_FAILED 10
196228940Sdelphij#define AS_REBUILD_STOP 11
197228940Sdelphij#define AS_SAVE_STATE   12
198228940Sdelphij#define AS_TRANSFORM_START 13
199228940Sdelphij#define AS_TRANSFORM_ABORT 14
200228940Sdelphij
201228940Sdelphij/************************************************************************
202228940Sdelphij * ioctl code
203228940Sdelphij * It would be better if ioctl code are the same on different platforms,
204228940Sdelphij * but we must not conflict with system defined ioctl code.
205228940Sdelphij ************************************************************************/
206228940Sdelphij#if defined(LINUX) || defined(__FreeBSD_version) || defined(linux)
207228940Sdelphij#define HPT_CTL_CODE(x) (x+0xFF00)
208228940Sdelphij#define HPT_CTL_CODE_LINUX_TO_IOP(x) ((x)-0xff00)
209228940Sdelphij#elif defined(_MS_WIN32_) || defined(WIN32)
210228940Sdelphij
211228940Sdelphij#ifndef CTL_CODE
212228940Sdelphij#define CTL_CODE( DeviceType, Function, Method, Access ) \
213228940Sdelphij			(((DeviceType) << 16) | ((Access) << 14) | ((Function) << 2) | (Method))
214228940Sdelphij#endif
215228940Sdelphij#define HPT_CTL_CODE(x) CTL_CODE(0x370, 0x900+(x), 0, 0)
216228940Sdelphij#define HPT_CTL_CODE_WIN32_TO_IOP(x) ((((x) & 0xffff)>>2)-0x900)
217228940Sdelphij
218228940Sdelphij#else
219228940Sdelphij#define HPT_CTL_CODE(x) (x)
220228940Sdelphij#endif
221228940Sdelphij
222228940Sdelphij#define HPT_IOCTL_GET_VERSION               HPT_CTL_CODE(0)
223228940Sdelphij#define HPT_IOCTL_GET_CONTROLLER_COUNT      HPT_CTL_CODE(1)
224228940Sdelphij#define HPT_IOCTL_GET_CONTROLLER_INFO       HPT_CTL_CODE(2)
225228940Sdelphij#define HPT_IOCTL_GET_CHANNEL_INFO          HPT_CTL_CODE(3)
226228940Sdelphij#define HPT_IOCTL_GET_LOGICAL_DEVICES       HPT_CTL_CODE(4)
227228940Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO           HPT_CTL_CODE(5)
228228940Sdelphij#define HPT_IOCTL_CREATE_ARRAY              HPT_CTL_CODE(6)
229228940Sdelphij#define HPT_IOCTL_DELETE_ARRAY              HPT_CTL_CODE(7)
230228940Sdelphij#define HPT_IOCTL_ARRAY_IO                  HPT_CTL_CODE(8)
231228940Sdelphij#define HPT_IOCTL_DEVICE_IO                 HPT_CTL_CODE(9)
232228940Sdelphij#define HPT_IOCTL_GET_EVENT                 HPT_CTL_CODE(10)
233228940Sdelphij#define HPT_IOCTL_REBUILD_MIRROR            HPT_CTL_CODE(11)
234228940Sdelphij/* use HPT_IOCTL_REBUILD_DATA_BLOCK from now on */
235228940Sdelphij#define HPT_IOCTL_REBUILD_DATA_BLOCK HPT_IOCTL_REBUILD_MIRROR
236228940Sdelphij#define HPT_IOCTL_ADD_SPARE_DISK            HPT_CTL_CODE(12)
237228940Sdelphij#define HPT_IOCTL_REMOVE_SPARE_DISK         HPT_CTL_CODE(13)
238228940Sdelphij#define HPT_IOCTL_ADD_DISK_TO_ARRAY         HPT_CTL_CODE(14)
239228940Sdelphij#define HPT_IOCTL_SET_ARRAY_STATE           HPT_CTL_CODE(15)
240228940Sdelphij#define HPT_IOCTL_SET_ARRAY_INFO            HPT_CTL_CODE(16)
241228940Sdelphij#define HPT_IOCTL_SET_DEVICE_INFO           HPT_CTL_CODE(17)
242228940Sdelphij#define HPT_IOCTL_RESCAN_DEVICES            HPT_CTL_CODE(18)
243228940Sdelphij#define HPT_IOCTL_GET_DRIVER_CAPABILITIES   HPT_CTL_CODE(19)
244228940Sdelphij#define HPT_IOCTL_GET_601_INFO              HPT_CTL_CODE(20)
245228940Sdelphij#define HPT_IOCTL_SET_601_INFO              HPT_CTL_CODE(21)
246228940Sdelphij#define HPT_IOCTL_LOCK_DEVICE               HPT_CTL_CODE(22)
247228940Sdelphij#define HPT_IOCTL_UNLOCK_DEVICE             HPT_CTL_CODE(23)
248228940Sdelphij#define HPT_IOCTL_IDE_PASS_THROUGH          HPT_CTL_CODE(24)
249228940Sdelphij#define HPT_IOCTL_VERIFY_DATA_BLOCK         HPT_CTL_CODE(25)
250228940Sdelphij#define HPT_IOCTL_INITIALIZE_DATA_BLOCK     HPT_CTL_CODE(26)
251228940Sdelphij#define HPT_IOCTL_ADD_DEDICATED_SPARE       HPT_CTL_CODE(27)
252228940Sdelphij#define HPT_IOCTL_DEVICE_IO_EX              HPT_CTL_CODE(28)
253228940Sdelphij#define HPT_IOCTL_SET_BOOT_MARK             HPT_CTL_CODE(29)
254228940Sdelphij#define HPT_IOCTL_QUERY_REMOVE              HPT_CTL_CODE(30)
255228940Sdelphij#define HPT_IOCTL_REMOVE_DEVICES            HPT_CTL_CODE(31)
256228940Sdelphij#define HPT_IOCTL_CREATE_ARRAY_V2           HPT_CTL_CODE(32)
257228940Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO_V2        HPT_CTL_CODE(33)
258228940Sdelphij#define HPT_IOCTL_SET_DEVICE_INFO_V2        HPT_CTL_CODE(34)
259228940Sdelphij#define HPT_IOCTL_REBUILD_DATA_BLOCK_V2     HPT_CTL_CODE(35)
260228940Sdelphij#define HPT_IOCTL_VERIFY_DATA_BLOCK_V2      HPT_CTL_CODE(36)
261228940Sdelphij#define HPT_IOCTL_INITIALIZE_DATA_BLOCK_V2  HPT_CTL_CODE(37)
262228940Sdelphij#define HPT_IOCTL_LOCK_DEVICE_V2            HPT_CTL_CODE(38)
263228940Sdelphij#define HPT_IOCTL_DEVICE_IO_V2              HPT_CTL_CODE(39)
264228940Sdelphij#define HPT_IOCTL_DEVICE_IO_EX_V2           HPT_CTL_CODE(40)
265228940Sdelphij#define HPT_IOCTL_CREATE_TRANSFORM          HPT_CTL_CODE(41)
266228940Sdelphij#define HPT_IOCTL_STEP_TRANSFORM            HPT_CTL_CODE(42)
267228940Sdelphij#define HPT_IOCTL_SET_VDEV_INFO             HPT_CTL_CODE(43)
268228940Sdelphij#define HPT_IOCTL_CALC_MAX_CAPACITY         HPT_CTL_CODE(44)
269228940Sdelphij#define HPT_IOCTL_INIT_DISKS                HPT_CTL_CODE(45)
270228940Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO_V3        HPT_CTL_CODE(46)
271228940Sdelphij#define HPT_IOCTL_GET_CONTROLLER_INFO_V2    HPT_CTL_CODE(47)
272228940Sdelphij#define HPT_IOCTL_I2C_TRANSACTION           HPT_CTL_CODE(48)
273228940Sdelphij#define HPT_IOCTL_GET_PARAMETER_LIST        HPT_CTL_CODE(49)
274228940Sdelphij#define HPT_IOCTL_GET_PARAMETER             HPT_CTL_CODE(50)
275228940Sdelphij#define HPT_IOCTL_SET_PARAMETER             HPT_CTL_CODE(51)
276228940Sdelphij#define HPT_IOCTL_GET_DRIVER_CAPABILITIES_V2 HPT_CTL_CODE(52)
277228940Sdelphij#define HPT_IOCTL_GET_CHANNEL_INFO_V2       HPT_CTL_CODE(53)
278228940Sdelphij#define HPT_IOCTL_GET_CONTROLLER_INFO_V3    HPT_CTL_CODE(54)
279228940Sdelphij#define HPT_IOCTL_GET_DEVICE_INFO_V4        HPT_CTL_CODE(55)
280228940Sdelphij#define HPT_IOCTL_CREATE_ARRAY_V3           HPT_CTL_CODE(56)
281228940Sdelphij#define HPT_IOCTL_CREATE_TRANSFORM_V2       HPT_CTL_CODE(57)
282228940Sdelphij#define HPT_IOCTL_CALC_MAX_CAPACITY_V2      HPT_CTL_CODE(58)
283228940Sdelphij#define HPT_IOCTL_SCSI_PASSTHROUGH          HPT_CTL_CODE(59)
284228940Sdelphij#define HPT_IOCTL_GET_PHYSICAL_DEVICES      HPT_CTL_CODE(60)
285228940Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_COUNT       HPT_CTL_CODE(61)
286228940Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_INFO        HPT_CTL_CODE(62)
287228940Sdelphij#define HPT_IOCTL_GET_PERFMON_STATUS        HPT_CTL_CODE(63)
288228940Sdelphij#define HPT_IOCTL_SET_PERFMON_STATUS        HPT_CTL_CODE(64)
289228940Sdelphij#define HPT_IOCTL_GET_PERFMON_DATA          HPT_CTL_CODE(65)
290228940Sdelphij#define HPT_IOCTL_IDE_PASS_THROUGH_V2       HPT_CTL_CODE(66)
291228940Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_INFO_V2    HPT_CTL_CODE(67)
292228940Sdelphij#define HPT_IOCTL_GET_ENCLOSURE_INFO_V3    HPT_CTL_CODE(68)
293228940Sdelphij
294228940Sdelphij#define HPT_IOCTL_GET_CONTROLLER_IDS        HPT_CTL_CODE(100)
295228940Sdelphij#define HPT_IOCTL_GET_DCB                   HPT_CTL_CODE(101)
296228940Sdelphij
297228940Sdelphij#define HPT_IOCTL_EPROM_IO                  HPT_CTL_CODE(102)
298228940Sdelphij#define HPT_IOCTL_GET_CONTROLLER_VENID      HPT_CTL_CODE(103)
299228940Sdelphij
300228940Sdelphij/************************************************************************
301228940Sdelphij * shared data structures
302228940Sdelphij ************************************************************************/
303228940Sdelphij
304228940Sdelphij/*
305228940Sdelphij * Chip Type
306228940Sdelphij */
307228940Sdelphij#define CHIP_TYPE_HPT366      1
308228940Sdelphij#define CHIP_TYPE_HPT368      2
309228940Sdelphij#define CHIP_TYPE_HPT370      3
310228940Sdelphij#define CHIP_TYPE_HPT370A     4
311228940Sdelphij#define CHIP_TYPE_HPT370B     5
312228940Sdelphij#define CHIP_TYPE_HPT374      6
313228940Sdelphij#define CHIP_TYPE_HPT372      7
314228940Sdelphij#define CHIP_TYPE_HPT372A     8
315228940Sdelphij#define CHIP_TYPE_HPT302      9
316228940Sdelphij#define CHIP_TYPE_HPT371      10
317228940Sdelphij#define CHIP_TYPE_HPT372N     11
318228940Sdelphij#define CHIP_TYPE_HPT302N     12
319228940Sdelphij#define CHIP_TYPE_HPT371N     13
320228940Sdelphij#define CHIP_TYPE_SI3112A     14
321228940Sdelphij#define CHIP_TYPE_ICH5        15
322228940Sdelphij#define CHIP_TYPE_ICH5R       16
323228940Sdelphij#define CHIP_TYPE_MV50XX      20
324228940Sdelphij#define CHIP_TYPE_MV60X1      21
325228940Sdelphij#define CHIP_TYPE_MV60X2      22
326228940Sdelphij#define CHIP_TYPE_MV70X2      23
327228940Sdelphij#define CHIP_TYPE_MV5182      24
328228940Sdelphij#define CHIP_TYPE_IOP331      31
329228940Sdelphij#define CHIP_TYPE_IOP333      32
330228940Sdelphij#define CHIP_TYPE_IOP341      33
331228940Sdelphij#define CHIP_TYPE_IOP348      34
332228940Sdelphij
333228940Sdelphij/*
334228940Sdelphij * Chip Flags
335228940Sdelphij */
336228940Sdelphij#define CHIP_SUPPORT_ULTRA_66   0x20
337228940Sdelphij#define CHIP_SUPPORT_ULTRA_100  0x40
338228940Sdelphij#define CHIP_HPT3XX_DPLL_MODE   0x80
339228940Sdelphij#define CHIP_SUPPORT_ULTRA_133  0x01
340228940Sdelphij#define CHIP_SUPPORT_ULTRA_150  0x02
341228940Sdelphij#define CHIP_MASTER             0x04
342228940Sdelphij#define CHIP_SUPPORT_SATA_300   0x08
343228940Sdelphij
344228940Sdelphij#define HPT_SPIN_UP_MODE_NOSUPPORT 0
345228940Sdelphij#define HPT_SPIN_UP_MODE_FULL      1
346228940Sdelphij#define HPT_SPIN_UP_MODE_STANDBY   2
347228940Sdelphij
348228940Sdelphijtypedef struct _DRIVER_CAPABILITIES {
349228940Sdelphij	HPT_U32 dwSize;
350228940Sdelphij
351228940Sdelphij	HPT_U8 MaximumControllers;           /* maximum controllers the driver can support */
352228940Sdelphij	HPT_U8 SupportCrossControllerRAID;   /* 1-support, 0-not support */
353228940Sdelphij	HPT_U8 MinimumBlockSizeShift;        /* minimum block size shift */
354228940Sdelphij	HPT_U8 MaximumBlockSizeShift;        /* maximum block size shift */
355228940Sdelphij
356228940Sdelphij	HPT_U8 SupportDiskModeSetting;
357228940Sdelphij	HPT_U8 SupportSparePool;
358228940Sdelphij	HPT_U8 MaximumArrayNameLength;
359228940Sdelphij	/* only one HPT_U8 left here! */
360228940Sdelphij#ifdef __BIG_ENDIAN_BITFIELD
361228940Sdelphij	HPT_U8 reserved: 2;
362228940Sdelphij	HPT_U8 SupportPerformanceMonitor: 1;
363228940Sdelphij	HPT_U8 SupportVariableSectorSize: 1;
364228940Sdelphij	HPT_U8 SupportHotSwap: 1;
365228940Sdelphij	HPT_U8 HighPerformanceRAID1: 1;
366228940Sdelphij	HPT_U8 RebuildProcessInDriver: 1;
367228940Sdelphij	HPT_U8 SupportDedicatedSpare: 1;
368228940Sdelphij#else
369228940Sdelphij	HPT_U8 SupportDedicatedSpare: 1;     /* call hpt_add_dedicated_spare() for dedicated spare. */
370228940Sdelphij	HPT_U8 RebuildProcessInDriver: 1;    /* Windows only. used by mid layer for rebuild control. */
371228940Sdelphij	HPT_U8 HighPerformanceRAID1: 1;
372228940Sdelphij	HPT_U8 SupportHotSwap: 1;
373228940Sdelphij	HPT_U8 SupportVariableSectorSize: 1;
374228940Sdelphij	HPT_U8 SupportPerformanceMonitor: 1;
375228940Sdelphij	HPT_U8 reserved: 2;
376228940Sdelphij#endif
377228940Sdelphij
378228940Sdelphij
379228940Sdelphij	HPT_U8 SupportedRAIDTypes[16];
380228940Sdelphij	/* maximum members in an array corresponding to SupportedRAIDTypes */
381228940Sdelphij	HPT_U8 MaximumArrayMembers[16];
382228940Sdelphij}
383228940SdelphijDRIVER_CAPABILITIES, *PDRIVER_CAPABILITIES;
384228940Sdelphij
385228940Sdelphijtypedef struct _DRIVER_CAPABILITIES_V2 {
386228940Sdelphij	DRIVER_CAPABILITIES v1;
387228940Sdelphij	HPT_U8 SupportedCachePolicies[16];
388228940Sdelphij	HPT_U32 reserved[17];
389228940Sdelphij}
390228940SdelphijDRIVER_CAPABILITIES_V2, *PDRIVER_CAPABILITIES_V2;
391228940Sdelphij
392228940Sdelphij/*
393228940Sdelphij * Controller information.
394228940Sdelphij */
395228940Sdelphijtypedef struct _CONTROLLER_INFO {
396228940Sdelphij	HPT_U8 ChipType;                    /* chip type */
397228940Sdelphij	HPT_U8 InterruptLevel;              /* IRQ level */
398228940Sdelphij	HPT_U8 NumBuses;                    /* bus count */
399228940Sdelphij	HPT_U8 ChipFlags;
400228940Sdelphij
401228940Sdelphij	HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
402228940Sdelphij	HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
403228940Sdelphij
404228940Sdelphij} CONTROLLER_INFO, *PCONTROLLER_INFO;
405228940Sdelphij
406228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
407228940Sdelphijtypedef struct _CONTROLLER_INFO_V2 {
408228940Sdelphij	HPT_U8 ChipType;                    /* chip type */
409228940Sdelphij	HPT_U8 InterruptLevel;              /* IRQ level */
410228940Sdelphij	HPT_U8 NumBuses;                    /* bus count */
411228940Sdelphij	HPT_U8 ChipFlags;
412228940Sdelphij
413228940Sdelphij	HPT_U8 szProductID[MAX_NAME_LENGTH];/* product name */
414228940Sdelphij	HPT_U8 szVendorID[MAX_NAME_LENGTH]; /* vender name */
415228940Sdelphij
416228940Sdelphij	HPT_U32 GroupId;                    /* low 32bit of vbus pointer the controller belongs
417228940Sdelphij										 * the master controller has CHIP_MASTER flag set*/
418228940Sdelphij	HPT_U8  pci_tree;
419228940Sdelphij	HPT_U8  pci_bus;
420228940Sdelphij	HPT_U8  pci_device;
421228940Sdelphij	HPT_U8  pci_function;
422228940Sdelphij
423228940Sdelphij	HPT_U32 ExFlags;
424228940Sdelphij} CONTROLLER_INFO_V2, *PCONTROLLER_INFO_V2;
425228940Sdelphij
426228940Sdelphij
427228940Sdelphij#define CEXF_IOPModel            1
428228940Sdelphij#define CEXF_SDRAMSize           2
429228940Sdelphij#define CEXF_BatteryInstalled    4
430228940Sdelphij#define CEXF_BatteryStatus       8
431228940Sdelphij#define CEXF_BatteryVoltage      0x10
432228940Sdelphij#define CEXF_BatteryBackupTime   0x20
433228940Sdelphij#define CEXF_FirmwareVersion     0x40
434228940Sdelphij#define CEXF_SerialNumber        0x80
435228940Sdelphij#define CEXF_BatteryTemperature  0x100
436228940Sdelphij#define CEXF_Power12v            0x200
437228940Sdelphij#define CEXF_Power5v             0x400
438228940Sdelphij#define CEXF_Power3p3v           0x800
439228940Sdelphij#define CEXF_Power2p5v           0x1000
440228940Sdelphij#define CEXF_Power1p8v           0x2000
441228940Sdelphij#define CEXF_Core1p8v            0x4000
442228940Sdelphij#define CEXF_Core1p2v            0x8000
443228940Sdelphij#define CEXF_DDR1p8v             0x10000
444228940Sdelphij#define CEXF_DDR1p8vRef          0x20000
445228940Sdelphij#define CEXF_CPUTemperature      0x40000
446228940Sdelphij#define CEXF_BoardTemperature    0x80000
447228940Sdelphij#define CEXF_FanSpeed            0x100000
448228940Sdelphij#define CEXF_Core1p0v            0x200000
449228940Sdelphij#define CEXF_Fan2Speed           0x400000
450228940Sdelphij
451228940Sdelphijtypedef struct _CONTROLLER_INFO_V3 {
452228940Sdelphij	HPT_U8 ChipType;
453228940Sdelphij	HPT_U8 InterruptLevel;
454228940Sdelphij	HPT_U8 NumBuses;
455228940Sdelphij	HPT_U8 ChipFlags;
456228940Sdelphij	HPT_U8 szProductID[MAX_NAME_LENGTH];
457228940Sdelphij	HPT_U8 szVendorID[MAX_NAME_LENGTH];
458228940Sdelphij	HPT_U32 GroupId;
459228940Sdelphij	HPT_U8  pci_tree;
460228940Sdelphij	HPT_U8  pci_bus;
461228940Sdelphij	HPT_U8  pci_device;
462228940Sdelphij	HPT_U8  pci_function;
463228940Sdelphij	HPT_U32 ExFlags;
464228940Sdelphij	HPT_U8  IOPModel[32];
465228940Sdelphij	HPT_U32 SDRAMSize;
466228940Sdelphij	HPT_U8  BatteryInstalled;
467228940Sdelphij	HPT_U8  BatteryStatus;
468228940Sdelphij	HPT_U16 BatteryVoltage;
469228940Sdelphij	HPT_U32 BatteryBackupTime;
470228940Sdelphij	HPT_U32 FirmwareVersion;
471228940Sdelphij	HPT_U8  SerialNumber[32];
472228940Sdelphij	HPT_U8  BatteryMBInstalled;
473228940Sdelphij	HPT_U8  BatteryTemperature;
474228940Sdelphij	signed char CPUTemperature;
475228940Sdelphij	signed char BoardTemperature;
476228940Sdelphij	HPT_U16 FanSpeed;
477228940Sdelphij	HPT_U16 Power12v;
478228940Sdelphij	HPT_U16 Power5v;
479228940Sdelphij	HPT_U16 Power3p3v;
480228940Sdelphij	HPT_U16 Power2p5v;
481228940Sdelphij	HPT_U16 Power1p8v;
482228940Sdelphij	HPT_U16 Core1p8v;
483228940Sdelphij	HPT_U16 Core1p2v;
484228940Sdelphij	HPT_U16 DDR1p8v;
485228940Sdelphij	HPT_U16 DDR1p8vRef;
486228940Sdelphij	HPT_U16 Core1p0v;
487228940Sdelphij	HPT_U16 Fan2Speed;
488228940Sdelphij	HPT_U8  reserve[60];
489228940Sdelphij}
490228940SdelphijCONTROLLER_INFO_V3, *PCONTROLLER_INFO_V3;
491228940Sdelphijtypedef char check_CONTROLLER_INFO_V3[sizeof(CONTROLLER_INFO_V3)==256? 1:-1];
492228940Sdelphij#endif
493228940Sdelphij/*
494228940Sdelphij * Channel information.
495228940Sdelphij */
496228940Sdelphijtypedef struct _CHANNEL_INFO {
497228940Sdelphij	HPT_U32         IoPort;         /* IDE Base Port Address */
498228940Sdelphij	HPT_U32         ControlPort;    /* IDE Control Port Address */
499228940Sdelphij
500228940Sdelphij	DEVICEID    Devices[2];         /* device connected to this channel */
501228940Sdelphij
502228940Sdelphij} CHANNEL_INFO, *PCHANNEL_INFO;
503228940Sdelphij
504228940Sdelphijtypedef struct _CHANNEL_INFO_V2 {
505228940Sdelphij	HPT_U32         IoPort;         /* IDE Base Port Address */
506228940Sdelphij	HPT_U32         ControlPort;    /* IDE Control Port Address */
507228940Sdelphij
508228940Sdelphij	DEVICEID        Devices[2+13];    /* device connected to this channel, PMPort max=15 */
509228940Sdelphij} CHANNEL_INFO_V2, *PCHANNEL_INFO_V2;
510228940Sdelphij
511228940Sdelphijtypedef struct _ENCLOSURE_INFO {
512228940Sdelphij	HPT_U8  EnclosureType;
513228940Sdelphij	HPT_U8  NumberOfPhys;
514228940Sdelphij	HPT_U8  AttachedTo;
515228940Sdelphij	HPT_U8  Status;
516228940Sdelphij	HPT_U8  VendorId[8];
517228940Sdelphij	HPT_U8  ProductId[16];
518228940Sdelphij	HPT_U8  ProductRevisionLevel[4];
519228940Sdelphij	HPT_U32 PortPhyMap;
520228940Sdelphij	HPT_U32 reserve[55];
521228940Sdelphij} ENCLOSURE_INFO, *PENCLOSURE_INFO;
522228940Sdelphij
523228940Sdelphij
524228940Sdelphijtypedef struct _SES_ELEMENT_STATUS {
525228940Sdelphij	HPT_U8   ElementType;
526228940Sdelphij	HPT_U8   ElementOverallIndex;
527228940Sdelphij	HPT_U8   ElementStatus;
528228940Sdelphij	HPT_U8   Reserved;
529228940Sdelphij	HPT_U32 ElementValue;
530228940Sdelphij	HPT_U8   ElementDescriptor[32];
531228940Sdelphij}SES_ELEMENT_STATUS,*PSES_ELEMENT_STATUS;
532228940Sdelphij
533228940Sdelphij#define MAX_ELEMENT_COUNT  80
534228940Sdelphij/* Element Type */
535228940Sdelphij#define SES_TYPE_UNSPECIFIED         0x00
536228940Sdelphij#define SES_TYPE_DEVICE              0x01
537228940Sdelphij#define SES_TYPE_POWER_SUPPLY        0x02
538228940Sdelphij#define SES_TYPE_FAN                 0x03
539228940Sdelphij#define SES_TYPE_TEMPERATURE_SENSOR  0x04
540228940Sdelphij#define SES_TYPE_DOOR_LOCK           0x05
541228940Sdelphij#define SES_TYPE_SPEAKER             0x06
542228940Sdelphij#define SES_TYPE_ES_CONTROLLER       0x07
543228940Sdelphij#define SES_TYPE_SCC_CONTROLLER      0x08
544228940Sdelphij#define SES_TYPE_NONVOLATILE_CACHE   0x09
545228940Sdelphij#define SES_TYPE_UPS                 0x0B
546228940Sdelphij#define SES_TYPE_DISPLAY             0x0C
547228940Sdelphij#define SES_TYPE_KEYPAD              0x0D
548228940Sdelphij#define SES_TYPE_ENCLOSURE           0x0E
549228940Sdelphij#define SES_TYPE_SCSI_TRANSCEIVER    0x0F
550228940Sdelphij#define SES_TYPE_LANGUAGE            0x10
551228940Sdelphij#define SES_TYPE_COMM_PORT           0x11
552228940Sdelphij#define SES_TYPE_VOLTAGE_SENSOR      0x12
553228940Sdelphij#define SES_TYPE_CURRENT_SENSOR      0x13
554228940Sdelphij#define SES_TYPE_SCSI_TARGET_PORT    0x14
555228940Sdelphij#define SES_TYPE_SCSI_INITIATOR_PORT 0x15
556228940Sdelphij#define SES_TYPE_SIMPLE_SUBENCLOSURE 0x16
557228940Sdelphij#define SES_TYPE_ARRAY_DEVICE        0x17
558228940Sdelphij#define SES_TYPE_VENDOR_SPECIFIC     0x80
559228940Sdelphij
560228940Sdelphij/* Element Status */
561228940Sdelphij
562228940Sdelphij#define	SES_STATUS_UNSUPPORTED   		0x00
563228940Sdelphij#define	SES_STATUS_OK					0x01
564228940Sdelphij#define	SES_STATUS_CRITICAL			0x02
565228940Sdelphij#define	SES_STATUS_NONCRITICAL 		0x03
566228940Sdelphij#define	SES_STATUS_UNRECOVERABLE	0x04
567228940Sdelphij#define	SES_STATUS_NOTINSTALLED		0x05
568228940Sdelphij#define	SES_STATUS_UNKNOWN			0x06
569228940Sdelphij#define	SES_STATUS_NOTAVAILABLE		0x06
570228940Sdelphij#define	SES_STATUS_RESERVED			0x07
571228940Sdelphij
572228940Sdelphij
573228940Sdelphijtypedef struct _ENCLOSURE_INFO_V2 {
574228940Sdelphij	HPT_U8  EnclosureType;
575228940Sdelphij	HPT_U8  NumberOfPhys;
576228940Sdelphij	HPT_U8  AttachedTo;
577228940Sdelphij	HPT_U8  Status;
578228940Sdelphij	HPT_U8  VendorId[8];
579228940Sdelphij	HPT_U8  ProductId[16];
580228940Sdelphij	HPT_U8  ProductRevisionLevel[4];
581228940Sdelphij	HPT_U32 PortPhyMap;
582228940Sdelphij	SES_ELEMENT_STATUS ElementStatus[MAX_ELEMENT_COUNT];
583228940Sdelphij} ENCLOSURE_INFO_V2, *PENCLOSURE_INFO_V2;
584228940Sdelphij
585228940Sdelphijtypedef struct _ENCLOSURE_INFO_V3 {
586228940Sdelphij	HPT_U8  EnclosureType;
587228940Sdelphij	HPT_U8  NumberOfPhys;
588228940Sdelphij	HPT_U8  AttachedTo;
589228940Sdelphij	HPT_U8  Status;
590228940Sdelphij	HPT_U8  VendorId[8];
591228940Sdelphij	HPT_U8  ProductId[16];
592228940Sdelphij	HPT_U8  ProductRevisionLevel[4];
593228940Sdelphij	HPT_U32 PortPhyMap;
594228940Sdelphij	HPT_U32	UnitId;	/*272x card has two Cores, unitId is used to distinguish them */
595228940Sdelphij	HPT_U32 reserved[32];
596228940Sdelphij	SES_ELEMENT_STATUS ElementStatus[MAX_ELEMENT_COUNT];
597228940Sdelphij} ENCLOSURE_INFO_V3, *PENCLOSURE_INFO_V3;
598228940Sdelphij
599228940Sdelphij#define ENCLOSURE_STATUS_OFFLINE 1
600228940Sdelphij
601228940Sdelphij#define ENCLOSURE_TYPE_INTERNAL 0
602228940Sdelphij#define ENCLOSURE_TYPE_SMP      1
603228940Sdelphij#define ENCLOSURE_TYPE_PM       2
604228940Sdelphij
605228940Sdelphij#ifndef __KERNEL__
606228940Sdelphij/*
607228940Sdelphij * time represented in HPT_U32 format
608228940Sdelphij */
609228940Sdelphijtypedef struct _TIME_RECORD {
610228940Sdelphij   HPT_U32        seconds:6;      /* 0 - 59 */
611228940Sdelphij   HPT_U32        minutes:6;      /* 0 - 59 */
612228940Sdelphij   HPT_U32        month:4;        /* 1 - 12 */
613228940Sdelphij   HPT_U32        hours:6;        /* 0 - 59 */
614228940Sdelphij   HPT_U32        day:5;          /* 1 - 31 */
615228940Sdelphij   HPT_U32        year:5;         /* 0=2000, 31=2031 */
616228940Sdelphij} TIME_RECORD;
617228940Sdelphij#endif
618228940Sdelphij
619228940Sdelphij/*
620228940Sdelphij * Array information.
621228940Sdelphij */
622228940Sdelphijtypedef struct _HPT_ARRAY_INFO {
623228940Sdelphij	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
624228940Sdelphij	HPT_U8      Description[64];        /* array description */
625228940Sdelphij	HPT_U8      CreateManager[16];      /* who created it */
626228940Sdelphij	TIME_RECORD CreateTime;             /* when created it */
627228940Sdelphij
628228940Sdelphij	HPT_U8      ArrayType;              /* array type */
629228940Sdelphij	HPT_U8      BlockSizeShift;         /* stripe size */
630228940Sdelphij	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
631228940Sdelphij	HPT_U8      SubArrayType;
632228940Sdelphij
633228940Sdelphij	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
634228940Sdelphij	HPT_U32     Members[MAX_ARRAY_MEMBERS_V1];  /* member array/disks */
635228940Sdelphij
636228940Sdelphij	/*
637228940Sdelphij	 * rebuilding progress, xx.xx% = sprintf(s, "%.2f%%", RebuildingProgress/100.0);
638228940Sdelphij	 * only valid if rebuilding is done by driver code.
639228940Sdelphij	 * Member Flags will have ARRAY_FLAG_REBUILDING set at this case.
640228940Sdelphij	 * Verify operation use same fields below, the only difference is
641228940Sdelphij	 * ARRAY_FLAG_VERIFYING is set.
642228940Sdelphij	 */
643228940Sdelphij	HPT_U32     RebuildingProgress;
644228940Sdelphij	HPT_U32     RebuiltSectors; /* rebuilding point (LBA) for single member */
645228940Sdelphij
646228940Sdelphij} HPT_ARRAY_INFO, *PHPT_ARRAY_INFO;
647228940Sdelphij
648228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
649228940Sdelphijtypedef struct _HPT_ARRAY_INFO_V2 {
650228940Sdelphij	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
651228940Sdelphij	HPT_U8      Description[64];        /* array description */
652228940Sdelphij	HPT_U8      CreateManager[16];      /* who created it */
653228940Sdelphij	TIME_RECORD CreateTime;             /* when created it */
654228940Sdelphij
655228940Sdelphij	HPT_U8      ArrayType;              /* array type */
656228940Sdelphij	HPT_U8      BlockSizeShift;         /* stripe size */
657228940Sdelphij	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
658228940Sdelphij	HPT_U8      SubArrayType;
659228940Sdelphij
660228940Sdelphij	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
661228940Sdelphij	HPT_U32     Members[MAX_ARRAY_MEMBERS_V2];  /* member array/disks */
662228940Sdelphij
663228940Sdelphij	HPT_U32     RebuildingProgress;
664228940Sdelphij	HPT_U64     RebuiltSectors; /* rebuilding point (LBA) for single member */
665228940Sdelphij
666228940Sdelphij	HPT_U32     reserve4[4];
667228940Sdelphij} HPT_ARRAY_INFO_V2, *PHPT_ARRAY_INFO_V2;
668228940Sdelphij#endif
669228940Sdelphij
670228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
671228940Sdelphijtypedef struct _HPT_ARRAY_INFO_V3 {
672228940Sdelphij	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
673228940Sdelphij	HPT_U8      Description[64];        /* array description */
674228940Sdelphij	HPT_U8      CreateManager[16];      /* who created it */
675228940Sdelphij	TIME_RECORD CreateTime;             /* when created it */
676228940Sdelphij
677228940Sdelphij	HPT_U8      ArrayType;              /* array type */
678228940Sdelphij	HPT_U8      BlockSizeShift;         /* stripe size */
679228940Sdelphij	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
680228940Sdelphij	HPT_U8      SubArrayType;
681228940Sdelphij
682228940Sdelphij	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
683228940Sdelphij	HPT_U32     Members[MAX_ARRAY_MEMBERS_V2];  /* member array/disks */
684228940Sdelphij
685228940Sdelphij	HPT_U32     RebuildingProgress;
686228940Sdelphij	HPT_U64     RebuiltSectors;         /* rebuilding point (LBA) for single member */
687228940Sdelphij
688228940Sdelphij	DEVICEID    TransformSource;
689228940Sdelphij	DEVICEID    TransformTarget;        /* destination device ID */
690228940Sdelphij	HPT_U32     TransformingProgress;
691228940Sdelphij	HPT_U32     Signature;              /* persistent identification*/
692228940Sdelphij#if MAX_ARRAY_MEMBERS_V2==16
693228940Sdelphij	HPT_U16     Critical_Members;       /* bit mask of critical members */
694228940Sdelphij	HPT_U16     reserve2;
695228940Sdelphij	HPT_U32     reserve;
696228940Sdelphij#else
697228940Sdelphij	HPT_U32     Critical_Members;
698228940Sdelphij	HPT_U32     reserve;
699228940Sdelphij#endif
700228940Sdelphij} HPT_ARRAY_INFO_V3, *PHPT_ARRAY_INFO_V3;
701228940Sdelphij#endif
702228940Sdelphij
703228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001
704228940Sdelphijtypedef struct _HPT_ARRAY_INFO_V4 {
705228940Sdelphij	HPT_U8      Name[MAX_ARRAYNAME_LEN];/* array name */
706228940Sdelphij	HPT_U8      Description[64];        /* array description */
707228940Sdelphij	HPT_U8      CreateManager[16];      /* who created it */
708228940Sdelphij	TIME_RECORD CreateTime;             /* when created it */
709228940Sdelphij
710228940Sdelphij	HPT_U8      ArrayType;              /* array type */
711228940Sdelphij	HPT_U8      BlockSizeShift;         /* stripe size */
712228940Sdelphij	HPT_U8      nDisk;                  /* member count: Number of ID in Members[] */
713228940Sdelphij	HPT_U8      SubArrayType;
714228940Sdelphij
715228940Sdelphij	HPT_U32     Flags;                  /* working flags, see ARRAY_FLAG_XXX */
716228940Sdelphij
717228940Sdelphij	HPT_U32     RebuildingProgress;
718228940Sdelphij	HPT_U64     RebuiltSectors; /* rebuilding point (LBA) for single member */
719228940Sdelphij
720228940Sdelphij	DEVICEID    TransformSource;
721228940Sdelphij	DEVICEID    TransformTarget;   /* destination device ID */
722228940Sdelphij	HPT_U32     TransformingProgress;
723228940Sdelphij	HPT_U32     Signature;          /* persistent identification*/
724228940Sdelphij	HPT_U8       SectorSizeShift; /*sector size = 512B<<SectorSizeShift*/
725228940Sdelphij	HPT_U8       reserved2[7];
726228940Sdelphij	HPT_U64     Critical_Members;
727228940Sdelphij	HPT_U32     Members[MAX_ARRAY_MEMBERS_V3];  /* member array/disks */
728228940Sdelphij} HPT_ARRAY_INFO_V4, *PHPT_ARRAY_INFO_V4;
729228940Sdelphij#endif
730228940Sdelphij
731228940Sdelphij
732228940Sdelphij/*
733228940Sdelphij * ATA/ATAPI Device identify data without the Reserved4.
734228940Sdelphij */
735228940Sdelphijtypedef struct _IDENTIFY_DATA2 {
736228940Sdelphij	HPT_U16 GeneralConfiguration;
737228940Sdelphij	HPT_U16 NumberOfCylinders;
738228940Sdelphij	HPT_U16 Reserved1;
739228940Sdelphij	HPT_U16 NumberOfHeads;
740228940Sdelphij	HPT_U16 UnformattedBytesPerTrack;
741228940Sdelphij	HPT_U16 UnformattedBytesPerSector;
742228940Sdelphij	HPT_U8  SasAddress[8];
743228940Sdelphij	HPT_U16 SerialNumber[10];
744228940Sdelphij	HPT_U16 BufferType;
745228940Sdelphij	HPT_U16 BufferSectorSize;
746228940Sdelphij	HPT_U16 NumberOfEccBytes;
747228940Sdelphij	HPT_U16 FirmwareRevision[4];
748228940Sdelphij	HPT_U16 ModelNumber[20];
749228940Sdelphij	HPT_U8  MaximumBlockTransfer;
750228940Sdelphij	HPT_U8  VendorUnique2;
751228940Sdelphij	HPT_U16 DoubleWordIo;
752228940Sdelphij	HPT_U16 Capabilities;
753228940Sdelphij	HPT_U16 Reserved2;
754228940Sdelphij	HPT_U8  VendorUnique3;
755228940Sdelphij	HPT_U8  PioCycleTimingMode;
756228940Sdelphij	HPT_U8  VendorUnique4;
757228940Sdelphij	HPT_U8  DmaCycleTimingMode;
758228940Sdelphij	HPT_U16 TranslationFieldsValid;
759228940Sdelphij	HPT_U16 NumberOfCurrentCylinders;
760228940Sdelphij	HPT_U16 NumberOfCurrentHeads;
761228940Sdelphij	HPT_U16 CurrentSectorsPerTrack;
762228940Sdelphij	HPT_U32 CurrentSectorCapacity;
763228940Sdelphij	HPT_U16 CurrentMultiSectorSetting;
764228940Sdelphij	HPT_U32 UserAddressableSectors;
765228940Sdelphij	HPT_U8  SingleWordDMASupport;
766228940Sdelphij	HPT_U8  SingleWordDMAActive;
767228940Sdelphij	HPT_U8  MultiWordDMASupport;
768228940Sdelphij	HPT_U8  MultiWordDMAActive;
769228940Sdelphij	HPT_U8  AdvancedPIOModes;
770228940Sdelphij	HPT_U8  Reserved4;
771228940Sdelphij	HPT_U16 MinimumMWXferCycleTime;
772228940Sdelphij	HPT_U16 RecommendedMWXferCycleTime;
773228940Sdelphij	HPT_U16 MinimumPIOCycleTime;
774228940Sdelphij	HPT_U16 MinimumPIOCycleTimeIORDY;
775228940Sdelphij	HPT_U16 Reserved5[2];
776228940Sdelphij	HPT_U16 ReleaseTimeOverlapped;
777228940Sdelphij	HPT_U16 ReleaseTimeServiceCommand;
778228940Sdelphij	HPT_U16 MajorRevision;
779228940Sdelphij	HPT_U16 MinorRevision;
780228940Sdelphij} __attribute__((packed)) IDENTIFY_DATA2, *PIDENTIFY_DATA2;
781228940Sdelphij
782228940Sdelphij/*
783228940Sdelphij * physical device information.
784228940Sdelphij * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
785228940Sdelphij */
786228940Sdelphijtypedef struct _DEVICE_INFO {
787228940Sdelphij	HPT_U8   ControllerId;          /* controller id */
788228940Sdelphij	HPT_U8   PathId;                /* bus */
789228940Sdelphij	HPT_U8   TargetId;              /* id */
790228940Sdelphij	HPT_U8   DeviceModeSetting;     /* Current Data Transfer mode: 0-4 PIO 0-4 */
791228940Sdelphij									/* 5-7 MW DMA0-2, 8-13 UDMA0-5             */
792228940Sdelphij	HPT_U8   DeviceType;            /* device type */
793228940Sdelphij	HPT_U8   UsableMode;            /* highest usable mode */
794228940Sdelphij
795228940Sdelphij#ifdef __BIG_ENDIAN_BITFIELD
796228940Sdelphij	HPT_U8   NCQEnabled: 1;
797228940Sdelphij	HPT_U8   NCQSupported: 1;
798228940Sdelphij	HPT_U8   TCQEnabled: 1;
799228940Sdelphij	HPT_U8   TCQSupported: 1;
800228940Sdelphij	HPT_U8   WriteCacheEnabled: 1;
801228940Sdelphij	HPT_U8   WriteCacheSupported: 1;
802228940Sdelphij	HPT_U8   ReadAheadEnabled: 1;
803228940Sdelphij	HPT_U8   ReadAheadSupported: 1;
804228940Sdelphij	HPT_U8   reserved6: 6;
805228940Sdelphij	HPT_U8   SpinUpMode: 2;
806228940Sdelphij#else
807228940Sdelphij	HPT_U8   ReadAheadSupported: 1;
808228940Sdelphij	HPT_U8   ReadAheadEnabled: 1;
809228940Sdelphij	HPT_U8   WriteCacheSupported: 1;
810228940Sdelphij	HPT_U8   WriteCacheEnabled: 1;
811228940Sdelphij	HPT_U8   TCQSupported: 1;
812228940Sdelphij	HPT_U8   TCQEnabled: 1;
813228940Sdelphij	HPT_U8   NCQSupported: 1;
814228940Sdelphij	HPT_U8   NCQEnabled: 1;
815228940Sdelphij	HPT_U8   SpinUpMode: 2;
816228940Sdelphij	HPT_U8   reserved6: 6;
817228940Sdelphij#endif
818228940Sdelphij
819228940Sdelphij	HPT_U32     Flags;              /* working flags, see DEVICE_FLAG_XXX */
820228940Sdelphij
821228940Sdelphij	IDENTIFY_DATA2 IdentifyData;    /* Identify Data of this device */
822228940Sdelphij
823228940Sdelphij}
824228940Sdelphij__attribute__((packed)) DEVICE_INFO, *PDEVICE_INFO;
825228940Sdelphij
826228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
827228940Sdelphij#define MAX_PARENTS_PER_DISK    8
828228940Sdelphij/*
829228940Sdelphij * physical device information.
830228940Sdelphij * IdentifyData.ModelNumber[] is HPT_U8-swapped from the original identify data.
831228940Sdelphij */
832228940Sdelphijtypedef struct _DEVICE_INFO_V2 {
833228940Sdelphij	HPT_U8   ControllerId;          /* controller id */
834228940Sdelphij	HPT_U8   PathId;                /* bus */
835228940Sdelphij	HPT_U8   TargetId;              /* id */
836228940Sdelphij	HPT_U8   DeviceModeSetting;     /* Current Data Transfer mode: 0-4 PIO 0-4 */
837228940Sdelphij									/* 5-7 MW DMA0-2, 8-13 UDMA0-5             */
838228940Sdelphij	HPT_U8   DeviceType;            /* device type */
839228940Sdelphij	HPT_U8   UsableMode;            /* highest usable mode */
840228940Sdelphij
841228940Sdelphij#ifdef __BIG_ENDIAN_BITFIELD
842228940Sdelphij	HPT_U8   NCQEnabled: 1;
843228940Sdelphij	HPT_U8   NCQSupported: 1;
844228940Sdelphij	HPT_U8   TCQEnabled: 1;
845228940Sdelphij	HPT_U8   TCQSupported: 1;
846228940Sdelphij	HPT_U8   WriteCacheEnabled: 1;
847228940Sdelphij	HPT_U8   WriteCacheSupported: 1;
848228940Sdelphij	HPT_U8   ReadAheadEnabled: 1;
849228940Sdelphij	HPT_U8   ReadAheadSupported: 1;
850228940Sdelphij	HPT_U8   reserved6: 6;
851228940Sdelphij	HPT_U8   SpinUpMode: 2;
852228940Sdelphij#else
853228940Sdelphij	HPT_U8   ReadAheadSupported: 1;
854228940Sdelphij	HPT_U8   ReadAheadEnabled: 1;
855228940Sdelphij	HPT_U8   WriteCacheSupported: 1;
856228940Sdelphij	HPT_U8   WriteCacheEnabled: 1;
857228940Sdelphij	HPT_U8   TCQSupported: 1;
858228940Sdelphij	HPT_U8   TCQEnabled: 1;
859228940Sdelphij	HPT_U8   NCQSupported: 1;
860228940Sdelphij	HPT_U8   NCQEnabled: 1;
861228940Sdelphij	HPT_U8   SpinUpMode: 2;
862228940Sdelphij	HPT_U8   reserved6: 6;
863228940Sdelphij#endif
864228940Sdelphij
865228940Sdelphij	HPT_U32     Flags;              /* working flags, see DEVICE_FLAG_XXX */
866228940Sdelphij
867228940Sdelphij	IDENTIFY_DATA2 IdentifyData;    /* Identify Data of this device */
868228940Sdelphij
869228940Sdelphij	HPT_U64 TotalFree;
870228940Sdelphij	HPT_U64 MaxFree;
871228940Sdelphij	HPT_U64 BadSectors;
872228940Sdelphij	DEVICEID ParentArrays[MAX_PARENTS_PER_DISK];
873228940Sdelphij
874228940Sdelphij}
875228940Sdelphij__attribute__((packed)) DEVICE_INFO_V2, *PDEVICE_INFO_V2, DEVICE_INFO_V3, *PDEVICE_INFO_V3;
876228940Sdelphij
877228940Sdelphij/*
878228940Sdelphij * HPT601 information
879228940Sdelphij */
880228940Sdelphij#endif
881228940Sdelphij/*
882228940Sdelphij * HPT601 information
883228940Sdelphij */
884228940Sdelphij#define HPT601_INFO_DEVICEID      1
885228940Sdelphij#define HPT601_INFO_TEMPERATURE   2
886228940Sdelphij#define HPT601_INFO_FANSTATUS     4
887228940Sdelphij#define HPT601_INFO_BEEPERCONTROL 8
888228940Sdelphij#define HPT601_INFO_LED1CONTROL   0x10
889228940Sdelphij#define HPT601_INFO_LED2CONTROL   0x20
890228940Sdelphij#define HPT601_INFO_POWERSTATUS   0x40
891228940Sdelphij
892228940Sdelphijtypedef struct _HPT601_INFO_ {
893228940Sdelphij	HPT_U16 ValidFields;        /* mark valid fields below */
894228940Sdelphij	HPT_U16 DeviceId;           /* 0x5A3E */
895228940Sdelphij	HPT_U16 Temperature;        /* Read: temperature sensor value. Write: temperature limit */
896228940Sdelphij	HPT_U16 FanStatus;          /* Fan status */
897228940Sdelphij	HPT_U16 BeeperControl;      /* bit4: beeper control bit. bit0-3: frequency bits */
898228940Sdelphij	HPT_U16 LED1Control;        /* bit4: twinkling control bit. bit0-3: frequency bits */
899228940Sdelphij	HPT_U16 LED2Control;        /* bit4: twinkling control bit. bit0-3: frequency bits */
900228940Sdelphij	HPT_U16 PowerStatus;        /* 1: has power 2: no power */
901228940Sdelphij} HPT601_INFO, *PHPT601_INFO;
902228940Sdelphij
903228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
904228940Sdelphij#ifndef __KERNEL__
905228940Sdelphij/* cache policy for each vdev, copied from ldm.h */
906228940Sdelphij#define CACHE_POLICY_NONE 0
907228940Sdelphij#define CACHE_POLICY_WRITE_THROUGH 1
908228940Sdelphij#define CACHE_POLICY_WRITE_BACK 2
909228940Sdelphij
910228940Sdelphij#endif
911228940Sdelphij#endif
912228940Sdelphij/*
913228940Sdelphij * Logical device information.
914228940Sdelphij * Union of ArrayInfo and DeviceInfo.
915228940Sdelphij * Common properties will be put in logical device information.
916228940Sdelphij */
917228940Sdelphijtypedef struct _LOGICAL_DEVICE_INFO {
918228940Sdelphij	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
919228940Sdelphij	HPT_U8      reserved[3];
920228940Sdelphij
921228940Sdelphij	HPT_U32     Capacity;               /* array capacity */
922228940Sdelphij	DEVICEID    ParentArray;
923228940Sdelphij
924228940Sdelphij	union {
925228940Sdelphij		HPT_ARRAY_INFO array;
926228940Sdelphij		DEVICE_INFO device;
927228940Sdelphij	} __attribute__((packed)) u;
928228940Sdelphij
929228940Sdelphij} __attribute__((packed)) LOGICAL_DEVICE_INFO, *PLOGICAL_DEVICE_INFO;
930228940Sdelphij
931228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
932228940Sdelphijtypedef struct _LOGICAL_DEVICE_INFO_V2 {
933228940Sdelphij	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
934228940Sdelphij	HPT_U8      reserved[3];
935228940Sdelphij
936228940Sdelphij	HPT_U64     Capacity;               /* array capacity */
937228940Sdelphij	DEVICEID    ParentArray;            /* for physical device, Please don't use this field.
938228940Sdelphij										 * use ParentArrays field in DEVICE_INFO_V2
939228940Sdelphij										 */
940228940Sdelphij
941228940Sdelphij	union {
942228940Sdelphij		HPT_ARRAY_INFO_V2 array;
943228940Sdelphij		DEVICE_INFO device;
944228940Sdelphij	} __attribute__((packed)) u;
945228940Sdelphij
946228940Sdelphij} __attribute__((packed)) LOGICAL_DEVICE_INFO_V2, *PLOGICAL_DEVICE_INFO_V2;
947228940Sdelphij#endif
948228940Sdelphij
949228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
950228940Sdelphij#define INVALID_TARGET_ID   0xFF
951228940Sdelphij#define INVALID_BUS_ID      0xFF
952228940Sdelphijtypedef struct _LOGICAL_DEVICE_INFO_V3 {
953228940Sdelphij	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
954228940Sdelphij	HPT_U8      CachePolicy;            /* refer to CACHE_POLICY_xxx */
955228940Sdelphij	HPT_U8      VBusId;                 /* vbus sequence in vbus_list */
956228940Sdelphij	HPT_U8      TargetId;               /* OS target id. Value 0xFF is invalid */
957228940Sdelphij										/* OS disk name: HPT DISK $VBusId_$TargetId */
958228940Sdelphij	HPT_U64     Capacity;               /* array capacity */
959228940Sdelphij	DEVICEID    ParentArray;            /* for physical device, don't use this field.
960228940Sdelphij										 * use ParentArrays field in DEVICE_INFO_V2 instead.
961228940Sdelphij										 */
962228940Sdelphij	HPT_U32     TotalIOs;
963228940Sdelphij	HPT_U32     TobalMBs;
964228940Sdelphij	HPT_U32     IOPerSec;
965228940Sdelphij	HPT_U32     MBPerSec;
966228940Sdelphij
967228940Sdelphij	union {
968228940Sdelphij		HPT_ARRAY_INFO_V3 array;
969228940Sdelphij		DEVICE_INFO_V2 device;
970228940Sdelphij	} __attribute__((packed)) u;
971228940Sdelphij
972228940Sdelphij}
973228940Sdelphij__attribute__((packed)) LOGICAL_DEVICE_INFO_V3, *PLOGICAL_DEVICE_INFO_V3;
974228940Sdelphij#endif
975228940Sdelphij
976228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001
977228940Sdelphijtypedef struct _LOGICAL_DEVICE_INFO_V4 {
978228940Sdelphij	HPT_U32    dwSize;
979228940Sdelphij	HPT_U8      revision;
980228940Sdelphij	HPT_U8      reserved[7];
981228940Sdelphij
982228940Sdelphij	HPT_U8      Type;                   /* LDT_ARRAY or LDT_DEVICE */
983228940Sdelphij	HPT_U8      CachePolicy;            /* refer to CACHE_POLICY_xxx */
984228940Sdelphij	HPT_U8      VBusId;                 /* vbus sequence in vbus_list */
985228940Sdelphij	HPT_U8      TargetId;               /* OS target id. Value 0xFF is invalid */
986228940Sdelphij										/* OS disk name: HPT DISK $VBusId_$TargetId */
987228940Sdelphij	HPT_U64     Capacity;               /* array capacity */
988228940Sdelphij	DEVICEID    ParentArray;            /* for physical device, don't use this field.
989228940Sdelphij										 * use ParentArrays field in DEVICE_INFO_V2 instead.
990228940Sdelphij										 */
991228940Sdelphij	HPT_U32     TotalIOs;
992228940Sdelphij	HPT_U32     TobalMBs;
993228940Sdelphij	HPT_U32     IOPerSec;
994228940Sdelphij	HPT_U32     MBPerSec;
995228940Sdelphij
996228940Sdelphij	union {
997228940Sdelphij		HPT_ARRAY_INFO_V4 array;
998228940Sdelphij		DEVICE_INFO_V3 device;
999228940Sdelphij	} __attribute__((packed)) u;
1000228940Sdelphij}
1001228940Sdelphij__attribute__((packed)) LOGICAL_DEVICE_INFO_V4, *PLOGICAL_DEVICE_INFO_V4;
1002228940Sdelphij
1003228940Sdelphij/*LOGICAL_DEVICE_INFO_V4 max revision number*/
1004228940Sdelphij#define LOGICAL_DEVICE_INFO_V4_REVISION 0
1005228940Sdelphij/*If new revision was defined please check evey revision size*/
1006228940Sdelphij#define LOGICAL_DEVICE_INFO_V4_R0_SIZE (sizeof(LOGICAL_DEVICE_INFO_V4))
1007228940Sdelphij#endif
1008228940Sdelphij
1009228940Sdelphij/*
1010228940Sdelphij * ALTERABLE_ARRAY_INFO and ALTERABLE_DEVICE_INFO, used in set_array_info()
1011228940Sdelphij * and set_device_info().
1012228940Sdelphij * When set_xxx_info() is called, the ValidFields member indicates which
1013228940Sdelphij * fields in the structure are valid.
1014228940Sdelphij */
1015228940Sdelphij/* field masks */
1016228940Sdelphij#define AAIF_NAME           1
1017228940Sdelphij#define AAIF_DESCRIPTION    2
1018228940Sdelphij
1019228940Sdelphij#define ADIF_MODE           1
1020228940Sdelphij#define ADIF_TCQ            2
1021228940Sdelphij#define ADIF_NCQ            4
1022228940Sdelphij#define ADIF_WRITE_CACHE    8
1023228940Sdelphij#define ADIF_READ_AHEAD     0x10
1024228940Sdelphij#define ADIF_SPIN_UP_MODE   0x20
1025228940Sdelphij
1026228940Sdelphijtypedef struct _ALTERABLE_ARRAY_INFO {
1027228940Sdelphij	HPT_U32   ValidFields;              /* mark valid fields below */
1028228940Sdelphij	HPT_U8  Name[MAX_ARRAYNAME_LEN];    /* array name */
1029228940Sdelphij	HPT_U8  Description[64];            /* array description */
1030228940Sdelphij}__attribute__((packed))ALTERABLE_ARRAY_INFO, *PALTERABLE_ARRAY_INFO;
1031228940Sdelphij
1032228940Sdelphijtypedef struct _ALTERABLE_DEVICE_INFO {
1033228940Sdelphij	HPT_U32   ValidFields;              /* mark valid fields below */
1034228940Sdelphij	HPT_U8   DeviceModeSetting;         /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
1035228940Sdelphij}__attribute__((packed))ALTERABLE_DEVICE_INFO, *PALTERABLE_DEVICE_INFO;
1036228940Sdelphij
1037228940Sdelphijtypedef struct _ALTERABLE_DEVICE_INFO_V2 {
1038228940Sdelphij	HPT_U32   ValidFields;              /* mark valid fields below */
1039228940Sdelphij	HPT_U8   DeviceModeSetting;         /* 0-4 PIO 0-4, 5-7 MW DMA0-2, 8-13 UDMA0-5 */
1040228940Sdelphij	HPT_U8   TCQEnabled;
1041228940Sdelphij	HPT_U8   NCQEnabled;
1042228940Sdelphij	HPT_U8   WriteCacheEnabled;
1043228940Sdelphij	HPT_U8   ReadAheadEnabled;
1044228940Sdelphij	HPT_U8   SpinUpMode;
1045228940Sdelphij	HPT_U8   reserve[2];
1046228940Sdelphij	HPT_U32  reserve2[13]; /* pad to 64 bytes */
1047228940Sdelphij}__attribute__((packed))ALTERABLE_DEVICE_INFO_V2, *PALTERABLE_DEVICE_INFO_V2;
1048228940Sdelphij
1049228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
1050228940Sdelphij
1051228940Sdelphij#define TARGET_TYPE_DEVICE  0
1052228940Sdelphij#define TARGET_TYPE_ARRAY   1
1053228940Sdelphij
1054228940Sdelphij
1055228940Sdelphij#define AIT_NAME            0
1056228940Sdelphij#define AIT_DESCRIPTION     1
1057228940Sdelphij#define AIT_CACHE_POLICY    2
1058228940Sdelphij
1059228940Sdelphij
1060228940Sdelphij#define DIT_MODE        0
1061228940Sdelphij#define DIT_READ_AHEAD  1
1062228940Sdelphij#define DIT_WRITE_CACHE 2
1063228940Sdelphij#define DIT_TCQ         3
1064228940Sdelphij#define DIT_NCQ         4
1065228940Sdelphij#define DIT_IDENTIFY    5
1066228940Sdelphij
1067228940Sdelphij/* param type is determined by target_type and info_type*/
1068228940Sdelphijtypedef struct _SET_DEV_INFO
1069228940Sdelphij{
1070228940Sdelphij	HPT_U8 target_type;
1071228940Sdelphij	HPT_U8 infor_type;
1072228940Sdelphij	HPT_U16 param_length;
1073228940Sdelphij	#define SET_VDEV_INFO_param(p) ((HPT_U8 *)(p)+sizeof(SET_VDEV_INFO))
1074228940Sdelphij	/* HPT_U8 param[0]; */
1075228940Sdelphij} SET_VDEV_INFO, * PSET_VDEV_INFO;
1076228940Sdelphij
1077228940Sdelphijtypedef HPT_U8 PARAM_ARRAY_NAME[MAX_ARRAYNAME_LEN] ;
1078228940Sdelphijtypedef HPT_U8 PARAM_ARRAY_DES[64];
1079228940Sdelphijtypedef HPT_U8 PARAM_DEVICE_MODE, PARAM_TCQ, PARAM_NCQ, PARAM_READ_AHEAD, PARAM_WRITE_CACHE, PARAM_CACHE_POLICY;
1080228940Sdelphij
1081228940Sdelphij#endif
1082228940Sdelphij
1083228940Sdelphij/*
1084228940Sdelphij * CREATE_ARRAY_PARAMS
1085228940Sdelphij *  Param structure used to create an array.
1086228940Sdelphij */
1087228940Sdelphijtypedef struct _CREATE_ARRAY_PARAMS {
1088228940Sdelphij	HPT_U8 ArrayType;                   /* 1-level array type */
1089228940Sdelphij	HPT_U8 nDisk;                       /* number of elements in Members[] array */
1090228940Sdelphij	HPT_U8 BlockSizeShift;              /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1091228940Sdelphij	HPT_U8 CreateFlags;                 /* See CAF_xxx */
1092228940Sdelphij
1093228940Sdelphij	HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1094228940Sdelphij	HPT_U8      Description[64];        /* array description */
1095228940Sdelphij	HPT_U8      CreateManager[16];      /* who created it */
1096228940Sdelphij	TIME_RECORD CreateTime;             /* when created it */
1097228940Sdelphij
1098228940Sdelphij	HPT_U32 Members[MAX_ARRAY_MEMBERS_V1];/* ID of array members, a member can be an array */
1099228940Sdelphij
1100228940Sdelphij} CREATE_ARRAY_PARAMS, *PCREATE_ARRAY_PARAMS;
1101228940Sdelphij
1102228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
1103228940Sdelphijtypedef struct _CREATE_ARRAY_PARAMS_V2 {
1104228940Sdelphij	HPT_U8 ArrayType;                   /* 1-level array type */
1105228940Sdelphij	HPT_U8 nDisk;                       /* number of elements in Members[] array */
1106228940Sdelphij	HPT_U8 BlockSizeShift;              /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1107228940Sdelphij	HPT_U8 CreateFlags;                 /* See CAF_xxx */
1108228940Sdelphij
1109228940Sdelphij	HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1110228940Sdelphij	HPT_U8 Description[64];             /* array description */
1111228940Sdelphij	HPT_U8 CreateManager[16];           /* who created it */
1112228940Sdelphij	TIME_RECORD CreateTime;             /* when created it */
1113228940Sdelphij	HPT_U64 Capacity;
1114228940Sdelphij
1115228940Sdelphij	HPT_U32 Members[MAX_ARRAY_MEMBERS_V2];/* ID of array members, a member can be an array */
1116228940Sdelphij
1117228940Sdelphij} CREATE_ARRAY_PARAMS_V2, *PCREATE_ARRAY_PARAMS_V2;
1118228940Sdelphij#endif
1119228940Sdelphij
1120228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001
1121228940Sdelphijtypedef struct _CREATE_ARRAY_PARAMS_V3 {
1122228940Sdelphij	HPT_U32  dwSize;
1123228940Sdelphij	HPT_U8 revision;			/*CREATE_ARRAY_PARAMS_V3_REVISION*/
1124228940Sdelphij	HPT_U8 reserved[5];
1125228940Sdelphij	HPT_U8 subDisks;            /* RAIDn0 sub array */
1126228940Sdelphij	HPT_U8 SectorSizeShift;     /*sector size = 512B<<SectorSizeShift*/
1127228940Sdelphij	HPT_U8 ArrayType;                   /* 1-level array type */
1128228940Sdelphij	HPT_U8 nDisk;                       /* number of elements in Members[] array */
1129228940Sdelphij	HPT_U8 BlockSizeShift;              /* Stripe size if ArrayType==AT_RAID0 / AT_RAID5 */
1130228940Sdelphij	HPT_U8 CreateFlags;                 /* See CAF_xxx */
1131228940Sdelphij
1132228940Sdelphij	HPT_U8 ArrayName[MAX_ARRAYNAME_LEN];/* Array name */
1133228940Sdelphij	HPT_U8 Description[64];     /* array description */
1134228940Sdelphij	HPT_U8 CreateManager[16];       /* who created it */
1135228940Sdelphij	TIME_RECORD CreateTime;             /* when created it */
1136228940Sdelphij	HPT_U64 Capacity;
1137228940Sdelphij
1138228940Sdelphij	HPT_U32 Members[MAX_ARRAY_MEMBERS_V3];/* ID of array members, a member can be an array */
1139228940Sdelphij} CREATE_ARRAY_PARAMS_V3, *PCREATE_ARRAY_PARAMS_V3;
1140228940Sdelphij
1141228940Sdelphij/*CREATE_ARRAY_PARAMS_V3 current max revision*/
1142228940Sdelphij#define CREATE_ARRAY_PARAMS_V3_REVISION 0
1143228940Sdelphij/*If new revision defined please check evey revision size*/
1144228940Sdelphij#define CREATE_ARRAY_PARAMS_V3_R0_SIZE (sizeof(CREATE_ARRAY_PARAMS_V3))
1145228940Sdelphij#endif
1146228940Sdelphij
1147228940Sdelphij#if HPT_INTERFACE_VERSION < 0x01020000
1148228940Sdelphij/*
1149228940Sdelphij * Flags used for creating an RAID 1 array
1150228940Sdelphij *
1151228940Sdelphij * CAF_CREATE_AND_DUPLICATE
1152228940Sdelphij *    Copy source disk contents to target for RAID 1. If user choose "create and duplicate"
1153228940Sdelphij *    to create an array, GUI will call CreateArray() with this flag set. Then GUI should
1154228940Sdelphij *    call hpt_get_device_info() with the returned array ID and check returned flags to
1155228940Sdelphij *    see if ARRAY_FLAG_REBUILDING is set. If not set, driver does not support rebuilding
1156228940Sdelphij *    and GUI must do duplication itself.
1157228940Sdelphij * CAF_DUPLICATE_MUST_DONE
1158228940Sdelphij *    If the duplication is aborted or fails, do not create the array.
1159228940Sdelphij */
1160228940Sdelphij#define CAF_CREATE_AND_DUPLICATE 1
1161228940Sdelphij#define CAF_DUPLICATE_MUST_DONE  2
1162228940Sdelphij#define CAF_CREATE_AS_RAID15     4
1163228940Sdelphij/*
1164228940Sdelphij * Flags used for creating an RAID 5 array
1165228940Sdelphij */
1166228940Sdelphij#define CAF_CREATE_R5_NO_BUILD     1
1167228940Sdelphij#define CAF_CREATE_R5_ZERO_INIT    2
1168228940Sdelphij#define CAF_CREATE_R5_BUILD_PARITY 4
1169228940Sdelphij
1170228940Sdelphij#else
1171228940Sdelphij/*
1172228940Sdelphij * Flags used for creating
1173228940Sdelphij */
1174228940Sdelphij#define CAF_FOREGROUND_INITIALIZE   1
1175228940Sdelphij#define CAF_BACKGROUND_INITIALIZE   2
1176228940Sdelphij#define CAF_CREATE_R5_WRITE_BACK    (CACHE_POLICY_WRITE_BACK<<CAF_CACHE_POLICY_SHIFT)
1177228940Sdelphij
1178228940Sdelphij
1179228940Sdelphij#define CAF_CACHE_POLICY_MASK       0x1C
1180228940Sdelphij#define CAF_CACHE_POLICY_SHIFT      2
1181228940Sdelphij
1182228940Sdelphij#endif
1183228940Sdelphij
1184228940Sdelphij#define CAF_KEEP_DATA_ALWAYS     0x80
1185228940Sdelphij
1186228940Sdelphij/* Flags used for deleting an array
1187228940Sdelphij *
1188228940Sdelphij * DAF_KEEP_DATA_IF_POSSIBLE
1189228940Sdelphij *    If this flag is set, deleting a RAID 1 array will not destroy the data on both disks.
1190228940Sdelphij *    Deleting a JBOD should keep partitions on first disk ( not implement now ).
1191228940Sdelphij *    Deleting a RAID 0/1 should result as two RAID 0 array ( not implement now ).
1192228940Sdelphij */
1193228940Sdelphij#define DAF_KEEP_DATA_IF_POSSIBLE 1
1194228940Sdelphij#define DAF_KEEP_DATA_ALWAYS      2
1195228940Sdelphij
1196228940Sdelphij/*
1197228940Sdelphij * event types
1198228940Sdelphij */
1199228940Sdelphij#define ET_DEVICE_REMOVED   1   /* device removed */
1200228940Sdelphij#define ET_DEVICE_PLUGGED   2   /* device plugged */
1201228940Sdelphij#define ET_DEVICE_ERROR     3   /* device I/O error */
1202228940Sdelphij#define ET_REBUILD_STARTED  4
1203228940Sdelphij#define ET_REBUILD_ABORTED  5
1204228940Sdelphij#define ET_REBUILD_FINISHED 6
1205228940Sdelphij#define ET_SPARE_TOOK_OVER  7
1206228940Sdelphij#define ET_REBUILD_FAILED   8
1207228940Sdelphij#define ET_VERIFY_STARTED   9
1208228940Sdelphij#define ET_VERIFY_ABORTED   10
1209228940Sdelphij#define ET_VERIFY_FAILED    11
1210228940Sdelphij#define ET_VERIFY_FINISHED  12
1211228940Sdelphij#define ET_INITIALIZE_STARTED   13
1212228940Sdelphij#define ET_INITIALIZE_ABORTED   14
1213228940Sdelphij#define ET_INITIALIZE_FAILED    15
1214228940Sdelphij#define ET_INITIALIZE_FINISHED  16
1215228940Sdelphij#define ET_VERIFY_DATA_ERROR    17
1216228940Sdelphij#define ET_TRANSFORM_STARTED    18
1217228940Sdelphij#define ET_TRANSFORM_ABORTED    19
1218228940Sdelphij#define ET_TRANSFORM_FAILED     20
1219228940Sdelphij#define ET_TRANSFORM_FINISHED   21
1220228940Sdelphij#define ET_SMART_FAILED         22
1221228940Sdelphij#define ET_SMART_PASSED         23
1222228940Sdelphij#define ET_SECTOR_REPAIR_FAIL     24
1223228940Sdelphij#define ET_SECTOR_REPAIR_SUCCESS  25
1224228940Sdelphij#define ET_ERASE_FAIL		26
1225228940Sdelphij#define ET_ERASE_SUCCESS	27
1226228940Sdelphij#define ET_CONTINUE_REBUILD_ON_ERROR 28
1227228940Sdelphij
1228228940Sdelphij
1229228940Sdelphij/*
1230228940Sdelphij * event structure
1231228940Sdelphij */
1232228940Sdelphijtypedef struct _HPT_EVENT {
1233228940Sdelphij	TIME_RECORD Time;
1234228940Sdelphij	DEVICEID    DeviceID;
1235228940Sdelphij	HPT_U8       EventType;
1236228940Sdelphij	HPT_U8      reserved[3];
1237228940Sdelphij
1238228940Sdelphij	HPT_U8      Data[32]; /* various data depend on EventType */
1239228940Sdelphij} HPT_EVENT, *PHPT_EVENT;
1240228940Sdelphij
1241228940Sdelphij/*
1242228940Sdelphij * IDE pass-through command. Use it at your own risk!
1243228940Sdelphij */
1244228940Sdelphijtypedef struct _IDE_PASS_THROUGH_HEADER {
1245228940Sdelphij	DEVICEID idDisk;             /* disk ID */
1246228940Sdelphij	HPT_U8     bFeaturesReg;     /* feature register */
1247228940Sdelphij	HPT_U8     bSectorCountReg;  /* IDE sector count register. */
1248228940Sdelphij	HPT_U8     bLbaLowReg;       /* IDE LBA low value. */
1249228940Sdelphij	HPT_U8     bLbaMidReg;       /* IDE LBA mid register. */
1250228940Sdelphij	HPT_U8     bLbaHighReg;      /* IDE LBA high value. */
1251228940Sdelphij	HPT_U8     bDriveHeadReg;    /* IDE drive/head register. */
1252228940Sdelphij	HPT_U8     bCommandReg;      /* Actual IDE command. Checked for validity by driver. */
1253228940Sdelphij	HPT_U8     nSectors;         /* data size in sectors, if the command has data transfer */
1254228940Sdelphij	HPT_U8     protocol;         /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
1255228940Sdelphij	HPT_U8     reserve[3];
1256228940Sdelphij	#define IDE_PASS_THROUGH_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER))
1257228940Sdelphij	/* HPT_U8     DataBuffer[0]; */
1258228940Sdelphij}
1259228940SdelphijIDE_PASS_THROUGH_HEADER, *PIDE_PASS_THROUGH_HEADER;
1260228940Sdelphij
1261228940Sdelphijtypedef struct _IDE_PASS_THROUGH_HEADER_V2 {
1262228940Sdelphij	DEVICEID idDisk;             /* disk ID */
1263228940Sdelphij	HPT_U16    bFeaturesReg;     /* feature register */
1264228940Sdelphij	HPT_U16    bSectorCountReg;  /* IDE sector count register. */
1265228940Sdelphij	HPT_U16    bLbaLowReg;       /* IDE LBA low value. */
1266228940Sdelphij	HPT_U16    bLbaMidReg;       /* IDE LBA mid register. */
1267228940Sdelphij	HPT_U16    bLbaHighReg;      /* IDE LBA high value. */
1268228940Sdelphij	HPT_U8     bDriveHeadReg;    /* IDE drive/head register. */
1269228940Sdelphij	HPT_U8     bCommandReg;      /* Actual IDE command. Checked for validity by driver. */
1270228940Sdelphij	HPT_U16    nSectors;         /* data size in sectors, if the command has data transfer */
1271228940Sdelphij	HPT_U8     protocol;         /* IO_COMMAND_(READ,WRITE) or zero for non-DATA */
1272228940Sdelphij	HPT_U8     reserve;
1273228940Sdelphij	#define IDE_PASS_THROUGH_V2_buffer(p) ((HPT_U8 *)(p) + sizeof(IDE_PASS_THROUGH_HEADER_V2))
1274228940Sdelphij	/* HPT_U8     DataBuffer[0]; */
1275228940Sdelphij}
1276228940SdelphijIDE_PASS_THROUGH_HEADER_V2, *PIDE_PASS_THROUGH_HEADER_V2;
1277228940Sdelphij
1278228940Sdelphijtypedef struct _HPT_SCSI_PASSTHROUGH_IN {
1279228940Sdelphij	DEVICEID idDisk;
1280228940Sdelphij	HPT_U8   protocol;
1281228940Sdelphij	HPT_U8   reserve1;
1282228940Sdelphij	HPT_U8   reserve2;
1283228940Sdelphij	HPT_U8   cdbLength;
1284228940Sdelphij	HPT_U8   cdb[16];
1285228940Sdelphij	HPT_U32  dataLength;
1286228940Sdelphij	/* data follows, if any */
1287228940Sdelphij}
1288228940SdelphijHPT_SCSI_PASSTHROUGH_IN, *PHPT_SCSI_PASSTHROUGH_IN;
1289228940Sdelphij
1290228940Sdelphijtypedef struct _HPT_SCSI_PASSTHROUGH_OUT {
1291228940Sdelphij	HPT_U8   scsiStatus;
1292228940Sdelphij	HPT_U8   reserve1;
1293228940Sdelphij	HPT_U8   reserve2;
1294228940Sdelphij	HPT_U8   reserve3;
1295228940Sdelphij	HPT_U32  dataLength;
1296228940Sdelphij	/* data/sense follows if any */
1297228940Sdelphij}
1298228940SdelphijHPT_SCSI_PASSTHROUGH_OUT, *PHPT_SCSI_PASSTHROUGH_OUT;
1299228940Sdelphij
1300228940Sdelphij/*
1301228940Sdelphij * device io packet format
1302228940Sdelphij */
1303228940Sdelphijtypedef struct _DEVICE_IO_EX_PARAMS {
1304228940Sdelphij	DEVICEID idDisk;
1305228940Sdelphij	HPT_U32    Lba;
1306228940Sdelphij	HPT_U16   nSectors;
1307228940Sdelphij	HPT_U8    Command;    /* IO_COMMAD_xxx */
1308228940Sdelphij	HPT_U8    BufferType; /* BUFFER_TYPE_xxx, see below */
1309228940Sdelphij	HPT_U32    BufferPtr;
1310228940Sdelphij}
1311228940SdelphijDEVICE_IO_EX_PARAMS, *PDEVICE_IO_EX_PARAMS;
1312228940Sdelphij
1313228940Sdelphij#define BUFFER_TYPE_LOGICAL              1 /* logical pointer to buffer */
1314228940Sdelphij#define BUFFER_TYPE_PHYSICAL             2 /* physical address of buffer */
1315228940Sdelphij#define BUFFER_TYPE_LOGICAL_LOGICAL_SG   3 /* logical pointer to logical S/G table */
1316228940Sdelphij#define BUFFER_TYPE_LOGICAL_PHYSICAL_SG  4 /* logical pointer to physical S/G table */
1317228940Sdelphij#define BUFFER_TYPE_PHYSICAL_LOGICAL_SG  5 /* physical address to logical S/G table */
1318228940Sdelphij#define BUFFER_TYPE_PHYSICAL_PHYSICAL_SG 6 /* physical address of physical S/G table */
1319228940Sdelphij#define BUFFER_TYPE_PHYSICAL_PHYSICAL_SG_PIO 7 /* non DMA capable physical address of physical S/G table */
1320228940Sdelphij
1321228940Sdelphijtypedef struct _HPT_DRIVER_PARAMETER {
1322228940Sdelphij	char    name[32];
1323228940Sdelphij	HPT_U8  value[32];
1324228940Sdelphij	HPT_U8  type;        /* HPT_DRIVER_PARAMETER_TYPE_* */
1325228940Sdelphij	HPT_U8  persistent;
1326228940Sdelphij	HPT_U8  reserve2[2];
1327228940Sdelphij	HPT_U8  location;    /* 0 - system */
1328228940Sdelphij	HPT_U8  controller;
1329228940Sdelphij	HPT_U8  bus;
1330228940Sdelphij	HPT_U8  reserve1;
1331228940Sdelphij	char    desc[128];
1332228940Sdelphij}
1333228940SdelphijHPT_DRIVER_PARAMETER, *PHPT_DRIVER_PARAMETER;
1334228940Sdelphij
1335228940Sdelphij#define HPT_DRIVER_PARAMETER_TYPE_INT 1
1336228940Sdelphij#define HPT_DRIVER_PARAMETER_TYPE_BOOL 2
1337228940Sdelphij
1338228940Sdelphijtypedef struct _HPT_PM_CMDSTAT {
1339228940Sdelphij	HPT_U64 timeStamp;
1340228940Sdelphij	HPT_U64 lba;
1341228940Sdelphij	HPT_U16 sectors;
1342228940Sdelphij	HPT_U16 reserved;
1343228940Sdelphij	HPT_U32 rspTime;
1344228940Sdelphij}
1345228940SdelphijHPT_PM_CMDSTAT, *PHPT_PM_CMDSTAT;
1346228940Sdelphij
1347228940Sdelphij#define HIGHEST_RSPTIME_CMD_SAVE 10
1348228940Sdelphij#define RSPTIME_HISTOGRAM_SEGMENT_COUNT 38
1349228940Sdelphij
1350228940Sdelphijtypedef struct _HPT_PM_IOSTAT {
1351228940Sdelphij	HPT_PM_CMDSTAT highestRspCmdStatData[HIGHEST_RSPTIME_CMD_SAVE];
1352228940Sdelphij	HPT_U32 rspTimeHistogram[RSPTIME_HISTOGRAM_SEGMENT_COUNT];
1353228940Sdelphij	HPT_U16 pendingIo;
1354228940Sdelphij	HPT_U16 activeIo;
1355228940Sdelphij	HPT_U32 instantKBPs;
1356228940Sdelphij	HPT_U32 averageKBPs;
1357228940Sdelphij	HPT_U32 instantIOPs;
1358228940Sdelphij	HPT_U32 averageIOPs;
1359228940Sdelphij}
1360228940SdelphijHPT_PM_IOSTAT, *PHPT_PM_IOSTAT;
1361228940Sdelphij
1362228940Sdelphij
1363228940Sdelphij
1364228940Sdelphij/*
1365228940Sdelphij * ioctl structure
1366228940Sdelphij */
1367228940Sdelphij#define HPT_IOCTL_MAGIC32 0x1A2B3C4D
1368228940Sdelphij#define HPT_IOCTL_MAGIC   0xA1B2C3D4
1369228940Sdelphij
1370228940Sdelphijtypedef struct _HPT_IOCTL_PARAM {
1371228940Sdelphij	HPT_U32   Magic;                 /* used to check if it's a valid ioctl packet */
1372228940Sdelphij	HPT_U32   dwIoControlCode;       /* operation control code */
1373228940Sdelphij	HPT_PTR   lpInBuffer;            /* input data buffer */
1374228940Sdelphij	HPT_U32   nInBufferSize;         /* size of input data buffer */
1375228940Sdelphij	HPT_PTR   lpOutBuffer;           /* output data buffer */
1376228940Sdelphij	HPT_U32   nOutBufferSize;        /* size of output data buffer */
1377228940Sdelphij	HPT_PTR   lpBytesReturned;       /* count of HPT_U8s returned */
1378228940Sdelphij}
1379228940SdelphijHPT_IOCTL_PARAM, *PHPT_IOCTL_PARAM;
1380228940Sdelphij
1381228940Sdelphij/* for 32-bit app running on 64-bit system */
1382228940Sdelphijtypedef struct _HPT_IOCTL_PARAM32 {
1383228940Sdelphij	HPT_U32   Magic;
1384228940Sdelphij	HPT_U32   dwIoControlCode;
1385228940Sdelphij	HPT_U32   lpInBuffer;
1386228940Sdelphij	HPT_U32   nInBufferSize;
1387228940Sdelphij	HPT_U32   lpOutBuffer;
1388228940Sdelphij	HPT_U32   nOutBufferSize;
1389228940Sdelphij	HPT_U32   lpBytesReturned;
1390228940Sdelphij}
1391228940SdelphijHPT_IOCTL_PARAM32, *PHPT_IOCTL_PARAM32;
1392228940Sdelphij
1393228940Sdelphij#if !defined(__KERNEL__) || defined(SIMULATE)
1394228940Sdelphij/*
1395228940Sdelphij * User-mode ioctl parameter passing conventions:
1396228940Sdelphij *   The ioctl function implementation is platform specific, so we don't
1397228940Sdelphij * have forced rules for it. However, it's suggested to use a parameter
1398228940Sdelphij * passing method as below
1399228940Sdelphij *   1) Put all input data continuously in an input buffer.
1400228940Sdelphij *   2) Prepare an output buffer with enough size if needed.
1401228940Sdelphij *   3) Fill a HPT_IOCTL_PARAM structure.
1402228940Sdelphij *   4) Pass the structure to driver through a platform-specific method.
1403228940Sdelphij * This is implemented in the mid-layer user-mode library. The UI
1404228940Sdelphij * programmer needn't care about it.
1405228940Sdelphij */
1406228940Sdelphij
1407228940Sdelphij/************************************************************************
1408228940Sdelphij * User mode functions
1409228940Sdelphij ************************************************************************/
1410228940Sdelphij/*
1411228940Sdelphij * hpt_get_version
1412228940Sdelphij * Version compatibility: all versions
1413228940Sdelphij * Parameters:
1414228940Sdelphij *  None
1415228940Sdelphij * Returns:
1416228940Sdelphij *  interface version. 0 when fail.
1417228940Sdelphij */
1418228940SdelphijHPT_U32 hpt_get_version(void);
1419228940Sdelphij
1420228940Sdelphij/*
1421228940Sdelphij * hpt_get_driver_capabilities
1422228940Sdelphij * Version compatibility: v1.0.0.2 or later
1423228940Sdelphij * Parameters:
1424228940Sdelphij *  Pointer to receive a DRIVE_CAPABILITIES structure. The caller must set
1425228940Sdelphij *  dwSize member to sizeof(DRIVER_CAPABILITIES). The callee must check this
1426228940Sdelphij *  member to see if it's correct.
1427228940Sdelphij * Returns:
1428228940Sdelphij *  0 - Success
1429228940Sdelphij */
1430228940Sdelphijint hpt_get_driver_capabilities(PDRIVER_CAPABILITIES cap);
1431228940Sdelphijint hpt_get_driver_capabilities_v2(PDRIVER_CAPABILITIES_V2 cap);
1432228940Sdelphij
1433228940Sdelphij/*
1434228940Sdelphij * hpt_get_controller_count
1435228940Sdelphij * Version compatibility: v1.0.0.1 or later
1436228940Sdelphij * Parameters:
1437228940Sdelphij *  None
1438228940Sdelphij * Returns:
1439228940Sdelphij *  number of controllers
1440228940Sdelphij */
1441228940Sdelphijint hpt_get_controller_count(void);
1442228940Sdelphij
1443228940Sdelphij/* hpt_get_controller_info
1444228940Sdelphij * Version compatibility: v1.0.0.1 or later
1445228940Sdelphij * Parameters:
1446228940Sdelphij *  id      Controller id
1447228940Sdelphij *  pInfo   pointer to CONTROLLER_INFO buffer
1448228940Sdelphij * Returns:
1449228940Sdelphij *  0       Success, controller info is put into (*pInfo ).
1450228940Sdelphij */
1451228940Sdelphijint hpt_get_controller_info(int id, PCONTROLLER_INFO pInfo);
1452228940Sdelphij
1453228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
1454228940Sdelphij/* hpt_get_controller_info_v2
1455228940Sdelphij * Version compatibility: v2.0.0.0 or later
1456228940Sdelphij * Parameters:
1457228940Sdelphij *  id      Controller id
1458228940Sdelphij *  pInfo   pointer to CONTROLLER_INFO_V2 buffer
1459228940Sdelphij * Returns:
1460228940Sdelphij *  0       Success, controller info is put into (*pInfo ).
1461228940Sdelphij */
1462228940Sdelphijint hpt_get_controller_info_v2(int id, PCONTROLLER_INFO_V2 pInfo);
1463228940Sdelphij
1464228940Sdelphij/* hpt_get_controller_info_v3
1465228940Sdelphij * Version compatibility: v2.0.0.0 or later
1466228940Sdelphij * Parameters:
1467228940Sdelphij *  id      Controller id
1468228940Sdelphij *  pInfo   pointer to CONTROLLER_INFO_V3 buffer
1469228940Sdelphij * Returns:
1470228940Sdelphij *  0       Success, controller info is put into (*pInfo ).
1471228940Sdelphij */
1472228940Sdelphijint hpt_get_controller_info_v3(int id, PCONTROLLER_INFO_V3 pInfo);
1473228940Sdelphij#endif
1474228940Sdelphij
1475228940Sdelphij/* hpt_get_channel_info
1476228940Sdelphij * Version compatibility: v1.0.0.1 or later
1477228940Sdelphij * Parameters:
1478228940Sdelphij *  id      Controller id
1479228940Sdelphij *  bus     bus number
1480228940Sdelphij *  pInfo   pointer to CHANNEL_INFO buffer
1481228940Sdelphij * Returns:
1482228940Sdelphij *  0       Success, channel info is put into (*pInfo ).
1483228940Sdelphij */
1484228940Sdelphijint hpt_get_channel_info(int id, int bus, PCHANNEL_INFO pInfo);
1485228940Sdelphij
1486228940Sdelphij/* hpt_get_channel_info_v2
1487228940Sdelphij * Version compatibility: v1.0.0.1 or later
1488228940Sdelphij * Parameters:
1489228940Sdelphij *  id      Controller id
1490228940Sdelphij *  bus     bus number
1491228940Sdelphij *  pInfo   pointer to CHANNEL_INFO buffer
1492228940Sdelphij * Returns:
1493228940Sdelphij *  0       Success, channel info is put into (*pInfo ).
1494228940Sdelphij */
1495228940Sdelphijint hpt_get_channel_info_v2(int id, int bus, PCHANNEL_INFO_V2 pInfo);
1496228940Sdelphij
1497228940Sdelphij/* hpt_get_logical_devices
1498228940Sdelphij * Version compatibility: v1.0.0.1 or later
1499228940Sdelphij * Parameters:
1500228940Sdelphij *  pIds        pointer to a DEVICEID array
1501228940Sdelphij *  nMaxCount   array size
1502228940Sdelphij * Returns:
1503228940Sdelphij *  Number of ID returned. All logical device IDs are put into pIds array.
1504228940Sdelphij *  Note: A spare disk is not a logical device.
1505228940Sdelphij */
1506228940Sdelphijint hpt_get_logical_devices(DEVICEID * pIds, int nMaxCount);
1507228940Sdelphij
1508228940Sdelphij/* hpt_get_physical_devices
1509228940Sdelphij * Version compatibility: v2.1.0.0 or later
1510228940Sdelphij * Parameters:
1511228940Sdelphij *  pIds        pointer to a DEVICEID array
1512228940Sdelphij *  nMaxCount   array size
1513228940Sdelphij * Returns:
1514228940Sdelphij *  Number of ID returned. All physical device IDs are put into pIds array.
1515228940Sdelphij */
1516228940Sdelphijint hpt_get_physical_devices(DEVICEID * pIds, int nMaxCount);
1517228940Sdelphij
1518228940Sdelphij/* hpt_get_device_info
1519228940Sdelphij * Version compatibility: v1.0.0.1 or later
1520228940Sdelphij * Parameters:
1521228940Sdelphij *  id      logical device id
1522228940Sdelphij *  pInfo   pointer to LOGICAL_DEVICE_INFO structure
1523228940Sdelphij * Returns:
1524228940Sdelphij *  0 - Success
1525228940Sdelphij */
1526228940Sdelphijint hpt_get_device_info(DEVICEID id, PLOGICAL_DEVICE_INFO pInfo);
1527228940Sdelphij
1528228940Sdelphij/* hpt_create_array
1529228940Sdelphij * Version compatibility: v1.0.0.1 or later
1530228940Sdelphij * Parameters:
1531228940Sdelphij *  pParam      pointer to CREATE_ARRAY_PARAMS structure
1532228940Sdelphij * Returns:
1533228940Sdelphij *  0   failed
1534228940Sdelphij *  else return array id
1535228940Sdelphij */
1536228940SdelphijDEVICEID hpt_create_array(PCREATE_ARRAY_PARAMS pParam);
1537228940Sdelphij
1538228940Sdelphij/* hpt_delete_array
1539228940Sdelphij * Version compatibility: v1.0.0.1 or later
1540228940Sdelphij * Parameters:
1541228940Sdelphij *  id      array id
1542228940Sdelphij * Returns:
1543228940Sdelphij *  0   Success
1544228940Sdelphij */
1545228940Sdelphijint hpt_delete_array(DEVICEID id, HPT_U32 options);
1546228940Sdelphij
1547228940Sdelphij/* hpt_device_io
1548228940Sdelphij *  Read/write data on array and physcal device.
1549228940Sdelphij * Version compatibility: v1.0.0.1 or later
1550228940Sdelphij * Parameters:
1551228940Sdelphij *  id      device id. If it's an array ID, IO will be performed on the array.
1552228940Sdelphij *          If it's a physical device ID, IO will be performed on the device.
1553228940Sdelphij *  cmd     IO_COMMAND_READ or IO_COMMAND_WRITE
1554228940Sdelphij *  buffer  data buffer
1555228940Sdelphij *  length  data size
1556228940Sdelphij * Returns:
1557228940Sdelphij *  0   Success
1558228940Sdelphij */
1559228940Sdelphijint hpt_device_io(DEVICEID id, int cmd, HPT_U32 lba, HPT_U32 nSector, void * buffer);
1560228940Sdelphij
1561228940Sdelphij/* hpt_add_disk_to_array
1562228940Sdelphij *   Used to dynamicly add a disk to an RAID1, RAID0/1, RAID1/0 or RAID5 array.
1563228940Sdelphij *   Auto-rebuild will start.
1564228940Sdelphij * Version compatibility: v1.0.0.1 or later
1565228940Sdelphij * Parameters:
1566228940Sdelphij *  idArray     array id
1567228940Sdelphij *  idDisk      disk id
1568228940Sdelphij * Returns:
1569228940Sdelphij *  0   Success
1570228940Sdelphij */
1571228940Sdelphijint hpt_add_disk_to_array(DEVICEID idArray, DEVICEID idDisk);
1572228940Sdelphij
1573228940Sdelphij/* hpt_add_spare_disk
1574228940Sdelphij * Version compatibility: v1.0.0.1 or later
1575228940Sdelphij *   Add a disk to spare pool.
1576228940Sdelphij * Parameters:
1577228940Sdelphij *  idDisk      disk id
1578228940Sdelphij * Returns:
1579228940Sdelphij *  0   Success
1580228940Sdelphij */
1581228940Sdelphijint hpt_add_spare_disk(DEVICEID idDisk);
1582228940Sdelphij
1583228940Sdelphij/* hpt_add_dedicated_spare
1584228940Sdelphij * Version compatibility: v1.0.0.3 or later
1585228940Sdelphij *   Add a spare disk to an array
1586228940Sdelphij * Parameters:
1587228940Sdelphij *  idDisk      disk id
1588228940Sdelphij *  idArray     array id
1589228940Sdelphij * Returns:
1590228940Sdelphij *  0   Success
1591228940Sdelphij */
1592228940Sdelphijint hpt_add_dedicated_spare(DEVICEID idDisk, DEVICEID idArray);
1593228940Sdelphij
1594228940Sdelphij/* hpt_remove_spare_disk
1595228940Sdelphij *   remove a disk from spare pool.
1596228940Sdelphij * Version compatibility: v1.0.0.1 or later
1597228940Sdelphij * Parameters:
1598228940Sdelphij *  idDisk      disk id
1599228940Sdelphij * Returns:
1600228940Sdelphij *  0   Success
1601228940Sdelphij */
1602228940Sdelphijint hpt_remove_spare_disk(DEVICEID idDisk);
1603228940Sdelphij
1604228940Sdelphij/* hpt_get_event
1605228940Sdelphij *   Used to poll events from driver.
1606228940Sdelphij * Version compatibility: v1.0.0.1 or later
1607228940Sdelphij * Parameters:
1608228940Sdelphij *   pEvent    pointer to HPT_EVENT structure
1609228940Sdelphij * Returns:
1610228940Sdelphij *  0   Success, event info is filled in *pEvent
1611228940Sdelphij */
1612228940Sdelphijint hpt_get_event(PHPT_EVENT pEvent);
1613228940Sdelphij
1614228940Sdelphij/* hpt_rebuild_data_block
1615228940Sdelphij *   Used to copy data from source disk and mirror disk.
1616228940Sdelphij * Version compatibility: v1.0.0.1 or later
1617228940Sdelphij * Parameters:
1618228940Sdelphij *   idArray        Array ID (RAID1, 0/1 or RAID5)
1619228940Sdelphij *   Lba            Start LBA for each array member
1620228940Sdelphij *   nSector        Number of sectors for each array member (RAID 5 will ignore this parameter)
1621228940Sdelphij *
1622228940Sdelphij * Returns:
1623228940Sdelphij *  0   Success, event info is filled in *pEvent
1624228940Sdelphij */
1625228940Sdelphijint hpt_rebuild_data_block(DEVICEID idMirror, HPT_U32 Lba, HPT_U8 nSector);
1626228940Sdelphij#define hpt_rebuild_mirror(p1, p2, p3) hpt_rebuild_data_block(p1, p2, p3)
1627228940Sdelphij
1628228940Sdelphij/* hpt_set_array_state
1629228940Sdelphij *   set array state.
1630228940Sdelphij * Version compatibility: v1.0.0.1 or later
1631228940Sdelphij * Parameters:
1632228940Sdelphij *   idArray        Array ID
1633228940Sdelphij *   state          See above 'array states' constants, possible values are:
1634228940Sdelphij *     MIRROR_REBUILD_START
1635228940Sdelphij *        Indicate that GUI wants to rebuild a mirror array
1636228940Sdelphij *     MIRROR_REBUILD_ABORT
1637228940Sdelphij *        GUI wants to abort rebuilding an array
1638228940Sdelphij *     MIRROR_REBUILD_COMPLETE
1639228940Sdelphij *        GUI finished to rebuild an array. If rebuild is done by driver this
1640228940Sdelphij *        state has no use
1641228940Sdelphij *
1642228940Sdelphij * Returns:
1643228940Sdelphij *  0   Success
1644228940Sdelphij */
1645228940Sdelphijint hpt_set_array_state(DEVICEID idArray, HPT_U32 state);
1646228940Sdelphij
1647228940Sdelphij/* hpt_set_array_info
1648228940Sdelphij *   set array info.
1649228940Sdelphij * Version compatibility: v1.0.0.1 or later
1650228940Sdelphij * Parameters:
1651228940Sdelphij *   idArray        Array ID
1652228940Sdelphij *   pInfo          pointer to new info
1653228940Sdelphij *
1654228940Sdelphij * Returns:
1655228940Sdelphij *  0   Success
1656228940Sdelphij */
1657228940Sdelphijint hpt_set_array_info(DEVICEID idArray, PALTERABLE_ARRAY_INFO pInfo);
1658228940Sdelphij
1659228940Sdelphij/* hpt_set_device_info
1660228940Sdelphij *   set device info.
1661228940Sdelphij * Version compatibility: v1.0.0.1 or later
1662228940Sdelphij * Parameters:
1663228940Sdelphij *   idDisk         device ID
1664228940Sdelphij *   pInfo          pointer to new info
1665228940Sdelphij *
1666228940Sdelphij * Returns:
1667228940Sdelphij *  0   Success
1668228940Sdelphij * Additional notes:
1669228940Sdelphij *  If idDisk==0, call to this function will stop buzzer on the adapter
1670228940Sdelphij *  (if supported by driver).
1671228940Sdelphij */
1672228940Sdelphijint hpt_set_device_info(DEVICEID idDisk, PALTERABLE_DEVICE_INFO pInfo);
1673228940Sdelphij
1674228940Sdelphij#if HPT_INTERFACE_VERSION >= 0x01000004
1675228940Sdelphijint hpt_set_device_info_v2(DEVICEID idDisk, PALTERABLE_DEVICE_INFO_V2 pInfo);
1676228940Sdelphij#endif
1677228940Sdelphij
1678228940Sdelphij/* hpt_rescan_devices
1679228940Sdelphij *   rescan devices
1680228940Sdelphij * Version compatibility: v1.0.0.1 or later
1681228940Sdelphij * Parameters:
1682228940Sdelphij *   None
1683228940Sdelphij * Returns:
1684228940Sdelphij *   0  Success
1685228940Sdelphij */
1686228940Sdelphijint hpt_rescan_devices(void);
1687228940Sdelphij
1688228940Sdelphij/* hpt_get_601_info
1689228940Sdelphij *   Get HPT601 status
1690228940Sdelphij * Version compatibiilty: v1.0.0.3 or later
1691228940Sdelphij * Parameters:
1692228940Sdelphij *   idDisk - Disk handle
1693228940Sdelphij *   PHPT601_INFO - pointer to HPT601 info buffer
1694228940Sdelphij * Returns:
1695228940Sdelphij *   0  Success
1696228940Sdelphij */
1697228940Sdelphijint hpt_get_601_info(DEVICEID idDisk, PHPT601_INFO pInfo);
1698228940Sdelphij
1699228940Sdelphij/* hpt_set_601_info
1700228940Sdelphij *   HPT601 function control
1701228940Sdelphij * Version compatibiilty: v1.0.0.3 or later
1702228940Sdelphij * Parameters:
1703228940Sdelphij *   idDisk - Disk handle
1704228940Sdelphij *   PHPT601_INFO - pointer to HPT601 info buffer
1705228940Sdelphij * Returns:
1706228940Sdelphij *   0  Success
1707228940Sdelphij */
1708228940Sdelphijint hpt_set_601_info(DEVICEID idDisk, PHPT601_INFO pInfo);
1709228940Sdelphij
1710228940Sdelphij/* hpt_lock_device
1711228940Sdelphij *   Lock a block on a device (prevent OS accessing it)
1712228940Sdelphij * Version compatibiilty: v1.0.0.3 or later
1713228940Sdelphij * Parameters:
1714228940Sdelphij *   idDisk - Disk handle
1715228940Sdelphij *   Lba - Start LBA
1716228940Sdelphij *   nSectors - number of sectors
1717228940Sdelphij * Returns:
1718228940Sdelphij *   0  Success
1719228940Sdelphij */
1720228940Sdelphijint hpt_lock_device(DEVICEID idDisk, HPT_U32 Lba, HPT_U8 nSectors);
1721228940Sdelphij
1722228940Sdelphij/* hpt_lock_device
1723228940Sdelphij *   Unlock a device
1724228940Sdelphij * Version compatibiilty: v1.0.0.3 or later
1725228940Sdelphij * Parameters:
1726228940Sdelphij *   idDisk - Disk handle
1727228940Sdelphij * Returns:
1728228940Sdelphij *   0  Success
1729228940Sdelphij */
1730228940Sdelphijint hpt_unlock_device(DEVICEID idDisk);
1731228940Sdelphij
1732228940Sdelphij/* hpt_ide_pass_through
1733228940Sdelphij *  send a ATA passthrough command to a device.
1734228940Sdelphij * Version compatibility: v1.0.0.3 or later
1735228940Sdelphij * Parameters:
1736228940Sdelphij *   p - IDE_PASS_THROUGH header pointer
1737228940Sdelphij * Returns:
1738228940Sdelphij *   0  Success
1739228940Sdelphij */
1740228940Sdelphijint hpt_ide_pass_through(PIDE_PASS_THROUGH_HEADER p);
1741228940Sdelphijint hpt_ide_pass_through_v2(PIDE_PASS_THROUGH_HEADER_V2 p);
1742228940Sdelphij
1743228940Sdelphij/* hpt_scsi_passthrough
1744228940Sdelphij *  send a SCSI passthrough command to a device.
1745228940Sdelphij * Version compatibility: v2.0.0.0 or later
1746228940Sdelphij * Parameters:
1747228940Sdelphij *   in  - HPT_SCSI_PASSTHROUGH_IN header pointer
1748228940Sdelphij *   out - PHPT_SCSI_PASSTHROUGH_OUT header pointer
1749228940Sdelphij *   insize, outsize - in/out buffer size
1750228940Sdelphij * Returns:
1751228940Sdelphij *   0  Success
1752228940Sdelphij */
1753228940Sdelphijint hpt_scsi_passthrough(PHPT_SCSI_PASSTHROUGH_IN in, HPT_U32 insize,
1754228940Sdelphij				PHPT_SCSI_PASSTHROUGH_OUT out, HPT_U32 outsize);
1755228940Sdelphij
1756228940Sdelphij/* hpt_verify_data_block
1757228940Sdelphij *   verify data block on RAID1 or RAID5.
1758228940Sdelphij * Version compatibility: v1.0.0.3 or later
1759228940Sdelphij * Parameters:
1760228940Sdelphij *   idArray - Array ID
1761228940Sdelphij *   Lba - block number (on each array member, not logical block!)
1762228940Sdelphij *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
1763228940Sdelphij * Returns:
1764228940Sdelphij *   0  Success
1765228940Sdelphij *   1  Data compare error
1766228940Sdelphij *   2  I/O error
1767228940Sdelphij */
1768228940Sdelphijint hpt_verify_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
1769228940Sdelphij
1770228940Sdelphij/* hpt_initialize_data_block
1771228940Sdelphij *   initialize data block (fill with zero) on RAID5
1772228940Sdelphij * Version compatibility: v1.0.0.3 or later
1773228940Sdelphij * Parameters:
1774228940Sdelphij *   idArray - Array ID
1775228940Sdelphij *   Lba - block number (on each array member, not logical block!)
1776228940Sdelphij *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
1777228940Sdelphij * Returns:
1778228940Sdelphij *   0  Success
1779228940Sdelphij */
1780228940Sdelphijint hpt_initialize_data_block(DEVICEID idArray, HPT_U32 Lba, HPT_U8 nSectors);
1781228940Sdelphij
1782228940Sdelphij/* hpt_device_io_ex
1783228940Sdelphij *   extended device I/O function
1784228940Sdelphij * Version compatibility: v1.0.0.3 or later
1785228940Sdelphij * Parameters:
1786228940Sdelphij *   idArray - Array ID
1787228940Sdelphij *   Lba - block number (on each array member, not logical block!)
1788228940Sdelphij *   nSectors - Sectors for each member
1789228940Sdelphij *   buffer - I/O buffer or s/g address
1790228940Sdelphij * Returns:
1791228940Sdelphij *   0  Success
1792228940Sdelphij */
1793228940Sdelphijint hpt_device_io_ex(PDEVICE_IO_EX_PARAMS param);
1794228940Sdelphij
1795228940Sdelphij/* hpt_set_boot_mark
1796228940Sdelphij *   select boot device
1797228940Sdelphij * Version compatibility: v1.0.0.3 or later
1798228940Sdelphij * Parameters:
1799228940Sdelphij *   id - logical device ID. If id is 0 the boot mark will be removed.
1800228940Sdelphij * Returns:
1801228940Sdelphij *   0  Success
1802228940Sdelphij */
1803228940Sdelphijint hpt_set_boot_mark(DEVICEID id);
1804228940Sdelphij
1805228940Sdelphij/* hpt_query_remove
1806228940Sdelphij *  check if device can be removed safely
1807228940Sdelphij * Version compatibility: v1.0.0.4 or later
1808228940Sdelphij * Parameters:
1809228940Sdelphij *  ndev - number of devices
1810228940Sdelphij *  pIds - device ID list
1811228940Sdelphij * Returns:
1812228940Sdelphij *  0  - Success
1813228940Sdelphij *  -1 - unknown error
1814228940Sdelphij *  n  - the n-th device that can't be removed
1815228940Sdelphij */
1816228940Sdelphijint hpt_query_remove(HPT_U32 ndev, DEVICEID *pIds);
1817228940Sdelphij
1818228940Sdelphij/* hpt_remove_devices
1819228940Sdelphij *  remove a list of devices
1820228940Sdelphij * Version compatibility: v1.0.0.4 or later
1821228940Sdelphij * Parameters:
1822228940Sdelphij *  ndev - number of devices
1823228940Sdelphij *  pIds - device ID list
1824228940Sdelphij * Returns:
1825228940Sdelphij *  0  - Success
1826228940Sdelphij *  -1 - unknown error
1827228940Sdelphij *  n  - the n-th device that can't be removed
1828228940Sdelphij */
1829228940Sdelphijint hpt_remove_devices(HPT_U32 ndev, DEVICEID *pIds);
1830228940Sdelphij
1831228940Sdelphij/* hpt_create_array_v2
1832228940Sdelphij * Version compatibility: v1.1.0.0 or later
1833228940Sdelphij * Parameters:
1834228940Sdelphij *  pParam      pointer to CREATE_ARRAY_PARAMS_V2 structure
1835228940Sdelphij * Returns:
1836228940Sdelphij *  0   failed
1837228940Sdelphij *  else return array id
1838228940Sdelphij */
1839228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
1840228940SdelphijDEVICEID hpt_create_array_v2(PCREATE_ARRAY_PARAMS_V2 pParam);
1841228940Sdelphij#endif
1842228940Sdelphij
1843228940Sdelphij/* hpt_create_array_v3
1844228940Sdelphij * Version compatibility: v2.0.0.1 or later
1845228940Sdelphij * Parameters:
1846228940Sdelphij *  pParam      pointer to CREATE_ARRAY_PARAMS_V3 structure
1847228940Sdelphij * Returns:
1848228940Sdelphij *  0   failed
1849228940Sdelphij *  else return array id
1850228940Sdelphij */
1851228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001
1852228940SdelphijDEVICEID hpt_create_array_v3(PCREATE_ARRAY_PARAMS_V3 pParam);
1853228940Sdelphij#endif
1854228940Sdelphij
1855228940Sdelphij/* hpt_get_device_info_v2
1856228940Sdelphij * Version compatibility: v1.1.0.0 or later
1857228940Sdelphij * Parameters:
1858228940Sdelphij *  id      logical device id
1859228940Sdelphij *  pInfo   pointer to LOGICAL_DEVICE_INFO_V2 structure
1860228940Sdelphij * Returns:
1861228940Sdelphij *  0 - Success
1862228940Sdelphij */
1863228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
1864228940Sdelphijint hpt_get_device_info_v2(DEVICEID id, PLOGICAL_DEVICE_INFO_V2 pInfo);
1865228940Sdelphij#endif
1866228940Sdelphij
1867228940Sdelphij/* hpt_get_device_info_v3
1868228940Sdelphij * Version compatibility: v1.2.0.0 or later
1869228940Sdelphij * Parameters:
1870228940Sdelphij *  id      logical device id
1871228940Sdelphij *  pInfo   pointer to LOGICAL_DEVICE_INFO_V3 structure
1872228940Sdelphij * Returns:
1873228940Sdelphij *  0 - Success
1874228940Sdelphij */
1875228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
1876228940Sdelphijint hpt_get_device_info_v3(DEVICEID id, PLOGICAL_DEVICE_INFO_V3 pInfo);
1877228940Sdelphij#endif
1878228940Sdelphij
1879228940Sdelphij/* hpt_get_device_info_v4
1880228940Sdelphij * Version compatibility: v2.0.0.1 or later
1881228940Sdelphij * Parameters:
1882228940Sdelphij *  id      logical device id
1883228940Sdelphij *  pInfo   pointer to LOGICAL_DEVICE_INFO_V4 structure
1884228940Sdelphij * Returns:
1885228940Sdelphij *  0 - Success
1886228940Sdelphij */
1887228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001
1888228940Sdelphijint hpt_get_device_info_v4(DEVICEID id, PLOGICAL_DEVICE_INFO_V4 pInfo);
1889228940Sdelphij#endif
1890228940Sdelphij
1891228940Sdelphij/* hpt_create_transform
1892228940Sdelphij *  create a transform instance.
1893228940Sdelphij * Version compatibility: v2.0.0.0 or later
1894228940Sdelphij * Parameters:
1895228940Sdelphij *  idArray - source array
1896228940Sdelphij *  destInfo - destination array info
1897228940Sdelphij * Returns:
1898228940Sdelphij *  destination array id
1899228940Sdelphij */
1900228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000000
1901228940SdelphijDEVICEID hpt_create_transform(DEVICEID idArray, PCREATE_ARRAY_PARAMS_V2 destInfo);
1902228940Sdelphij#endif
1903228940Sdelphij
1904228940Sdelphij/* hpt_create_transform_v2
1905228940Sdelphij *  create a transform instance.
1906228940Sdelphij * Version compatibility: v2.0.0.1 or later
1907228940Sdelphij * Parameters:
1908228940Sdelphij *  idArray - source array
1909228940Sdelphij *  destInfo - destination array info
1910228940Sdelphij * Returns:
1911228940Sdelphij *  destination array id
1912228940Sdelphij */
1913228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001
1914228940SdelphijDEVICEID hpt_create_transform_v2(DEVICEID idArray, PCREATE_ARRAY_PARAMS_V3 destInfo);
1915228940Sdelphij#endif
1916228940Sdelphij
1917228940Sdelphij/* hpt_step_transform
1918228940Sdelphij *  move a block in a tranform progress.
1919228940Sdelphij *  This function is called by mid-layer, not GUI (which uses set_array_state instead).
1920228940Sdelphij * Version compatibility: v2.0.0.0 or later
1921228940Sdelphij * Parameters:
1922228940Sdelphij *  idArray - destination array ID
1923228940Sdelphij *            the source ID will be invalid when transform complete.
1924228940Sdelphij * Returns:
1925228940Sdelphij *  0 - Success
1926228940Sdelphij */
1927228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000000
1928228940Sdelphijint hpt_step_transform(DEVICEID idArray);
1929228940Sdelphij#endif
1930228940Sdelphij
1931228940Sdelphij/* hpt_set_vdev_info
1932228940Sdelphij *  set information for disk or array
1933228940Sdelphij * Version compatibility: v1.2.0.0 or later
1934228940Sdelphij * Parameters:
1935228940Sdelphij *  dev - destination device
1936228940Sdelphij *
1937228940Sdelphij * Returns:
1938228940Sdelphij *  0 - Success
1939228940Sdelphij */
1940228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
1941228940Sdelphijint hpt_set_vdev_info(DEVICEID dev, PSET_VDEV_INFO pInfo);
1942228940Sdelphij#endif
1943228940Sdelphij
1944228940Sdelphij/* hpt_init_disks
1945228940Sdelphij *  initialize disks for use
1946228940Sdelphij * Version compatibility: v2.0.0.0 or later
1947228940Sdelphij * Parameters:
1948228940Sdelphij *  ndev - number of disks to initialize
1949228940Sdelphij *  pIds - array of DEVICEID
1950228940Sdelphij *
1951228940Sdelphij * Returns:
1952228940Sdelphij *  0 - Success
1953228940Sdelphij */
1954228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000000
1955228940Sdelphijint hpt_init_disks(HPT_U32 ndev, DEVICEID * pIds);
1956228940Sdelphij#endif
1957228940Sdelphij
1958228940Sdelphij/* hpt_calc_max_array_capacity
1959228940Sdelphij *  cap max capacity of the array user want to create or transform
1960228940Sdelphij * Version compatibility: v1.2.0.0 or later
1961228940Sdelphij * Parameters:
1962228940Sdelphij *  source - if transform, this is the source array, otherwise, it should be zero
1963228940Sdelphij *  destInfo - target array params
1964228940Sdelphij * Returns:
1965228940Sdelphij *  0 - Success
1966228940Sdelphij *  cap - max capacity of the target array
1967228940Sdelphij */
1968228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
1969228940Sdelphijint hpt_calc_max_array_capacity(DEVICEID source, PCREATE_ARRAY_PARAMS_V2 destInfo, HPT_U64 * cap);
1970228940Sdelphij#endif
1971228940Sdelphij
1972228940Sdelphij/* hpt_calc_max_array_capacity_v2
1973228940Sdelphij *  cap max capacity of the array user want to create or transform
1974228940Sdelphij * Version compatibility: v2.0.0.1 or later
1975228940Sdelphij * Parameters:
1976228940Sdelphij *  source - if transform, this is the source array, otherwise, it should be zero
1977228940Sdelphij *  destInfo - target array params
1978228940Sdelphij * Returns:
1979228940Sdelphij *  0 - Success
1980228940Sdelphij *  cap - max capacity of the target array
1981228940Sdelphij */
1982228940Sdelphij#if HPT_INTERFACE_VERSION>=0x02000001
1983228940Sdelphijint hpt_calc_max_array_capacity_v2(DEVICEID source, PCREATE_ARRAY_PARAMS_V3 destInfo, HPT_U64 * cap);
1984228940Sdelphij#endif
1985228940Sdelphij
1986228940Sdelphij/* hpt_rebuild_data_block2
1987228940Sdelphij *   Used to copy data from source disk and mirror disk.
1988228940Sdelphij * Version compatibility: v1.1.0.0 or later
1989228940Sdelphij * Parameters:
1990228940Sdelphij *   idArray        Array ID (RAID1, 0/1 or RAID5)
1991228940Sdelphij *   Lba            Start LBA for each array member
1992228940Sdelphij *   nSector        Number of sectors for each array member (RAID 5 will ignore this parameter)
1993228940Sdelphij *
1994228940Sdelphij * Returns:
1995228940Sdelphij *  0   Success, event info is filled in *pEvent
1996228940Sdelphij */
1997228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
1998228940Sdelphijint hpt_rebuild_data_block_v2(DEVICEID idMirror, HPT_U64 Lba, HPT_U16 nSector);
1999228940Sdelphij#endif
2000228940Sdelphij
2001228940Sdelphij/* hpt_verify_data_block2
2002228940Sdelphij *   verify data block on RAID1 or RAID5.
2003228940Sdelphij * Version compatibility: v1.1.0.0 or later
2004228940Sdelphij * Parameters:
2005228940Sdelphij *   idArray - Array ID
2006228940Sdelphij *   Lba - block number (on each array member, not logical block!)
2007228940Sdelphij *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
2008228940Sdelphij * Returns:
2009228940Sdelphij *   0  Success
2010228940Sdelphij *   1  Data compare error
2011228940Sdelphij *   2  I/O error
2012228940Sdelphij */
2013228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
2014228940Sdelphijint hpt_verify_data_block_v2(DEVICEID idArray, HPT_U64 Lba, HPT_U16 nSectors);
2015228940Sdelphij#endif
2016228940Sdelphij
2017228940Sdelphij/* hpt_initialize_data_block2
2018228940Sdelphij *   initialize data block (fill with zero) on RAID5
2019228940Sdelphij * Version compatibility: v1.1.0.0 or later
2020228940Sdelphij * Parameters:
2021228940Sdelphij *   idArray - Array ID
2022228940Sdelphij *   Lba - block number (on each array member, not logical block!)
2023228940Sdelphij *   nSectors - Sectors for each member (RAID 5 will ignore this parameter)
2024228940Sdelphij * Returns:
2025228940Sdelphij *   0  Success
2026228940Sdelphij */
2027228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01010000
2028228940Sdelphijint hpt_initialize_data_block_v2(DEVICEID idArray, HPT_U64 Lba, HPT_U16 nSectors);
2029228940Sdelphij#endif
2030228940Sdelphij
2031228940Sdelphij/* hpt_i2c_transaction
2032228940Sdelphij *   perform an transaction on i2c bus
2033228940Sdelphij * Version compatibility: v2.0.0.0 or later
2034228940Sdelphij * Parameters:
2035228940Sdelphij *   indata[0] - controller ID
2036228940Sdelphij * Returns:
2037228940Sdelphij *   0  Success
2038228940Sdelphij */
2039228940Sdelphij#if HPT_INTERFACE_VERSION>=0x01020000
2040228940Sdelphijint hpt_i2c_transaction(HPT_U8 *indata, HPT_U32 inlen, HPT_U8 *outdata, HPT_U32 outlen, HPT_U32 *poutlen);
2041228940Sdelphij#endif
2042228940Sdelphij
2043228940Sdelphij/* hpt_get_parameter_list
2044228940Sdelphij *   get a list of driver parameters.
2045228940Sdelphij * Version compatibility: v1.0.0.0 or later
2046228940Sdelphij * Parameters:
2047228940Sdelphij *   location - parameter location
2048228940Sdelphij *   outBuffer - a buffer to hold the output
2049228940Sdelphij *   outBufferSize - size of outBuffer
2050228940Sdelphij * Returns:
2051228940Sdelphij *   0  Success
2052228940Sdelphij *      put in outBuffer a list of zero terminated parameter names. the whole list
2053228940Sdelphij *      is terminated with an additional zero byte.
2054228940Sdelphij */
2055228940Sdelphijint hpt_get_parameter_list(HPT_U32 location, char *outBuffer, HPT_U32 outBufferSize);
2056228940Sdelphij
2057228940Sdelphij/* hpt_{get,set}_parameter
2058228940Sdelphij *   get/set a parameter value.
2059228940Sdelphij * Version compatibility: v1.0.0.0 or later
2060228940Sdelphij * Parameters:
2061228940Sdelphij *   pParam - a pointer to HPT_DRIVER_PARAMETER.
2062228940Sdelphij * Returns:
2063228940Sdelphij *   0  Success
2064228940Sdelphij */
2065228940Sdelphijint hpt_get_parameter(PHPT_DRIVER_PARAMETER pParam);
2066228940Sdelphijint hpt_set_parameter(PHPT_DRIVER_PARAMETER pParam);
2067228940Sdelphijint hpt_reenumerate_device(DEVICEID id);
2068228940Sdelphij
2069228940Sdelphij/*
2070228940Sdelphij * hpt_get_enclosure_count
2071228940Sdelphij * Version compatibility: v2.1.0.0 or later
2072228940Sdelphij * Parameters:
2073228940Sdelphij *  controller_id
2074228940Sdelphij * Returns:
2075228940Sdelphij *  number of enclosurers
2076228940Sdelphij */
2077228940Sdelphijint hpt_get_enclosure_count(int ctlr_id);
2078228940Sdelphij
2079228940Sdelphij/* hpt_get_enclosure_info
2080228940Sdelphij * Version compatibility: v2.1.0.0 or later
2081228940Sdelphij * Parameters:
2082228940Sdelphij *  id      enclosure id
2083228940Sdelphij *  pInfo   pointer to ENCLOSURE_INFO buffer
2084228940Sdelphij * Returns:
2085228940Sdelphij *  0       Success, enclosure info is put into (*pInfo ).
2086228940Sdelphij */
2087228940Sdelphijint hpt_get_enclosure_info(int ctlr_id, int enc_id, PENCLOSURE_INFO pInfo);
2088228940Sdelphij
2089228940Sdelphijint hpt_get_enclosure_info_v2(int ctlr_id, int enc_id, PENCLOSURE_INFO_V2 pInfo);
2090228940Sdelphij
2091228940Sdelphijint hpt_get_enclosure_info_v3(int ctlr_id, int enc_id, PENCLOSURE_INFO_V3 pInfo);
2092228940Sdelphij
2093228940Sdelphij/* performance monitor interface
2094228940Sdelphij * Version compatibility: v2.1.0.0 or later
2095228940Sdelphij */
2096228940Sdelphijint hpt_get_perfmon_status(int ctlr_id, int *p_status);
2097228940Sdelphijint hpt_set_perfmon_status(int ctlr_id, int enable);
2098228940Sdelphijint hpt_get_perfmon_data(DEVICEID id, PHPT_PM_IOSTAT iostat);
2099228940Sdelphij
2100228940Sdelphij/* hpt_get_controller_venid
2101228940Sdelphij * Version compatibility: v1.0.0.0 or later
2102228940Sdelphij */
2103228940Sdelphijint hpt_get_controller_venid(int ctlr_id, HPT_U32 *venid);
2104228940Sdelphij
2105228940Sdelphij#endif
2106228940Sdelphij
2107228940Sdelphij#pragma pack()
2108228940Sdelphij
2109228940Sdelphij#ifdef __cplusplus
2110228940Sdelphij}
2111228940Sdelphij#endif
2112228940Sdelphij#endif
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