glxiic.c revision 221961
1/*- 2 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/dev/glxiic/glxiic.c 221961 2011-05-15 14:01:23Z brix $"); 28/* 29 * AMD Geode LX CS5536 System Management Bus controller. 30 * 31 * Although AMD refers to this device as an SMBus controller, it 32 * really is an I2C controller (It lacks SMBus ALERT# and Alert 33 * Response support). 34 * 35 * The driver is implemented as an interrupt-driven state machine, 36 * supporting both master and slave mode. 37 */ 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/lock.h> 44#include <sys/mutex.h> 45#include <sys/sysctl.h> 46#ifdef GLXIIC_DEBUG 47#include <sys/syslog.h> 48#endif 49 50#include <dev/pci/pcireg.h> 51#include <dev/pci/pcivar.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <dev/iicbus/iiconf.h> 58#include <dev/iicbus/iicbus.h> 59 60#include "iicbus_if.h" 61 62/* CS5536 PCI-ISA ID. */ 63#define GLXIIC_CS5536_DEV_ID 0x20901022 64 65/* MSRs. */ 66#define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021 67 68/* Bus speeds. */ 69#define GLXIIC_SLOW 0x0258 /* 10 kHz. */ 70#define GLXIIC_FAST 0x0078 /* 50 kHz. */ 71#define GLXIIC_FASTEST 0x003c /* 100 kHz. */ 72 73/* Default bus activity timeout in milliseconds. */ 74#define GLXIIC_DEFAULT_TIMEOUT 35 75 76/* GPIO register offsets. */ 77#define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10 78#define GLXIIC_GPIOL_IN_AUX1_SEL 0x34 79 80/* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */ 81#define GLXIIC_GPIO_14_15_ENABLE 0x0000c000 82#define GLXIIC_GPIO_14_15_DISABLE 0xc0000000 83 84/* SMB register offsets. */ 85#define GLXIIC_SMB_SDA 0x00 86#define GLXIIC_SMB_STS 0x01 87#define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7) 88#define GLXIIC_SMB_STS_SDAST_BIT (1 << 6) 89#define GLXIIC_SMB_STS_BER_BIT (1 << 5) 90#define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4) 91#define GLXIIC_SMB_STS_STASTR_BIT (1 << 3) 92#define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2) 93#define GLXIIC_SMB_STS_MASTER_BIT (1 << 1) 94#define GLXIIC_SMB_STS_XMIT_BIT (1 << 0) 95#define GLXIIC_SMB_CTRL_STS 0x02 96#define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5) 97#define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4) 98#define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3) 99#define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2) 100#define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1) 101#define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0) 102#define GLXIIC_SMB_CTRL1 0x03 103#define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7) 104#define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6) 105#define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5) 106#define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4) 107#define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2) 108#define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1) 109#define GLXIIC_SMB_CTRL1_START_BIT (1 << 0) 110#define GLXIIC_SMB_ADDR 0x04 111#define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7) 112#define GLXIIC_SMB_CTRL2 0x05 113#define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0) 114#define GLXIIC_SMB_CTRL3 0x06 115 116typedef enum { 117 GLXIIC_STATE_IDLE, 118 GLXIIC_STATE_SLAVE_TX, 119 GLXIIC_STATE_SLAVE_RX, 120 GLXIIC_STATE_MASTER_ADDR, 121 GLXIIC_STATE_MASTER_TX, 122 GLXIIC_STATE_MASTER_RX, 123 GLXIIC_STATE_MASTER_STOP, 124 GLXIIC_STATE_MAX, 125} glxiic_state_t; 126 127struct glxiic_softc { 128 device_t dev; /* Myself. */ 129 device_t iicbus; /* IIC bus. */ 130 struct mtx mtx; /* Lock. */ 131 glxiic_state_t state; /* Driver state. */ 132 struct callout callout; /* Driver state timeout callout. */ 133 int timeout; /* Driver state timeout (ms). */ 134 135 int smb_rid; /* SMB controller resource ID. */ 136 struct resource *smb_res; /* SMB controller resource. */ 137 int gpio_rid; /* GPIO resource ID. */ 138 struct resource *gpio_res; /* GPIO resource. */ 139 140 int irq_rid; /* IRQ resource ID. */ 141 struct resource *irq_res; /* IRQ resource. */ 142 void *irq_handler; /* IRQ handler cookie. */ 143 int old_irq; /* IRQ mapped by board firmware. */ 144 145 struct iic_msg *msg; /* Current master mode message. */ 146 uint32_t nmsgs; /* Number of messages remaining. */ 147 uint8_t *data; /* Current master mode data byte. */ 148 uint16_t ndata; /* Number of data bytes remaining. */ 149 int error; /* Last master mode error. */ 150 151 uint8_t addr; /* Own address. */ 152 uint16_t sclfrq; /* Bus frequency. */ 153}; 154 155#ifdef GLXIIC_DEBUG 156#define DEBUG(fmt, args...) log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args) 157#else 158#define DEBUG(fmt, args...) 159#endif 160 161#define GLXIIC_SCLFRQ(n) ((n << 1)) 162#define GLXIIC_SMBADDR(n) ((n >> 1)) 163#define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16)) 164#define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf) 165 166#define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx) 167#define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx) 168#define GLXIIC_LOCK_INIT(_sc) \ 169 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF) 170#define GLXIIC_SLEEP(_sc) \ 171 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0) 172#define GLXIIC_WAKEUP(_sc) wakeup(_sc); 173#define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 174#define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 175 176typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc, 177 uint8_t status); 178 179static glxiic_state_callback_t glxiic_state_idle_callback; 180static glxiic_state_callback_t glxiic_state_slave_tx_callback; 181static glxiic_state_callback_t glxiic_state_slave_rx_callback; 182static glxiic_state_callback_t glxiic_state_master_addr_callback; 183static glxiic_state_callback_t glxiic_state_master_tx_callback; 184static glxiic_state_callback_t glxiic_state_master_rx_callback; 185static glxiic_state_callback_t glxiic_state_master_stop_callback; 186 187struct glxiic_state_table_entry { 188 glxiic_state_callback_t *callback; 189 boolean_t master; 190}; 191typedef struct glxiic_state_table_entry glxiic_state_table_entry_t; 192 193static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = { 194 [GLXIIC_STATE_IDLE] = { 195 .callback = &glxiic_state_idle_callback, 196 .master = FALSE, 197 }, 198 199 [GLXIIC_STATE_SLAVE_TX] = { 200 .callback = &glxiic_state_slave_tx_callback, 201 .master = FALSE, 202 }, 203 204 [GLXIIC_STATE_SLAVE_RX] = { 205 .callback = &glxiic_state_slave_rx_callback, 206 .master = FALSE, 207 }, 208 209 [GLXIIC_STATE_MASTER_ADDR] = { 210 .callback = &glxiic_state_master_addr_callback, 211 .master = TRUE, 212 }, 213 214 [GLXIIC_STATE_MASTER_TX] = { 215 .callback = &glxiic_state_master_tx_callback, 216 .master = TRUE, 217 }, 218 219 [GLXIIC_STATE_MASTER_RX] = { 220 .callback = &glxiic_state_master_rx_callback, 221 .master = TRUE, 222 }, 223 224 [GLXIIC_STATE_MASTER_STOP] = { 225 .callback = &glxiic_state_master_stop_callback, 226 .master = TRUE, 227 }, 228}; 229 230static void glxiic_identify(driver_t *driver, device_t parent); 231static int glxiic_probe(device_t dev); 232static int glxiic_attach(device_t dev); 233static int glxiic_detach(device_t dev); 234 235static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc); 236static void glxiic_stop_locked(struct glxiic_softc *sc); 237static void glxiic_timeout(void *arg); 238static void glxiic_start_timeout_locked(struct glxiic_softc *sc); 239static void glxiic_set_state_locked(struct glxiic_softc *sc, 240 glxiic_state_t state); 241static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc, 242 uint8_t status); 243static void glxiic_intr(void *arg); 244 245static int glxiic_reset(device_t dev, u_char speed, u_char addr, 246 u_char *oldaddr); 247static int glxiic_transfer(device_t dev, struct iic_msg *msgs, 248 uint32_t nmsgs); 249 250static void glxiic_smb_map_interrupt(int irq); 251static void glxiic_gpio_enable(struct glxiic_softc *sc); 252static void glxiic_gpio_disable(struct glxiic_softc *sc); 253static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, 254 uint8_t addr); 255static void glxiic_smb_disable(struct glxiic_softc *sc); 256 257static device_method_t glxiic_methods[] = { 258 DEVMETHOD(device_identify, glxiic_identify), 259 DEVMETHOD(device_probe, glxiic_probe), 260 DEVMETHOD(device_attach, glxiic_attach), 261 DEVMETHOD(device_detach, glxiic_detach), 262 263 DEVMETHOD(iicbus_reset, glxiic_reset), 264 DEVMETHOD(iicbus_transfer, glxiic_transfer), 265 DEVMETHOD(iicbus_callback, iicbus_null_callback), 266 267 { 0, 0 } 268}; 269 270static driver_t glxiic_driver = { 271 "glxiic", 272 glxiic_methods, 273 sizeof(struct glxiic_softc), 274}; 275 276static devclass_t glxiic_devclass; 277 278DRIVER_MODULE(glxiic, isab, glxiic_driver, glxiic_devclass, 0, 0); 279DRIVER_MODULE(iicbus, glxiic, iicbus_driver, iicbus_devclass, 0, 0); 280MODULE_DEPEND(glxiic, iicbus, 1, 1, 1); 281 282static void 283glxiic_identify(driver_t *driver, device_t parent) 284{ 285 286 /* Prevent child from being added more than once. */ 287 if (device_find_child(parent, driver->name, -1) != NULL) 288 return; 289 290 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) { 291 if (device_add_child(parent, driver->name, -1) == NULL) 292 device_printf(parent, "Could not add glxiic child\n"); 293 } 294} 295 296static int 297glxiic_probe(device_t dev) 298{ 299 300 if (resource_disabled("glxiic", device_get_unit(dev))) 301 return (ENXIO); 302 303 device_set_desc(dev, "AMD Geode CS5536 SMBus controller"); 304 305 return (BUS_PROBE_DEFAULT); 306} 307 308static int 309glxiic_attach(device_t dev) 310{ 311 struct glxiic_softc *sc; 312 struct sysctl_ctx_list *ctx; 313 struct sysctl_oid *tree; 314 int error, irq, unit; 315 uint32_t irq_map; 316 char tn[32]; 317 318 sc = device_get_softc(dev); 319 sc->dev = dev; 320 sc->state = GLXIIC_STATE_IDLE; 321 error = 0; 322 323 GLXIIC_LOCK_INIT(sc); 324 callout_init_mtx(&sc->callout, &sc->mtx, 0); 325 326 sc->smb_rid = PCIR_BAR(0); 327 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid, 328 RF_ACTIVE); 329 if (sc->smb_res == NULL) { 330 device_printf(dev, "Could not allocate SMBus I/O port\n"); 331 error = ENXIO; 332 goto out; 333 } 334 335 sc->gpio_rid = PCIR_BAR(1); 336 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 337 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE); 338 if (sc->gpio_res == NULL) { 339 device_printf(dev, "Could not allocate GPIO I/O port\n"); 340 error = ENXIO; 341 goto out; 342 } 343 344 /* Ensure the controller is not enabled by firmware. */ 345 glxiic_smb_disable(sc); 346 347 /* Read the existing IRQ map. */ 348 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 349 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 350 351 unit = device_get_unit(dev); 352 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) { 353 if (irq < 1 || irq > 15) { 354 device_printf(dev, "Bad value %d for glxiic.%d.irq\n", 355 irq, unit); 356 error = ENXIO; 357 goto out; 358 } 359 360 if (bootverbose) 361 device_printf(dev, "Using irq %d set by hint\n", irq); 362 } else if (sc->old_irq != 0) { 363 if (bootverbose) 364 device_printf(dev, "Using irq %d set by firmware\n", 365 irq); 366 irq = sc->old_irq; 367 } else { 368 device_printf(dev, "No irq mapped by firmware"); 369 printf(" and no glxiic.%d.irq hint provided\n", unit); 370 error = ENXIO; 371 goto out; 372 } 373 374 /* Map the SMBus interrupt to the requested legacy IRQ. */ 375 glxiic_smb_map_interrupt(irq); 376 377 sc->irq_rid = 0; 378 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 379 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE); 380 if (sc->irq_res == NULL) { 381 device_printf(dev, "Could not allocate IRQ %d\n", irq); 382 error = ENXIO; 383 goto out; 384 } 385 386 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 387 NULL, glxiic_intr, sc, &(sc->irq_handler)); 388 if (error != 0) { 389 device_printf(dev, "Could not setup IRQ handler\n"); 390 error = ENXIO; 391 goto out; 392 } 393 394 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 395 device_printf(dev, "Could not allocate iicbus instance\n"); 396 error = ENXIO; 397 goto out; 398 } 399 400 ctx = device_get_sysctl_ctx(dev); 401 tree = device_get_sysctl_tree(dev); 402 403 sc->timeout = GLXIIC_DEFAULT_TIMEOUT; 404 snprintf(tn, sizeof(tn), "dev.glxiic.%d.timeout", unit); 405 TUNABLE_INT_FETCH(tn, &sc->timeout); 406 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 407 "timeout", CTLFLAG_RW | CTLFLAG_TUN, &sc->timeout, 0, 408 "activity timeout in ms"); 409 410 glxiic_gpio_enable(sc); 411 glxiic_smb_enable(sc, IIC_FASTEST, 0); 412 413 error = bus_generic_attach(dev); 414 if (error != 0) { 415 device_printf(dev, "Could not probe and attach children\n"); 416 error = ENXIO; 417 } 418out: 419 if (error != 0) { 420 callout_drain(&sc->callout); 421 422 if (sc->iicbus != NULL) 423 device_delete_child(dev, sc->iicbus); 424 if (sc->smb_res != NULL) { 425 glxiic_smb_disable(sc); 426 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 427 sc->smb_res); 428 } 429 if (sc->gpio_res != NULL) { 430 glxiic_gpio_disable(sc); 431 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 432 sc->gpio_res); 433 } 434 if (sc->irq_handler != NULL) 435 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 436 if (sc->irq_res != NULL) 437 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 438 sc->irq_res); 439 440 /* Restore the old SMBus interrupt mapping. */ 441 glxiic_smb_map_interrupt(sc->old_irq); 442 443 GLXIIC_LOCK_DESTROY(sc); 444 } 445 446 return (error); 447} 448 449static int 450glxiic_detach(device_t dev) 451{ 452 struct glxiic_softc *sc; 453 int error; 454 455 sc = device_get_softc(dev); 456 457 error = bus_generic_detach(dev); 458 if (error != 0) 459 goto out; 460 if (sc->iicbus != NULL) 461 error = device_delete_child(dev, sc->iicbus); 462 463out: 464 callout_drain(&sc->callout); 465 466 if (sc->smb_res != NULL) { 467 glxiic_smb_disable(sc); 468 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, 469 sc->smb_res); 470 } 471 if (sc->gpio_res != NULL) { 472 glxiic_gpio_disable(sc); 473 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, 474 sc->gpio_res); 475 } 476 if (sc->irq_handler != NULL) 477 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); 478 if (sc->irq_res != NULL) 479 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 480 sc->irq_res); 481 482 /* Restore the old SMBus interrupt mapping. */ 483 glxiic_smb_map_interrupt(sc->old_irq); 484 485 GLXIIC_LOCK_DESTROY(sc); 486 487 return (error); 488} 489 490static uint8_t 491glxiic_read_status_locked(struct glxiic_softc *sc) 492{ 493 uint8_t status; 494 495 GLXIIC_ASSERT_LOCKED(sc); 496 497 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS); 498 499 /* Clear all status flags except SDAST and STASTR after reading. */ 500 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT | 501 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT | 502 GLXIIC_SMB_STS_NMATCH_BIT)); 503 504 return (status); 505} 506 507static void 508glxiic_stop_locked(struct glxiic_softc *sc) 509{ 510 uint8_t status, ctrl1; 511 512 GLXIIC_ASSERT_LOCKED(sc); 513 514 status = glxiic_read_status_locked(sc); 515 516 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 517 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 518 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT); 519 520 /* 521 * Perform a dummy read of SDA in master receive mode to clear 522 * SDAST if set. 523 */ 524 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 && 525 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0) 526 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 527 528 /* Check stall after start bit and clear if needed */ 529 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 530 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 531 GLXIIC_SMB_STS_STASTR_BIT); 532 } 533} 534 535static void 536glxiic_timeout(void *arg) 537{ 538 struct glxiic_softc *sc; 539 uint8_t error; 540 541 sc = (struct glxiic_softc *)arg; 542 543 DEBUG("timeout in state %d", sc->state); 544 545 if (glxiic_state_table[sc->state].master) { 546 sc->error = IIC_ETIMEOUT; 547 GLXIIC_WAKEUP(sc); 548 } else { 549 error = IIC_ETIMEOUT; 550 iicbus_intr(sc->iicbus, INTR_ERROR, &error); 551 } 552 553 glxiic_smb_disable(sc); 554 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr); 555 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 556} 557 558static void 559glxiic_start_timeout_locked(struct glxiic_softc *sc) 560{ 561 562 GLXIIC_ASSERT_LOCKED(sc); 563 564 callout_reset(&sc->callout, sc->timeout * 1000 / hz, glxiic_timeout, 565 sc); 566} 567 568static void 569glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state) 570{ 571 572 GLXIIC_ASSERT_LOCKED(sc); 573 574 if (state == GLXIIC_STATE_IDLE) 575 callout_stop(&sc->callout); 576 else if (sc->timeout > 0) 577 glxiic_start_timeout_locked(sc); 578 579 sc->state = state; 580} 581 582static int 583glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status) 584{ 585 uint8_t ctrl_sts, addr; 586 587 GLXIIC_ASSERT_LOCKED(sc); 588 589 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS); 590 591 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) { 592 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) { 593 addr = sc->addr | LSB; 594 glxiic_set_state_locked(sc, 595 GLXIIC_STATE_SLAVE_TX); 596 } else { 597 addr = sc->addr & ~LSB; 598 glxiic_set_state_locked(sc, 599 GLXIIC_STATE_SLAVE_RX); 600 } 601 iicbus_intr(sc->iicbus, INTR_START, &addr); 602 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) { 603 addr = 0; 604 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX); 605 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr); 606 } else { 607 DEBUG("unknown slave match"); 608 return (IIC_ESTATUS); 609 } 610 611 return (IIC_NOERR); 612} 613 614static int 615glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status) 616{ 617 618 GLXIIC_ASSERT_LOCKED(sc); 619 620 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 621 DEBUG("bus error in idle"); 622 return (IIC_EBUSERR); 623 } 624 625 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 626 return (glxiic_handle_slave_match_locked(sc, status)); 627 } 628 629 return (IIC_NOERR); 630} 631 632static int 633glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status) 634{ 635 uint8_t data; 636 637 GLXIIC_ASSERT_LOCKED(sc); 638 639 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 640 DEBUG("bus error in slave tx"); 641 return (IIC_EBUSERR); 642 } 643 644 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 645 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 646 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 647 return (IIC_NOERR); 648 } 649 650 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 651 iicbus_intr(sc->iicbus, INTR_NOACK, NULL); 652 return (IIC_NOERR); 653 } 654 655 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 656 /* Handle repeated start in slave mode. */ 657 return (glxiic_handle_slave_match_locked(sc, status)); 658 } 659 660 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 661 DEBUG("not awaiting data in slave tx"); 662 return (IIC_ESTATUS); 663 } 664 665 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); 666 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data); 667 668 glxiic_start_timeout_locked(sc); 669 670 return (IIC_NOERR); 671} 672 673static int 674glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status) 675{ 676 uint8_t data; 677 678 GLXIIC_ASSERT_LOCKED(sc); 679 680 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 681 DEBUG("bus error in slave rx"); 682 return (IIC_EBUSERR); 683 } 684 685 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { 686 iicbus_intr(sc->iicbus, INTR_STOP, NULL); 687 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 688 return (IIC_NOERR); 689 } 690 691 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { 692 /* Handle repeated start in slave mode. */ 693 return (glxiic_handle_slave_match_locked(sc, status)); 694 } 695 696 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 697 DEBUG("no pending data in slave rx"); 698 return (IIC_ESTATUS); 699 } 700 701 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 702 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data); 703 704 glxiic_start_timeout_locked(sc); 705 706 return (IIC_NOERR); 707} 708 709static int 710glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status) 711{ 712 uint8_t slave; 713 714 GLXIIC_ASSERT_LOCKED(sc); 715 716 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 717 DEBUG("bus error after master start"); 718 return (IIC_EBUSERR); 719 } 720 721 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 722 DEBUG("not bus master after master start"); 723 return (IIC_ESTATUS); 724 } 725 726 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 727 DEBUG("not awaiting address in master addr"); 728 return (IIC_ESTATUS); 729 } 730 731 if ((sc->msg->flags & IIC_M_RD) != 0) { 732 slave = sc->msg->slave | LSB; 733 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX); 734 } else { 735 slave = sc->msg->slave & ~LSB; 736 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX); 737 } 738 739 sc->data = sc->msg->buf; 740 sc->ndata = sc->msg->len; 741 742 /* Handle address-only transfer. */ 743 if (sc->ndata == 0) 744 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 745 746 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave); 747 748 return (IIC_NOERR); 749} 750 751static int 752glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status) 753{ 754 755 GLXIIC_ASSERT_LOCKED(sc); 756 757 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 758 DEBUG("bus error in master tx"); 759 return (IIC_EBUSERR); 760 } 761 762 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 763 DEBUG("not bus master in master tx"); 764 return (IIC_ESTATUS); 765 } 766 767 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 768 DEBUG("slave nack in master tx"); 769 return (IIC_ENOACK); 770 } 771 772 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 773 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 774 GLXIIC_SMB_STS_STASTR_BIT); 775 } 776 777 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 778 DEBUG("not awaiting data in master tx"); 779 return (IIC_ESTATUS); 780 } 781 782 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++); 783 if (--sc->ndata == 0) 784 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 785 else 786 glxiic_start_timeout_locked(sc); 787 788 return (IIC_NOERR); 789} 790 791static int 792glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status) 793{ 794 uint8_t ctrl1; 795 796 GLXIIC_ASSERT_LOCKED(sc); 797 798 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 799 DEBUG("bus error in master rx"); 800 return (IIC_EBUSERR); 801 } 802 803 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 804 DEBUG("not bus master in master rx"); 805 return (IIC_ESTATUS); 806 } 807 808 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 809 DEBUG("slave nack in rx"); 810 return (IIC_ENOACK); 811 } 812 813 if (sc->ndata == 1) { 814 /* Last byte from slave, set NACK. */ 815 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 816 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 817 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); 818 } 819 820 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { 821 /* Bus is stalled, clear and wait for data. */ 822 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, 823 GLXIIC_SMB_STS_STASTR_BIT); 824 return (IIC_NOERR); 825 } 826 827 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { 828 DEBUG("no pending data in master rx"); 829 return (IIC_ESTATUS); 830 } 831 832 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); 833 if (--sc->ndata == 0) { 834 /* Proceed with stop on reading last byte. */ 835 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); 836 return (glxiic_state_table[sc->state].callback(sc, status)); 837 } 838 839 glxiic_start_timeout_locked(sc); 840 841 return (IIC_NOERR); 842} 843 844static int 845glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status) 846{ 847 uint8_t ctrl1; 848 849 GLXIIC_ASSERT_LOCKED(sc); 850 851 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { 852 DEBUG("bus error in master stop"); 853 return (IIC_EBUSERR); 854 } 855 856 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { 857 DEBUG("not bus master in master stop"); 858 return (IIC_ESTATUS); 859 } 860 861 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { 862 DEBUG("slave nack in master stop"); 863 return (IIC_ENOACK); 864 } 865 866 if (--sc->nmsgs > 0) { 867 /* Start transfer of next message. */ 868 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) { 869 glxiic_stop_locked(sc); 870 } 871 872 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 873 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 874 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 875 876 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 877 sc->msg++; 878 } else { 879 /* Last message. */ 880 glxiic_stop_locked(sc); 881 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 882 sc->error = IIC_NOERR; 883 GLXIIC_WAKEUP(sc); 884 } 885 886 return (IIC_NOERR); 887} 888 889static void 890glxiic_intr(void *arg) 891{ 892 struct glxiic_softc *sc; 893 int error; 894 uint8_t status, data; 895 896 sc = (struct glxiic_softc *)arg; 897 898 GLXIIC_LOCK(sc); 899 900 status = glxiic_read_status_locked(sc); 901 902 /* Check if this interrupt originated from the SMBus. */ 903 if ((status & 904 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) { 905 906 error = glxiic_state_table[sc->state].callback(sc, status); 907 908 if (error != IIC_NOERR) { 909 if (glxiic_state_table[sc->state].master) { 910 glxiic_stop_locked(sc); 911 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 912 sc->error = error; 913 GLXIIC_WAKEUP(sc); 914 } else { 915 data = error & 0xff; 916 iicbus_intr(sc->iicbus, INTR_ERROR, &data); 917 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 918 } 919 } 920 } 921 922 GLXIIC_UNLOCK(sc); 923} 924 925static int 926glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 927{ 928 struct glxiic_softc *sc; 929 930 sc = device_get_softc(dev); 931 932 GLXIIC_LOCK(sc); 933 934 if (oldaddr != NULL) 935 *oldaddr = sc->addr; 936 sc->addr = addr; 937 938 /* A disable/enable cycle resets the controller. */ 939 glxiic_smb_disable(sc); 940 glxiic_smb_enable(sc, speed, addr); 941 942 if (glxiic_state_table[sc->state].master) { 943 sc->error = IIC_ESTATUS; 944 GLXIIC_WAKEUP(sc); 945 } 946 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); 947 948 GLXIIC_UNLOCK(sc); 949 950 return (IIC_NOERR); 951} 952 953static int 954glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 955{ 956 struct glxiic_softc *sc; 957 int error; 958 uint8_t ctrl1; 959 960 sc = device_get_softc(dev); 961 962 GLXIIC_LOCK(sc); 963 964 if (sc->state != GLXIIC_STATE_IDLE) { 965 error = IIC_EBUSBSY; 966 goto out; 967 } 968 969 sc->msg = msgs; 970 sc->nmsgs = nmsgs; 971 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); 972 973 /* Set start bit and let glxiic_intr() handle the transfer. */ 974 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); 975 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 976 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); 977 978 GLXIIC_SLEEP(sc); 979 error = sc->error; 980out: 981 GLXIIC_UNLOCK(sc); 982 983 return (error); 984} 985 986static void 987glxiic_smb_map_interrupt(int irq) 988{ 989 uint32_t irq_map; 990 int old_irq; 991 992 /* Protect the read-modify-write operation. */ 993 critical_enter(); 994 995 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); 996 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); 997 998 if (irq != old_irq) { 999 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq); 1000 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq); 1001 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map); 1002 } 1003 1004 critical_exit(); 1005} 1006 1007static void 1008glxiic_gpio_enable(struct glxiic_softc *sc) 1009{ 1010 1011 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1012 GLXIIC_GPIO_14_15_ENABLE); 1013 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1014 GLXIIC_GPIO_14_15_ENABLE); 1015} 1016 1017static void 1018glxiic_gpio_disable(struct glxiic_softc *sc) 1019{ 1020 1021 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, 1022 GLXIIC_GPIO_14_15_DISABLE); 1023 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, 1024 GLXIIC_GPIO_14_15_DISABLE); 1025} 1026 1027static void 1028glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr) 1029{ 1030 uint8_t ctrl1; 1031 1032 ctrl1 = 0; 1033 1034 switch (speed) { 1035 case IIC_SLOW: 1036 sc->sclfrq = GLXIIC_SLOW; 1037 break; 1038 case IIC_FAST: 1039 sc->sclfrq = GLXIIC_FAST; 1040 break; 1041 case IIC_FASTEST: 1042 sc->sclfrq = GLXIIC_FASTEST; 1043 break; 1044 case IIC_UNKNOWN: 1045 default: 1046 /* Reuse last frequency. */ 1047 break; 1048 } 1049 1050 /* Set bus speed and enable controller. */ 1051 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1052 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT); 1053 1054 if (addr != 0) { 1055 /* Enable new match and global call match interrupts. */ 1056 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT | 1057 GLXIIC_SMB_CTRL1_GCMEN_BIT; 1058 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 1059 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr)); 1060 } else { 1061 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0); 1062 } 1063 1064 /* Enable stall after start and interrupt. */ 1065 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, 1066 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT); 1067} 1068 1069static void 1070glxiic_smb_disable(struct glxiic_softc *sc) 1071{ 1072 uint16_t sclfrq; 1073 1074 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2); 1075 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, 1076 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT); 1077} 1078