1139749Simp/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 391398Stmm * All rights reserved. 491398Stmm * 591398Stmm * 691398Stmm * Redistribution and use in source and binary forms, with or without 791398Stmm * modification, are permitted provided that the following conditions 891398Stmm * are met: 991398Stmm * 1. Redistributions of source code must retain the above copyright 1091398Stmm * notice, this list of conditions and the following disclaimer. 1191398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1291398Stmm * notice, this list of conditions and the following disclaimer in the 1391398Stmm * documentation and/or other materials provided with the distribution. 1491398Stmm * 1591398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1691398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1791398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1891398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1991398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2091398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2191398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2291398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2391398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2491398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2591398Stmm * SUCH DAMAGE. 2691398Stmm * 27177560Smarius * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp 2891398Stmm * 2991398Stmm * $FreeBSD$ 3091398Stmm */ 3191398Stmm 3291398Stmm#ifndef _IF_GEMREG_H 3391398Stmm#define _IF_GEMREG_H 3491398Stmm 35194763Smarius/* register definitions for Apple GMAC, Sun ERI and Sun GEM */ 3691398Stmm 37177560Smarius/* 38223944Smarius * First bank: these registers live at the start of the PCI 39177560Smarius * mapping, and at the start of the second bank of the SBus 40177560Smarius * version. 41177560Smarius */ 4291398Stmm#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 4391398Stmm#define GEM_CONFIG 0x0004 /* config reg */ 4491398Stmm#define GEM_STATUS 0x000c /* status reg */ 45174987Smarius/* Note: Reading the status reg clears bits 0-6. */ 4691398Stmm#define GEM_INTMASK 0x0010 4791398Stmm#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 4891398Stmm#define GEM_STATUS_ALIAS 0x001c 49177560Smarius 5091398Stmm/* Bits in GEM_SEB register */ 51194763Smarius#define GEM_SEB_ARB 0x00000002 /* Arbitration status */ 52194763Smarius#define GEM_SEB_RXWON 0x00000004 5391398Stmm 5491398Stmm/* Bits in GEM_CONFIG register */ 55194763Smarius#define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */ 56194763Smarius#define GEM_CONFIG_BURST_INF 0x00000001 /* infinite for entire packet */ 57194763Smarius#define GEM_CONFIG_TXDMA_LIMIT 0x0000003e 58194763Smarius#define GEM_CONFIG_RXDMA_LIMIT 0x000007c0 59172334Smarius/* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 60194763Smarius#define GEM_CONFIG_RONPAULBIT 0x00000800 /* after infinite burst use */ 61172334Smarius /* memory read multiple for */ 62172334Smarius /* PCI commands */ 63194763Smarius#define GEM_CONFIG_BUG2FIX 0x00001000 /* fix RX hang after overflow */ 6491398Stmm 6591398Stmm#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 6691398Stmm#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 6791398Stmm 6891398Stmm/* Top part of GEM_STATUS has TX completion information */ 69194763Smarius#define GEM_STATUS_TX_COMPLETION_MASK 0xfff80000 /* TX completion reg. */ 70194763Smarius#define GEM_STATUS_TX_COMPLETION_SHFT 19 7191398Stmm 72172334Smarius/* 73174987Smarius * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs 74172334Smarius * Bits 0-6 auto-clear when read. 75172334Smarius */ 76194763Smarius#define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */ 77194763Smarius#define GEM_INTR_TX_EMPTY 0x00000002 /* TX ring empty */ 78194763Smarius#define GEM_INTR_TX_DONE 0x00000004 /* TX complete */ 79194763Smarius#define GEM_INTR_RX_DONE 0x00000010 /* Got a packet */ 80194763Smarius#define GEM_INTR_RX_NOBUF 0x00000020 81194763Smarius#define GEM_INTR_RX_TAG_ERR 0x00000040 82194763Smarius#define GEM_INTR_PERR 0x00000080 /* Parity error */ 83194763Smarius#define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */ 84194763Smarius#define GEM_INTR_TX_MAC 0x00004000 85194763Smarius#define GEM_INTR_RX_MAC 0x00008000 86194763Smarius#define GEM_INTR_MAC_CONTROL 0x00010000 /* MAC control interrupt */ 87194763Smarius#define GEM_INTR_MIF 0x00020000 88194763Smarius#define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */ 89172334Smarius#define GEM_INTR_BITS "\177\020" \ 9091398Stmm "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 9191398Stmm "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 92172334Smarius "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 93172334Smarius "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 9491398Stmm 95194763Smarius/* 96223944Smarius * Second bank: these registers live at offset 0x1000 of the PCI 97194763Smarius * mapping, and at the start of the first bank of the SBus 98194763Smarius * version. 99194763Smarius */ 100194763Smarius#define GEM_PCI_BANK2_OFFSET 0x1000 101194763Smarius#define GEM_PCI_BANK2_SIZE 0x14 102194763Smarius/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 103194763Smarius#define GEM_PCI_ERROR_STATUS 0x0000 /* PCI error status */ 104194763Smarius#define GEM_PCI_ERROR_MASK 0x0004 /* PCI error mask */ 105194763Smarius#define GEM_PCI_BIF_CONFIG 0x0008 /* PCI BIF configuration */ 106194763Smarius#define GEM_PCI_BIF_DIAG 0x000c /* PCI BIF diagnostic */ 10791398Stmm 108194763Smarius#define GEM_SBUS_BIF_RESET 0x0000 /* SBus BIF only software reset */ 109194763Smarius#define GEM_SBUS_CONFIG 0x0004 /* SBus IO configuration */ 110194763Smarius#define GEM_SBUS_STATUS 0x0008 /* SBus IO status */ 111194763Smarius#define GEM_SBUS_REVISION 0x000c /* SBus revision ID */ 11291398Stmm 113194763Smarius#define GEM_RESET 0x0010 /* software reset */ 11491398Stmm 115194763Smarius/* GEM_PCI_ERROR_STATUS and GEM_PCI_ERROR_MASK error bits */ 116194763Smarius#define GEM_PCI_ERR_STAT_BADACK 0x00000001 /* No ACK64# */ 117194763Smarius#define GEM_PCI_ERR_STAT_DTRTO 0x00000002 /* Delayed xaction timeout */ 118194763Smarius#define GEM_PCI_ERR_STAT_OTHERS 0x00000004 119194763Smarius#define GEM_PCI_ERR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 120194763Smarius 121194763Smarius/* GEM_PCI_BIF_CONFIG register bits */ 122194763Smarius#define GEM_PCI_BIF_CNF_SLOWCLK 0x00000001 /* Parity error timing */ 123194763Smarius#define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */ 124194763Smarius#define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */ 125194763Smarius#define GEM_PCI_BIF_CNF_M66EN 0x00000008 126194763Smarius#define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 127172334Smarius "b\2B64DIS\0b\3M66EN\0\0" 12891398Stmm 129194763Smarius/* GEM_PCI_BIF_DIAG register bits */ 130194763Smarius#define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */ 131223944Smarius#define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */ 13291398Stmm 133194763Smarius/* Bits in GEM_SBUS_CONFIG register */ 134194763Smarius#define GEM_SBUS_CFG_BURST_32 0x00000001 /* 32 byte bursts */ 135194763Smarius#define GEM_SBUS_CFG_BURST_64 0x00000002 /* 64 byte bursts */ 136194763Smarius#define GEM_SBUS_CFG_BURST_128 0x00000004 /* 128 byte bursts */ 137194763Smarius#define GEM_SBUS_CFG_64BIT 0x00000008 /* extended transfer mode */ 138194763Smarius#define GEM_SBUS_CFG_PARITY 0x00000200 /* enable parity checking */ 139194763Smarius 140194763Smarius/* GEM_SBUS_STATUS register bits */ 141194763Smarius#define GEM_SBUS_STATUS_LERR 0x00000001 /* LERR from SBus slave */ 142194763Smarius#define GEM_SBUS_STATUS_SACK 0x00000002 /* size ack. error */ 143194763Smarius#define GEM_SBUS_STATUS_EACK 0x00000004 /* SBus ctrl. or slave error */ 144194763Smarius#define GEM_SBUS_STATUS_MPARITY 0x00000008 /* SBus master parity error */ 145194763Smarius 14691398Stmm/* GEM_RESET register bits -- TX and RX self clear when complete. */ 147194763Smarius#define GEM_RESET_TX 0x00000001 /* Reset TX half. */ 148194763Smarius#define GEM_RESET_RX 0x00000002 /* Reset RX half. */ 149194763Smarius#define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ 150223944Smarius#define GEM_RESET_CLSZ_MASK 0x00ff0000 /* ERI cache line size */ 151223944Smarius#define GEM_RESET_CLSZ_SHFT 16 15291398Stmm 153194763Smarius/* The rest of the registers live in the first bank again. */ 15491398Stmm 155194763Smarius/* TX DMA registers */ 15691398Stmm#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 15791398Stmm#define GEM_TX_CONFIG 0x2004 15891398Stmm#define GEM_TX_RING_PTR_LO 0x2008 15991398Stmm#define GEM_TX_RING_PTR_HI 0x200c 16091398Stmm 16191398Stmm#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 16291398Stmm#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 16391398Stmm#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 16491398Stmm#define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 16591398Stmm#define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 16691398Stmm 16791398Stmm#define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 16891398Stmm#define GEM_TX_DATA_PTR_LO 0x2030 16991398Stmm#define GEM_TX_DATA_PTR_HI 0x2034 17091398Stmm 17191398Stmm#define GEM_TX_COMPLETION 0x2100 17291398Stmm#define GEM_TX_FIFO_ADDRESS 0x2104 17391398Stmm#define GEM_TX_FIFO_TAG 0x2108 17491398Stmm#define GEM_TX_FIFO_DATA_LO 0x210c 17591398Stmm#define GEM_TX_FIFO_DATA_HI_T1 0x2110 17691398Stmm#define GEM_TX_FIFO_DATA_HI_T0 0x2114 17791398Stmm#define GEM_TX_FIFO_SIZE 0x2118 17891398Stmm#define GEM_TX_DEBUG 0x3028 17991398Stmm 180174987Smarius/* GEM_TX_CONFIG register bits */ 18191398Stmm#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 18291398Stmm#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 18391398Stmm#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 18491398Stmm#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 18591398Stmm 18691398Stmm#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 18791398Stmm#define GEM_RING_SZ_64 (1<<1) 18891398Stmm#define GEM_RING_SZ_128 (2<<1) 18991398Stmm#define GEM_RING_SZ_256 (3<<1) 19091398Stmm#define GEM_RING_SZ_512 (4<<1) 19191398Stmm#define GEM_RING_SZ_1024 (5<<1) 19291398Stmm#define GEM_RING_SZ_2048 (6<<1) 19391398Stmm#define GEM_RING_SZ_4096 (7<<1) 19491398Stmm#define GEM_RING_SZ_8192 (8<<1) 19591398Stmm 19691398Stmm/* GEM_TX_COMPLETION register bits */ 19791398Stmm#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 19891398Stmm 199194763Smarius/* RX DMA registers */ 20091398Stmm#define GEM_RX_CONFIG 0x4000 20191398Stmm#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 20291398Stmm#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 20391398Stmm 20491398Stmm#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 20591398Stmm#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 20691398Stmm#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 20791398Stmm#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 20891398Stmm 20991398Stmm#define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 21091398Stmm#define GEM_RX_PAUSE_THRESH 0x4020 21191398Stmm 21291398Stmm#define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 21391398Stmm#define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 21491398Stmm 21591398Stmm#define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 21691398Stmm#define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 21791398Stmm#define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 21891398Stmm 21991398Stmm#define GEM_RX_FIFO_ADDRESS 0x410c 22091398Stmm#define GEM_RX_FIFO_TAG 0x4110 22191398Stmm#define GEM_RX_FIFO_DATA_LO 0x4114 22291398Stmm#define GEM_RX_FIFO_DATA_HI_T1 0x4118 22391398Stmm#define GEM_RX_FIFO_DATA_HI_T0 0x411c 22491398Stmm#define GEM_RX_FIFO_SIZE 0x4120 22591398Stmm 226174987Smarius/* GEM_RX_CONFIG register bits */ 22791398Stmm#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 22891398Stmm#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 22991398Stmm#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 23091398Stmm#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 231172334Smarius#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 23291398Stmm#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 23391398Stmm 23491398Stmm#define GEM_THRSH_64 0 23591398Stmm#define GEM_THRSH_128 1 23691398Stmm#define GEM_THRSH_256 2 23791398Stmm#define GEM_THRSH_512 3 23891398Stmm#define GEM_THRSH_1024 4 23991398Stmm#define GEM_THRSH_2048 5 24091398Stmm 24191398Stmm#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 24291398Stmm#define GEM_RX_CONFIG_FBOFF_SHFT 10 24391398Stmm#define GEM_RX_CONFIG_CXM_START_SHFT 13 24491398Stmm 24591398Stmm/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 24691398Stmm#define GEM_RX_PTH_XOFF_THRESH 0x000001ff 24799726Sbenno#define GEM_RX_PTH_XON_THRESH 0x001ff000 24891398Stmm 24991398Stmm/* GEM_RX_BLANKING register bits */ 25091398Stmm#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 25199726Sbenno#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 25299726Sbenno#define GEM_RX_BLANKING_TIME_SHIFT 12 25399726Sbenno/* One tick is 2048 PCI clocks, or 16us at 66MHz */ 25491398Stmm 25591398Stmm/* GEM_MAC registers */ 25691398Stmm#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 25791398Stmm#define GEM_MAC_RXRESET 0x6004 /* ditto */ 25891398Stmm#define GEM_MAC_SEND_PAUSE_CMD 0x6008 25991398Stmm#define GEM_MAC_TX_STATUS 0x6010 26091398Stmm#define GEM_MAC_RX_STATUS 0x6014 26191398Stmm#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 26291398Stmm#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 26391398Stmm#define GEM_MAC_RX_MASK 0x6024 26491398Stmm#define GEM_MAC_CONTROL_MASK 0x6028 26591398Stmm#define GEM_MAC_TX_CONFIG 0x6030 26691398Stmm#define GEM_MAC_RX_CONFIG 0x6034 26791398Stmm#define GEM_MAC_CONTROL_CONFIG 0x6038 26891398Stmm#define GEM_MAC_XIF_CONFIG 0x603c 26991398Stmm#define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 27091398Stmm#define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 27191398Stmm#define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 272172334Smarius#define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ 27391398Stmm#define GEM_MAC_MAC_MIN_FRAME 0x6050 27491398Stmm#define GEM_MAC_MAC_MAX_FRAME 0x6054 27591398Stmm#define GEM_MAC_PREAMBLE_LEN 0x6058 27691398Stmm#define GEM_MAC_JAM_SIZE 0x605c 27791398Stmm#define GEM_MAC_ATTEMPT_LIMIT 0x6060 27891398Stmm#define GEM_MAC_CONTROL_TYPE 0x6064 27991398Stmm 28091398Stmm#define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 28191398Stmm#define GEM_MAC_ADDR1 0x6084 28291398Stmm#define GEM_MAC_ADDR2 0x6088 28391398Stmm#define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 28491398Stmm#define GEM_MAC_ADDR4 0x6090 28591398Stmm#define GEM_MAC_ADDR5 0x6094 28691398Stmm#define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 28791398Stmm#define GEM_MAC_ADDR7 0x609c 28891398Stmm#define GEM_MAC_ADDR8 0x60a0 28991398Stmm 29091398Stmm#define GEM_MAC_ADDR_FILTER0 0x60a4 29191398Stmm#define GEM_MAC_ADDR_FILTER1 0x60a8 29291398Stmm#define GEM_MAC_ADDR_FILTER2 0x60ac 29391398Stmm#define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 29491398Stmm#define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 29591398Stmm 29691398Stmm#define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 29791398Stmm#define GEM_MAC_HASH1 0x60c4 29891398Stmm#define GEM_MAC_HASH2 0x60c8 29991398Stmm#define GEM_MAC_HASH3 0x60cc 30091398Stmm#define GEM_MAC_HASH4 0x60d0 30191398Stmm#define GEM_MAC_HASH5 0x60d4 30291398Stmm#define GEM_MAC_HASH6 0x60d8 30391398Stmm#define GEM_MAC_HASH7 0x60dc 30491398Stmm#define GEM_MAC_HASH8 0x60e0 30591398Stmm#define GEM_MAC_HASH9 0x60e4 30691398Stmm#define GEM_MAC_HASH10 0x60e8 30791398Stmm#define GEM_MAC_HASH11 0x60ec 30891398Stmm#define GEM_MAC_HASH12 0x60f0 30991398Stmm#define GEM_MAC_HASH13 0x60f4 31091398Stmm#define GEM_MAC_HASH14 0x60f8 31191398Stmm#define GEM_MAC_HASH15 0x60fc 31291398Stmm 31391398Stmm#define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 31491398Stmm#define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 31591398Stmm#define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 31691398Stmm#define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 31791398Stmm#define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 31891398Stmm#define GEM_MAC_PEAK_ATTEMPTS 0x6114 31991398Stmm#define GEM_MAC_RX_FRAME_COUNT 0x6118 32091398Stmm#define GEM_MAC_RX_LEN_ERR_CNT 0x611c 32191398Stmm#define GEM_MAC_RX_ALIGN_ERR 0x6120 32291398Stmm#define GEM_MAC_RX_CRC_ERR_CNT 0x6124 32391398Stmm#define GEM_MAC_RX_CODE_VIOL 0x6128 32491398Stmm#define GEM_MAC_RANDOM_SEED 0x6130 325172334Smarius#define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */ 32691398Stmm 32791398Stmm/* GEM_MAC_SEND_PAUSE_CMD register bits */ 32891398Stmm#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 32991398Stmm#define GEM_MAC_PAUSE_CMD_SEND 0x00010000 33091398Stmm 33191398Stmm/* GEM_MAC_TX_STATUS and _MASK register bits */ 33291398Stmm#define GEM_MAC_TX_XMIT_DONE 0x00000001 33391398Stmm#define GEM_MAC_TX_UNDERRUN 0x00000002 33491398Stmm#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 33591398Stmm#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 33691398Stmm#define GEM_MAC_TX_ECC_EXP 0x00000010 33791398Stmm#define GEM_MAC_TX_LCC_EXP 0x00000020 33891398Stmm#define GEM_MAC_TX_FCC_EXP 0x00000040 33991398Stmm#define GEM_MAC_TX_DEFER_EXP 0x00000080 34091398Stmm#define GEM_MAC_TX_PEAK_EXP 0x00000100 34191398Stmm 34291398Stmm/* GEM_MAC_RX_STATUS and _MASK register bits */ 34391398Stmm#define GEM_MAC_RX_DONE 0x00000001 34491398Stmm#define GEM_MAC_RX_OVERFLOW 0x00000002 34591398Stmm#define GEM_MAC_RX_FRAME_CNT 0x00000004 34691398Stmm#define GEM_MAC_RX_ALIGN_EXP 0x00000008 34791398Stmm#define GEM_MAC_RX_CRC_EXP 0x00000010 34891398Stmm#define GEM_MAC_RX_LEN_EXP 0x00000020 34991398Stmm#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 35091398Stmm 35191398Stmm/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 35291398Stmm#define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 35391398Stmm#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 35491398Stmm#define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 355172334Smarius#define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */ 356172334Smarius#define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 35791398Stmm 358172334Smarius#define GEM_MAC_PAUSE_TIME_SHFT 16 359172334Smarius#define GEM_MAC_PAUSE_TIME(x) \ 360172334Smarius (((x) & GEM_MAC_PAUSE_TIME_SLTS) >> GEM_MAC_PAUSE_TIME_SHFT) 361172334Smarius 36291398Stmm/* GEM_MAC_XIF_CONFIG register bits */ 36391398Stmm#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 36491398Stmm#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 36591398Stmm#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 36699726Sbenno#define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 36791398Stmm#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 36891398Stmm#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 36991398Stmm#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 370172334Smarius#define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 371172334Smarius "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 372172334Smarius "b\6FDLED\0\0" 37391398Stmm 374172334Smarius/* 375172334Smarius * GEM_MAC_SLOT_TIME register 376172334Smarius * The slot time is used as PAUSE time unit, value depends on whether carrier 377172334Smarius * extension is enabled. 378172334Smarius */ 379172334Smarius#define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 380172334Smarius#define GEM_MAC_SLOT_TIME_NORMAL 0x40 381172334Smarius 38291398Stmm/* GEM_MAC_TX_CONFIG register bits */ 38391398Stmm#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 38491398Stmm#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 385172334Smarius#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 386174987Smarius#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */ 38791398Stmm#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 38891398Stmm#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 38991398Stmm#define GEM_MAC_TX_NO_BACKOFF 0x00000040 39091398Stmm#define GEM_MAC_TX_SLOWDOWN 0x00000080 39191398Stmm#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 39291398Stmm#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 393194763Smarius/* Carrier Extension is required for half duplex Gbps operation. */ 394172334Smarius#define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 395172334Smarius "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 396172334Smarius "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 397172334Smarius "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 398172334Smarius "b\x9TXCARREXT\0\0" 39991398Stmm 40091398Stmm/* GEM_MAC_RX_CONFIG register bits */ 40191398Stmm#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 40291398Stmm#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 40391398Stmm#define GEM_MAC_RX_STRIP_CRC 0x00000004 40491398Stmm#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 40591398Stmm#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 40691398Stmm#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 40791398Stmm#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 40891398Stmm#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 40991398Stmm#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 41091398Stmm/* 41191398Stmm * Carrier Extension enables reception of packet bursts generated by 41291398Stmm * senders with carrier extension enabled. 41391398Stmm */ 414172334Smarius#define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 415172334Smarius "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 416172334Smarius "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 417172334Smarius "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 41891398Stmm 41991398Stmm/* GEM_MAC_CONTROL_CONFIG bits */ 42091398Stmm#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 42191398Stmm#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 42291398Stmm#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 423172334Smarius#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 42491398Stmm 425194763Smarius/* 426194763Smarius * MIF registers 427194763Smarius * Bit bang registers use low bit only. 428194763Smarius */ 42991398Stmm#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 43091398Stmm#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 43191398Stmm#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 43291398Stmm#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 43391398Stmm#define GEM_MIF_CONFIG 0x6210 434194763Smarius#define GEM_MIF_MASK 0x6214 435194763Smarius#define GEM_MIF_STATUS 0x6218 43691398Stmm#define GEM_MIF_STATE_MACHINE 0x621c 43791398Stmm 43891398Stmm/* GEM_MIF_FRAME bits */ 43991398Stmm#define GEM_MIF_FRAME_DATA 0x0000ffff 440194763Smarius#define GEM_MIF_FRAME_TA0 0x00010000 /* TA LSB, 1 for completion */ 441194763Smarius#define GEM_MIF_FRAME_TA1 0x00020000 /* TA MSB, 1 for instruction */ 44291398Stmm#define GEM_MIF_FRAME_REG_ADDR 0x007c0000 443194763Smarius#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address */ 44491398Stmm#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 44591398Stmm#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 44691398Stmm 44791398Stmm#define GEM_MIF_FRAME_READ 0x60020000 44891398Stmm#define GEM_MIF_FRAME_WRITE 0x50020000 44991398Stmm 45091398Stmm#define GEM_MIF_REG_SHIFT 18 45191398Stmm#define GEM_MIF_PHY_SHIFT 23 45291398Stmm 45391398Stmm/* GEM_MIF_CONFIG register bits */ 454194763Smarius#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0: MDIO_0 */ 45591398Stmm#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 45691398Stmm#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 45791398Stmm#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 458194763Smarius#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 attached/data */ 459194763Smarius#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 attached/data */ 46091398Stmm#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 461174987Smarius/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */ 462172334Smarius#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 463172334Smarius "b\x8MDIO0\0b\x9MDIO1\0\0" 46491398Stmm 465194763Smarius/* GEM_MIF_STATUS and GEM_MIF_MASK bits */ 466194763Smarius#define GEM_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */ 467194763Smarius#define GEM_MIF_POLL_STATUS_SHFT 0 468194763Smarius#define GEM_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */ 469194763Smarius#define GEM_MIF_POLL_DATA_SHFT 8 47091398Stmm/* 47191398Stmm * The Basic part is the last value read in the POLL field of the config 47291398Stmm * register. 47391398Stmm * The status part indicates the bits that have changed. 47491398Stmm */ 47591398Stmm 476174987Smarius/* GEM PCS/Serial link registers */ 477172334Smarius/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 47891398Stmm#define GEM_MII_CONTROL 0x9000 47991398Stmm#define GEM_MII_STATUS 0x9004 48091398Stmm#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 481172334Smarius#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 48291398Stmm#define GEM_MII_CONFIG 0x9010 48391398Stmm#define GEM_MII_STATE_MACHINE 0x9014 484172334Smarius#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ 48591398Stmm#define GEM_MII_DATAPATH_MODE 0x9050 48691398Stmm#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 48791398Stmm#define GEM_MII_OUTPUT_SELECT 0x9058 488194763Smarius#define GEM_MII_SLINK_STATUS 0x905c /* Serialink status */ 48991398Stmm 490172334Smarius/* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */ 491194763Smarius#define GEM_MII_CONTROL_1000M 0x00000040 /* 1000Mbps speed select */ 492194763Smarius#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 493194763Smarius#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full-duplex, always 0 */ 494194763Smarius#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto-negotiation */ 495194763Smarius#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY from MII */ 496194763Smarius#define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down */ 497194763Smarius#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto-negotiation enable */ 498194763Smarius#define GEM_MII_CONTROL_10_100M 0x00002000 /* 10/100Mbps speed select */ 49991398Stmm#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 500194763Smarius#define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS. */ 501172334Smarius#define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 502172334Smarius "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 503172334Smarius "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 50491398Stmm 505172334Smarius/* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ 506194763Smarius#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability */ 507194763Smarius#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 508194763Smarius#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 509194763Smarius#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto-negotiate */ 51091398Stmm#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 511194763Smarius#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */ 512194763Smarius#define GEM_MII_STATUS_EXTENDED 0x00000100 /* extended status */ 513172334Smarius#define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 514194763Smarius "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0\0" 51591398Stmm 516172334Smarius/* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ 517194763Smarius#define GEM_MII_ANEG_FDUPLX 0x00000020 /* full-duplex */ 518194763Smarius#define GEM_MII_ANEG_HDUPLX 0x00000040 /* half-duplex */ 519194763Smarius#define GEM_MII_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */ 520194763Smarius#define GEM_MII_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */ 521194763Smarius#define GEM_MII_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */ 522194763Smarius#define GEM_MII_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */ 523194763Smarius#define GEM_MII_ANEG_RFLT_MASK \ 524194763Smarius(CAS_PCS_ANEG_RFLT_FAIL | CAS_PCS_ANEG_RFLT_OFF) 525194763Smarius#define GEM_MII_ANEG_ACK 0x00004000 /* acknowledge */ 526194763Smarius#define GEM_MII_ANEG_NP 0x00008000 /* next page */ 527172334Smarius#define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 528172334Smarius "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 529172334Smarius "\b\xfNPBIT\0\0" 53091398Stmm 53191398Stmm/* GEM_MII_CONFIG reg */ 532194763Smarius#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS. */ 533194763Smarius#define GEM_MII_CONFIG_SDO 0x00000002 /* signal detect override */ 534194763Smarius#define GEM_MII_CONFIG_SDL 0x00000004 /* signal detect active-low */ 535194763Smarius#define GEM_MII_CONFIG_JS_NORM 0x00000000 /* jitter study - normal op. */ 536194763Smarius#define GEM_MII_CONFIG_JS_HF 0x00000008 /* jitter study - HF test */ 537194763Smarius#define GEM_MII_CONFIG_JS_LF 0x00000010 /* jitter study - LF test */ 538194763Smarius#define GEM_MII_CONFIG_JS_MASK \ 539194763Smarius (GEM_MII_CONFIG_JS_HF | GEM_MII_CONFIG_JS_LF) 540194763Smarius#define GEM_MII_CONFIG_ANTO 0x00000020 /* auto-neg. timer override */ 541172334Smarius#define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 54291398Stmm 543172334Smarius/* 544172334Smarius * GEM_MII_INTERRUP_STATUS reg 545172334Smarius * No mask register; mask with the global interrupt mask register. 546172334Smarius */ 547172334Smarius#define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */ 548172334Smarius 54991398Stmm/* GEM_MII_DATAPATH_MODE reg */ 550194763Smarius#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serialink */ 551194763Smarius#define GEM_MII_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */ 552194763Smarius#define GEM_MII_DATAPATH_MII 0x00000004 /* GMII/MII */ 553194763Smarius#define GEM_MII_DATAPATH_GMIIOE 0x00000008 /* serial output on GMII en. */ 554172334Smarius#define GEM_MII_DATAPATH_BITS "\177\020" \ 555194763Smarius "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3GMIIOE\0\0" 55691398Stmm 55791398Stmm/* GEM_MII_SLINK_CONTROL reg */ 558194763Smarius#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at SL, logic 559172334Smarius * reversed for SERDES */ 56091398Stmm#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 561194763Smarius#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock to reference clock */ 562194763Smarius#define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */ 563194763Smarius#define GEM_MII_SLINK_SELFTEST 0x000001c0 /* self-test */ 564194763Smarius#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink. */ 565194763Smarius#define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink. */ 566194763Smarius#define GEM_MII_SLINK_RX_POLE 0x00003000 /* PLL input to Serialink. */ 567194763Smarius#define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink. */ 568194763Smarius#define GEM_MII_SLINK_TX_POLE 0x00030000 /* PLL input to Serialink. */ 569172334Smarius#define GEM_MII_SLINK_CONTROL_BITS \ 570172334Smarius "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 571172334Smarius "\0b\3EMPHASIS\0b\x9PWRDWN\0\0" 57291398Stmm 57391398Stmm/* GEM_MII_SLINK_STATUS reg */ 57491398Stmm#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 575194763Smarius#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us w/ lockrefn */ 57691398Stmm#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 57791398Stmm#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 57891398Stmm 579172334Smarius/* 580172334Smarius * PCI Expansion ROM runtime access 581172334Smarius * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half 582172334Smarius * of the first register bank, although they only support up to 64KB ROMs. 583172334Smarius */ 584172334Smarius#define GEM_PCI_ROM_OFFSET 0x100000 585172334Smarius#define GEM_PCI_ROM_SIZE 0x10000 58691398Stmm 587194763Smarius/* Wired PHY addresses */ 58891398Stmm#define GEM_PHYAD_INTERNAL 1 58991398Stmm#define GEM_PHYAD_EXTERNAL 0 59091398Stmm 591223944Smarius/* Miscellaneous */ 592223944Smarius#define GEM_ERI_CACHE_LINE_SIZE 16 593223944Smarius#define GEM_ERI_LATENCY_TIMER 64 594223944Smarius 59591398Stmm/* 596194763Smarius * descriptor table structures 59791398Stmm */ 59891398Stmmstruct gem_desc { 59991398Stmm uint64_t gd_flags; 60091398Stmm uint64_t gd_addr; 60191398Stmm}; 60291398Stmm 603223944Smarius/* 604223944Smarius * Transmit flags 605223944Smarius * GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_START, GEM_TD_CXSUM_STUFF and 606223944Smarius * GEM_TD_INTERRUPT_ME only need to be set in the first descriptor of a group. 607223944Smarius */ 608194763Smarius#define GEM_TD_BUFSIZE 0x0000000000007fffULL 609194763Smarius#define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */ 610170273Syongari#define GEM_TD_CXSUM_STARTSHFT 15 611194763Smarius#define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */ 612170273Syongari#define GEM_TD_CXSUM_STUFFSHFT 21 613194763Smarius#define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */ 614194763Smarius#define GEM_TD_END_OF_PACKET 0x0000000040000000ULL 615194763Smarius#define GEM_TD_START_OF_PACKET 0x0000000080000000ULL 616194763Smarius#define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */ 617194763Smarius#define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */ 61891398Stmm 61991398Stmm/* Receive flags */ 620194763Smarius#define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */ 621194763Smarius#define GEM_RD_BUFSIZE 0x000000007fff0000ULL 622194763Smarius#define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */ 623194763Smarius#define GEM_RD_HASHVAL 0x0ffff00000000000ULL 624194763Smarius#define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 625194763Smarius#define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */ 626194763Smarius#define GEM_RD_BAD_CRC 0x4000000000000000ULL 62791398Stmm#define GEM_RD_BUFSHIFT 16 628172334Smarius#define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT) 62991398Stmm 63091398Stmm#endif 631