if_gem.c revision 95533
191398Stmm/* 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 391398Stmm * All rights reserved. 491398Stmm * 591398Stmm * Redistribution and use in source and binary forms, with or without 691398Stmm * modification, are permitted provided that the following conditions 791398Stmm * are met: 891398Stmm * 1. Redistributions of source code must retain the above copyright 991398Stmm * notice, this list of conditions and the following disclaimer. 1091398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1191398Stmm * notice, this list of conditions and the following disclaimer in the 1291398Stmm * documentation and/or other materials provided with the distribution. 1391398Stmm * 1491398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1591398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1691398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1791398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1891398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1991398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2091398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2191398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2291398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2391398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2491398Stmm * SUCH DAMAGE. 2591398Stmm * 2691398Stmm * from: NetBSD: gem.c,v 1.9 2001/10/21 20:45:15 thorpej Exp 2791398Stmm * 2891398Stmm * $FreeBSD: head/sys/dev/gem/if_gem.c 95533 2002-04-26 22:48:23Z mike $ 2991398Stmm */ 3091398Stmm 3191398Stmm/* 3291398Stmm * Driver for Sun GEM ethernet controllers. 3391398Stmm */ 3491398Stmm 3591398Stmm#define GEM_DEBUG 3691398Stmm 3791398Stmm#include <sys/param.h> 3891398Stmm#include <sys/systm.h> 3991398Stmm#include <sys/bus.h> 4091398Stmm#include <sys/callout.h> 4195533Smike#include <sys/endian.h> 4291398Stmm#include <sys/mbuf.h> 4391398Stmm#include <sys/malloc.h> 4491398Stmm#include <sys/kernel.h> 4591398Stmm#include <sys/socket.h> 4691398Stmm#include <sys/sockio.h> 4791398Stmm 4891398Stmm#include <net/ethernet.h> 4991398Stmm#include <net/if.h> 5091398Stmm#include <net/if_arp.h> 5191398Stmm#include <net/if_dl.h> 5291398Stmm#include <net/if_media.h> 5391398Stmm 5491398Stmm#include <machine/bus.h> 5591398Stmm 5691398Stmm#include <dev/mii/mii.h> 5791398Stmm#include <dev/mii/miivar.h> 5891398Stmm 5991398Stmm#include <gem/if_gemreg.h> 6091398Stmm#include <gem/if_gemvar.h> 6191398Stmm 6291398Stmm#define TRIES 10000 6391398Stmm 6492739Salfredstatic void gem_start(struct ifnet *); 6592739Salfredstatic void gem_stop(struct ifnet *, int); 6692739Salfredstatic int gem_ioctl(struct ifnet *, u_long, caddr_t); 6792739Salfredstatic void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); 6892739Salfredstatic void gem_rxdma_callback(void *, bus_dma_segment_t *, int, int); 6992739Salfredstatic void gem_txdma_callback(void *, bus_dma_segment_t *, int, int); 7092739Salfredstatic void gem_tick(void *); 7192739Salfredstatic void gem_watchdog(struct ifnet *); 7292739Salfredstatic void gem_init(void *); 7392739Salfredstatic void gem_init_regs(struct gem_softc *sc); 7492739Salfredstatic int gem_ringsize(int sz); 7592739Salfredstatic int gem_meminit(struct gem_softc *); 7692739Salfredstatic int gem_dmamap_load_mbuf(struct gem_softc *, struct mbuf *, 7792739Salfred bus_dmamap_callback_t *, struct gem_txjob *, int); 7892739Salfredstatic void gem_dmamap_unload_mbuf(struct gem_softc *, struct gem_txjob *); 7992739Salfredstatic void gem_dmamap_commit_mbuf(struct gem_softc *, struct gem_txjob *); 8092739Salfredstatic void gem_mifinit(struct gem_softc *); 8192739Salfredstatic int gem_bitwait(struct gem_softc *sc, bus_addr_t r, 8292739Salfred u_int32_t clr, u_int32_t set); 8392739Salfredstatic int gem_reset_rx(struct gem_softc *); 8492739Salfredstatic int gem_reset_tx(struct gem_softc *); 8592739Salfredstatic int gem_disable_rx(struct gem_softc *); 8692739Salfredstatic int gem_disable_tx(struct gem_softc *); 8792739Salfredstatic void gem_rxdrain(struct gem_softc *); 8892739Salfredstatic int gem_add_rxbuf(struct gem_softc *, int); 8992739Salfredstatic void gem_setladrf(struct gem_softc *); 9091398Stmm 9192739Salfredstruct mbuf *gem_get(struct gem_softc *, int, int); 9292739Salfredstatic void gem_eint(struct gem_softc *, u_int); 9392739Salfredstatic void gem_rint(struct gem_softc *); 9493045Stmmstatic void gem_rint_timeout(void *); 9592739Salfredstatic void gem_tint(struct gem_softc *); 9691398Stmm#ifdef notyet 9792739Salfredstatic void gem_power(int, void *); 9891398Stmm#endif 9991398Stmm 10091398Stmmdevclass_t gem_devclass; 10191398StmmDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 10291398StmmMODULE_DEPEND(gem, miibus, 1, 1, 1); 10391398Stmm 10491398Stmm#ifdef GEM_DEBUG 10591398Stmm#define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 10691398Stmm printf x 10791398Stmm#include <sys/ktr.h> 10891398Stmm#define KTR_GEM KTR_CT2 10991398Stmm#else 11091398Stmm#define DPRINTF(sc, x) /* nothing */ 11191398Stmm#endif 11291398Stmm 11391398Stmm#define GEM_NSEGS GEM_NTXSEGS 11491398Stmm 11591398Stmm/* 11691398Stmm * gem_attach: 11791398Stmm * 11891398Stmm * Attach a Gem interface to the system. 11991398Stmm */ 12091398Stmmint 12191398Stmmgem_attach(sc) 12291398Stmm struct gem_softc *sc; 12391398Stmm{ 12491398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 12591398Stmm struct mii_softc *child; 12691398Stmm int i, error; 12791398Stmm 12891398Stmm /* Make sure the chip is stopped. */ 12991398Stmm ifp->if_softc = sc; 13091398Stmm gem_reset(sc); 13191398Stmm 13291398Stmm error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 13391398Stmm BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS, 13491398Stmm BUS_SPACE_MAXSIZE_32BIT, 0, &sc->sc_pdmatag); 13591398Stmm if (error) 13691398Stmm return (error); 13791398Stmm 13891398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 13991398Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE, 14091398Stmm GEM_NSEGS, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, 14191398Stmm &sc->sc_dmatag); 14291398Stmm if (error) 14391398Stmm goto fail_0; 14491398Stmm 14591398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 14691398Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 14791398Stmm sizeof(struct gem_control_data), 1, 14891398Stmm sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW, 14991398Stmm &sc->sc_cdmatag); 15091398Stmm if (error) 15191398Stmm goto fail_1; 15291398Stmm 15391398Stmm /* 15491398Stmm * Allocate the control data structures, and create and load the 15591398Stmm * DMA map for it. 15691398Stmm */ 15791398Stmm if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 15891398Stmm (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) { 15991398Stmm device_printf(sc->sc_dev, "unable to allocate control data," 16091398Stmm " error = %d\n", error); 16191398Stmm goto fail_2; 16291398Stmm } 16391398Stmm 16491398Stmm sc->sc_cddma = 0; 16591398Stmm if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 16691398Stmm sc->sc_control_data, sizeof(struct gem_control_data), 16791398Stmm gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 16891398Stmm device_printf(sc->sc_dev, "unable to load control data DMA " 16991398Stmm "map, error = %d\n", error); 17091398Stmm goto fail_3; 17191398Stmm } 17291398Stmm 17391398Stmm /* 17491398Stmm * Initialize the transmit job descriptors. 17591398Stmm */ 17691398Stmm STAILQ_INIT(&sc->sc_txfreeq); 17791398Stmm STAILQ_INIT(&sc->sc_txdirtyq); 17891398Stmm 17991398Stmm /* 18091398Stmm * Create the transmit buffer DMA maps. 18191398Stmm */ 18291398Stmm error = ENOMEM; 18391398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 18491398Stmm struct gem_txsoft *txs; 18591398Stmm 18691398Stmm txs = &sc->sc_txsoft[i]; 18791398Stmm txs->txs_mbuf = NULL; 18891398Stmm txs->txs_ndescs = 0; 18991398Stmm if ((error = bus_dmamap_create(sc->sc_dmatag, 0, 19091398Stmm &txs->txs_dmamap)) != 0) { 19191398Stmm device_printf(sc->sc_dev, "unable to create tx DMA map " 19291398Stmm "%d, error = %d\n", i, error); 19391398Stmm goto fail_4; 19491398Stmm } 19591398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 19691398Stmm } 19791398Stmm 19891398Stmm /* 19991398Stmm * Create the receive buffer DMA maps. 20091398Stmm */ 20191398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 20291398Stmm if ((error = bus_dmamap_create(sc->sc_dmatag, 0, 20391398Stmm &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 20491398Stmm device_printf(sc->sc_dev, "unable to create rx DMA map " 20591398Stmm "%d, error = %d\n", i, error); 20691398Stmm goto fail_5; 20791398Stmm } 20891398Stmm sc->sc_rxsoft[i].rxs_mbuf = NULL; 20991398Stmm } 21091398Stmm 21191398Stmm 21291398Stmm gem_mifinit(sc); 21391398Stmm 21491398Stmm if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange, 21591398Stmm gem_mediastatus)) != 0) { 21691398Stmm device_printf(sc->sc_dev, "phy probe failed: %d\n", error); 21791398Stmm goto fail_5; 21891398Stmm } 21991398Stmm sc->sc_mii = device_get_softc(sc->sc_miibus); 22091398Stmm 22191398Stmm /* 22291398Stmm * From this point forward, the attachment cannot fail. A failure 22391398Stmm * before this point releases all resources that may have been 22491398Stmm * allocated. 22591398Stmm */ 22691398Stmm 22791398Stmm /* Announce ourselves. */ 22891398Stmm device_printf(sc->sc_dev, "Ethernet address:"); 22991398Stmm for (i = 0; i < 6; i++) 23091398Stmm printf("%c%02x", i > 0 ? ':' : ' ', sc->sc_arpcom.ac_enaddr[i]); 23191398Stmm printf("\n"); 23291398Stmm 23391398Stmm /* Initialize ifnet structure. */ 23491398Stmm ifp->if_softc = sc; 23591398Stmm ifp->if_unit = device_get_unit(sc->sc_dev); 23691398Stmm ifp->if_name = "gem"; 23791398Stmm ifp->if_mtu = ETHERMTU; 23891398Stmm ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 23991398Stmm ifp->if_start = gem_start; 24091398Stmm ifp->if_ioctl = gem_ioctl; 24191398Stmm ifp->if_watchdog = gem_watchdog; 24291398Stmm ifp->if_init = gem_init; 24391398Stmm ifp->if_output = ether_output; 24491398Stmm ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN; 24591398Stmm /* 24691398Stmm * Walk along the list of attached MII devices and 24791398Stmm * establish an `MII instance' to `phy number' 24891398Stmm * mapping. We'll use this mapping in media change 24991398Stmm * requests to determine which phy to use to program 25091398Stmm * the MIF configuration register. 25191398Stmm */ 25291398Stmm for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL; 25391398Stmm child = LIST_NEXT(child, mii_list)) { 25491398Stmm /* 25591398Stmm * Note: we support just two PHYs: the built-in 25691398Stmm * internal device and an external on the MII 25791398Stmm * connector. 25891398Stmm */ 25991398Stmm if (child->mii_phy > 1 || child->mii_inst > 1) { 26091398Stmm device_printf(sc->sc_dev, "cannot accomodate " 26191398Stmm "MII device %s at phy %d, instance %d\n", 26291398Stmm device_get_name(child->mii_dev), 26391398Stmm child->mii_phy, child->mii_inst); 26491398Stmm continue; 26591398Stmm } 26691398Stmm 26791398Stmm sc->sc_phys[child->mii_inst] = child->mii_phy; 26891398Stmm } 26991398Stmm 27091398Stmm /* 27191398Stmm * Now select and activate the PHY we will use. 27291398Stmm * 27391398Stmm * The order of preference is External (MDI1), 27491398Stmm * Internal (MDI0), Serial Link (no MII). 27591398Stmm */ 27691398Stmm if (sc->sc_phys[1]) { 27791398Stmm#ifdef GEM_DEBUG 27891398Stmm printf("using external phy\n"); 27991398Stmm#endif 28091398Stmm sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 28191398Stmm } else { 28291398Stmm#ifdef GEM_DEBUG 28391398Stmm printf("using internal phy\n"); 28491398Stmm#endif 28591398Stmm sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 28691398Stmm } 28791398Stmm bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 28891398Stmm sc->sc_mif_config); 28991398Stmm /* Attach the interface. */ 29091398Stmm ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 29191398Stmm 29291398Stmm#if notyet 29391398Stmm /* 29491398Stmm * Add a suspend hook to make sure we come back up after a 29591398Stmm * resume. 29691398Stmm */ 29791398Stmm sc->sc_powerhook = powerhook_establish(gem_power, sc); 29891398Stmm if (sc->sc_powerhook == NULL) 29991398Stmm device_printf(sc->sc_dev, "WARNING: unable to establish power " 30091398Stmm "hook\n"); 30191398Stmm#endif 30291398Stmm 30391398Stmm callout_init(&sc->sc_tick_ch, 0); 30493045Stmm callout_init(&sc->sc_rx_ch, 0); 30591398Stmm return (0); 30691398Stmm 30791398Stmm /* 30891398Stmm * Free any resources we've allocated during the failed attach 30991398Stmm * attempt. Do this in reverse order and fall through. 31091398Stmm */ 31191398Stmmfail_5: 31291398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 31391398Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 31491398Stmm bus_dmamap_destroy(sc->sc_dmatag, 31591398Stmm sc->sc_rxsoft[i].rxs_dmamap); 31691398Stmm } 31791398Stmmfail_4: 31891398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 31991398Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 32091398Stmm bus_dmamap_destroy(sc->sc_dmatag, 32191398Stmm sc->sc_txsoft[i].txs_dmamap); 32291398Stmm } 32391398Stmm bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 32491398Stmmfail_3: 32591398Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 32691398Stmm sc->sc_cddmamap); 32791398Stmmfail_2: 32891398Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 32991398Stmmfail_1: 33091398Stmm bus_dma_tag_destroy(sc->sc_dmatag); 33191398Stmmfail_0: 33291398Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 33391398Stmm return (error); 33491398Stmm} 33591398Stmm 33691398Stmmstatic void 33791398Stmmgem_cddma_callback(xsc, segs, nsegs, error) 33891398Stmm void *xsc; 33991398Stmm bus_dma_segment_t *segs; 34091398Stmm int nsegs; 34191398Stmm int error; 34291398Stmm{ 34391398Stmm struct gem_softc *sc = (struct gem_softc *)xsc; 34491398Stmm 34591398Stmm if (error != 0) 34691398Stmm return; 34791398Stmm if (nsegs != 1) { 34891398Stmm /* can't happen... */ 34991398Stmm panic("gem_cddma_callback: bad control buffer segment count"); 35091398Stmm } 35191398Stmm sc->sc_cddma = segs[0].ds_addr; 35291398Stmm} 35391398Stmm 35491398Stmmstatic void 35591398Stmmgem_rxdma_callback(xsc, segs, nsegs, error) 35691398Stmm void *xsc; 35791398Stmm bus_dma_segment_t *segs; 35891398Stmm int nsegs; 35991398Stmm int error; 36091398Stmm{ 36191398Stmm struct gem_rxsoft *rxs = (struct gem_rxsoft *)xsc; 36291398Stmm 36391398Stmm if (error != 0) 36491398Stmm return; 36591398Stmm if (nsegs != 1) { 36691398Stmm /* can't happen... */ 36791398Stmm panic("gem_rxdma_callback: bad control buffer segment count"); 36891398Stmm } 36991398Stmm rxs->rxs_paddr = segs[0].ds_addr; 37091398Stmm} 37191398Stmm 37291398Stmm/* 37391398Stmm * This is called multiple times in our version of dmamap_load_mbuf, but should 37491398Stmm * be fit for a generic version that only calls it once. 37591398Stmm */ 37691398Stmmstatic void 37791398Stmmgem_txdma_callback(xsc, segs, nsegs, error) 37891398Stmm void *xsc; 37991398Stmm bus_dma_segment_t *segs; 38091398Stmm int nsegs; 38191398Stmm int error; 38291398Stmm{ 38391398Stmm struct gem_txdma *tx = (struct gem_txdma *)xsc; 38491398Stmm int seg; 38591398Stmm 38691398Stmm tx->txd_error = error; 38791398Stmm if (error != 0) 38891398Stmm return; 38991398Stmm tx->txd_nsegs = nsegs; 39091398Stmm 39191398Stmm /* 39291398Stmm * Initialize the transmit descriptors. 39391398Stmm */ 39491398Stmm for (seg = 0; seg < nsegs; 39591398Stmm seg++, tx->txd_nexttx = GEM_NEXTTX(tx->txd_nexttx)) { 39691398Stmm uint64_t flags; 39791398Stmm 39891398Stmm DPRINTF(tx->txd_sc, ("txdma_cb: mapping seg %d (txd %d), len " 39991398Stmm "%lx, addr %#lx (%#lx)\n", seg, tx->txd_nexttx, 40091398Stmm segs[seg].ds_len, segs[seg].ds_addr, 40191398Stmm GEM_DMA_WRITE(tx->txd_sc, segs[seg].ds_addr))); 40291398Stmm CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len " 40391398Stmm "%lx, addr %#lx (%#lx)", seg, tx->txd_nexttx, 40491398Stmm segs[seg].ds_len, segs[seg].ds_addr, 40591398Stmm GEM_DMA_WRITE(tx->txd_sc, segs[seg].ds_addr)); 40691398Stmm /* 40791398Stmm * If this is the first descriptor we're 40891398Stmm * enqueueing, set the start of packet flag, 40991398Stmm * and the checksum stuff if we want the hardware 41091398Stmm * to do it. 41191398Stmm */ 41291398Stmm tx->txd_sc->sc_txdescs[tx->txd_nexttx].gd_addr = 41391398Stmm GEM_DMA_WRITE(tx->txd_sc, segs[seg].ds_addr); 41491398Stmm flags = segs[seg].ds_len & GEM_TD_BUFSIZE; 41591398Stmm if ((tx->txd_flags & GTXD_FIRST) != 0 && seg == 0) { 41691398Stmm CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, " 41791398Stmm "tx %d", seg, tx->txd_nexttx); 41891398Stmm flags |= GEM_TD_START_OF_PACKET; 41991398Stmm } 42091398Stmm if ((tx->txd_flags & GTXD_LAST) != 0 && seg == nsegs - 1) { 42191398Stmm CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, " 42291398Stmm "tx %d", seg, tx->txd_nexttx); 42391398Stmm flags |= GEM_TD_END_OF_PACKET; 42491398Stmm } 42591398Stmm tx->txd_sc->sc_txdescs[tx->txd_nexttx].gd_flags = 42691398Stmm GEM_DMA_WRITE(tx->txd_sc, flags); 42791398Stmm tx->txd_lasttx = tx->txd_nexttx; 42891398Stmm } 42991398Stmm} 43091398Stmm 43191398Stmmstatic void 43291398Stmmgem_tick(arg) 43391398Stmm void *arg; 43491398Stmm{ 43591398Stmm struct gem_softc *sc = arg; 43691398Stmm int s; 43791398Stmm 43891398Stmm s = splnet(); 43991398Stmm mii_tick(sc->sc_mii); 44091398Stmm splx(s); 44191398Stmm 44291398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 44391398Stmm} 44491398Stmm 44591398Stmmstatic int 44691398Stmmgem_bitwait(sc, r, clr, set) 44791398Stmm struct gem_softc *sc; 44891398Stmm bus_addr_t r; 44991398Stmm u_int32_t clr; 45091398Stmm u_int32_t set; 45191398Stmm{ 45291398Stmm int i; 45391398Stmm u_int32_t reg; 45491398Stmm 45591398Stmm for (i = TRIES; i--; DELAY(100)) { 45691398Stmm reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 45791398Stmm if ((r & clr) == 0 && (r & set) == set) 45891398Stmm return (1); 45991398Stmm } 46091398Stmm return (0); 46191398Stmm} 46291398Stmm 46391398Stmmvoid 46491398Stmmgem_reset(sc) 46591398Stmm struct gem_softc *sc; 46691398Stmm{ 46791398Stmm bus_space_tag_t t = sc->sc_bustag; 46891398Stmm bus_space_handle_t h = sc->sc_h; 46991398Stmm int s; 47091398Stmm 47191398Stmm s = splnet(); 47291398Stmm DPRINTF(sc, ("%s: gem_reset\n", device_get_name(sc->sc_dev))); 47391398Stmm CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 47491398Stmm gem_reset_rx(sc); 47591398Stmm gem_reset_tx(sc); 47691398Stmm 47791398Stmm /* Do a full reset */ 47891398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 47991398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 48091398Stmm device_printf(sc->sc_dev, "cannot reset device\n"); 48191398Stmm splx(s); 48291398Stmm} 48391398Stmm 48491398Stmm 48591398Stmm/* 48691398Stmm * gem_rxdrain: 48791398Stmm * 48891398Stmm * Drain the receive queue. 48991398Stmm */ 49091398Stmmstatic void 49191398Stmmgem_rxdrain(sc) 49291398Stmm struct gem_softc *sc; 49391398Stmm{ 49491398Stmm struct gem_rxsoft *rxs; 49591398Stmm int i; 49691398Stmm 49791398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 49891398Stmm rxs = &sc->sc_rxsoft[i]; 49991398Stmm if (rxs->rxs_mbuf != NULL) { 50091398Stmm bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 50191398Stmm m_freem(rxs->rxs_mbuf); 50291398Stmm rxs->rxs_mbuf = NULL; 50391398Stmm } 50491398Stmm } 50591398Stmm} 50691398Stmm 50791398Stmm/* 50891398Stmm * Reset the whole thing. 50991398Stmm */ 51091398Stmmstatic void 51191398Stmmgem_stop(ifp, disable) 51291398Stmm struct ifnet *ifp; 51391398Stmm int disable; 51491398Stmm{ 51591398Stmm struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 51691398Stmm struct gem_txsoft *txs; 51791398Stmm 51891398Stmm DPRINTF(sc, ("%s: gem_stop\n", device_get_name(sc->sc_dev))); 51991398Stmm CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev)); 52091398Stmm 52191398Stmm callout_stop(&sc->sc_tick_ch); 52291398Stmm 52391398Stmm /* XXX - Should we reset these instead? */ 52491398Stmm gem_disable_tx(sc); 52591398Stmm gem_disable_rx(sc); 52691398Stmm 52791398Stmm /* 52891398Stmm * Release any queued transmit buffers. 52991398Stmm */ 53091398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 53191398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 53291398Stmm if (txs->txs_ndescs != 0) { 53391398Stmm bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 53491398Stmm if (txs->txs_mbuf != NULL) { 53591398Stmm m_freem(txs->txs_mbuf); 53691398Stmm txs->txs_mbuf = NULL; 53791398Stmm } 53891398Stmm } 53991398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 54091398Stmm } 54191398Stmm 54291398Stmm if (disable) 54391398Stmm gem_rxdrain(sc); 54491398Stmm 54591398Stmm /* 54691398Stmm * Mark the interface down and cancel the watchdog timer. 54791398Stmm */ 54891398Stmm ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 54991398Stmm ifp->if_timer = 0; 55091398Stmm} 55191398Stmm 55291398Stmm/* 55391398Stmm * Reset the receiver 55491398Stmm */ 55591398Stmmint 55691398Stmmgem_reset_rx(sc) 55791398Stmm struct gem_softc *sc; 55891398Stmm{ 55991398Stmm bus_space_tag_t t = sc->sc_bustag; 56091398Stmm bus_space_handle_t h = sc->sc_h; 56191398Stmm 56291398Stmm /* 56391398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 56491398Stmm * disable DMA first. 56591398Stmm */ 56691398Stmm gem_disable_rx(sc); 56791398Stmm bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 56891398Stmm /* Wait till it finishes */ 56991398Stmm if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 57091398Stmm device_printf(sc->sc_dev, "cannot disable read dma\n"); 57191398Stmm 57291398Stmm /* Wait 5ms extra. */ 57391398Stmm DELAY(5000); 57491398Stmm 57591398Stmm /* Finally, reset the ERX */ 57691398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 57791398Stmm /* Wait till it finishes */ 57891398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 57991398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 58091398Stmm return (1); 58191398Stmm } 58291398Stmm return (0); 58391398Stmm} 58491398Stmm 58591398Stmm 58691398Stmm/* 58791398Stmm * Reset the transmitter 58891398Stmm */ 58991398Stmmstatic int 59091398Stmmgem_reset_tx(sc) 59191398Stmm struct gem_softc *sc; 59291398Stmm{ 59391398Stmm bus_space_tag_t t = sc->sc_bustag; 59491398Stmm bus_space_handle_t h = sc->sc_h; 59591398Stmm int i; 59691398Stmm 59791398Stmm /* 59891398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 59991398Stmm * disable DMA first. 60091398Stmm */ 60191398Stmm gem_disable_tx(sc); 60291398Stmm bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 60391398Stmm /* Wait till it finishes */ 60491398Stmm if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 60591398Stmm device_printf(sc->sc_dev, "cannot disable read dma\n"); 60691398Stmm 60791398Stmm /* Wait 5ms extra. */ 60891398Stmm DELAY(5000); 60991398Stmm 61091398Stmm /* Finally, reset the ETX */ 61191398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 61291398Stmm /* Wait till it finishes */ 61391398Stmm for (i = TRIES; i--; DELAY(100)) 61491398Stmm if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 61591398Stmm break; 61691398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 61791398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 61891398Stmm return (1); 61991398Stmm } 62091398Stmm return (0); 62191398Stmm} 62291398Stmm 62391398Stmm/* 62491398Stmm * disable receiver. 62591398Stmm */ 62691398Stmmstatic int 62791398Stmmgem_disable_rx(sc) 62891398Stmm struct gem_softc *sc; 62991398Stmm{ 63091398Stmm bus_space_tag_t t = sc->sc_bustag; 63191398Stmm bus_space_handle_t h = sc->sc_h; 63291398Stmm u_int32_t cfg; 63391398Stmm 63491398Stmm /* Flip the enable bit */ 63591398Stmm cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 63691398Stmm cfg &= ~GEM_MAC_RX_ENABLE; 63791398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 63891398Stmm 63991398Stmm /* Wait for it to finish */ 64091398Stmm return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 64191398Stmm} 64291398Stmm 64391398Stmm/* 64491398Stmm * disable transmitter. 64591398Stmm */ 64691398Stmmstatic int 64791398Stmmgem_disable_tx(sc) 64891398Stmm struct gem_softc *sc; 64991398Stmm{ 65091398Stmm bus_space_tag_t t = sc->sc_bustag; 65191398Stmm bus_space_handle_t h = sc->sc_h; 65291398Stmm u_int32_t cfg; 65391398Stmm 65491398Stmm /* Flip the enable bit */ 65591398Stmm cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 65691398Stmm cfg &= ~GEM_MAC_TX_ENABLE; 65791398Stmm bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 65891398Stmm 65991398Stmm /* Wait for it to finish */ 66091398Stmm return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 66191398Stmm} 66291398Stmm 66391398Stmm/* 66491398Stmm * Initialize interface. 66591398Stmm */ 66691398Stmmstatic int 66791398Stmmgem_meminit(sc) 66891398Stmm struct gem_softc *sc; 66991398Stmm{ 67091398Stmm struct gem_rxsoft *rxs; 67191398Stmm int i, error; 67291398Stmm 67391398Stmm /* 67491398Stmm * Initialize the transmit descriptor ring. 67591398Stmm */ 67691398Stmm memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 67791398Stmm for (i = 0; i < GEM_NTXDESC; i++) { 67891398Stmm sc->sc_txdescs[i].gd_flags = 0; 67991398Stmm sc->sc_txdescs[i].gd_addr = 0; 68091398Stmm } 68191398Stmm GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 68291398Stmm BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 68391398Stmm sc->sc_txfree = GEM_NTXDESC; 68491398Stmm sc->sc_txnext = 0; 68591398Stmm 68691398Stmm /* 68791398Stmm * Initialize the receive descriptor and receive job 68891398Stmm * descriptor rings. 68991398Stmm */ 69091398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 69191398Stmm rxs = &sc->sc_rxsoft[i]; 69291398Stmm if (rxs->rxs_mbuf == NULL) { 69391398Stmm if ((error = gem_add_rxbuf(sc, i)) != 0) { 69491398Stmm device_printf(sc->sc_dev, "unable to " 69591398Stmm "allocate or map rx buffer %d, error = " 69691398Stmm "%d\n", i, error); 69791398Stmm /* 69891398Stmm * XXX Should attempt to run with fewer receive 69991398Stmm * XXX buffers instead of just failing. 70091398Stmm */ 70191398Stmm gem_rxdrain(sc); 70291398Stmm return (1); 70391398Stmm } 70491398Stmm } else 70591398Stmm GEM_INIT_RXDESC(sc, i); 70691398Stmm } 70791398Stmm sc->sc_rxptr = 0; 70891398Stmm 70991398Stmm return (0); 71091398Stmm} 71191398Stmm 71291398Stmmstatic int 71391398Stmmgem_ringsize(sz) 71491398Stmm int sz; 71591398Stmm{ 71691398Stmm int v = 0; 71791398Stmm 71891398Stmm switch (sz) { 71991398Stmm case 32: 72091398Stmm v = GEM_RING_SZ_32; 72191398Stmm break; 72291398Stmm case 64: 72391398Stmm v = GEM_RING_SZ_64; 72491398Stmm break; 72591398Stmm case 128: 72691398Stmm v = GEM_RING_SZ_128; 72791398Stmm break; 72891398Stmm case 256: 72991398Stmm v = GEM_RING_SZ_256; 73091398Stmm break; 73191398Stmm case 512: 73291398Stmm v = GEM_RING_SZ_512; 73391398Stmm break; 73491398Stmm case 1024: 73591398Stmm v = GEM_RING_SZ_1024; 73691398Stmm break; 73791398Stmm case 2048: 73891398Stmm v = GEM_RING_SZ_2048; 73991398Stmm break; 74091398Stmm case 4096: 74191398Stmm v = GEM_RING_SZ_4096; 74291398Stmm break; 74391398Stmm case 8192: 74491398Stmm v = GEM_RING_SZ_8192; 74591398Stmm break; 74691398Stmm default: 74791398Stmm printf("gem: invalid Receive Descriptor ring size\n"); 74891398Stmm break; 74991398Stmm } 75091398Stmm return (v); 75191398Stmm} 75291398Stmm 75391398Stmm/* 75491398Stmm * Initialization of interface; set up initialization block 75591398Stmm * and transmit/receive descriptor rings. 75691398Stmm */ 75791398Stmmstatic void 75891398Stmmgem_init(xsc) 75991398Stmm void *xsc; 76091398Stmm{ 76191398Stmm struct gem_softc *sc = (struct gem_softc *)xsc; 76291398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 76391398Stmm bus_space_tag_t t = sc->sc_bustag; 76491398Stmm bus_space_handle_t h = sc->sc_h; 76591398Stmm int s; 76691398Stmm u_int32_t v; 76791398Stmm 76891398Stmm s = splnet(); 76991398Stmm 77091398Stmm DPRINTF(sc, ("%s: gem_init: calling stop\n", device_get_name(sc->sc_dev))); 77191398Stmm CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 77291398Stmm /* 77391398Stmm * Initialization sequence. The numbered steps below correspond 77491398Stmm * to the sequence outlined in section 6.3.5.1 in the Ethernet 77591398Stmm * Channel Engine manual (part of the PCIO manual). 77691398Stmm * See also the STP2002-STQ document from Sun Microsystems. 77791398Stmm */ 77891398Stmm 77991398Stmm /* step 1 & 2. Reset the Ethernet Channel */ 78091398Stmm gem_stop(&sc->sc_arpcom.ac_if, 0); 78191398Stmm gem_reset(sc); 78291398Stmm DPRINTF(sc, ("%s: gem_init: restarting\n", device_get_name(sc->sc_dev))); 78391398Stmm CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev)); 78491398Stmm 78591398Stmm /* Re-initialize the MIF */ 78691398Stmm gem_mifinit(sc); 78791398Stmm 78891398Stmm /* Call MI reset function if any */ 78991398Stmm if (sc->sc_hwreset) 79091398Stmm (*sc->sc_hwreset)(sc); 79191398Stmm 79291398Stmm /* step 3. Setup data structures in host memory */ 79391398Stmm gem_meminit(sc); 79491398Stmm 79591398Stmm /* step 4. TX MAC registers & counters */ 79691398Stmm gem_init_regs(sc); 79791398Stmm /* XXX: VLAN code from NetBSD temporarily removed. */ 79891398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 79991398Stmm (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 80091398Stmm 80191398Stmm /* step 5. RX MAC registers & counters */ 80291398Stmm gem_setladrf(sc); 80391398Stmm 80491398Stmm /* step 6 & 7. Program Descriptor Ring Base Addresses */ 80591398Stmm /* NOTE: we use only 32-bit DMA addresses here. */ 80691398Stmm bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 80791398Stmm bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 80891398Stmm 80991398Stmm bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 81091398Stmm bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 81191398Stmm DPRINTF(sc, ("loading rx ring %lx, tx ring %lx, cddma %lx\n", 81291398Stmm GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma)); 81391398Stmm CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 81491398Stmm GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 81591398Stmm 81691398Stmm /* step 8. Global Configuration & Interrupt Mask */ 81791398Stmm bus_space_write_4(t, h, GEM_INTMASK, 81891398Stmm ~(GEM_INTR_TX_INTME| 81991398Stmm GEM_INTR_TX_EMPTY| 82091398Stmm GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 82191398Stmm GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 82291398Stmm GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 82391398Stmm GEM_INTR_BERR)); 82491398Stmm bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 82591398Stmm bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 82691398Stmm bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 82791398Stmm 82891398Stmm /* step 9. ETX Configuration: use mostly default values */ 82991398Stmm 83091398Stmm /* Enable DMA */ 83191398Stmm v = gem_ringsize(GEM_NTXDESC /*XXX*/); 83291398Stmm bus_space_write_4(t, h, GEM_TX_CONFIG, 83391398Stmm v|GEM_TX_CONFIG_TXDMA_EN| 83491398Stmm ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 83591398Stmm 83691398Stmm /* step 10. ERX Configuration */ 83791398Stmm 83891398Stmm /* Encode Receive Descriptor ring size: four possible values */ 83991398Stmm v = gem_ringsize(GEM_NRXDESC /*XXX*/); 84091398Stmm 84191398Stmm /* Enable DMA */ 84291398Stmm bus_space_write_4(t, h, GEM_RX_CONFIG, 84391398Stmm v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 84491398Stmm (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 84591398Stmm (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 84691398Stmm /* 84791398Stmm * The following value is for an OFF Threshold of about 15.5 Kbytes 84891398Stmm * and an ON Threshold of 4K bytes. 84991398Stmm */ 85091398Stmm bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 85191398Stmm bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 85291398Stmm 85391398Stmm /* step 11. Configure Media */ 85491398Stmm (void)gem_mii_statchg(sc->sc_dev); 85591398Stmm 85691398Stmm /* step 12. RX_MAC Configuration Register */ 85791398Stmm v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 85891398Stmm v |= GEM_MAC_RX_ENABLE; 85991398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 86091398Stmm 86191398Stmm /* step 14. Issue Transmit Pending command */ 86291398Stmm 86391398Stmm /* Call MI initialization function if any */ 86491398Stmm if (sc->sc_hwinit) 86591398Stmm (*sc->sc_hwinit)(sc); 86691398Stmm 86791398Stmm /* step 15. Give the reciever a swift kick */ 86891398Stmm bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 86991398Stmm 87091398Stmm /* Start the one second timer. */ 87191398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 87291398Stmm 87391398Stmm ifp->if_flags |= IFF_RUNNING; 87491398Stmm ifp->if_flags &= ~IFF_OACTIVE; 87591398Stmm ifp->if_timer = 0; 87691398Stmm sc->sc_flags = ifp->if_flags; 87791398Stmm splx(s); 87891398Stmm} 87991398Stmm 88091398Stmm/* 88191398Stmm * XXX: This is really a substitute for bus_dmamap_load_mbuf(), which FreeBSD 88291398Stmm * does not yet have, with some adaptions for this driver. 88391398Stmm * Some changes are mandated by the fact that multiple maps may needed to map 88491398Stmm * a single mbuf. 88591398Stmm * It should be removed once generic support is available. 88691398Stmm * 88791398Stmm * This is derived from NetBSD (syssrc/sys/arch/sparc64/sparc64/machdep.c), for 88891398Stmm * a copyright notice see sparc64/sparc64/bus_machdep.c. 88991398Stmm * 89091398Stmm * Not every error condition is passed to the callback in this version, and the 89191398Stmm * callback may be called more than once. 89291398Stmm * It also gropes in the entails of the callback arg... 89391398Stmm */ 89491398Stmmstatic int 89591398Stmmgem_dmamap_load_mbuf(sc, m0, cb, txj, flags) 89691398Stmm struct gem_softc *sc; 89791398Stmm struct mbuf *m0; 89891398Stmm bus_dmamap_callback_t *cb; 89991398Stmm struct gem_txjob *txj; 90091398Stmm int flags; 90191398Stmm{ 90291398Stmm struct gem_txdma txd; 90391398Stmm struct gem_txsoft *txs; 90491398Stmm struct mbuf *m; 90591398Stmm void *vaddr; 90691398Stmm int error, first = 1, len, totlen; 90791398Stmm 90891398Stmm if ((m0->m_flags & M_PKTHDR) == 0) 90991398Stmm panic("gem_dmamap_load_mbuf: no packet header"); 91091398Stmm totlen = m0->m_pkthdr.len; 91191398Stmm len = 0; 91291398Stmm txd.txd_sc = sc; 91391398Stmm txd.txd_nexttx = txj->txj_nexttx; 91491398Stmm txj->txj_nsegs = 0; 91591398Stmm STAILQ_INIT(&txj->txj_txsq); 91691398Stmm m = m0; 91791398Stmm while (m != NULL && len < totlen) { 91891398Stmm if (m->m_len == 0) 91991398Stmm continue; 92091398Stmm /* Get a work queue entry. */ 92191398Stmm if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 92291398Stmm /* 92391398Stmm * Ran out of descriptors, return a value that 92491398Stmm * cannot be returned by bus_dmamap_load to notify 92591398Stmm * the caller. 92691398Stmm */ 92791398Stmm error = -1; 92891398Stmm goto fail; 92991398Stmm } 93091398Stmm len += m->m_len; 93191398Stmm txd.txd_flags = first ? GTXD_FIRST : 0; 93291398Stmm if (m->m_next == NULL || len >= totlen) 93391398Stmm txd.txd_flags |= GTXD_LAST; 93491398Stmm vaddr = mtod(m, void *); 93591398Stmm error = bus_dmamap_load(sc->sc_dmatag, txs->txs_dmamap, vaddr, 93691398Stmm m->m_len, cb, &txd, flags); 93791398Stmm if (error != 0 || txd.txd_error != 0) 93891398Stmm goto fail; 93991398Stmm /* Sync the DMA map. */ 94091398Stmm bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 94191398Stmm BUS_DMASYNC_PREWRITE); 94291398Stmm m = m->m_next; 94391398Stmm /* 94491398Stmm * Store a pointer to the packet so we can free it later, 94591398Stmm * and remember what txdirty will be once the packet is 94691398Stmm * done. 94791398Stmm */ 94891398Stmm txs->txs_mbuf = first ? m0 : NULL; 94991398Stmm txs->txs_firstdesc = txj->txj_nexttx; 95091398Stmm txs->txs_lastdesc = txd.txd_lasttx; 95191398Stmm txs->txs_ndescs = txd.txd_nsegs; 95291398Stmm CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, " 95391398Stmm "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc, 95491398Stmm txs->txs_ndescs); 95591398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 95691398Stmm STAILQ_INSERT_TAIL(&txj->txj_txsq, txs, txs_q); 95791398Stmm txj->txj_nexttx = txd.txd_nexttx; 95891398Stmm txj->txj_nsegs += txd.txd_nsegs; 95991398Stmm first = 0; 96091398Stmm } 96191398Stmm txj->txj_lasttx = txd.txd_lasttx; 96291398Stmm return (0); 96391398Stmm 96491398Stmmfail: 96591398Stmm CTR1(KTR_GEM, "gem_dmamap_load_mbuf failed (%d)", error); 96691398Stmm gem_dmamap_unload_mbuf(sc, txj); 96791398Stmm return (error); 96891398Stmm} 96991398Stmm 97091398Stmm/* 97191398Stmm * Unload an mbuf using the txd the information was placed in. 97291398Stmm * The tx interrupt code frees the tx segments one by one, because the txd is 97391398Stmm * not available any more. 97491398Stmm */ 97591398Stmmstatic void 97691398Stmmgem_dmamap_unload_mbuf(sc, txj) 97791398Stmm struct gem_softc *sc; 97891398Stmm struct gem_txjob *txj; 97991398Stmm{ 98091398Stmm struct gem_txsoft *txs; 98191398Stmm 98291398Stmm /* Readd the removed descriptors and unload the segments. */ 98391398Stmm while ((txs = STAILQ_FIRST(&txj->txj_txsq)) != NULL) { 98491398Stmm bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 98591398Stmm STAILQ_REMOVE_HEAD(&txj->txj_txsq, txs_q); 98691398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 98791398Stmm } 98891398Stmm} 98991398Stmm 99091398Stmmstatic void 99191398Stmmgem_dmamap_commit_mbuf(sc, txj) 99291398Stmm struct gem_softc *sc; 99391398Stmm struct gem_txjob *txj; 99491398Stmm{ 99591398Stmm struct gem_txsoft *txs; 99691398Stmm 99791398Stmm /* Commit the txjob by transfering the txsoft's to the txdirtyq. */ 99891398Stmm while ((txs = STAILQ_FIRST(&txj->txj_txsq)) != NULL) { 99991398Stmm STAILQ_REMOVE_HEAD(&txj->txj_txsq, txs_q); 100091398Stmm STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 100191398Stmm } 100291398Stmm} 100391398Stmm 100491398Stmmstatic void 100591398Stmmgem_init_regs(sc) 100691398Stmm struct gem_softc *sc; 100791398Stmm{ 100891398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 100991398Stmm bus_space_tag_t t = sc->sc_bustag; 101091398Stmm bus_space_handle_t h = sc->sc_h; 101191398Stmm 101291398Stmm /* These regs are not cleared on reset */ 101391398Stmm sc->sc_inited = 0; 101491398Stmm if (!sc->sc_inited) { 101591398Stmm 101691398Stmm /* Wooo. Magic values. */ 101791398Stmm bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 101891398Stmm bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 101991398Stmm bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 102091398Stmm 102191398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 102291398Stmm /* Max frame and max burst size */ 102391398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 102491398Stmm (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 102591398Stmm bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 102691398Stmm bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 102791398Stmm bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 102891398Stmm /* Dunno.... */ 102991398Stmm bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 103091398Stmm bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 103191398Stmm ((sc->sc_arpcom.ac_enaddr[5]<<8)| 103291398Stmm sc->sc_arpcom.ac_enaddr[4])&0x3ff); 103391398Stmm /* Secondary MAC addr set to 0:0:0:0:0:0 */ 103491398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 103591398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 103691398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 103791398Stmm /* MAC control addr set to 0:1:c2:0:1:80 */ 103891398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 103991398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 104091398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 104191398Stmm 104291398Stmm /* MAC filter addr set to 0:0:0:0:0:0 */ 104391398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 104491398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 104591398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 104691398Stmm 104791398Stmm bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 104891398Stmm bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 104991398Stmm 105091398Stmm sc->sc_inited = 1; 105191398Stmm } 105291398Stmm 105391398Stmm /* Counters need to be zeroed */ 105491398Stmm bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 105591398Stmm bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 105691398Stmm bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 105791398Stmm bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 105891398Stmm bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 105991398Stmm bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 106091398Stmm bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 106191398Stmm bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 106291398Stmm bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 106391398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 106491398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 106591398Stmm 106691398Stmm /* Un-pause stuff */ 106791398Stmm#if 0 106891398Stmm bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 106991398Stmm#else 107091398Stmm bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 107191398Stmm#endif 107291398Stmm 107391398Stmm /* 107491398Stmm * Set the station address. 107591398Stmm */ 107691398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR0, 107791398Stmm (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); 107891398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR1, 107991398Stmm (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); 108091398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR2, 108191398Stmm (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); 108291398Stmm} 108391398Stmm 108491398Stmmstatic void 108591398Stmmgem_start(ifp) 108691398Stmm struct ifnet *ifp; 108791398Stmm{ 108891398Stmm struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 108991398Stmm struct mbuf *m0 = NULL, *m; 109091398Stmm struct gem_txjob txj; 109191398Stmm int firsttx, ofree, seg, ntx, txmfail; 109291398Stmm 109391398Stmm if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 109491398Stmm return; 109591398Stmm 109691398Stmm /* 109791398Stmm * Remember the previous number of free descriptors and 109891398Stmm * the first descriptor we'll use. 109991398Stmm */ 110091398Stmm ofree = sc->sc_txfree; 110191398Stmm firsttx = sc->sc_txnext; 110291398Stmm 110391398Stmm DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 110491398Stmm device_get_name(sc->sc_dev), ofree, firsttx)); 110591398Stmm CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d", 110691398Stmm device_get_name(sc->sc_dev), ofree, firsttx); 110791398Stmm 110891398Stmm txj.txj_nexttx = firsttx; 110991398Stmm txj.txj_lasttx = 0; 111091398Stmm /* 111191398Stmm * Loop through the send queue, setting up transmit descriptors 111291398Stmm * until we drain the queue, or use up all available transmit 111391398Stmm * descriptors. 111491398Stmm */ 111591398Stmm txmfail = 0; 111691398Stmm for (ntx = 0;; ntx++) { 111791398Stmm /* 111891398Stmm * Grab a packet off the queue. 111991398Stmm */ 112091398Stmm IF_DEQUEUE(&ifp->if_snd, m0); 112191398Stmm if (m0 == NULL) 112291398Stmm break; 112391398Stmm m = NULL; 112491398Stmm 112591398Stmm /* 112691398Stmm * Load the DMA map. If this fails, the packet either 112791398Stmm * didn't fit in the alloted number of segments, or we were 112891398Stmm * short on resources. In this case, we'll copy and try 112991398Stmm * again. 113091398Stmm */ 113191398Stmm txmfail = gem_dmamap_load_mbuf(sc, m0, 113291398Stmm gem_txdma_callback, &txj, BUS_DMA_NOWAIT); 113391398Stmm if (txmfail == -1) { 113491398Stmm IF_PREPEND(&ifp->if_snd, m0); 113591398Stmm break; 113691398Stmm } 113791398Stmm if (txmfail > 0) { 113891398Stmm MGETHDR(m, M_DONTWAIT, MT_DATA); 113991398Stmm if (m == NULL) { 114091398Stmm device_printf(sc->sc_dev, "unable to " 114191398Stmm "allocate Tx mbuf\n"); 114291398Stmm /* Failed; requeue. */ 114391398Stmm IF_PREPEND(&ifp->if_snd, m0); 114491398Stmm break; 114591398Stmm } 114691398Stmm if (m0->m_pkthdr.len > MHLEN) { 114791398Stmm MCLGET(m, M_DONTWAIT); 114891398Stmm if ((m->m_flags & M_EXT) == 0) { 114991398Stmm device_printf(sc->sc_dev, "unable to " 115091398Stmm "allocate Tx cluster\n"); 115191398Stmm IF_PREPEND(&ifp->if_snd, m0); 115291398Stmm m_freem(m); 115391398Stmm break; 115491398Stmm } 115591398Stmm } 115691398Stmm m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 115791398Stmm m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 115891398Stmm txmfail = gem_dmamap_load_mbuf(sc, m, 115991398Stmm gem_txdma_callback, &txj, BUS_DMA_NOWAIT); 116091398Stmm if (txmfail != 0) { 116191398Stmm if (txmfail > 0) { 116291398Stmm device_printf(sc->sc_dev, "unable to " 116391398Stmm "load Tx buffer, error = %d\n", 116491398Stmm txmfail); 116591398Stmm } 116691398Stmm m_freem(m); 116791398Stmm IF_PREPEND(&ifp->if_snd, m0); 116891398Stmm break; 116991398Stmm } 117091398Stmm } 117191398Stmm 117291398Stmm /* 117391398Stmm * Ensure we have enough descriptors free to describe 117491398Stmm * the packet. Note, we always reserve one descriptor 117591398Stmm * at the end of the ring as a termination point, to 117691398Stmm * prevent wrap-around. 117791398Stmm */ 117891398Stmm if (txj.txj_nsegs > (sc->sc_txfree - 1)) { 117991398Stmm /* 118091398Stmm * Not enough free descriptors to transmit this 118191398Stmm * packet. We haven't committed to anything yet, 118291398Stmm * so just unload the DMA map, put the packet 118391398Stmm * back on the queue, and punt. Notify the upper 118491398Stmm * layer that there are no more slots left. 118591398Stmm * 118691398Stmm * XXX We could allocate an mbuf and copy, but 118791398Stmm * XXX it is worth it? 118891398Stmm */ 118991398Stmm ifp->if_flags |= IFF_OACTIVE; 119091398Stmm gem_dmamap_unload_mbuf(sc, &txj); 119191398Stmm if (m != NULL) 119291398Stmm m_freem(m); 119391398Stmm IF_PREPEND(&ifp->if_snd, m0); 119491398Stmm break; 119591398Stmm } 119691398Stmm 119791398Stmm if (m != NULL) 119891398Stmm m_freem(m0); 119991398Stmm 120091398Stmm /* 120191398Stmm * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 120291398Stmm */ 120391398Stmm 120491398Stmm#ifdef GEM_DEBUG 120591398Stmm if (ifp->if_flags & IFF_DEBUG) { 120691398Stmm printf(" gem_start %p transmit chain:\n", 120791398Stmm STAILQ_FIRST(&txj.txj_txsq)); 120891398Stmm for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 120991398Stmm printf("descriptor %d:\t", seg); 121091398Stmm printf("gd_flags: 0x%016llx\t", (long long) 121191398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 121291398Stmm printf("gd_addr: 0x%016llx\n", (long long) 121391398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 121491398Stmm if (seg == txj.txj_lasttx) 121591398Stmm break; 121691398Stmm } 121791398Stmm } 121891398Stmm#endif 121991398Stmm 122091398Stmm /* Sync the descriptors we're using. */ 122191398Stmm GEM_CDTXSYNC(sc, sc->sc_txnext, txj.txj_nsegs, 122291398Stmm BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 122391398Stmm 122491398Stmm /* Advance the tx pointer. */ 122591398Stmm sc->sc_txfree -= txj.txj_nsegs; 122691398Stmm sc->sc_txnext = txj.txj_nexttx; 122791398Stmm 122891398Stmm gem_dmamap_commit_mbuf(sc, &txj); 122991398Stmm } 123091398Stmm 123191398Stmm if (txmfail == -1 || sc->sc_txfree == 0) { 123291398Stmm ifp->if_flags |= IFF_OACTIVE; 123391398Stmm /* No more slots left; notify upper layer. */ 123491398Stmm } 123591398Stmm 123691398Stmm if (ntx > 0) { 123791398Stmm DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 123891398Stmm device_get_name(sc->sc_dev), txj.txj_lasttx, firsttx)); 123991398Stmm CTR3(KTR_GEM, "%s: packets enqueued, IC on %d, OWN on %d", 124091398Stmm device_get_name(sc->sc_dev), txj.txj_lasttx, firsttx); 124191398Stmm /* 124291398Stmm * The entire packet chain is set up. 124391398Stmm * Kick the transmitter. 124491398Stmm */ 124591398Stmm DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 124691398Stmm device_get_name(sc->sc_dev), txj.txj_nexttx)); 124791398Stmm CTR3(KTR_GEM, "%s: gem_start: kicking tx %d=%d", 124891398Stmm device_get_name(sc->sc_dev), txj.txj_nexttx, 124991398Stmm sc->sc_txnext); 125091398Stmm bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 125191398Stmm sc->sc_txnext); 125291398Stmm 125391398Stmm /* Set a watchdog timer in case the chip flakes out. */ 125491398Stmm ifp->if_timer = 5; 125591398Stmm DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 125691398Stmm device_get_name(sc->sc_dev), ifp->if_timer)); 125791398Stmm CTR2(KTR_GEM, "%s: gem_start: watchdog %d", 125891398Stmm device_get_name(sc->sc_dev), ifp->if_timer); 125991398Stmm } 126091398Stmm} 126191398Stmm 126291398Stmm/* 126391398Stmm * Transmit interrupt. 126491398Stmm */ 126591398Stmmstatic void 126691398Stmmgem_tint(sc) 126791398Stmm struct gem_softc *sc; 126891398Stmm{ 126991398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 127091398Stmm bus_space_tag_t t = sc->sc_bustag; 127191398Stmm bus_space_handle_t mac = sc->sc_h; 127291398Stmm struct gem_txsoft *txs; 127391398Stmm int txlast; 127491398Stmm 127591398Stmm 127691398Stmm DPRINTF(sc, ("%s: gem_tint\n", device_get_name(sc->sc_dev))); 127791398Stmm CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 127891398Stmm 127991398Stmm /* 128091398Stmm * Unload collision counters 128191398Stmm */ 128291398Stmm ifp->if_collisions += 128391398Stmm bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 128491398Stmm bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 128591398Stmm bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 128691398Stmm bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 128791398Stmm 128891398Stmm /* 128991398Stmm * then clear the hardware counters. 129091398Stmm */ 129191398Stmm bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 129291398Stmm bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 129391398Stmm bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 129491398Stmm bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 129591398Stmm 129691398Stmm /* 129791398Stmm * Go through our Tx list and free mbufs for those 129891398Stmm * frames that have been transmitted. 129991398Stmm */ 130091398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 130191398Stmm GEM_CDTXSYNC(sc, txs->txs_lastdesc, 130291398Stmm txs->txs_ndescs, 130391398Stmm BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 130491398Stmm 130591398Stmm#ifdef GEM_DEBUG 130691398Stmm if (ifp->if_flags & IFF_DEBUG) { 130791398Stmm int i; 130891398Stmm printf(" txsoft %p transmit chain:\n", txs); 130991398Stmm for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 131091398Stmm printf("descriptor %d: ", i); 131191398Stmm printf("gd_flags: 0x%016llx\t", (long long) 131291398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 131391398Stmm printf("gd_addr: 0x%016llx\n", (long long) 131491398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 131591398Stmm if (i == txs->txs_lastdesc) 131691398Stmm break; 131791398Stmm } 131891398Stmm } 131991398Stmm#endif 132091398Stmm 132191398Stmm /* 132291398Stmm * In theory, we could harveast some descriptors before 132391398Stmm * the ring is empty, but that's a bit complicated. 132491398Stmm * 132591398Stmm * GEM_TX_COMPLETION points to the last descriptor 132691398Stmm * processed +1. 132791398Stmm */ 132891398Stmm txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 132991398Stmm DPRINTF(sc, 133091398Stmm ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 133191398Stmm txs->txs_lastdesc, txlast)); 133291398Stmm CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 133391398Stmm "txs->txs_lastdesc = %d, txlast = %d", 133491398Stmm txs->txs_firstdesc, txs->txs_lastdesc, txlast); 133591398Stmm if (txs->txs_firstdesc <= txs->txs_lastdesc) { 133691398Stmm if ((txlast >= txs->txs_firstdesc) && 133791398Stmm (txlast <= txs->txs_lastdesc)) 133891398Stmm break; 133991398Stmm } else { 134091398Stmm /* Ick -- this command wraps */ 134191398Stmm if ((txlast >= txs->txs_firstdesc) || 134291398Stmm (txlast <= txs->txs_lastdesc)) 134391398Stmm break; 134491398Stmm } 134591398Stmm 134691398Stmm DPRINTF(sc, ("gem_tint: releasing a desc\n")); 134791398Stmm CTR0(KTR_GEM, "gem_tint: releasing a desc"); 134891398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 134991398Stmm 135091398Stmm sc->sc_txfree += txs->txs_ndescs; 135191398Stmm 135291398Stmm bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 135391398Stmm BUS_DMASYNC_POSTWRITE); 135491398Stmm bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 135591398Stmm if (txs->txs_mbuf != NULL) { 135691398Stmm m_freem(txs->txs_mbuf); 135791398Stmm txs->txs_mbuf = NULL; 135891398Stmm } 135991398Stmm 136091398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 136191398Stmm 136291398Stmm ifp->if_opackets++; 136391398Stmm } 136491398Stmm 136591398Stmm DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 136691398Stmm "GEM_TX_DATA_PTR %llx " 136791398Stmm "GEM_TX_COMPLETION %x\n", 136891398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 136991398Stmm ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 137091398Stmm GEM_TX_DATA_PTR_HI) << 32) | 137191398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, 137291398Stmm GEM_TX_DATA_PTR_LO), 137391398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 137491398Stmm CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 137591398Stmm "GEM_TX_DATA_PTR %llx " 137691398Stmm "GEM_TX_COMPLETION %x", 137791398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 137891398Stmm ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 137991398Stmm GEM_TX_DATA_PTR_HI) << 32) | 138091398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, 138191398Stmm GEM_TX_DATA_PTR_LO), 138291398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION)); 138391398Stmm 138491398Stmm if (STAILQ_FIRST(&sc->sc_txdirtyq) == NULL) 138591398Stmm ifp->if_timer = 0; 138691398Stmm 138791398Stmm 138891398Stmm DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 138991398Stmm device_get_name(sc->sc_dev), ifp->if_timer)); 139091398Stmm CTR2(KTR_GEM, "%s: gem_tint: watchdog %d", 139191398Stmm device_get_name(sc->sc_dev), ifp->if_timer); 139291398Stmm 139391398Stmm /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 139491398Stmm ifp->if_flags &= ~IFF_OACTIVE; 139591398Stmm gem_start(ifp); 139691398Stmm} 139791398Stmm 139893045Stmmstatic void 139993045Stmmgem_rint_timeout(arg) 140093045Stmm void *arg; 140193045Stmm{ 140293045Stmm 140393045Stmm gem_rint((struct gem_softc *)arg); 140493045Stmm} 140593045Stmm 140691398Stmm/* 140791398Stmm * Receive interrupt. 140891398Stmm */ 140991398Stmmstatic void 141091398Stmmgem_rint(sc) 141191398Stmm struct gem_softc *sc; 141291398Stmm{ 141391398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 141491398Stmm bus_space_tag_t t = sc->sc_bustag; 141591398Stmm bus_space_handle_t h = sc->sc_h; 141691398Stmm struct ether_header *eh; 141791398Stmm struct gem_rxsoft *rxs; 141891398Stmm struct mbuf *m; 141991398Stmm u_int64_t rxstat; 142091398Stmm int i, len; 142191398Stmm 142293045Stmm callout_stop(&sc->sc_rx_ch); 142391398Stmm DPRINTF(sc, ("%s: gem_rint\n", device_get_name(sc->sc_dev))); 142491398Stmm CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 142591398Stmm /* 142691398Stmm * XXXX Read the lastrx only once at the top for speed. 142791398Stmm */ 142891398Stmm DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 142991398Stmm sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 143091398Stmm CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 143191398Stmm sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 143291398Stmm for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 143391398Stmm i = GEM_NEXTRX(i)) { 143491398Stmm rxs = &sc->sc_rxsoft[i]; 143591398Stmm 143691398Stmm GEM_CDRXSYNC(sc, i, 143791398Stmm BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 143891398Stmm 143991398Stmm rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 144091398Stmm 144191398Stmm if (rxstat & GEM_RD_OWN) { 144291398Stmm /* 144393045Stmm * The descriptor is still marked as owned, although 144493045Stmm * it is supposed to have completed. This has been 144593045Stmm * observed on some machines. Just exiting here 144693045Stmm * might leave the packet sitting around until another 144793045Stmm * one arrives to trigger a new interrupt, which is 144893045Stmm * generally undesirable, so set up a timeout. 144991398Stmm */ 145093045Stmm callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 145193045Stmm gem_rint_timeout, sc); 145291398Stmm break; 145391398Stmm } 145491398Stmm 145591398Stmm if (rxstat & GEM_RD_BAD_CRC) { 145691398Stmm device_printf(sc->sc_dev, "receive error: CRC error\n"); 145791398Stmm GEM_INIT_RXDESC(sc, i); 145891398Stmm continue; 145991398Stmm } 146091398Stmm 146191398Stmm bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 146291398Stmm BUS_DMASYNC_POSTREAD); 146391398Stmm#ifdef GEM_DEBUG 146491398Stmm if (ifp->if_flags & IFF_DEBUG) { 146591398Stmm printf(" rxsoft %p descriptor %d: ", rxs, i); 146691398Stmm printf("gd_flags: 0x%016llx\t", (long long) 146791398Stmm GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 146891398Stmm printf("gd_addr: 0x%016llx\n", (long long) 146991398Stmm GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 147091398Stmm } 147191398Stmm#endif 147291398Stmm 147391398Stmm /* 147491398Stmm * No errors; receive the packet. Note the Gem 147591398Stmm * includes the CRC with every packet. 147691398Stmm */ 147791398Stmm len = GEM_RD_BUFLEN(rxstat); 147891398Stmm 147991398Stmm /* 148091398Stmm * Allocate a new mbuf cluster. If that fails, we are 148191398Stmm * out of memory, and must drop the packet and recycle 148291398Stmm * the buffer that's already attached to this descriptor. 148391398Stmm */ 148491398Stmm m = rxs->rxs_mbuf; 148591398Stmm if (gem_add_rxbuf(sc, i) != 0) { 148691398Stmm ifp->if_ierrors++; 148791398Stmm GEM_INIT_RXDESC(sc, i); 148891398Stmm bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 148991398Stmm BUS_DMASYNC_PREREAD); 149091398Stmm continue; 149191398Stmm } 149291398Stmm m->m_data += 2; /* We're already off by two */ 149391398Stmm 149491398Stmm ifp->if_ipackets++; 149591398Stmm eh = mtod(m, struct ether_header *); 149691398Stmm m->m_pkthdr.rcvif = ifp; 149791398Stmm m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN; 149891398Stmm m_adj(m, sizeof(struct ether_header)); 149991398Stmm 150091398Stmm /* Pass it on. */ 150191398Stmm ether_input(ifp, eh, m); 150291398Stmm } 150391398Stmm 150491398Stmm /* Update the receive pointer. */ 150591398Stmm sc->sc_rxptr = i; 150691398Stmm bus_space_write_4(t, h, GEM_RX_KICK, i); 150791398Stmm 150891398Stmm DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 150991398Stmm sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 151091398Stmm CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", 151191398Stmm sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 151291398Stmm 151391398Stmm} 151491398Stmm 151591398Stmm 151691398Stmm/* 151791398Stmm * gem_add_rxbuf: 151891398Stmm * 151991398Stmm * Add a receive buffer to the indicated descriptor. 152091398Stmm */ 152191398Stmmstatic int 152291398Stmmgem_add_rxbuf(sc, idx) 152391398Stmm struct gem_softc *sc; 152491398Stmm int idx; 152591398Stmm{ 152691398Stmm struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 152791398Stmm struct mbuf *m; 152891398Stmm int error; 152991398Stmm 153091398Stmm MGETHDR(m, M_DONTWAIT, MT_DATA); 153191398Stmm if (m == NULL) 153291398Stmm return (ENOBUFS); 153391398Stmm 153491398Stmm MCLGET(m, M_DONTWAIT); 153591398Stmm if ((m->m_flags & M_EXT) == 0) { 153691398Stmm m_freem(m); 153791398Stmm return (ENOBUFS); 153891398Stmm } 153991398Stmm 154091398Stmm#ifdef GEM_DEBUG 154191398Stmm /* bzero the packet to check dma */ 154291398Stmm memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 154391398Stmm#endif 154491398Stmm 154591398Stmm if (rxs->rxs_mbuf != NULL) 154691398Stmm bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 154791398Stmm 154891398Stmm rxs->rxs_mbuf = m; 154991398Stmm 155091398Stmm error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 155191398Stmm m->m_ext.ext_buf, m->m_ext.ext_size, gem_rxdma_callback, rxs, 155291398Stmm BUS_DMA_NOWAIT); 155391398Stmm if (error != 0 || rxs->rxs_paddr == 0) { 155491398Stmm device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " 155591398Stmm "%d\n", idx, error); 155691398Stmm panic("gem_add_rxbuf"); /* XXX */ 155791398Stmm } 155891398Stmm 155991398Stmm bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 156091398Stmm 156191398Stmm GEM_INIT_RXDESC(sc, idx); 156291398Stmm 156391398Stmm return (0); 156491398Stmm} 156591398Stmm 156691398Stmm 156791398Stmmstatic void 156891398Stmmgem_eint(sc, status) 156991398Stmm struct gem_softc *sc; 157091398Stmm u_int status; 157191398Stmm{ 157291398Stmm 157391398Stmm if ((status & GEM_INTR_MIF) != 0) { 157491398Stmm device_printf(sc->sc_dev, "XXXlink status changed\n"); 157591398Stmm return; 157691398Stmm } 157791398Stmm 157891398Stmm device_printf(sc->sc_dev, "status=%x\n", status); 157991398Stmm} 158091398Stmm 158191398Stmm 158291398Stmmvoid 158391398Stmmgem_intr(v) 158491398Stmm void *v; 158591398Stmm{ 158691398Stmm struct gem_softc *sc = (struct gem_softc *)v; 158791398Stmm bus_space_tag_t t = sc->sc_bustag; 158891398Stmm bus_space_handle_t seb = sc->sc_h; 158991398Stmm u_int32_t status; 159091398Stmm 159191398Stmm status = bus_space_read_4(t, seb, GEM_STATUS); 159291398Stmm DPRINTF(sc, ("%s: gem_intr: cplt %x, status %x\n", 159391398Stmm device_get_name(sc->sc_dev), (status>>19), 159491398Stmm (u_int)status)); 159591398Stmm CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 159691398Stmm device_get_name(sc->sc_dev), (status>>19), 159791398Stmm (u_int)status); 159891398Stmm 159991398Stmm if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 160091398Stmm gem_eint(sc, status); 160191398Stmm 160291398Stmm if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 160391398Stmm gem_tint(sc); 160491398Stmm 160591398Stmm if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 160691398Stmm gem_rint(sc); 160791398Stmm 160891398Stmm /* We should eventually do more than just print out error stats. */ 160991398Stmm if (status & GEM_INTR_TX_MAC) { 161091398Stmm int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 161191398Stmm if (txstat & ~GEM_MAC_TX_XMIT_DONE) 161291398Stmm printf("MAC tx fault, status %x\n", txstat); 161391398Stmm } 161491398Stmm if (status & GEM_INTR_RX_MAC) { 161591398Stmm int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 161691398Stmm if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 161791398Stmm printf("MAC rx fault, status %x\n", rxstat); 161891398Stmm } 161991398Stmm} 162091398Stmm 162191398Stmm 162291398Stmmstatic void 162391398Stmmgem_watchdog(ifp) 162491398Stmm struct ifnet *ifp; 162591398Stmm{ 162691398Stmm struct gem_softc *sc = ifp->if_softc; 162791398Stmm 162891398Stmm DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 162991398Stmm "GEM_MAC_RX_CONFIG %x\n", 163091398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 163191398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 163291398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 163391398Stmm CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 163491398Stmm "GEM_MAC_RX_CONFIG %x", 163591398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 163691398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 163791398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)); 163891398Stmm CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 163991398Stmm "GEM_MAC_TX_CONFIG %x", 164091398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 164191398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS), 164291398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 164391398Stmm 164491398Stmm device_printf(sc->sc_dev, "device timeout\n"); 164591398Stmm ++ifp->if_oerrors; 164691398Stmm 164791398Stmm /* Try to get more packets going. */ 164891398Stmm gem_start(ifp); 164991398Stmm} 165091398Stmm 165191398Stmm/* 165291398Stmm * Initialize the MII Management Interface 165391398Stmm */ 165491398Stmmstatic void 165591398Stmmgem_mifinit(sc) 165691398Stmm struct gem_softc *sc; 165791398Stmm{ 165891398Stmm bus_space_tag_t t = sc->sc_bustag; 165991398Stmm bus_space_handle_t mif = sc->sc_h; 166091398Stmm 166191398Stmm /* Configure the MIF in frame mode */ 166291398Stmm sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 166391398Stmm sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 166491398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 166591398Stmm} 166691398Stmm 166791398Stmm/* 166891398Stmm * MII interface 166991398Stmm * 167091398Stmm * The GEM MII interface supports at least three different operating modes: 167191398Stmm * 167291398Stmm * Bitbang mode is implemented using data, clock and output enable registers. 167391398Stmm * 167491398Stmm * Frame mode is implemented by loading a complete frame into the frame 167591398Stmm * register and polling the valid bit for completion. 167691398Stmm * 167791398Stmm * Polling mode uses the frame register but completion is indicated by 167891398Stmm * an interrupt. 167991398Stmm * 168091398Stmm */ 168191398Stmmint 168291398Stmmgem_mii_readreg(dev, phy, reg) 168391398Stmm device_t dev; 168491398Stmm int phy, reg; 168591398Stmm{ 168691398Stmm struct gem_softc *sc = device_get_softc(dev); 168791398Stmm bus_space_tag_t t = sc->sc_bustag; 168891398Stmm bus_space_handle_t mif = sc->sc_h; 168991398Stmm int n; 169091398Stmm u_int32_t v; 169191398Stmm 169291398Stmm#ifdef GEM_DEBUG_PHY 169391398Stmm printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 169491398Stmm#endif 169591398Stmm 169691398Stmm#if 0 169791398Stmm /* Select the desired PHY in the MIF configuration register */ 169891398Stmm v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 169991398Stmm /* Clear PHY select bit */ 170091398Stmm v &= ~GEM_MIF_CONFIG_PHY_SEL; 170191398Stmm if (phy == GEM_PHYAD_EXTERNAL) 170291398Stmm /* Set PHY select bit to get at external device */ 170391398Stmm v |= GEM_MIF_CONFIG_PHY_SEL; 170491398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 170591398Stmm#endif 170691398Stmm 170791398Stmm /* Construct the frame command */ 170891398Stmm v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 170991398Stmm GEM_MIF_FRAME_READ; 171091398Stmm 171191398Stmm bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 171291398Stmm for (n = 0; n < 100; n++) { 171391398Stmm DELAY(1); 171491398Stmm v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 171591398Stmm if (v & GEM_MIF_FRAME_TA0) 171691398Stmm return (v & GEM_MIF_FRAME_DATA); 171791398Stmm } 171891398Stmm 171991398Stmm device_printf(sc->sc_dev, "mii_read timeout\n"); 172091398Stmm return (0); 172191398Stmm} 172291398Stmm 172391398Stmmint 172491398Stmmgem_mii_writereg(dev, phy, reg, val) 172591398Stmm device_t dev; 172691398Stmm int phy, reg, val; 172791398Stmm{ 172891398Stmm struct gem_softc *sc = device_get_softc(dev); 172991398Stmm bus_space_tag_t t = sc->sc_bustag; 173091398Stmm bus_space_handle_t mif = sc->sc_h; 173191398Stmm int n; 173291398Stmm u_int32_t v; 173391398Stmm 173491398Stmm#ifdef GEM_DEBUG_PHY 173591398Stmm printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 173691398Stmm#endif 173791398Stmm 173891398Stmm#if 0 173991398Stmm /* Select the desired PHY in the MIF configuration register */ 174091398Stmm v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 174191398Stmm /* Clear PHY select bit */ 174291398Stmm v &= ~GEM_MIF_CONFIG_PHY_SEL; 174391398Stmm if (phy == GEM_PHYAD_EXTERNAL) 174491398Stmm /* Set PHY select bit to get at external device */ 174591398Stmm v |= GEM_MIF_CONFIG_PHY_SEL; 174691398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 174791398Stmm#endif 174891398Stmm /* Construct the frame command */ 174991398Stmm v = GEM_MIF_FRAME_WRITE | 175091398Stmm (phy << GEM_MIF_PHY_SHIFT) | 175191398Stmm (reg << GEM_MIF_REG_SHIFT) | 175291398Stmm (val & GEM_MIF_FRAME_DATA); 175391398Stmm 175491398Stmm bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 175591398Stmm for (n = 0; n < 100; n++) { 175691398Stmm DELAY(1); 175791398Stmm v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 175891398Stmm if (v & GEM_MIF_FRAME_TA0) 175991398Stmm return (1); 176091398Stmm } 176191398Stmm 176291398Stmm device_printf(sc->sc_dev, "mii_write timeout\n"); 176391398Stmm return (0); 176491398Stmm} 176591398Stmm 176691398Stmmvoid 176791398Stmmgem_mii_statchg(dev) 176891398Stmm device_t dev; 176991398Stmm{ 177091398Stmm struct gem_softc *sc = device_get_softc(dev); 177191398Stmm#ifdef GEM_DEBUG 177291398Stmm int instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 177391398Stmm#endif 177491398Stmm bus_space_tag_t t = sc->sc_bustag; 177591398Stmm bus_space_handle_t mac = sc->sc_h; 177691398Stmm u_int32_t v; 177791398Stmm 177891398Stmm#ifdef GEM_DEBUG 177991398Stmm if (sc->sc_debug) 178091398Stmm printf("gem_mii_statchg: status change: phy = %d\n", 178191398Stmm sc->sc_phys[instance]); 178291398Stmm#endif 178391398Stmm 178491398Stmm /* Set tx full duplex options */ 178591398Stmm bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 178691398Stmm DELAY(10000); /* reg must be cleared and delay before changing. */ 178791398Stmm v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 178891398Stmm GEM_MAC_TX_ENABLE; 178991398Stmm if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 179091398Stmm v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 179191398Stmm } 179291398Stmm bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 179391398Stmm 179491398Stmm /* XIF Configuration */ 179591398Stmm /* We should really calculate all this rather than rely on defaults */ 179691398Stmm v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 179791398Stmm v = GEM_MAC_XIF_LINK_LED; 179891398Stmm v |= GEM_MAC_XIF_TX_MII_ENA; 179991398Stmm /* If an external transceiver is connected, enable its MII drivers */ 180091398Stmm sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 180191398Stmm if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 180291398Stmm /* External MII needs echo disable if half duplex. */ 180391398Stmm if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 180491398Stmm /* turn on full duplex LED */ 180591398Stmm v |= GEM_MAC_XIF_FDPLX_LED; 180691398Stmm else 180791398Stmm /* half duplex -- disable echo */ 180891398Stmm v |= GEM_MAC_XIF_ECHO_DISABL; 180991398Stmm } else { 181091398Stmm /* Internal MII needs buf enable */ 181191398Stmm v |= GEM_MAC_XIF_MII_BUF_ENA; 181291398Stmm } 181391398Stmm bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 181491398Stmm} 181591398Stmm 181691398Stmmint 181791398Stmmgem_mediachange(ifp) 181891398Stmm struct ifnet *ifp; 181991398Stmm{ 182091398Stmm struct gem_softc *sc = ifp->if_softc; 182191398Stmm 182291398Stmm /* XXX Add support for serial media. */ 182391398Stmm 182491398Stmm return (mii_mediachg(sc->sc_mii)); 182591398Stmm} 182691398Stmm 182791398Stmmvoid 182891398Stmmgem_mediastatus(ifp, ifmr) 182991398Stmm struct ifnet *ifp; 183091398Stmm struct ifmediareq *ifmr; 183191398Stmm{ 183291398Stmm struct gem_softc *sc = ifp->if_softc; 183391398Stmm 183491398Stmm if ((ifp->if_flags & IFF_UP) == 0) 183591398Stmm return; 183691398Stmm 183791398Stmm mii_pollstat(sc->sc_mii); 183891398Stmm ifmr->ifm_active = sc->sc_mii->mii_media_active; 183991398Stmm ifmr->ifm_status = sc->sc_mii->mii_media_status; 184091398Stmm} 184191398Stmm 184291398Stmm/* 184391398Stmm * Process an ioctl request. 184491398Stmm */ 184591398Stmmstatic int 184691398Stmmgem_ioctl(ifp, cmd, data) 184791398Stmm struct ifnet *ifp; 184891398Stmm u_long cmd; 184991398Stmm caddr_t data; 185091398Stmm{ 185191398Stmm struct gem_softc *sc = ifp->if_softc; 185291398Stmm struct ifreq *ifr = (struct ifreq *)data; 185391398Stmm int s, error = 0; 185491398Stmm 185591398Stmm switch (cmd) { 185691398Stmm case SIOCSIFADDR: 185791398Stmm case SIOCGIFADDR: 185891398Stmm case SIOCSIFMTU: 185991398Stmm error = ether_ioctl(ifp, cmd, data); 186091398Stmm break; 186191398Stmm case SIOCSIFFLAGS: 186291398Stmm if (ifp->if_flags & IFF_UP) { 186391398Stmm if ((sc->sc_flags ^ ifp->if_flags) == IFF_PROMISC) 186491398Stmm gem_setladrf(sc); 186591398Stmm else 186691398Stmm gem_init(sc); 186791398Stmm } else { 186891398Stmm if (ifp->if_flags & IFF_RUNNING) 186991398Stmm gem_stop(ifp, 0); 187091398Stmm } 187191398Stmm sc->sc_flags = ifp->if_flags; 187291398Stmm error = 0; 187391398Stmm break; 187491398Stmm case SIOCADDMULTI: 187591398Stmm case SIOCDELMULTI: 187691398Stmm gem_setladrf(sc); 187791398Stmm error = 0; 187891398Stmm break; 187991398Stmm case SIOCGIFMEDIA: 188091398Stmm case SIOCSIFMEDIA: 188191398Stmm error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 188291398Stmm break; 188391398Stmm default: 188491398Stmm error = ENOTTY; 188591398Stmm break; 188691398Stmm } 188791398Stmm 188891398Stmm /* Try to get things going again */ 188991398Stmm if (ifp->if_flags & IFF_UP) 189091398Stmm gem_start(ifp); 189191398Stmm splx(s); 189291398Stmm return (error); 189391398Stmm} 189491398Stmm 189591398Stmm/* 189691398Stmm * Set up the logical address filter. 189791398Stmm */ 189891398Stmmstatic void 189991398Stmmgem_setladrf(sc) 190091398Stmm struct gem_softc *sc; 190191398Stmm{ 190291398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 190391398Stmm struct ifmultiaddr *inm; 190491398Stmm struct sockaddr_dl *sdl; 190591398Stmm bus_space_tag_t t = sc->sc_bustag; 190691398Stmm bus_space_handle_t h = sc->sc_h; 190791398Stmm u_char *cp; 190891398Stmm u_int32_t crc; 190991398Stmm u_int32_t hash[16]; 191091398Stmm u_int32_t v; 191191398Stmm int len; 191291398Stmm 191391398Stmm /* Clear hash table */ 191491398Stmm memset(hash, 0, sizeof(hash)); 191591398Stmm 191691398Stmm /* Get current RX configuration */ 191791398Stmm v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 191891398Stmm 191991398Stmm if ((ifp->if_flags & IFF_PROMISC) != 0) { 192091398Stmm /* Turn on promiscuous mode; turn off the hash filter */ 192191398Stmm v |= GEM_MAC_RX_PROMISCUOUS; 192291398Stmm v &= ~GEM_MAC_RX_HASH_FILTER; 192391398Stmm ; 192491398Stmm goto chipit; 192591398Stmm } 192691398Stmm if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 192791398Stmm hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 192891398Stmm ifp->if_flags |= IFF_ALLMULTI; 192991398Stmm goto chipit; 193091398Stmm } 193191398Stmm 193291398Stmm /* Turn off promiscuous mode; turn on the hash filter */ 193391398Stmm v &= ~GEM_MAC_RX_PROMISCUOUS; 193491398Stmm v |= GEM_MAC_RX_HASH_FILTER; 193591398Stmm 193691398Stmm /* 193791398Stmm * Set up multicast address filter by passing all multicast addresses 193891398Stmm * through a crc generator, and then using the high order 6 bits as an 193991398Stmm * index into the 256 bit logical address filter. The high order bit 194091398Stmm * selects the word, while the rest of the bits select the bit within 194191398Stmm * the word. 194291398Stmm */ 194391398Stmm 194491398Stmm TAILQ_FOREACH(inm, &sc->sc_arpcom.ac_if.if_multiaddrs, ifma_link) { 194591398Stmm if (inm->ifma_addr->sa_family != AF_LINK) 194691398Stmm continue; 194791398Stmm sdl = (struct sockaddr_dl *)inm->ifma_addr; 194891398Stmm cp = LLADDR(sdl); 194991398Stmm crc = 0xffffffff; 195091398Stmm for (len = sdl->sdl_alen; --len >= 0;) { 195191398Stmm int octet = *cp++; 195291398Stmm int i; 195391398Stmm 195491398Stmm#define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 195591398Stmm for (i = 0; i < 8; i++) { 195691398Stmm if ((crc & 1) ^ (octet & 1)) { 195791398Stmm crc >>= 1; 195891398Stmm crc ^= MC_POLY_LE; 195991398Stmm } else { 196091398Stmm crc >>= 1; 196191398Stmm } 196291398Stmm octet >>= 1; 196391398Stmm } 196491398Stmm } 196591398Stmm /* Just want the 8 most significant bits. */ 196691398Stmm crc >>= 24; 196791398Stmm 196891398Stmm /* Set the corresponding bit in the filter. */ 196991398Stmm hash[crc >> 4] |= 1 << (crc & 0xf); 197091398Stmm } 197191398Stmm 197291398Stmmchipit: 197391398Stmm /* Now load the hash table into the chip */ 197491398Stmm bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 197591398Stmm bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 197691398Stmm bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 197791398Stmm bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 197891398Stmm bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 197991398Stmm bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 198091398Stmm bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 198191398Stmm bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 198291398Stmm bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 198391398Stmm bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 198491398Stmm bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 198591398Stmm bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 198691398Stmm bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 198791398Stmm bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 198891398Stmm bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 198991398Stmm bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 199091398Stmm 199191398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 199291398Stmm} 199391398Stmm 199491398Stmm#if notyet 199591398Stmm 199691398Stmm/* 199791398Stmm * gem_power: 199891398Stmm * 199991398Stmm * Power management (suspend/resume) hook. 200091398Stmm */ 200191398Stmmvoid 200291398Stmmstatic gem_power(why, arg) 200391398Stmm int why; 200491398Stmm void *arg; 200591398Stmm{ 200691398Stmm struct gem_softc *sc = arg; 200791398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 200891398Stmm int s; 200991398Stmm 201091398Stmm s = splnet(); 201191398Stmm switch (why) { 201291398Stmm case PWR_SUSPEND: 201391398Stmm case PWR_STANDBY: 201491398Stmm gem_stop(ifp, 1); 201591398Stmm if (sc->sc_power != NULL) 201691398Stmm (*sc->sc_power)(sc, why); 201791398Stmm break; 201891398Stmm case PWR_RESUME: 201991398Stmm if (ifp->if_flags & IFF_UP) { 202091398Stmm if (sc->sc_power != NULL) 202191398Stmm (*sc->sc_power)(sc, why); 202291398Stmm gem_init(ifp); 202391398Stmm } 202491398Stmm break; 202591398Stmm case PWR_SOFTSUSPEND: 202691398Stmm case PWR_SOFTSTANDBY: 202791398Stmm case PWR_SOFTRESUME: 202891398Stmm break; 202991398Stmm } 203091398Stmm splx(s); 203191398Stmm} 203291398Stmm#endif 2033