if_gem.c revision 220941
1119418Sobrien/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 3108832Stmm * Copyright (c) 2001-2003 Thomas Moestl 4174987Smarius * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 591398Stmm * All rights reserved. 691398Stmm * 791398Stmm * Redistribution and use in source and binary forms, with or without 891398Stmm * modification, are permitted provided that the following conditions 991398Stmm * are met: 1091398Stmm * 1. Redistributions of source code must retain the above copyright 1191398Stmm * notice, this list of conditions and the following disclaimer. 1291398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1391398Stmm * notice, this list of conditions and the following disclaimer in the 1491398Stmm * documentation and/or other materials provided with the distribution. 1591398Stmm * 1691398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1791398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1891398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1991398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 2091398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2191398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2291398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2391398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2491398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2591398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2691398Stmm * SUCH DAMAGE. 2791398Stmm * 2899726Sbenno * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 2991398Stmm */ 3091398Stmm 31119418Sobrien#include <sys/cdefs.h> 32119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 220941 2011-04-22 09:41:51Z marius $"); 33119418Sobrien 3491398Stmm/* 35172334Smarius * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 3691398Stmm */ 3791398Stmm 38115030Stmm#if 0 3991398Stmm#define GEM_DEBUG 40115030Stmm#endif 4191398Stmm 42148368Smarius#if 0 /* XXX: In case of emergency, re-enable this. */ 43148368Smarius#define GEM_RINT_TIMEOUT 44148368Smarius#endif 45148368Smarius 4691398Stmm#include <sys/param.h> 4791398Stmm#include <sys/systm.h> 4891398Stmm#include <sys/bus.h> 4991398Stmm#include <sys/callout.h> 5095533Smike#include <sys/endian.h> 5191398Stmm#include <sys/mbuf.h> 5291398Stmm#include <sys/malloc.h> 5391398Stmm#include <sys/kernel.h> 54148369Smarius#include <sys/lock.h> 55130026Sphk#include <sys/module.h> 56148369Smarius#include <sys/mutex.h> 5791398Stmm#include <sys/socket.h> 5891398Stmm#include <sys/sockio.h> 59169269Sphk#include <sys/rman.h> 6091398Stmm 61105982Stmm#include <net/bpf.h> 6291398Stmm#include <net/ethernet.h> 6391398Stmm#include <net/if.h> 6491398Stmm#include <net/if_arp.h> 6591398Stmm#include <net/if_dl.h> 6691398Stmm#include <net/if_media.h> 67147256Sbrooks#include <net/if_types.h> 68149552Smarius#include <net/if_vlan_var.h> 6991398Stmm 70170273Syongari#include <netinet/in.h> 71170273Syongari#include <netinet/in_systm.h> 72170273Syongari#include <netinet/ip.h> 73170273Syongari#include <netinet/tcp.h> 74170273Syongari#include <netinet/udp.h> 75170273Syongari 7691398Stmm#include <machine/bus.h> 7791398Stmm 7891398Stmm#include <dev/mii/mii.h> 7991398Stmm#include <dev/mii/miivar.h> 8091398Stmm 81119355Simp#include <dev/gem/if_gemreg.h> 82119355Simp#include <dev/gem/if_gemvar.h> 8391398Stmm 84172334SmariusCTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85172334SmariusCTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86172334Smarius 87194763Smarius#define GEM_TRIES 10000 88172334Smarius 89170273Syongari/* 90182060Smarius * The hardware supports basic TCP/UDP checksum offloading. However, 91170273Syongari * the hardware doesn't compensate the checksum for UDP datagram which 92174987Smarius * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93174987Smarius * by default. It can be reactivated by setting special link option 94170273Syongari * link0 with ifconfig(8). 95170273Syongari */ 96170273Syongari#define GEM_CSUM_FEATURES (CSUM_TCP) 9791398Stmm 98174987Smariusstatic int gem_add_rxbuf(struct gem_softc *sc, int idx); 99177560Smariusstatic int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 100177560Smarius uint32_t clr, uint32_t set); 101174987Smariusstatic void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 102174987Smarius int nsegs, int error); 103174987Smariusstatic int gem_disable_rx(struct gem_softc *sc); 104174987Smariusstatic int gem_disable_tx(struct gem_softc *sc); 105174987Smariusstatic void gem_eint(struct gem_softc *sc, u_int status); 106174987Smariusstatic void gem_init(void *xsc); 107174987Smariusstatic void gem_init_locked(struct gem_softc *sc); 108174987Smariusstatic void gem_init_regs(struct gem_softc *sc); 109174987Smariusstatic int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 110174987Smariusstatic int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 111174987Smariusstatic int gem_meminit(struct gem_softc *sc); 112174987Smariusstatic void gem_mifinit(struct gem_softc *sc); 113174987Smariusstatic void gem_reset(struct gem_softc *sc); 114174987Smariusstatic int gem_reset_rx(struct gem_softc *sc); 115172334Smariusstatic void gem_reset_rxdma(struct gem_softc *sc); 116174987Smariusstatic int gem_reset_tx(struct gem_softc *sc); 117174987Smariusstatic u_int gem_ringsize(u_int sz); 118174987Smariusstatic void gem_rint(struct gem_softc *sc); 119148368Smarius#ifdef GEM_RINT_TIMEOUT 120174987Smariusstatic void gem_rint_timeout(void *arg); 121100587Sjake#endif 122194763Smariusstatic inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 123174987Smariusstatic void gem_rxdrain(struct gem_softc *sc); 124174987Smariusstatic void gem_setladrf(struct gem_softc *sc); 125174987Smariusstatic void gem_start(struct ifnet *ifp); 126174987Smariusstatic void gem_start_locked(struct ifnet *ifp); 127174987Smariusstatic void gem_stop(struct ifnet *ifp, int disable); 128174987Smariusstatic void gem_tick(void *arg); 129174987Smariusstatic void gem_tint(struct gem_softc *sc); 130194763Smariusstatic inline void gem_txkick(struct gem_softc *sc); 131174987Smariusstatic int gem_watchdog(struct gem_softc *sc); 13291398Stmm 13391398Stmmdevclass_t gem_devclass; 13491398StmmDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 13591398StmmMODULE_DEPEND(gem, miibus, 1, 1, 1); 13691398Stmm 13791398Stmm#ifdef GEM_DEBUG 13891398Stmm#include <sys/ktr.h> 139210334Sattilio#define KTR_GEM KTR_SPARE2 14091398Stmm#endif 14191398Stmm 142177560Smarius#define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 143177560Smarius gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 144177560Smarius#define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 145177560Smarius gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 146177560Smarius 14791398Stmmint 148174987Smariusgem_attach(struct gem_softc *sc) 14991398Stmm{ 150174987Smarius struct gem_txsoft *txs; 151147256Sbrooks struct ifnet *ifp; 152213893Smarius int error, i, phy; 153174987Smarius uint32_t v; 15491398Stmm 155194763Smarius if (bootverbose) 156194763Smarius device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 157194763Smarius 158194763Smarius /* Set up ifnet structure. */ 159147256Sbrooks ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160147256Sbrooks if (ifp == NULL) 161147256Sbrooks return (ENOSPC); 162194763Smarius sc->sc_csum_features = GEM_CSUM_FEATURES; 163194763Smarius ifp->if_softc = sc; 164194763Smarius if_initname(ifp, device_get_name(sc->sc_dev), 165194763Smarius device_get_unit(sc->sc_dev)); 166194763Smarius ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 167194763Smarius ifp->if_start = gem_start; 168194763Smarius ifp->if_ioctl = gem_ioctl; 169194763Smarius ifp->if_init = gem_init; 170194763Smarius IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 171194763Smarius ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 172194763Smarius IFQ_SET_READY(&ifp->if_snd); 173147256Sbrooks 174150285Smarius callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 175150285Smarius#ifdef GEM_RINT_TIMEOUT 176150285Smarius callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 177150285Smarius#endif 178150285Smarius 17991398Stmm /* Make sure the chip is stopped. */ 18091398Stmm gem_reset(sc); 18191398Stmm 182161928Sjmg error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183161928Sjmg BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 184174987Smarius BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 185174987Smarius NULL, &sc->sc_pdmatag); 186194763Smarius if (error != 0) 187147256Sbrooks goto fail_ifnet; 18891398Stmm 18991398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 190170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 191170273Syongari 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 192194763Smarius if (error != 0) 193108832Stmm goto fail_ptag; 19491398Stmm 195108832Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 196170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 197170273Syongari MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198117126Sscottl BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 199194763Smarius if (error != 0) 200108832Stmm goto fail_rtag; 201108832Stmm 20291398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 203170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 20491398Stmm sizeof(struct gem_control_data), 1, 205170273Syongari sizeof(struct gem_control_data), 0, 206170273Syongari NULL, NULL, &sc->sc_cdmatag); 207194763Smarius if (error != 0) 208108832Stmm goto fail_ttag; 20991398Stmm 21091398Stmm /* 211174987Smarius * Allocate the control data structures, create and load the 21291398Stmm * DMA map for it. 21391398Stmm */ 21491398Stmm if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 215170273Syongari (void **)&sc->sc_control_data, 216170273Syongari BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 217194763Smarius &sc->sc_cddmamap)) != 0) { 218174987Smarius device_printf(sc->sc_dev, 219174987Smarius "unable to allocate control data, error = %d\n", error); 220108832Stmm goto fail_ctag; 22191398Stmm } 22291398Stmm 22391398Stmm sc->sc_cddma = 0; 22491398Stmm if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 22591398Stmm sc->sc_control_data, sizeof(struct gem_control_data), 22691398Stmm gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 227174987Smarius device_printf(sc->sc_dev, 228174987Smarius "unable to load control data DMA map, error = %d\n", 229174987Smarius error); 230108832Stmm goto fail_cmem; 23191398Stmm } 23291398Stmm 23391398Stmm /* 23491398Stmm * Initialize the transmit job descriptors. 23591398Stmm */ 23691398Stmm STAILQ_INIT(&sc->sc_txfreeq); 23791398Stmm STAILQ_INIT(&sc->sc_txdirtyq); 23891398Stmm 23991398Stmm /* 24091398Stmm * Create the transmit buffer DMA maps. 24191398Stmm */ 24291398Stmm error = ENOMEM; 24391398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 24491398Stmm txs = &sc->sc_txsoft[i]; 24591398Stmm txs->txs_mbuf = NULL; 24691398Stmm txs->txs_ndescs = 0; 247108832Stmm if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 24891398Stmm &txs->txs_dmamap)) != 0) { 249174987Smarius device_printf(sc->sc_dev, 250174987Smarius "unable to create TX DMA map %d, error = %d\n", 251174987Smarius i, error); 252108832Stmm goto fail_txd; 25391398Stmm } 25491398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 25591398Stmm } 25691398Stmm 25791398Stmm /* 25891398Stmm * Create the receive buffer DMA maps. 25991398Stmm */ 26091398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 261108832Stmm if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 26291398Stmm &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263174987Smarius device_printf(sc->sc_dev, 264174987Smarius "unable to create RX DMA map %d, error = %d\n", 265174987Smarius i, error); 266108832Stmm goto fail_rxd; 26791398Stmm } 26891398Stmm sc->sc_rxsoft[i].rxs_mbuf = NULL; 26991398Stmm } 27091398Stmm 271212725Smarius /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 272212725Smarius if ((sc->sc_flags & GEM_SERDES) != 0) 273212725Smarius goto serdes; 274212725Smarius 275172334Smarius /* Bad things will happen when touching this register on ERI. */ 276212725Smarius if (sc->sc_variant != GEM_SUN_ERI) { 277177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 278172334Smarius GEM_MII_DATAPATH_MII); 279212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 280212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 281212725Smarius } 282172334Smarius 28391398Stmm gem_mifinit(sc); 28491398Stmm 285172334Smarius /* 286172334Smarius * Look for an external PHY. 287172334Smarius */ 288172334Smarius error = ENXIO; 289177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 290172334Smarius if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 291172334Smarius v |= GEM_MIF_CONFIG_PHY_SEL; 292177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 293212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 294212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 295172334Smarius switch (sc->sc_variant) { 296172334Smarius case GEM_SUN_ERI: 297213893Smarius phy = GEM_PHYAD_EXTERNAL; 298172334Smarius break; 299172334Smarius default: 300213893Smarius phy = MII_PHY_ANY; 301172334Smarius break; 302172334Smarius } 303213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 304213893Smarius gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 305215722Smarius MII_OFFSET_ANY, MIIF_DOPAUSE); 306172334Smarius } 307172334Smarius 308172334Smarius /* 309172334Smarius * Fall back on an internal PHY if no external PHY was found. 310204222Smarius * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 311204222Smarius * trusted when the firmware has powered down the chip. 312172334Smarius */ 313204222Smarius if (error != 0 && 314204222Smarius ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 315172334Smarius v &= ~GEM_MIF_CONFIG_PHY_SEL; 316177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 317212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 318212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 319172334Smarius switch (sc->sc_variant) { 320172334Smarius case GEM_SUN_ERI: 321172334Smarius case GEM_APPLE_K2_GMAC: 322213893Smarius phy = GEM_PHYAD_INTERNAL; 323172334Smarius break; 324172334Smarius case GEM_APPLE_GMAC: 325213893Smarius phy = GEM_PHYAD_EXTERNAL; 326172334Smarius break; 327172334Smarius default: 328213893Smarius phy = MII_PHY_ANY; 329172334Smarius break; 330172334Smarius } 331213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 332213893Smarius gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 333215722Smarius MII_OFFSET_ANY, MIIF_DOPAUSE); 334172334Smarius } 335172334Smarius 336172334Smarius /* 337172334Smarius * Try the external PCS SERDES if we didn't find any PHYs. 338172334Smarius */ 339172334Smarius if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 340212725Smarius serdes: 341177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 342172334Smarius GEM_MII_DATAPATH_SERDES); 343212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 344212725Smarius BUS_SPACE_BARRIER_WRITE); 345177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 346172334Smarius GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 347212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 348212725Smarius BUS_SPACE_BARRIER_WRITE); 349177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 350212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 351212725Smarius BUS_SPACE_BARRIER_WRITE); 352172334Smarius sc->sc_flags |= GEM_SERDES; 353213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 354213893Smarius gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, 355215722Smarius GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 356172334Smarius } 357172334Smarius if (error != 0) { 358213893Smarius device_printf(sc->sc_dev, "attaching PHYs failed\n"); 359108832Stmm goto fail_rxd; 36091398Stmm } 36191398Stmm sc->sc_mii = device_get_softc(sc->sc_miibus); 36291398Stmm 36391398Stmm /* 36491398Stmm * From this point forward, the attachment cannot fail. A failure 36591398Stmm * before this point releases all resources that may have been 36691398Stmm * allocated. 36791398Stmm */ 36891398Stmm 369176996Smarius /* Get RX FIFO size. */ 37099726Sbenno sc->sc_rxfifosize = 64 * 371177560Smarius GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 37299726Sbenno 373176996Smarius /* Get TX FIFO size. */ 374177560Smarius v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 375128588Stmm device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 376128588Stmm sc->sc_rxfifosize / 1024, v / 16); 37799726Sbenno 37891398Stmm /* Attach the interface. */ 379147256Sbrooks ether_ifattach(ifp, sc->sc_enaddr); 38091398Stmm 38191398Stmm /* 382170273Syongari * Tell the upper layer(s) we support long frames/checksum offloads. 383149552Smarius */ 384149552Smarius ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 385170273Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 386170273Syongari ifp->if_hwassist |= sc->sc_csum_features; 387170273Syongari ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 388149552Smarius 38991398Stmm return (0); 39091398Stmm 39191398Stmm /* 39291398Stmm * Free any resources we've allocated during the failed attach 39391398Stmm * attempt. Do this in reverse order and fall through. 39491398Stmm */ 395174987Smarius fail_rxd: 396174987Smarius for (i = 0; i < GEM_NRXDESC; i++) 39791398Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 398108832Stmm bus_dmamap_destroy(sc->sc_rdmatag, 39991398Stmm sc->sc_rxsoft[i].rxs_dmamap); 400174987Smarius fail_txd: 401174987Smarius for (i = 0; i < GEM_TXQUEUELEN; i++) 40291398Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 403108832Stmm bus_dmamap_destroy(sc->sc_tdmatag, 40491398Stmm sc->sc_txsoft[i].txs_dmamap); 405108832Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 406174987Smarius fail_cmem: 40791398Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 40891398Stmm sc->sc_cddmamap); 409174987Smarius fail_ctag: 41091398Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 411174987Smarius fail_ttag: 412108832Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 413174987Smarius fail_rtag: 414108832Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 415174987Smarius fail_ptag: 41691398Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 417174987Smarius fail_ifnet: 418147256Sbrooks if_free(ifp); 41991398Stmm return (error); 42091398Stmm} 42191398Stmm 422108964Stmmvoid 423174987Smariusgem_detach(struct gem_softc *sc) 424108964Stmm{ 425147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 426108964Stmm int i; 427108964Stmm 428194886Smarius ether_ifdetach(ifp); 429148369Smarius GEM_LOCK(sc); 430147317Sbrooks gem_stop(ifp, 1); 431148369Smarius GEM_UNLOCK(sc); 432150285Smarius callout_drain(&sc->sc_tick_ch); 433150285Smarius#ifdef GEM_RINT_TIMEOUT 434150285Smarius callout_drain(&sc->sc_rx_ch); 435150285Smarius#endif 436147256Sbrooks if_free(ifp); 437108964Stmm device_delete_child(sc->sc_dev, sc->sc_miibus); 438108964Stmm 439174987Smarius for (i = 0; i < GEM_NRXDESC; i++) 440108964Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 441108964Stmm bus_dmamap_destroy(sc->sc_rdmatag, 442108964Stmm sc->sc_rxsoft[i].rxs_dmamap); 443174987Smarius for (i = 0; i < GEM_TXQUEUELEN; i++) 444108964Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 445108964Stmm bus_dmamap_destroy(sc->sc_tdmatag, 446108964Stmm sc->sc_txsoft[i].txs_dmamap); 447179925Smarius GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 448108964Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 449108964Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 450108964Stmm sc->sc_cddmamap); 451108964Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 452108964Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 453108964Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 454108964Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 455108964Stmm} 456108964Stmm 457108964Stmmvoid 458174987Smariusgem_suspend(struct gem_softc *sc) 459108964Stmm{ 460147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 461108964Stmm 462148369Smarius GEM_LOCK(sc); 463108964Stmm gem_stop(ifp, 0); 464148369Smarius GEM_UNLOCK(sc); 465108964Stmm} 466108964Stmm 467108964Stmmvoid 468174987Smariusgem_resume(struct gem_softc *sc) 469108964Stmm{ 470147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 471108964Stmm 472148369Smarius GEM_LOCK(sc); 473149552Smarius /* 474149552Smarius * On resume all registers have to be initialized again like 475149552Smarius * after power-on. 476149552Smarius */ 477172334Smarius sc->sc_flags &= ~GEM_INITED; 478108964Stmm if (ifp->if_flags & IFF_UP) 479148369Smarius gem_init_locked(sc); 480148369Smarius GEM_UNLOCK(sc); 481108964Stmm} 482108964Stmm 483194763Smariusstatic inline void 484170273Syongarigem_rxcksum(struct mbuf *m, uint64_t flags) 485170273Syongari{ 486170273Syongari struct ether_header *eh; 487170273Syongari struct ip *ip; 488170273Syongari struct udphdr *uh; 489174987Smarius uint16_t *opts; 490170273Syongari int32_t hlen, len, pktlen; 491170273Syongari uint32_t temp32; 492174987Smarius uint16_t cksum; 493170273Syongari 494170273Syongari pktlen = m->m_pkthdr.len; 495170273Syongari if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 496170273Syongari return; 497170273Syongari eh = mtod(m, struct ether_header *); 498170273Syongari if (eh->ether_type != htons(ETHERTYPE_IP)) 499170273Syongari return; 500170273Syongari ip = (struct ip *)(eh + 1); 501170273Syongari if (ip->ip_v != IPVERSION) 502170273Syongari return; 503170273Syongari 504170273Syongari hlen = ip->ip_hl << 2; 505170273Syongari pktlen -= sizeof(struct ether_header); 506170273Syongari if (hlen < sizeof(struct ip)) 507170273Syongari return; 508170273Syongari if (ntohs(ip->ip_len) < hlen) 509170273Syongari return; 510170273Syongari if (ntohs(ip->ip_len) != pktlen) 511170273Syongari return; 512170273Syongari if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 513174987Smarius return; /* Cannot handle fragmented packet. */ 514170273Syongari 515170273Syongari switch (ip->ip_p) { 516170273Syongari case IPPROTO_TCP: 517170273Syongari if (pktlen < (hlen + sizeof(struct tcphdr))) 518170273Syongari return; 519170273Syongari break; 520170273Syongari case IPPROTO_UDP: 521170273Syongari if (pktlen < (hlen + sizeof(struct udphdr))) 522170273Syongari return; 523170273Syongari uh = (struct udphdr *)((uint8_t *)ip + hlen); 524170273Syongari if (uh->uh_sum == 0) 525170273Syongari return; /* no checksum */ 526170273Syongari break; 527170273Syongari default: 528170273Syongari return; 529170273Syongari } 530170273Syongari 531170273Syongari cksum = ~(flags & GEM_RD_CHECKSUM); 532170273Syongari /* checksum fixup for IP options */ 533170273Syongari len = hlen - sizeof(struct ip); 534170273Syongari if (len > 0) { 535170273Syongari opts = (uint16_t *)(ip + 1); 536170273Syongari for (; len > 0; len -= sizeof(uint16_t), opts++) { 537170273Syongari temp32 = cksum - *opts; 538170273Syongari temp32 = (temp32 >> 16) + (temp32 & 65535); 539170273Syongari cksum = temp32 & 65535; 540170273Syongari } 541170273Syongari } 542170273Syongari m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 543170273Syongari m->m_pkthdr.csum_data = cksum; 544170273Syongari} 545170273Syongari 54691398Stmmstatic void 547174987Smariusgem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 54891398Stmm{ 549174987Smarius struct gem_softc *sc = xsc; 55091398Stmm 55191398Stmm if (error != 0) 55291398Stmm return; 553174987Smarius if (nsegs != 1) 554172334Smarius panic("%s: bad control buffer segment count", __func__); 55591398Stmm sc->sc_cddma = segs[0].ds_addr; 55691398Stmm} 55791398Stmm 55891398Stmmstatic void 559174987Smariusgem_tick(void *arg) 56091398Stmm{ 561170273Syongari struct gem_softc *sc = arg; 562194763Smarius struct ifnet *ifp = sc->sc_ifp; 563182060Smarius uint32_t v; 56491398Stmm 565170273Syongari GEM_LOCK_ASSERT(sc, MA_OWNED); 566170273Syongari 567108832Stmm /* 568182060Smarius * Unload collision and error counters. 569108832Stmm */ 570170273Syongari ifp->if_collisions += 571177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 572182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 573182060Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 574177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 575182060Smarius ifp->if_collisions += v; 576182060Smarius ifp->if_oerrors += v; 577182060Smarius ifp->if_ierrors += 578182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 579182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 580182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 581182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 58291398Stmm 58391398Stmm /* 584176996Smarius * Then clear the hardware counters. 58591398Stmm */ 586177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 587177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 588177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 589177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 590182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 591182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 592182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 593182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 594108832Stmm 59591398Stmm mii_tick(sc->sc_mii); 59691398Stmm 597164931Smarius if (gem_watchdog(sc) == EJUSTRETURN) 598164931Smarius return; 599164931Smarius 60091398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 60191398Stmm} 60291398Stmm 60391398Stmmstatic int 604177560Smariusgem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 605177560Smarius uint32_t set) 60691398Stmm{ 60791398Stmm int i; 608174987Smarius uint32_t reg; 60991398Stmm 610194763Smarius for (i = GEM_TRIES; i--; DELAY(100)) { 611177560Smarius reg = GEM_BANKN_READ_M(bank, 4, sc, r); 612170847Smarius if ((reg & clr) == 0 && (reg & set) == set) 61391398Stmm return (1); 61491398Stmm } 61591398Stmm return (0); 61691398Stmm} 61791398Stmm 618172334Smariusstatic void 619194763Smariusgem_reset(struct gem_softc *sc) 62091398Stmm{ 62191398Stmm 622115030Stmm#ifdef GEM_DEBUG 623170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 624115030Stmm#endif 62591398Stmm gem_reset_rx(sc); 62691398Stmm gem_reset_tx(sc); 62791398Stmm 628174987Smarius /* Do a full reset. */ 629177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 630179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 631179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 632177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 63391398Stmm device_printf(sc->sc_dev, "cannot reset device\n"); 63491398Stmm} 63591398Stmm 63691398Stmmstatic void 637174987Smariusgem_rxdrain(struct gem_softc *sc) 63891398Stmm{ 63991398Stmm struct gem_rxsoft *rxs; 64091398Stmm int i; 64191398Stmm 64291398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 64391398Stmm rxs = &sc->sc_rxsoft[i]; 64491398Stmm if (rxs->rxs_mbuf != NULL) { 645109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 646109648Stmm BUS_DMASYNC_POSTREAD); 647108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 64891398Stmm m_freem(rxs->rxs_mbuf); 64991398Stmm rxs->rxs_mbuf = NULL; 65091398Stmm } 65191398Stmm } 65291398Stmm} 65391398Stmm 65491398Stmmstatic void 655174987Smariusgem_stop(struct ifnet *ifp, int disable) 65691398Stmm{ 657174987Smarius struct gem_softc *sc = ifp->if_softc; 65891398Stmm struct gem_txsoft *txs; 65991398Stmm 660115030Stmm#ifdef GEM_DEBUG 661170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 662115030Stmm#endif 66391398Stmm 66491398Stmm callout_stop(&sc->sc_tick_ch); 665150285Smarius#ifdef GEM_RINT_TIMEOUT 666150285Smarius callout_stop(&sc->sc_rx_ch); 667172334Smarius#endif 66891398Stmm 669194763Smarius gem_reset_tx(sc); 670194763Smarius gem_reset_rx(sc); 67191398Stmm 67291398Stmm /* 67391398Stmm * Release any queued transmit buffers. 67491398Stmm */ 67591398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 67691398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 67791398Stmm if (txs->txs_ndescs != 0) { 678109648Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 679109648Stmm BUS_DMASYNC_POSTWRITE); 680108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 68191398Stmm if (txs->txs_mbuf != NULL) { 68291398Stmm m_freem(txs->txs_mbuf); 68391398Stmm txs->txs_mbuf = NULL; 68491398Stmm } 68591398Stmm } 68691398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 68791398Stmm } 68891398Stmm 68991398Stmm if (disable) 69091398Stmm gem_rxdrain(sc); 69191398Stmm 69291398Stmm /* 69391398Stmm * Mark the interface down and cancel the watchdog timer. 69491398Stmm */ 695148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 696172334Smarius sc->sc_flags &= ~GEM_LINK; 697164931Smarius sc->sc_wdog_timer = 0; 69891398Stmm} 69991398Stmm 700172334Smariusstatic int 701174987Smariusgem_reset_rx(struct gem_softc *sc) 70291398Stmm{ 70391398Stmm 70491398Stmm /* 70591398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 70691398Stmm * disable DMA first. 70791398Stmm */ 70891398Stmm gem_disable_rx(sc); 709177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 710179925Smarius GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 711179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 712177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 713172334Smarius device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 71491398Stmm 715215722Smarius /* Wait 5ms extra. */ 716215722Smarius DELAY(5000); 717215722Smarius 718176996Smarius /* Finally, reset the ERX. */ 719177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX); 720179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 721179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 722177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 723177560Smarius 0)) { 72491398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 72591398Stmm return (1); 72691398Stmm } 72791398Stmm return (0); 72891398Stmm} 72991398Stmm 730172334Smarius/* 731172334Smarius * Reset the receiver DMA engine. 732172334Smarius * 733172334Smarius * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 734172334Smarius * etc in order to reset the receiver DMA engine only and not do a full 735172334Smarius * reset which amongst others also downs the link and clears the FIFOs. 736172334Smarius */ 737172334Smariusstatic void 738172334Smariusgem_reset_rxdma(struct gem_softc *sc) 739172334Smarius{ 740172334Smarius int i; 74191398Stmm 742172334Smarius if (gem_reset_rx(sc) != 0) 743172334Smarius return (gem_init_locked(sc)); 744172334Smarius for (i = 0; i < GEM_NRXDESC; i++) 745172334Smarius if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 746172334Smarius GEM_UPDATE_RXDESC(sc, i); 747172334Smarius sc->sc_rxptr = 0; 748194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 749172334Smarius 750172334Smarius /* NOTE: we use only 32-bit DMA addresses here. */ 751177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 752177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 753177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 754177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 755174987Smarius gem_ringsize(GEM_NRXDESC /* XXX */) | 756172334Smarius ((ETHER_HDR_LEN + sizeof(struct ip)) << 757172334Smarius GEM_RX_CONFIG_CXM_START_SHFT) | 758172334Smarius (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 759194763Smarius (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 760194763Smarius /* Adjust for the SBus clock probably isn't worth the fuzz. */ 761177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 762194763Smarius ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 763194763Smarius GEM_RX_BLANKING_TIME_SHIFT) | 6); 764177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 765174987Smarius (3 * sc->sc_rxfifosize / 256) | 766174987Smarius ((sc->sc_rxfifosize / 256) << 12)); 767177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 768177560Smarius GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 769177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 770172334Smarius GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 771177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 772177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE); 773172334Smarius} 774172334Smarius 77591398Stmmstatic int 776174987Smariusgem_reset_tx(struct gem_softc *sc) 77791398Stmm{ 77891398Stmm 77991398Stmm /* 78091398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 78191398Stmm * disable DMA first. 78291398Stmm */ 78391398Stmm gem_disable_tx(sc); 784177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 785179925Smarius GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 786179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 787177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 788172334Smarius device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 78991398Stmm 790215722Smarius /* Wait 5ms extra. */ 791215722Smarius DELAY(5000); 792215722Smarius 793176996Smarius /* Finally, reset the ETX. */ 794177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX); 795179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 796179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 797177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 798177560Smarius 0)) { 799172334Smarius device_printf(sc->sc_dev, "cannot reset transmitter\n"); 80091398Stmm return (1); 80191398Stmm } 80291398Stmm return (0); 80391398Stmm} 80491398Stmm 80591398Stmmstatic int 806174987Smariusgem_disable_rx(struct gem_softc *sc) 80791398Stmm{ 80891398Stmm 809177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 810177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 811179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 812179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 813177560Smarius return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 814177560Smarius 0)); 81591398Stmm} 81691398Stmm 81791398Stmmstatic int 818174987Smariusgem_disable_tx(struct gem_softc *sc) 81991398Stmm{ 82091398Stmm 821177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 822177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 823179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 824179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 825177560Smarius return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 826177560Smarius 0)); 82791398Stmm} 82891398Stmm 82991398Stmmstatic int 830194763Smariusgem_meminit(struct gem_softc *sc) 83191398Stmm{ 83291398Stmm struct gem_rxsoft *rxs; 833174987Smarius int error, i; 83491398Stmm 835194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 836194763Smarius 83791398Stmm /* 83891398Stmm * Initialize the transmit descriptor ring. 83991398Stmm */ 84091398Stmm for (i = 0; i < GEM_NTXDESC; i++) { 84191398Stmm sc->sc_txdescs[i].gd_flags = 0; 84291398Stmm sc->sc_txdescs[i].gd_addr = 0; 84391398Stmm } 844108832Stmm sc->sc_txfree = GEM_MAXTXFREE; 84591398Stmm sc->sc_txnext = 0; 84699726Sbenno sc->sc_txwin = 0; 84791398Stmm 84891398Stmm /* 84991398Stmm * Initialize the receive descriptor and receive job 85091398Stmm * descriptor rings. 85191398Stmm */ 85291398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 85391398Stmm rxs = &sc->sc_rxsoft[i]; 85491398Stmm if (rxs->rxs_mbuf == NULL) { 85591398Stmm if ((error = gem_add_rxbuf(sc, i)) != 0) { 856174987Smarius device_printf(sc->sc_dev, 857174987Smarius "unable to allocate or map RX buffer %d, " 858174987Smarius "error = %d\n", i, error); 85991398Stmm /* 860174987Smarius * XXX we should attempt to run with fewer 861174987Smarius * receive buffers instead of just failing. 86291398Stmm */ 86391398Stmm gem_rxdrain(sc); 86491398Stmm return (1); 86591398Stmm } 86691398Stmm } else 86791398Stmm GEM_INIT_RXDESC(sc, i); 86891398Stmm } 86991398Stmm sc->sc_rxptr = 0; 87091398Stmm 871194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 872194763Smarius 87391398Stmm return (0); 87491398Stmm} 87591398Stmm 876172334Smariusstatic u_int 877174987Smariusgem_ringsize(u_int sz) 87891398Stmm{ 87991398Stmm 88091398Stmm switch (sz) { 88191398Stmm case 32: 882172334Smarius return (GEM_RING_SZ_32); 88391398Stmm case 64: 884172334Smarius return (GEM_RING_SZ_64); 88591398Stmm case 128: 886172334Smarius return (GEM_RING_SZ_128); 88791398Stmm case 256: 888172334Smarius return (GEM_RING_SZ_256); 88991398Stmm case 512: 890172334Smarius return (GEM_RING_SZ_512); 89191398Stmm case 1024: 892172334Smarius return (GEM_RING_SZ_1024); 89391398Stmm case 2048: 894172334Smarius return (GEM_RING_SZ_2048); 89591398Stmm case 4096: 896172334Smarius return (GEM_RING_SZ_4096); 89791398Stmm case 8192: 898172334Smarius return (GEM_RING_SZ_8192); 89991398Stmm default: 900172334Smarius printf("%s: invalid ring size %d\n", __func__, sz); 901172334Smarius return (GEM_RING_SZ_32); 90291398Stmm } 90391398Stmm} 90491398Stmm 905148369Smariusstatic void 906174987Smariusgem_init(void *xsc) 907148369Smarius{ 908174987Smarius struct gem_softc *sc = xsc; 909148369Smarius 910148369Smarius GEM_LOCK(sc); 911148369Smarius gem_init_locked(sc); 912148369Smarius GEM_UNLOCK(sc); 913148369Smarius} 914148369Smarius 91591398Stmm/* 91691398Stmm * Initialization of interface; set up initialization block 91791398Stmm * and transmit/receive descriptor rings. 91891398Stmm */ 91991398Stmmstatic void 920174987Smariusgem_init_locked(struct gem_softc *sc) 92191398Stmm{ 922147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 923174987Smarius uint32_t v; 92491398Stmm 925148369Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 92691398Stmm 927115030Stmm#ifdef GEM_DEBUG 928170273Syongari CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 929170273Syongari __func__); 930115030Stmm#endif 93191398Stmm /* 932174987Smarius * Initialization sequence. The numbered steps below correspond 93391398Stmm * to the sequence outlined in section 6.3.5.1 in the Ethernet 93491398Stmm * Channel Engine manual (part of the PCIO manual). 93591398Stmm * See also the STP2002-STQ document from Sun Microsystems. 93691398Stmm */ 93791398Stmm 938174987Smarius /* step 1 & 2. Reset the Ethernet Channel. */ 939179925Smarius gem_stop(ifp, 0); 94091398Stmm gem_reset(sc); 941115030Stmm#ifdef GEM_DEBUG 942170273Syongari CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 943170273Syongari __func__); 944115030Stmm#endif 94591398Stmm 946212725Smarius if ((sc->sc_flags & GEM_SERDES) == 0) 947212725Smarius /* Re-initialize the MIF. */ 948212725Smarius gem_mifinit(sc); 94991398Stmm 950174987Smarius /* step 3. Setup data structures in host memory. */ 951172334Smarius if (gem_meminit(sc) != 0) 952172334Smarius return; 95391398Stmm 954174987Smarius /* step 4. TX MAC registers & counters */ 95591398Stmm gem_init_regs(sc); 95691398Stmm 957174987Smarius /* step 5. RX MAC registers & counters */ 95891398Stmm gem_setladrf(sc); 95991398Stmm 960174987Smarius /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 96191398Stmm /* NOTE: we use only 32-bit DMA addresses here. */ 962177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 963177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 96491398Stmm 965177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 966177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 967115030Stmm#ifdef GEM_DEBUG 968174987Smarius CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 96991398Stmm GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 970115030Stmm#endif 97191398Stmm 972174987Smarius /* step 8. Global Configuration & Interrupt Mask */ 973194763Smarius 974194763Smarius /* 975194763Smarius * Set the internal arbitration to "infinite" bursts of the 976194763Smarius * maximum length of 31 * 64 bytes so DMA transfers aren't 977194763Smarius * split up in cache line size chunks. This greatly improves 978194763Smarius * RX performance. 979194763Smarius * Enable silicon bug workarounds for the Apple variants. 980194763Smarius */ 981194763Smarius GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 982194763Smarius GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 983194763Smarius ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 984194763Smarius GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 985194763Smarius GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 986194763Smarius 987177560Smarius GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 988172334Smarius ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 989172334Smarius GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 990172334Smarius GEM_INTR_BERR 991172334Smarius#ifdef GEM_DEBUG 992172334Smarius | GEM_INTR_PCS | GEM_INTR_MIF 993172334Smarius#endif 994172334Smarius )); 995177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 996172334Smarius GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 997177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 998194763Smarius GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 999194763Smarius GEM_MAC_TX_PEAK_EXP); 1000172334Smarius#ifdef GEM_DEBUG 1001177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 1002172334Smarius ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 1003172334Smarius#else 1004177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 1005172334Smarius GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1006172334Smarius#endif 100791398Stmm 1008174987Smarius /* step 9. ETX Configuration: use mostly default values. */ 100991398Stmm 1010174987Smarius /* Enable DMA. */ 1011194763Smarius v = gem_ringsize(GEM_NTXDESC); 1012194763Smarius /* Set TX FIFO threshold and enable DMA. */ 1013179925Smarius v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1014179925Smarius GEM_TX_CONFIG_TXFIFO_TH; 1015179925Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 101691398Stmm 1017174987Smarius /* step 10. ERX Configuration */ 101891398Stmm 1019172334Smarius /* Encode Receive Descriptor ring size. */ 1020174987Smarius v = gem_ringsize(GEM_NRXDESC /* XXX */); 1021174987Smarius /* RX TCP/UDP checksum offset */ 1022170273Syongari v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 1023170273Syongari GEM_RX_CONFIG_CXM_START_SHFT); 1024194763Smarius /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1025177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1026174987Smarius v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1027194763Smarius (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1028194763Smarius GEM_RX_CONFIG_RXDMA_EN); 1029172334Smarius 1030194763Smarius /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1031177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1032194763Smarius ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1033194763Smarius GEM_RX_BLANKING_TIME_SHIFT) | 6); 1034172334Smarius 103591398Stmm /* 103699726Sbenno * The following value is for an OFF Threshold of about 3/4 full 103799726Sbenno * and an ON Threshold of 1/4 full. 103891398Stmm */ 1039177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 104099726Sbenno (3 * sc->sc_rxfifosize / 256) | 1041174987Smarius ((sc->sc_rxfifosize / 256) << 12)); 104291398Stmm 1043174987Smarius /* step 11. Configure Media. */ 104491398Stmm 1045174987Smarius /* step 12. RX_MAC Configuration Register */ 1046177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1047179925Smarius v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1048177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 1049179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1050179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1051177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1052179925Smarius device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1053177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 105491398Stmm 1055194763Smarius /* step 13. TX_MAC Configuration Register */ 1056179925Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1057179925Smarius v |= GEM_MAC_TX_ENABLE; 1058179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1059179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1060179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1061179925Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1062179925Smarius device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1063179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1064179925Smarius 1065174987Smarius /* step 14. Issue Transmit Pending command. */ 106691398Stmm 1067220941Smarius /* step 15. Give the receiver a swift kick. */ 1068177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 106991398Stmm 1070172334Smarius ifp->if_drv_flags |= IFF_DRV_RUNNING; 1071172334Smarius ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1072172334Smarius 1073172334Smarius mii_mediachg(sc->sc_mii); 1074172334Smarius 107591398Stmm /* Start the one second timer. */ 1076164931Smarius sc->sc_wdog_timer = 0; 107791398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 107891398Stmm} 107991398Stmm 108091398Stmmstatic int 1081174987Smariusgem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 108291398Stmm{ 1083174987Smarius bus_dma_segment_t txsegs[GEM_NTXSEGS]; 108491398Stmm struct gem_txsoft *txs; 1085179925Smarius struct ip *ip; 1086170273Syongari struct mbuf *m; 1087174987Smarius uint64_t cflags, flags; 1088179925Smarius int error, nexttx, nsegs, offset, seg; 108991398Stmm 1090194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1091194763Smarius 1092108832Stmm /* Get a work queue entry. */ 1093108832Stmm if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1094108832Stmm /* Ran out of descriptors. */ 1095170273Syongari return (ENOBUFS); 1096108832Stmm } 1097179925Smarius 1098179925Smarius cflags = 0; 1099179925Smarius if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1100179925Smarius if (M_WRITABLE(*m_head) == 0) { 1101179925Smarius m = m_dup(*m_head, M_DONTWAIT); 1102179925Smarius m_freem(*m_head); 1103179925Smarius *m_head = m; 1104179925Smarius if (m == NULL) 1105179925Smarius return (ENOBUFS); 1106179925Smarius } 1107179925Smarius offset = sizeof(struct ether_header); 1108179925Smarius m = m_pullup(*m_head, offset + sizeof(struct ip)); 1109179925Smarius if (m == NULL) { 1110179925Smarius *m_head = NULL; 1111179925Smarius return (ENOBUFS); 1112179925Smarius } 1113179925Smarius ip = (struct ip *)(mtod(m, caddr_t) + offset); 1114179925Smarius offset += (ip->ip_hl << 2); 1115179925Smarius cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1116179925Smarius ((offset + m->m_pkthdr.csum_data) << 1117179925Smarius GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1118179925Smarius *m_head = m; 1119179925Smarius } 1120179925Smarius 1121170273Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1122170273Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1123170273Syongari if (error == EFBIG) { 1124175418Sjhb m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 1125170273Syongari if (m == NULL) { 1126170273Syongari m_freem(*m_head); 1127170273Syongari *m_head = NULL; 1128170273Syongari return (ENOBUFS); 1129170273Syongari } 1130170273Syongari *m_head = m; 1131174987Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1132174987Smarius txs->txs_dmamap, *m_head, txsegs, &nsegs, 1133174987Smarius BUS_DMA_NOWAIT); 1134170273Syongari if (error != 0) { 1135170273Syongari m_freem(*m_head); 1136170273Syongari *m_head = NULL; 1137170273Syongari return (error); 1138170273Syongari } 1139170273Syongari } else if (error != 0) 1140170273Syongari return (error); 1141176996Smarius /* If nsegs is wrong then the stack is corrupt. */ 1142176996Smarius KASSERT(nsegs <= GEM_NTXSEGS, 1143176996Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1144170273Syongari if (nsegs == 0) { 1145170273Syongari m_freem(*m_head); 1146170273Syongari *m_head = NULL; 1147170273Syongari return (EIO); 1148170273Syongari } 1149170273Syongari 1150170273Syongari /* 1151170273Syongari * Ensure we have enough descriptors free to describe 1152170273Syongari * the packet. Note, we always reserve one descriptor 1153174987Smarius * at the end of the ring as a termination point, in 1154174987Smarius * order to prevent wrap-around. 1155170273Syongari */ 1156170273Syongari if (nsegs > sc->sc_txfree - 1) { 1157170273Syongari txs->txs_ndescs = 0; 1158170273Syongari bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1159170273Syongari return (ENOBUFS); 1160170273Syongari } 1161170273Syongari 1162170273Syongari txs->txs_ndescs = nsegs; 1163108832Stmm txs->txs_firstdesc = sc->sc_txnext; 1164170273Syongari nexttx = txs->txs_firstdesc; 1165170273Syongari for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1166172334Smarius#ifdef GEM_DEBUG 1167174987Smarius CTR6(KTR_GEM, 1168174987Smarius "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1169174987Smarius __func__, seg, nexttx, txsegs[seg].ds_len, 1170174987Smarius txsegs[seg].ds_addr, 1171170273Syongari GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1172170273Syongari#endif 1173170273Syongari sc->sc_txdescs[nexttx].gd_addr = 1174170273Syongari GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1175170273Syongari KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1176170273Syongari ("%s: segment size too large!", __func__)); 1177170273Syongari flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1178170273Syongari sc->sc_txdescs[nexttx].gd_flags = 1179170273Syongari GEM_DMA_WRITE(sc, flags | cflags); 1180170273Syongari txs->txs_lastdesc = nexttx; 118191398Stmm } 118291398Stmm 1183174987Smarius /* Set EOP on the last descriptor. */ 1184172334Smarius#ifdef GEM_DEBUG 1185174987Smarius CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1186174987Smarius __func__, seg, nexttx); 1187170273Syongari#endif 1188170273Syongari sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1189170273Syongari GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1190170273Syongari 1191174987Smarius /* Lastly set SOP on the first descriptor. */ 1192172334Smarius#ifdef GEM_DEBUG 1193174987Smarius CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1194174987Smarius __func__, seg, nexttx); 1195170273Syongari#endif 1196170273Syongari if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1197170273Syongari sc->sc_txwin = 0; 1198170273Syongari sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1199170273Syongari GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1200170273Syongari GEM_TD_START_OF_PACKET); 1201170273Syongari } else 1202170273Syongari sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1203170273Syongari GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1204170273Syongari 1205108832Stmm /* Sync the DMA map. */ 1206174987Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1207174987Smarius BUS_DMASYNC_PREWRITE); 120891398Stmm 1209115030Stmm#ifdef GEM_DEBUG 1210170273Syongari CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1211174987Smarius __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1212174987Smarius txs->txs_ndescs); 1213115030Stmm#endif 1214108832Stmm STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1215108832Stmm STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1216170273Syongari txs->txs_mbuf = *m_head; 121791398Stmm 1218108832Stmm sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1219108832Stmm sc->sc_txfree -= txs->txs_ndescs; 1220170273Syongari 1221108832Stmm return (0); 122291398Stmm} 122391398Stmm 122491398Stmmstatic void 1225174987Smariusgem_init_regs(struct gem_softc *sc) 122691398Stmm{ 1227152315Sru const u_char *laddr = IF_LLADDR(sc->sc_ifp); 122891398Stmm 1229194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1230194763Smarius 1231174987Smarius /* These registers are not cleared on reset. */ 1232172334Smarius if ((sc->sc_flags & GEM_INITED) == 0) { 1233174987Smarius /* magic values */ 1234177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1235177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1236177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 123791398Stmm 1238194763Smarius /* min frame length */ 1239177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1240194763Smarius /* max frame length and max burst size */ 1241177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1242172334Smarius (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 124399726Sbenno 1244194763Smarius /* more magic values */ 1245177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1246177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1247177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1248215722Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8808); 1249194763Smarius 1250194763Smarius /* random number seed */ 1251177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1252174987Smarius ((laddr[5] << 8) | laddr[4]) & 0x3ff); 125399726Sbenno 1254174987Smarius /* secondary MAC address: 0:0:0:0:0:0 */ 1255177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1256177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1257177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 125899726Sbenno 1259174987Smarius /* MAC control address: 01:80:c2:00:00:01 */ 1260177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1261177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1262177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 126391398Stmm 1264174987Smarius /* MAC filter address: 0:0:0:0:0:0 */ 1265177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1266177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1267177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1268177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1269177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 127091398Stmm 1271172334Smarius sc->sc_flags |= GEM_INITED; 127291398Stmm } 127391398Stmm 1274174987Smarius /* Counters need to be zeroed. */ 1275177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1276177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1277177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1278177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1279177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1280177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1281177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1282177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1283177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1284177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1285177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 128691398Stmm 1287172334Smarius /* Set XOFF PAUSE time. */ 1288177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 128991398Stmm 1290174987Smarius /* Set the station address. */ 1291177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1292177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1293177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 129499726Sbenno 1295172334Smarius /* Enable MII outputs. */ 1296177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 129791398Stmm} 129891398Stmm 129991398Stmmstatic void 1300174987Smariusgem_start(struct ifnet *ifp) 130191398Stmm{ 1302174987Smarius struct gem_softc *sc = ifp->if_softc; 1303148369Smarius 1304148369Smarius GEM_LOCK(sc); 1305148369Smarius gem_start_locked(ifp); 1306148369Smarius GEM_UNLOCK(sc); 1307148369Smarius} 1308148369Smarius 1309194763Smariusstatic inline void 1310194763Smariusgem_txkick(struct gem_softc *sc) 1311194763Smarius{ 1312194763Smarius 1313194763Smarius /* 1314194763Smarius * Update the TX kick register. This register has to point to the 1315194763Smarius * descriptor after the last valid one and for optimum performance 1316194763Smarius * should be incremented in multiples of 4 (the DMA engine fetches/ 1317194763Smarius * updates descriptors in batches of 4). 1318194763Smarius */ 1319194763Smarius#ifdef GEM_DEBUG 1320194763Smarius CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1321194763Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1322194763Smarius#endif 1323194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1324194763Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1325194763Smarius} 1326194763Smarius 1327148369Smariusstatic void 1328174987Smariusgem_start_locked(struct ifnet *ifp) 1329148369Smarius{ 1330174987Smarius struct gem_softc *sc = ifp->if_softc; 1331170273Syongari struct mbuf *m; 1332194763Smarius int kicked, ntx; 133391398Stmm 1334194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1335194763Smarius 1336148887Srwatson if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1337172334Smarius IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 133891398Stmm return; 133991398Stmm 1340115030Stmm#ifdef GEM_DEBUG 1341170273Syongari CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1342172334Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1343172334Smarius sc->sc_txnext); 1344115030Stmm#endif 1345174987Smarius ntx = 0; 1346194763Smarius kicked = 0; 1347170273Syongari for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1348170273Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1349170273Syongari if (m == NULL) 135091398Stmm break; 1351172334Smarius if (gem_load_txmbuf(sc, &m) != 0) { 1352170273Syongari if (m == NULL) 1353170273Syongari break; 1354170273Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1355170273Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m); 135691398Stmm break; 135791398Stmm } 1358194763Smarius if ((sc->sc_txnext % 4) == 0) { 1359194763Smarius gem_txkick(sc); 1360194763Smarius kicked = 1; 1361194763Smarius } else 1362194763Smarius kicked = 0; 1363115030Stmm ntx++; 1364170273Syongari BPF_MTAP(ifp, m); 136591398Stmm } 136691398Stmm 136791398Stmm if (ntx > 0) { 1368194763Smarius if (kicked == 0) 1369194763Smarius gem_txkick(sc); 1370115030Stmm#ifdef GEM_DEBUG 1371108832Stmm CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1372172334Smarius device_get_name(sc->sc_dev), sc->sc_txnext); 1373115030Stmm#endif 137491398Stmm 137591398Stmm /* Set a watchdog timer in case the chip flakes out. */ 1376164931Smarius sc->sc_wdog_timer = 5; 1377115030Stmm#ifdef GEM_DEBUG 1378170273Syongari CTR3(KTR_GEM, "%s: %s: watchdog %d", 1379174987Smarius device_get_name(sc->sc_dev), __func__, 1380174987Smarius sc->sc_wdog_timer); 1381115030Stmm#endif 138291398Stmm } 138391398Stmm} 138491398Stmm 138591398Stmmstatic void 1386174987Smariusgem_tint(struct gem_softc *sc) 138791398Stmm{ 1388147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 138991398Stmm struct gem_txsoft *txs; 1390194763Smarius int progress; 1391194763Smarius uint32_t txlast; 1392174987Smarius#ifdef GEM_DEBUG 1393174987Smarius int i; 139491398Stmm 1395194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1396194763Smarius 1397170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1398115030Stmm#endif 139991398Stmm 140091398Stmm /* 1401174987Smarius * Go through our TX list and free mbufs for those 140291398Stmm * frames that have been transmitted. 140391398Stmm */ 1404174987Smarius progress = 0; 1405109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 140691398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 140791398Stmm#ifdef GEM_DEBUG 1408174987Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 140991398Stmm printf(" txsoft %p transmit chain:\n", txs); 141091398Stmm for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 141191398Stmm printf("descriptor %d: ", i); 1412174987Smarius printf("gd_flags: 0x%016llx\t", 1413174987Smarius (long long)GEM_DMA_READ(sc, 1414174987Smarius sc->sc_txdescs[i].gd_flags)); 1415174987Smarius printf("gd_addr: 0x%016llx\n", 1416174987Smarius (long long)GEM_DMA_READ(sc, 1417174987Smarius sc->sc_txdescs[i].gd_addr)); 141891398Stmm if (i == txs->txs_lastdesc) 141991398Stmm break; 142091398Stmm } 142191398Stmm } 142291398Stmm#endif 142391398Stmm 142491398Stmm /* 1425172334Smarius * In theory, we could harvest some descriptors before 142691398Stmm * the ring is empty, but that's a bit complicated. 142791398Stmm * 142891398Stmm * GEM_TX_COMPLETION points to the last descriptor 1429174987Smarius * processed + 1. 143091398Stmm */ 1431177560Smarius txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1432115030Stmm#ifdef GEM_DEBUG 1433170273Syongari CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 143491398Stmm "txs->txs_lastdesc = %d, txlast = %d", 1435170273Syongari __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1436115030Stmm#endif 143791398Stmm if (txs->txs_firstdesc <= txs->txs_lastdesc) { 143891398Stmm if ((txlast >= txs->txs_firstdesc) && 1439174987Smarius (txlast <= txs->txs_lastdesc)) 144091398Stmm break; 144191398Stmm } else { 1442174987Smarius /* Ick -- this command wraps. */ 144391398Stmm if ((txlast >= txs->txs_firstdesc) || 1444174987Smarius (txlast <= txs->txs_lastdesc)) 144591398Stmm break; 144691398Stmm } 144791398Stmm 1448115030Stmm#ifdef GEM_DEBUG 1449174987Smarius CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1450115030Stmm#endif 145191398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 145291398Stmm 145391398Stmm sc->sc_txfree += txs->txs_ndescs; 145491398Stmm 1455108832Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 145691398Stmm BUS_DMASYNC_POSTWRITE); 1457108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 145891398Stmm if (txs->txs_mbuf != NULL) { 145991398Stmm m_freem(txs->txs_mbuf); 146091398Stmm txs->txs_mbuf = NULL; 146191398Stmm } 146291398Stmm 146391398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 146491398Stmm 146591398Stmm ifp->if_opackets++; 146699726Sbenno progress = 1; 146791398Stmm } 146891398Stmm 1469115030Stmm#ifdef GEM_DEBUG 1470174987Smarius CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1471172334Smarius "GEM_TX_COMPLETION %x", 1472177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1473177560Smarius ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1474177560Smarius GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1475177560Smarius GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1476115030Stmm#endif 147791398Stmm 147899726Sbenno if (progress) { 147999726Sbenno if (sc->sc_txfree == GEM_NTXDESC - 1) 148099726Sbenno sc->sc_txwin = 0; 148191398Stmm 1482174987Smarius /* 1483174987Smarius * We freed some descriptors, so reset IFF_DRV_OACTIVE 1484174987Smarius * and restart. 1485174987Smarius */ 1486148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1487194763Smarius if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1488194763Smarius sc->sc_wdog_timer = 0; 1489179925Smarius gem_start_locked(ifp); 149099726Sbenno } 149199726Sbenno 1492115030Stmm#ifdef GEM_DEBUG 1493170273Syongari CTR3(KTR_GEM, "%s: %s: watchdog %d", 1494170273Syongari device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1495115030Stmm#endif 149691398Stmm} 149791398Stmm 1498148368Smarius#ifdef GEM_RINT_TIMEOUT 149993045Stmmstatic void 1500174987Smariusgem_rint_timeout(void *arg) 150193045Stmm{ 1502174987Smarius struct gem_softc *sc = arg; 150393045Stmm 1504150285Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1505194763Smarius 1506148369Smarius gem_rint(sc); 150793045Stmm} 1508100587Sjake#endif 150993045Stmm 151091398Stmmstatic void 1511174987Smariusgem_rint(struct gem_softc *sc) 151291398Stmm{ 1513147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 151491398Stmm struct mbuf *m; 1515174987Smarius uint64_t rxstat; 1516174987Smarius uint32_t rxcomp; 151791398Stmm 1518194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1519194763Smarius 1520148368Smarius#ifdef GEM_RINT_TIMEOUT 152193045Stmm callout_stop(&sc->sc_rx_ch); 1522148368Smarius#endif 1523115030Stmm#ifdef GEM_DEBUG 1524170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1525115030Stmm#endif 152699726Sbenno 152791398Stmm /* 152899726Sbenno * Read the completion register once. This limits 152999726Sbenno * how long the following loop can execute. 153099726Sbenno */ 1531177560Smarius rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1532115030Stmm#ifdef GEM_DEBUG 1533194763Smarius CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1534170273Syongari __func__, sc->sc_rxptr, rxcomp); 1535115030Stmm#endif 1536194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1537172334Smarius for (; sc->sc_rxptr != rxcomp;) { 1538172334Smarius m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1539172334Smarius rxstat = GEM_DMA_READ(sc, 1540172334Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 154191398Stmm 154291398Stmm if (rxstat & GEM_RD_OWN) { 1543148368Smarius#ifdef GEM_RINT_TIMEOUT 154491398Stmm /* 154593045Stmm * The descriptor is still marked as owned, although 1546174987Smarius * it is supposed to have completed. This has been 1547174987Smarius * observed on some machines. Just exiting here 154893045Stmm * might leave the packet sitting around until another 154993045Stmm * one arrives to trigger a new interrupt, which is 155093045Stmm * generally undesirable, so set up a timeout. 155191398Stmm */ 155293045Stmm callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 155393045Stmm gem_rint_timeout, sc); 155499726Sbenno#endif 1555172334Smarius m = NULL; 1556172334Smarius goto kickit; 155791398Stmm } 155891398Stmm 155991398Stmm if (rxstat & GEM_RD_BAD_CRC) { 156099726Sbenno ifp->if_ierrors++; 156191398Stmm device_printf(sc->sc_dev, "receive error: CRC error\n"); 1562172334Smarius GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1563172334Smarius m = NULL; 1564172334Smarius goto kickit; 156591398Stmm } 156691398Stmm 156791398Stmm#ifdef GEM_DEBUG 1568174987Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 1569172334Smarius printf(" rxsoft %p descriptor %d: ", 1570172334Smarius &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1571174987Smarius printf("gd_flags: 0x%016llx\t", 1572174987Smarius (long long)GEM_DMA_READ(sc, 1573174987Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1574174987Smarius printf("gd_addr: 0x%016llx\n", 1575174987Smarius (long long)GEM_DMA_READ(sc, 1576174987Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 157791398Stmm } 157891398Stmm#endif 157991398Stmm 158091398Stmm /* 158191398Stmm * Allocate a new mbuf cluster. If that fails, we are 158291398Stmm * out of memory, and must drop the packet and recycle 158391398Stmm * the buffer that's already attached to this descriptor. 158491398Stmm */ 1585172334Smarius if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 158691398Stmm ifp->if_ierrors++; 1587172334Smarius GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1588172334Smarius m = NULL; 1589172334Smarius } 1590172334Smarius 1591174987Smarius kickit: 1592174987Smarius /* 1593174987Smarius * Update the RX kick register. This register has to point 1594172334Smarius * to the descriptor after the last valid one (before the 1595194763Smarius * current batch) and for optimum performance should be 1596194763Smarius * incremented in multiples of 4 (the DMA engine fetches/ 1597194763Smarius * updates descriptors in batches of 4). 1598172334Smarius */ 1599172334Smarius sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1600172334Smarius if ((sc->sc_rxptr % 4) == 0) { 1601179925Smarius GEM_CDSYNC(sc, 1602179925Smarius BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1603177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1604172334Smarius (sc->sc_rxptr + GEM_NRXDESC - 4) & 1605172334Smarius GEM_NRXDESC_MASK); 1606172334Smarius } 1607172334Smarius 1608172334Smarius if (m == NULL) { 1609172334Smarius if (rxstat & GEM_RD_OWN) 1610172334Smarius break; 161191398Stmm continue; 161291398Stmm } 1613172334Smarius 1614172334Smarius ifp->if_ipackets++; 1615194763Smarius m->m_data += ETHER_ALIGN; /* first byte offset */ 161691398Stmm m->m_pkthdr.rcvif = ifp; 1617172334Smarius m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 161891398Stmm 1619170273Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1620170273Syongari gem_rxcksum(m, rxstat); 1621170273Syongari 162291398Stmm /* Pass it on. */ 1623148369Smarius GEM_UNLOCK(sc); 1624106937Ssam (*ifp->if_input)(ifp, m); 1625148369Smarius GEM_LOCK(sc); 162691398Stmm } 162791398Stmm 1628115030Stmm#ifdef GEM_DEBUG 1629194763Smarius CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1630177560Smarius sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1631115030Stmm#endif 163291398Stmm} 163391398Stmm 163491398Stmmstatic int 1635174987Smariusgem_add_rxbuf(struct gem_softc *sc, int idx) 163691398Stmm{ 163791398Stmm struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 163891398Stmm struct mbuf *m; 1639148368Smarius bus_dma_segment_t segs[1]; 1640148368Smarius int error, nsegs; 164191398Stmm 1642194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1643194763Smarius 1644111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 164591398Stmm if (m == NULL) 164691398Stmm return (ENOBUFS); 1647108832Stmm m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 164891398Stmm 164991398Stmm#ifdef GEM_DEBUG 1650174987Smarius /* Bzero the packet to check DMA. */ 165191398Stmm memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 165291398Stmm#endif 165391398Stmm 1654109648Stmm if (rxs->rxs_mbuf != NULL) { 1655109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1656109648Stmm BUS_DMASYNC_POSTREAD); 1657108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1658109648Stmm } 165991398Stmm 1660148368Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1661148368Smarius m, segs, &nsegs, BUS_DMA_NOWAIT); 1662148368Smarius if (error != 0) { 1663174987Smarius device_printf(sc->sc_dev, 1664174987Smarius "cannot load RS DMA map %d, error = %d\n", idx, error); 1665148368Smarius m_freem(m); 1666172334Smarius return (error); 166791398Stmm } 1668174987Smarius /* If nsegs is wrong then the stack is corrupt. */ 1669176996Smarius KASSERT(nsegs == 1, 1670176996Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1671172334Smarius rxs->rxs_mbuf = m; 1672148368Smarius rxs->rxs_paddr = segs[0].ds_addr; 167391398Stmm 1674174987Smarius bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1675174987Smarius BUS_DMASYNC_PREREAD); 167691398Stmm 167791398Stmm GEM_INIT_RXDESC(sc, idx); 167891398Stmm 167991398Stmm return (0); 168091398Stmm} 168191398Stmm 168291398Stmmstatic void 1683174987Smariusgem_eint(struct gem_softc *sc, u_int status) 168491398Stmm{ 168591398Stmm 1686172334Smarius sc->sc_ifp->if_ierrors++; 1687172334Smarius if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1688172334Smarius gem_reset_rxdma(sc); 168991398Stmm return; 169091398Stmm } 169191398Stmm 1692194763Smarius device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1693194763Smarius if ((status & GEM_INTR_BERR) != 0) { 1694194763Smarius if ((sc->sc_flags & GEM_PCI) != 0) 1695194763Smarius printf(", PCI bus error 0x%x\n", 1696194763Smarius GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1697194763Smarius else 1698194763Smarius printf(", SBus error 0x%x\n", 1699194763Smarius GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1700194763Smarius } 170191398Stmm} 170291398Stmm 170391398Stmmvoid 1704174987Smariusgem_intr(void *v) 170591398Stmm{ 1706174987Smarius struct gem_softc *sc = v; 1707172334Smarius uint32_t status, status2; 170891398Stmm 1709148369Smarius GEM_LOCK(sc); 1710177560Smarius status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1711172334Smarius 1712115030Stmm#ifdef GEM_DEBUG 1713170273Syongari CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1714194763Smarius device_get_name(sc->sc_dev), __func__, 1715194763Smarius (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1716172334Smarius 1717172334Smarius /* 1718172334Smarius * PCS interrupts must be cleared, otherwise no traffic is passed! 1719172334Smarius */ 1720172334Smarius if ((status & GEM_INTR_PCS) != 0) { 1721174987Smarius status2 = 1722177560Smarius GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1723177560Smarius GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1724172334Smarius if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1725172334Smarius device_printf(sc->sc_dev, 1726172334Smarius "%s: PCS link status changed\n", __func__); 1727172334Smarius } 1728172334Smarius if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1729177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1730172334Smarius if ((status2 & GEM_MAC_PAUSED) != 0) 1731172334Smarius device_printf(sc->sc_dev, 1732172334Smarius "%s: PAUSE received (PAUSE time %d slots)\n", 1733172334Smarius __func__, GEM_MAC_PAUSE_TIME(status2)); 1734172334Smarius if ((status2 & GEM_MAC_PAUSE) != 0) 1735172334Smarius device_printf(sc->sc_dev, 1736172334Smarius "%s: transited to PAUSE state\n", __func__); 1737172334Smarius if ((status2 & GEM_MAC_RESUME) != 0) 1738172334Smarius device_printf(sc->sc_dev, 1739172334Smarius "%s: transited to non-PAUSE state\n", __func__); 1740172334Smarius } 1741172334Smarius if ((status & GEM_INTR_MIF) != 0) 1742172334Smarius device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1743115030Stmm#endif 174491398Stmm 1745194763Smarius if (__predict_false(status & 1746172334Smarius (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 174791398Stmm gem_eint(sc, status); 174891398Stmm 1749172334Smarius if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1750172334Smarius gem_rint(sc); 1751172334Smarius 175291398Stmm if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 175391398Stmm gem_tint(sc); 175491398Stmm 1755194763Smarius if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1756177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1757174987Smarius if ((status2 & 1758194763Smarius ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1759194763Smarius GEM_MAC_TX_PEAK_EXP)) != 0) 1760174987Smarius device_printf(sc->sc_dev, 1761174987Smarius "MAC TX fault, status %x\n", status2); 1762174987Smarius if ((status2 & 1763194763Smarius (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1764194763Smarius sc->sc_ifp->if_oerrors++; 1765148369Smarius gem_init_locked(sc); 1766194763Smarius } 176791398Stmm } 1768194763Smarius if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1769177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1770149552Smarius /* 1771172334Smarius * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1772172334Smarius * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1773174987Smarius * silicon bug so handle them silently. Moreover, it's 1774172334Smarius * likely that the receiver has hung so we reset it. 1775149552Smarius */ 1776174987Smarius if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1777172334Smarius sc->sc_ifp->if_ierrors++; 1778172334Smarius gem_reset_rxdma(sc); 1779174987Smarius } else if ((status2 & 1780174987Smarius ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1781174987Smarius device_printf(sc->sc_dev, 1782174987Smarius "MAC RX fault, status %x\n", status2); 178391398Stmm } 1784148369Smarius GEM_UNLOCK(sc); 178591398Stmm} 178691398Stmm 1787164931Smariusstatic int 1788174987Smariusgem_watchdog(struct gem_softc *sc) 178991398Stmm{ 1790179925Smarius struct ifnet *ifp = sc->sc_ifp; 179191398Stmm 1792164931Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1793164931Smarius 1794115030Stmm#ifdef GEM_DEBUG 1795174987Smarius CTR4(KTR_GEM, 1796174987Smarius "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1797177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1798177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1799177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1800174987Smarius CTR4(KTR_GEM, 1801174987Smarius "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1802177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1803177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1804177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1805115030Stmm#endif 180691398Stmm 1807164931Smarius if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1808164931Smarius return (0); 1809164931Smarius 1810172334Smarius if ((sc->sc_flags & GEM_LINK) != 0) 1811172334Smarius device_printf(sc->sc_dev, "device timeout\n"); 1812172334Smarius else if (bootverbose) 1813172334Smarius device_printf(sc->sc_dev, "device timeout (no link)\n"); 1814179925Smarius ++ifp->if_oerrors; 181591398Stmm 181691398Stmm /* Try to get more packets going. */ 1817148369Smarius gem_init_locked(sc); 1818179925Smarius gem_start_locked(ifp); 1819164931Smarius return (EJUSTRETURN); 182091398Stmm} 182191398Stmm 182291398Stmmstatic void 1823174987Smariusgem_mifinit(struct gem_softc *sc) 182491398Stmm{ 182591398Stmm 1826176996Smarius /* Configure the MIF in frame mode. */ 1827177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1828177560Smarius GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1829212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 1830212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 183191398Stmm} 183291398Stmm 183391398Stmm/* 183491398Stmm * MII interface 183591398Stmm * 1836182060Smarius * The MII interface supports at least three different operating modes: 183791398Stmm * 183891398Stmm * Bitbang mode is implemented using data, clock and output enable registers. 183991398Stmm * 184091398Stmm * Frame mode is implemented by loading a complete frame into the frame 184191398Stmm * register and polling the valid bit for completion. 184291398Stmm * 184391398Stmm * Polling mode uses the frame register but completion is indicated by 184491398Stmm * an interrupt. 184591398Stmm * 184691398Stmm */ 184791398Stmmint 1848174987Smariusgem_mii_readreg(device_t dev, int phy, int reg) 184991398Stmm{ 1850174987Smarius struct gem_softc *sc; 185191398Stmm int n; 1852174987Smarius uint32_t v; 185391398Stmm 185491398Stmm#ifdef GEM_DEBUG_PHY 1855172334Smarius printf("%s: phy %d reg %d\n", __func__, phy, reg); 185691398Stmm#endif 185791398Stmm 1858174987Smarius sc = device_get_softc(dev); 1859172334Smarius if ((sc->sc_flags & GEM_SERDES) != 0) { 1860172334Smarius switch (reg) { 1861172334Smarius case MII_BMCR: 1862172334Smarius reg = GEM_MII_CONTROL; 1863172334Smarius break; 1864172334Smarius case MII_BMSR: 1865172334Smarius reg = GEM_MII_STATUS; 1866172334Smarius break; 1867172334Smarius case MII_PHYIDR1: 1868172334Smarius case MII_PHYIDR2: 1869172334Smarius return (0); 1870172334Smarius case MII_ANAR: 1871172334Smarius reg = GEM_MII_ANAR; 1872172334Smarius break; 1873172334Smarius case MII_ANLPAR: 1874172334Smarius reg = GEM_MII_ANLPAR; 1875172334Smarius break; 1876172334Smarius case MII_EXTSR: 1877172334Smarius return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1878172334Smarius default: 1879172334Smarius device_printf(sc->sc_dev, 1880172334Smarius "%s: unhandled register %d\n", __func__, reg); 1881172334Smarius return (0); 1882172334Smarius } 1883177560Smarius return (GEM_BANK1_READ_4(sc, reg)); 1884172334Smarius } 1885172334Smarius 1886174987Smarius /* Construct the frame command. */ 1887172334Smarius v = GEM_MIF_FRAME_READ | 1888172334Smarius (phy << GEM_MIF_PHY_SHIFT) | 1889172334Smarius (reg << GEM_MIF_REG_SHIFT); 189091398Stmm 1891177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1892179925Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1893179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 189491398Stmm for (n = 0; n < 100; n++) { 189591398Stmm DELAY(1); 1896177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1897150285Smarius if (v & GEM_MIF_FRAME_TA0) 189891398Stmm return (v & GEM_MIF_FRAME_DATA); 189991398Stmm } 190091398Stmm 1901174987Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 190291398Stmm return (0); 190391398Stmm} 190491398Stmm 190591398Stmmint 1906174987Smariusgem_mii_writereg(device_t dev, int phy, int reg, int val) 190791398Stmm{ 1908174987Smarius struct gem_softc *sc; 190991398Stmm int n; 1910174987Smarius uint32_t v; 191191398Stmm 191291398Stmm#ifdef GEM_DEBUG_PHY 1913172334Smarius printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 191491398Stmm#endif 191591398Stmm 1916174987Smarius sc = device_get_softc(dev); 1917172334Smarius if ((sc->sc_flags & GEM_SERDES) != 0) { 1918172334Smarius switch (reg) { 1919172334Smarius case MII_BMSR: 1920172334Smarius reg = GEM_MII_STATUS; 1921172334Smarius break; 1922179925Smarius case MII_BMCR: 1923179925Smarius reg = GEM_MII_CONTROL; 1924179925Smarius if ((val & GEM_MII_CONTROL_RESET) == 0) 1925179925Smarius break; 1926179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1927179925Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1928179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1929179925Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1930179925Smarius GEM_MII_CONTROL_RESET, 0)) 1931179925Smarius device_printf(sc->sc_dev, 1932179925Smarius "cannot reset PCS\n"); 1933179925Smarius /* FALLTHROUGH */ 1934172334Smarius case MII_ANAR: 1935177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1936177560Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1937172334Smarius BUS_SPACE_BARRIER_WRITE); 1938177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1939212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 1940212725Smarius BUS_SPACE_BARRIER_WRITE); 1941177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1942172334Smarius GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1943212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 1944212725Smarius BUS_SPACE_BARRIER_WRITE); 1945177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1946172334Smarius GEM_MII_CONFIG_ENABLE); 1947212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1948212725Smarius BUS_SPACE_BARRIER_WRITE); 1949172334Smarius return (0); 1950172334Smarius case MII_ANLPAR: 1951172334Smarius reg = GEM_MII_ANLPAR; 1952172334Smarius break; 1953172334Smarius default: 1954172334Smarius device_printf(sc->sc_dev, 1955172334Smarius "%s: unhandled register %d\n", __func__, reg); 1956172334Smarius return (0); 1957172334Smarius } 1958177560Smarius GEM_BANK1_WRITE_4(sc, reg, val); 1959212725Smarius GEM_BANK1_BARRIER(sc, reg, 4, 1960212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1961172334Smarius return (0); 1962172334Smarius } 1963172334Smarius 1964174987Smarius /* Construct the frame command. */ 1965172334Smarius v = GEM_MIF_FRAME_WRITE | 1966172334Smarius (phy << GEM_MIF_PHY_SHIFT) | 1967172334Smarius (reg << GEM_MIF_REG_SHIFT) | 196891398Stmm (val & GEM_MIF_FRAME_DATA); 196991398Stmm 1970177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1971179925Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1972179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 197391398Stmm for (n = 0; n < 100; n++) { 197491398Stmm DELAY(1); 1975177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1976150285Smarius if (v & GEM_MIF_FRAME_TA0) 197791398Stmm return (1); 197891398Stmm } 197991398Stmm 1980174987Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 198191398Stmm return (0); 198291398Stmm} 198391398Stmm 198491398Stmmvoid 1985174987Smariusgem_mii_statchg(device_t dev) 198691398Stmm{ 1987174987Smarius struct gem_softc *sc; 1988172334Smarius int gigabit; 1989172334Smarius uint32_t rxcfg, txcfg, v; 199091398Stmm 1991174987Smarius sc = device_get_softc(dev); 1992174987Smarius 1993194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1994194763Smarius 199591398Stmm#ifdef GEM_DEBUG 1996174987Smarius if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1997213893Smarius device_printf(sc->sc_dev, "%s: status change\n", __func__); 199891398Stmm#endif 199991398Stmm 2000172334Smarius if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2001172334Smarius IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2002172334Smarius sc->sc_flags |= GEM_LINK; 2003172334Smarius else 2004172334Smarius sc->sc_flags &= ~GEM_LINK; 2005172334Smarius 2006172334Smarius switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2007172334Smarius case IFM_1000_SX: 2008172334Smarius case IFM_1000_LX: 2009172334Smarius case IFM_1000_CX: 2010172334Smarius case IFM_1000_T: 2011172334Smarius gigabit = 1; 2012172334Smarius break; 2013172334Smarius default: 2014172334Smarius gigabit = 0; 201591398Stmm } 201691398Stmm 2017172334Smarius /* 2018172334Smarius * The configuration done here corresponds to the steps F) and 2019172334Smarius * G) and as far as enabling of RX and TX MAC goes also step H) 2020172334Smarius * of the initialization sequence outlined in section 3.2.1 of 2021172334Smarius * the GEM Gigabit Ethernet ASIC Specification. 2022172334Smarius */ 2023172334Smarius 2024177560Smarius rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2025172334Smarius rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2026172334Smarius txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2027172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2028172334Smarius txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2029172334Smarius else if (gigabit != 0) { 2030172334Smarius rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2031172334Smarius txcfg |= GEM_MAC_TX_CARR_EXTEND; 2032172334Smarius } 2033177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 2034179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 2035179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2036177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2037172334Smarius device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2038177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2039177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 2040179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2041179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2042177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2043172334Smarius device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2044177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2045172334Smarius 2046177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2047172334Smarius ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2048174987Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2049174987Smarius IFM_ETH_RXPAUSE) != 0) 2050172334Smarius v |= GEM_MAC_CC_RX_PAUSE; 2051174987Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2052174987Smarius IFM_ETH_TXPAUSE) != 0) 2053172334Smarius v |= GEM_MAC_CC_TX_PAUSE; 2054177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2055172334Smarius 2056172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2057172334Smarius gigabit != 0) 2058177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2059172334Smarius GEM_MAC_SLOT_TIME_CARR_EXTEND); 2060172334Smarius else 2061177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2062172334Smarius GEM_MAC_SLOT_TIME_NORMAL); 2063172334Smarius 206491398Stmm /* XIF Configuration */ 206591398Stmm v = GEM_MAC_XIF_LINK_LED; 206691398Stmm v |= GEM_MAC_XIF_TX_MII_ENA; 2067172334Smarius if ((sc->sc_flags & GEM_SERDES) == 0) { 2068177560Smarius if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2069182060Smarius GEM_MIF_CONFIG_PHY_SEL) != 0) { 2070172334Smarius /* External MII needs echo disable if half duplex. */ 2071194763Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2072182060Smarius IFM_FDX) == 0) 2073182060Smarius v |= GEM_MAC_XIF_ECHO_DISABL; 2074182060Smarius } else 2075172334Smarius /* 2076172334Smarius * Internal MII needs buffer enable. 2077172334Smarius * XXX buffer enable makes only sense for an 2078172334Smarius * external PHY. 2079172334Smarius */ 2080172334Smarius v |= GEM_MAC_XIF_MII_BUF_ENA; 2081172334Smarius } 2082172334Smarius if (gigabit != 0) 2083172334Smarius v |= GEM_MAC_XIF_GMII_MODE; 2084172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2085172334Smarius v |= GEM_MAC_XIF_FDPLX_LED; 2086177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 208799726Sbenno 2088172334Smarius if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2089172334Smarius (sc->sc_flags & GEM_LINK) != 0) { 2090177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2091172334Smarius txcfg | GEM_MAC_TX_ENABLE); 2092177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2093172334Smarius rxcfg | GEM_MAC_RX_ENABLE); 209491398Stmm } 209591398Stmm} 209691398Stmm 209791398Stmmint 2098174987Smariusgem_mediachange(struct ifnet *ifp) 209991398Stmm{ 210091398Stmm struct gem_softc *sc = ifp->if_softc; 2101150285Smarius int error; 210291398Stmm 2103174987Smarius /* XXX add support for serial media. */ 210491398Stmm 2105150285Smarius GEM_LOCK(sc); 2106150285Smarius error = mii_mediachg(sc->sc_mii); 2107150285Smarius GEM_UNLOCK(sc); 2108150285Smarius return (error); 210991398Stmm} 211091398Stmm 211191398Stmmvoid 2112174987Smariusgem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 211391398Stmm{ 211491398Stmm struct gem_softc *sc = ifp->if_softc; 211591398Stmm 2116148369Smarius GEM_LOCK(sc); 2117148369Smarius if ((ifp->if_flags & IFF_UP) == 0) { 2118148369Smarius GEM_UNLOCK(sc); 211991398Stmm return; 2120148369Smarius } 212191398Stmm 212291398Stmm mii_pollstat(sc->sc_mii); 212391398Stmm ifmr->ifm_active = sc->sc_mii->mii_media_active; 212491398Stmm ifmr->ifm_status = sc->sc_mii->mii_media_status; 2125148369Smarius GEM_UNLOCK(sc); 212691398Stmm} 212791398Stmm 212891398Stmmstatic int 2129174987Smariusgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 213091398Stmm{ 213191398Stmm struct gem_softc *sc = ifp->if_softc; 213291398Stmm struct ifreq *ifr = (struct ifreq *)data; 2133174987Smarius int error; 213491398Stmm 2135174987Smarius error = 0; 213691398Stmm switch (cmd) { 2137150285Smarius case SIOCSIFFLAGS: 2138148369Smarius GEM_LOCK(sc); 2139174987Smarius if ((ifp->if_flags & IFF_UP) != 0) { 2140172334Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2141172334Smarius ((ifp->if_flags ^ sc->sc_ifflags) & 2142172334Smarius (IFF_ALLMULTI | IFF_PROMISC)) != 0) 214391398Stmm gem_setladrf(sc); 214491398Stmm else 2145148369Smarius gem_init_locked(sc); 2146174987Smarius } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2147174987Smarius gem_stop(ifp, 0); 2148170273Syongari if ((ifp->if_flags & IFF_LINK0) != 0) 2149170273Syongari sc->sc_csum_features |= CSUM_UDP; 2150170273Syongari else 2151170273Syongari sc->sc_csum_features &= ~CSUM_UDP; 2152170273Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2153170273Syongari ifp->if_hwassist = sc->sc_csum_features; 215499726Sbenno sc->sc_ifflags = ifp->if_flags; 2155150285Smarius GEM_UNLOCK(sc); 215691398Stmm break; 215791398Stmm case SIOCADDMULTI: 215891398Stmm case SIOCDELMULTI: 2159150285Smarius GEM_LOCK(sc); 216091398Stmm gem_setladrf(sc); 2161150285Smarius GEM_UNLOCK(sc); 216291398Stmm break; 216391398Stmm case SIOCGIFMEDIA: 216491398Stmm case SIOCSIFMEDIA: 216591398Stmm error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 216691398Stmm break; 2167170273Syongari case SIOCSIFCAP: 2168170273Syongari GEM_LOCK(sc); 2169170273Syongari ifp->if_capenable = ifr->ifr_reqcap; 2170170273Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2171170273Syongari ifp->if_hwassist = sc->sc_csum_features; 2172170273Syongari else 2173170273Syongari ifp->if_hwassist = 0; 2174170273Syongari GEM_UNLOCK(sc); 2175170273Syongari break; 217691398Stmm default: 2177150285Smarius error = ether_ioctl(ifp, cmd, data); 217891398Stmm break; 217991398Stmm } 218091398Stmm 218191398Stmm return (error); 218291398Stmm} 218391398Stmm 218491398Stmmstatic void 2185174987Smariusgem_setladrf(struct gem_softc *sc) 218691398Stmm{ 2187147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 218891398Stmm struct ifmultiaddr *inm; 218999726Sbenno int i; 2190174987Smarius uint32_t hash[16]; 2191174987Smarius uint32_t crc, v; 219291398Stmm 2193148369Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 2194148369Smarius 2195174987Smarius /* Get the current RX configuration. */ 2196177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 219791398Stmm 219899726Sbenno /* 219999726Sbenno * Turn off promiscuous mode, promiscuous group mode (all multicast), 220099726Sbenno * and hash filter. Depending on the case, the right bit will be 220199726Sbenno * enabled. 220299726Sbenno */ 2203174987Smarius v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 220499726Sbenno GEM_MAC_RX_PROMISC_GRP); 220599726Sbenno 2206177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2207179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2208179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2209177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 2210177560Smarius 0)) 2211172334Smarius device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2212172334Smarius 221391398Stmm if ((ifp->if_flags & IFF_PROMISC) != 0) { 221491398Stmm v |= GEM_MAC_RX_PROMISCUOUS; 221591398Stmm goto chipit; 221691398Stmm } 221791398Stmm if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 221899726Sbenno v |= GEM_MAC_RX_PROMISC_GRP; 221991398Stmm goto chipit; 222091398Stmm } 222191398Stmm 222291398Stmm /* 2223174987Smarius * Set up multicast address filter by passing all multicast 2224174987Smarius * addresses through a crc generator, and then using the high 2225174987Smarius * order 8 bits as an index into the 256 bit logical address 2226174987Smarius * filter. The high order 4 bits selects the word, while the 2227174987Smarius * other 4 bits select the bit within the word (where bit 0 2228174987Smarius * is the MSB). 222991398Stmm */ 223091398Stmm 2231174987Smarius /* Clear the hash table. */ 223299726Sbenno memset(hash, 0, sizeof(hash)); 223399726Sbenno 2234195049Srwatson if_maddr_rlock(ifp); 2235147256Sbrooks TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 223691398Stmm if (inm->ifma_addr->sa_family != AF_LINK) 223791398Stmm continue; 2238130288Smarius crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2239130288Smarius inm->ifma_addr), ETHER_ADDR_LEN); 224091398Stmm 2241174987Smarius /* We just want the 8 most significant bits. */ 224291398Stmm crc >>= 24; 224391398Stmm 224491398Stmm /* Set the corresponding bit in the filter. */ 224599726Sbenno hash[crc >> 4] |= 1 << (15 - (crc & 15)); 224691398Stmm } 2247195049Srwatson if_maddr_runlock(ifp); 224891398Stmm 224999726Sbenno v |= GEM_MAC_RX_HASH_FILTER; 225099726Sbenno 2251174987Smarius /* Now load the hash table into the chip (if we are using it). */ 2252174987Smarius for (i = 0; i < 16; i++) 2253177560Smarius GEM_BANK1_WRITE_4(sc, 2254174987Smarius GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 225599726Sbenno hash[i]); 225699726Sbenno 2257174987Smarius chipit: 2258177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 225991398Stmm} 2260