if_gem.c revision 213893
1119418Sobrien/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 3108832Stmm * Copyright (c) 2001-2003 Thomas Moestl 4174987Smarius * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 591398Stmm * All rights reserved. 691398Stmm * 791398Stmm * Redistribution and use in source and binary forms, with or without 891398Stmm * modification, are permitted provided that the following conditions 991398Stmm * are met: 1091398Stmm * 1. Redistributions of source code must retain the above copyright 1191398Stmm * notice, this list of conditions and the following disclaimer. 1291398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1391398Stmm * notice, this list of conditions and the following disclaimer in the 1491398Stmm * documentation and/or other materials provided with the distribution. 1591398Stmm * 1691398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1791398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1891398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1991398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 2091398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2191398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2291398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2391398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2491398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2591398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2691398Stmm * SUCH DAMAGE. 2791398Stmm * 2899726Sbenno * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 2991398Stmm */ 3091398Stmm 31119418Sobrien#include <sys/cdefs.h> 32119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 213893 2010-10-15 14:52:11Z marius $"); 33119418Sobrien 3491398Stmm/* 35172334Smarius * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 3691398Stmm */ 3791398Stmm 38115030Stmm#if 0 3991398Stmm#define GEM_DEBUG 40115030Stmm#endif 4191398Stmm 42148368Smarius#if 0 /* XXX: In case of emergency, re-enable this. */ 43148368Smarius#define GEM_RINT_TIMEOUT 44148368Smarius#endif 45148368Smarius 4691398Stmm#include <sys/param.h> 4791398Stmm#include <sys/systm.h> 4891398Stmm#include <sys/bus.h> 4991398Stmm#include <sys/callout.h> 5095533Smike#include <sys/endian.h> 5191398Stmm#include <sys/mbuf.h> 5291398Stmm#include <sys/malloc.h> 5391398Stmm#include <sys/kernel.h> 54148369Smarius#include <sys/lock.h> 55130026Sphk#include <sys/module.h> 56148369Smarius#include <sys/mutex.h> 5791398Stmm#include <sys/socket.h> 5891398Stmm#include <sys/sockio.h> 59169269Sphk#include <sys/rman.h> 6091398Stmm 61105982Stmm#include <net/bpf.h> 6291398Stmm#include <net/ethernet.h> 6391398Stmm#include <net/if.h> 6491398Stmm#include <net/if_arp.h> 6591398Stmm#include <net/if_dl.h> 6691398Stmm#include <net/if_media.h> 67147256Sbrooks#include <net/if_types.h> 68149552Smarius#include <net/if_vlan_var.h> 6991398Stmm 70170273Syongari#include <netinet/in.h> 71170273Syongari#include <netinet/in_systm.h> 72170273Syongari#include <netinet/ip.h> 73170273Syongari#include <netinet/tcp.h> 74170273Syongari#include <netinet/udp.h> 75170273Syongari 7691398Stmm#include <machine/bus.h> 7791398Stmm 7891398Stmm#include <dev/mii/mii.h> 7991398Stmm#include <dev/mii/miivar.h> 8091398Stmm 81119355Simp#include <dev/gem/if_gemreg.h> 82119355Simp#include <dev/gem/if_gemvar.h> 8391398Stmm 84172334SmariusCTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85172334SmariusCTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86172334Smarius 87194763Smarius#define GEM_TRIES 10000 88172334Smarius 89170273Syongari/* 90182060Smarius * The hardware supports basic TCP/UDP checksum offloading. However, 91170273Syongari * the hardware doesn't compensate the checksum for UDP datagram which 92174987Smarius * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93174987Smarius * by default. It can be reactivated by setting special link option 94170273Syongari * link0 with ifconfig(8). 95170273Syongari */ 96170273Syongari#define GEM_CSUM_FEATURES (CSUM_TCP) 9791398Stmm 98174987Smariusstatic int gem_add_rxbuf(struct gem_softc *sc, int idx); 99177560Smariusstatic int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 100177560Smarius uint32_t clr, uint32_t set); 101174987Smariusstatic void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 102174987Smarius int nsegs, int error); 103174987Smariusstatic int gem_disable_rx(struct gem_softc *sc); 104174987Smariusstatic int gem_disable_tx(struct gem_softc *sc); 105174987Smariusstatic void gem_eint(struct gem_softc *sc, u_int status); 106174987Smariusstatic void gem_init(void *xsc); 107174987Smariusstatic void gem_init_locked(struct gem_softc *sc); 108174987Smariusstatic void gem_init_regs(struct gem_softc *sc); 109174987Smariusstatic int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 110174987Smariusstatic int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 111174987Smariusstatic int gem_meminit(struct gem_softc *sc); 112174987Smariusstatic void gem_mifinit(struct gem_softc *sc); 113174987Smariusstatic void gem_reset(struct gem_softc *sc); 114174987Smariusstatic int gem_reset_rx(struct gem_softc *sc); 115172334Smariusstatic void gem_reset_rxdma(struct gem_softc *sc); 116174987Smariusstatic int gem_reset_tx(struct gem_softc *sc); 117174987Smariusstatic u_int gem_ringsize(u_int sz); 118174987Smariusstatic void gem_rint(struct gem_softc *sc); 119148368Smarius#ifdef GEM_RINT_TIMEOUT 120174987Smariusstatic void gem_rint_timeout(void *arg); 121100587Sjake#endif 122194763Smariusstatic inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 123174987Smariusstatic void gem_rxdrain(struct gem_softc *sc); 124174987Smariusstatic void gem_setladrf(struct gem_softc *sc); 125174987Smariusstatic void gem_start(struct ifnet *ifp); 126174987Smariusstatic void gem_start_locked(struct ifnet *ifp); 127174987Smariusstatic void gem_stop(struct ifnet *ifp, int disable); 128174987Smariusstatic void gem_tick(void *arg); 129174987Smariusstatic void gem_tint(struct gem_softc *sc); 130194763Smariusstatic inline void gem_txkick(struct gem_softc *sc); 131174987Smariusstatic int gem_watchdog(struct gem_softc *sc); 13291398Stmm 13391398Stmmdevclass_t gem_devclass; 13491398StmmDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 13591398StmmMODULE_DEPEND(gem, miibus, 1, 1, 1); 13691398Stmm 13791398Stmm#ifdef GEM_DEBUG 13891398Stmm#include <sys/ktr.h> 139210334Sattilio#define KTR_GEM KTR_SPARE2 14091398Stmm#endif 14191398Stmm 142177560Smarius#define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 143177560Smarius gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 144177560Smarius#define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 145177560Smarius gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 146177560Smarius 14791398Stmmint 148174987Smariusgem_attach(struct gem_softc *sc) 14991398Stmm{ 150174987Smarius struct gem_txsoft *txs; 151147256Sbrooks struct ifnet *ifp; 152213893Smarius int error, i, phy; 153174987Smarius uint32_t v; 15491398Stmm 155194763Smarius if (bootverbose) 156194763Smarius device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 157194763Smarius 158194763Smarius /* Set up ifnet structure. */ 159147256Sbrooks ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160147256Sbrooks if (ifp == NULL) 161147256Sbrooks return (ENOSPC); 162194763Smarius sc->sc_csum_features = GEM_CSUM_FEATURES; 163194763Smarius ifp->if_softc = sc; 164194763Smarius if_initname(ifp, device_get_name(sc->sc_dev), 165194763Smarius device_get_unit(sc->sc_dev)); 166194763Smarius ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 167194763Smarius ifp->if_start = gem_start; 168194763Smarius ifp->if_ioctl = gem_ioctl; 169194763Smarius ifp->if_init = gem_init; 170194763Smarius IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 171194763Smarius ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 172194763Smarius IFQ_SET_READY(&ifp->if_snd); 173147256Sbrooks 174150285Smarius callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 175150285Smarius#ifdef GEM_RINT_TIMEOUT 176150285Smarius callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 177150285Smarius#endif 178150285Smarius 17991398Stmm /* Make sure the chip is stopped. */ 18091398Stmm gem_reset(sc); 18191398Stmm 182161928Sjmg error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183161928Sjmg BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 184174987Smarius BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 185174987Smarius NULL, &sc->sc_pdmatag); 186194763Smarius if (error != 0) 187147256Sbrooks goto fail_ifnet; 18891398Stmm 18991398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 190170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 191170273Syongari 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 192194763Smarius if (error != 0) 193108832Stmm goto fail_ptag; 19491398Stmm 195108832Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 196170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 197170273Syongari MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198117126Sscottl BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 199194763Smarius if (error != 0) 200108832Stmm goto fail_rtag; 201108832Stmm 20291398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 203170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 20491398Stmm sizeof(struct gem_control_data), 1, 205170273Syongari sizeof(struct gem_control_data), 0, 206170273Syongari NULL, NULL, &sc->sc_cdmatag); 207194763Smarius if (error != 0) 208108832Stmm goto fail_ttag; 20991398Stmm 21091398Stmm /* 211174987Smarius * Allocate the control data structures, create and load the 21291398Stmm * DMA map for it. 21391398Stmm */ 21491398Stmm if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 215170273Syongari (void **)&sc->sc_control_data, 216170273Syongari BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 217194763Smarius &sc->sc_cddmamap)) != 0) { 218174987Smarius device_printf(sc->sc_dev, 219174987Smarius "unable to allocate control data, error = %d\n", error); 220108832Stmm goto fail_ctag; 22191398Stmm } 22291398Stmm 22391398Stmm sc->sc_cddma = 0; 22491398Stmm if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 22591398Stmm sc->sc_control_data, sizeof(struct gem_control_data), 22691398Stmm gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 227174987Smarius device_printf(sc->sc_dev, 228174987Smarius "unable to load control data DMA map, error = %d\n", 229174987Smarius error); 230108832Stmm goto fail_cmem; 23191398Stmm } 23291398Stmm 23391398Stmm /* 23491398Stmm * Initialize the transmit job descriptors. 23591398Stmm */ 23691398Stmm STAILQ_INIT(&sc->sc_txfreeq); 23791398Stmm STAILQ_INIT(&sc->sc_txdirtyq); 23891398Stmm 23991398Stmm /* 24091398Stmm * Create the transmit buffer DMA maps. 24191398Stmm */ 24291398Stmm error = ENOMEM; 24391398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 24491398Stmm txs = &sc->sc_txsoft[i]; 24591398Stmm txs->txs_mbuf = NULL; 24691398Stmm txs->txs_ndescs = 0; 247108832Stmm if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 24891398Stmm &txs->txs_dmamap)) != 0) { 249174987Smarius device_printf(sc->sc_dev, 250174987Smarius "unable to create TX DMA map %d, error = %d\n", 251174987Smarius i, error); 252108832Stmm goto fail_txd; 25391398Stmm } 25491398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 25591398Stmm } 25691398Stmm 25791398Stmm /* 25891398Stmm * Create the receive buffer DMA maps. 25991398Stmm */ 26091398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 261108832Stmm if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 26291398Stmm &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263174987Smarius device_printf(sc->sc_dev, 264174987Smarius "unable to create RX DMA map %d, error = %d\n", 265174987Smarius i, error); 266108832Stmm goto fail_rxd; 26791398Stmm } 26891398Stmm sc->sc_rxsoft[i].rxs_mbuf = NULL; 26991398Stmm } 27091398Stmm 271212725Smarius /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 272212725Smarius if ((sc->sc_flags & GEM_SERDES) != 0) 273212725Smarius goto serdes; 274212725Smarius 275172334Smarius /* Bad things will happen when touching this register on ERI. */ 276212725Smarius if (sc->sc_variant != GEM_SUN_ERI) { 277177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 278172334Smarius GEM_MII_DATAPATH_MII); 279212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 280212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 281212725Smarius } 282172334Smarius 28391398Stmm gem_mifinit(sc); 28491398Stmm 285172334Smarius /* 286172334Smarius * Look for an external PHY. 287172334Smarius */ 288172334Smarius error = ENXIO; 289177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 290172334Smarius if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 291172334Smarius v |= GEM_MIF_CONFIG_PHY_SEL; 292177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 293212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 294212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 295172334Smarius switch (sc->sc_variant) { 296172334Smarius case GEM_SUN_ERI: 297213893Smarius phy = GEM_PHYAD_EXTERNAL; 298172334Smarius break; 299172334Smarius default: 300213893Smarius phy = MII_PHY_ANY; 301172334Smarius break; 302172334Smarius } 303213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 304213893Smarius gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 305213893Smarius MII_OFFSET_ANY, 0); 306172334Smarius } 307172334Smarius 308172334Smarius /* 309172334Smarius * Fall back on an internal PHY if no external PHY was found. 310204222Smarius * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 311204222Smarius * trusted when the firmware has powered down the chip. 312172334Smarius */ 313204222Smarius if (error != 0 && 314204222Smarius ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 315172334Smarius v &= ~GEM_MIF_CONFIG_PHY_SEL; 316177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 317212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 318212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 319172334Smarius switch (sc->sc_variant) { 320172334Smarius case GEM_SUN_ERI: 321172334Smarius case GEM_APPLE_K2_GMAC: 322213893Smarius phy = GEM_PHYAD_INTERNAL; 323172334Smarius break; 324172334Smarius case GEM_APPLE_GMAC: 325213893Smarius phy = GEM_PHYAD_EXTERNAL; 326172334Smarius break; 327172334Smarius default: 328213893Smarius phy = MII_PHY_ANY; 329172334Smarius break; 330172334Smarius } 331213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 332213893Smarius gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 333213893Smarius MII_OFFSET_ANY, 0); 334172334Smarius } 335172334Smarius 336172334Smarius /* 337172334Smarius * Try the external PCS SERDES if we didn't find any PHYs. 338172334Smarius */ 339172334Smarius if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 340212725Smarius serdes: 341177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 342172334Smarius GEM_MII_DATAPATH_SERDES); 343212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 344212725Smarius BUS_SPACE_BARRIER_WRITE); 345177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 346172334Smarius GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 347212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 348212725Smarius BUS_SPACE_BARRIER_WRITE); 349177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 350212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 351212725Smarius BUS_SPACE_BARRIER_WRITE); 352172334Smarius sc->sc_flags |= GEM_SERDES; 353213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 354213893Smarius gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, 355213893Smarius GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, 0); 356172334Smarius } 357172334Smarius if (error != 0) { 358213893Smarius device_printf(sc->sc_dev, "attaching PHYs failed\n"); 359108832Stmm goto fail_rxd; 36091398Stmm } 36191398Stmm sc->sc_mii = device_get_softc(sc->sc_miibus); 36291398Stmm 36391398Stmm /* 36491398Stmm * From this point forward, the attachment cannot fail. A failure 36591398Stmm * before this point releases all resources that may have been 36691398Stmm * allocated. 36791398Stmm */ 36891398Stmm 369176996Smarius /* Get RX FIFO size. */ 37099726Sbenno sc->sc_rxfifosize = 64 * 371177560Smarius GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 37299726Sbenno 373176996Smarius /* Get TX FIFO size. */ 374177560Smarius v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 375128588Stmm device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 376128588Stmm sc->sc_rxfifosize / 1024, v / 16); 37799726Sbenno 37891398Stmm /* Attach the interface. */ 379147256Sbrooks ether_ifattach(ifp, sc->sc_enaddr); 38091398Stmm 38191398Stmm /* 382170273Syongari * Tell the upper layer(s) we support long frames/checksum offloads. 383149552Smarius */ 384149552Smarius ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 385170273Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 386170273Syongari ifp->if_hwassist |= sc->sc_csum_features; 387170273Syongari ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 388149552Smarius 38991398Stmm return (0); 39091398Stmm 39191398Stmm /* 39291398Stmm * Free any resources we've allocated during the failed attach 39391398Stmm * attempt. Do this in reverse order and fall through. 39491398Stmm */ 395174987Smarius fail_rxd: 396174987Smarius for (i = 0; i < GEM_NRXDESC; i++) 39791398Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 398108832Stmm bus_dmamap_destroy(sc->sc_rdmatag, 39991398Stmm sc->sc_rxsoft[i].rxs_dmamap); 400174987Smarius fail_txd: 401174987Smarius for (i = 0; i < GEM_TXQUEUELEN; i++) 40291398Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 403108832Stmm bus_dmamap_destroy(sc->sc_tdmatag, 40491398Stmm sc->sc_txsoft[i].txs_dmamap); 405108832Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 406174987Smarius fail_cmem: 40791398Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 40891398Stmm sc->sc_cddmamap); 409174987Smarius fail_ctag: 41091398Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 411174987Smarius fail_ttag: 412108832Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 413174987Smarius fail_rtag: 414108832Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 415174987Smarius fail_ptag: 41691398Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 417174987Smarius fail_ifnet: 418147256Sbrooks if_free(ifp); 41991398Stmm return (error); 42091398Stmm} 42191398Stmm 422108964Stmmvoid 423174987Smariusgem_detach(struct gem_softc *sc) 424108964Stmm{ 425147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 426108964Stmm int i; 427108964Stmm 428194886Smarius ether_ifdetach(ifp); 429148369Smarius GEM_LOCK(sc); 430147317Sbrooks gem_stop(ifp, 1); 431148369Smarius GEM_UNLOCK(sc); 432150285Smarius callout_drain(&sc->sc_tick_ch); 433150285Smarius#ifdef GEM_RINT_TIMEOUT 434150285Smarius callout_drain(&sc->sc_rx_ch); 435150285Smarius#endif 436147256Sbrooks if_free(ifp); 437108964Stmm device_delete_child(sc->sc_dev, sc->sc_miibus); 438108964Stmm 439174987Smarius for (i = 0; i < GEM_NRXDESC; i++) 440108964Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 441108964Stmm bus_dmamap_destroy(sc->sc_rdmatag, 442108964Stmm sc->sc_rxsoft[i].rxs_dmamap); 443174987Smarius for (i = 0; i < GEM_TXQUEUELEN; i++) 444108964Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 445108964Stmm bus_dmamap_destroy(sc->sc_tdmatag, 446108964Stmm sc->sc_txsoft[i].txs_dmamap); 447179925Smarius GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 448108964Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 449108964Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 450108964Stmm sc->sc_cddmamap); 451108964Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 452108964Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 453108964Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 454108964Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 455108964Stmm} 456108964Stmm 457108964Stmmvoid 458174987Smariusgem_suspend(struct gem_softc *sc) 459108964Stmm{ 460147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 461108964Stmm 462148369Smarius GEM_LOCK(sc); 463108964Stmm gem_stop(ifp, 0); 464148369Smarius GEM_UNLOCK(sc); 465108964Stmm} 466108964Stmm 467108964Stmmvoid 468174987Smariusgem_resume(struct gem_softc *sc) 469108964Stmm{ 470147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 471108964Stmm 472148369Smarius GEM_LOCK(sc); 473149552Smarius /* 474149552Smarius * On resume all registers have to be initialized again like 475149552Smarius * after power-on. 476149552Smarius */ 477172334Smarius sc->sc_flags &= ~GEM_INITED; 478108964Stmm if (ifp->if_flags & IFF_UP) 479148369Smarius gem_init_locked(sc); 480148369Smarius GEM_UNLOCK(sc); 481108964Stmm} 482108964Stmm 483194763Smariusstatic inline void 484170273Syongarigem_rxcksum(struct mbuf *m, uint64_t flags) 485170273Syongari{ 486170273Syongari struct ether_header *eh; 487170273Syongari struct ip *ip; 488170273Syongari struct udphdr *uh; 489174987Smarius uint16_t *opts; 490170273Syongari int32_t hlen, len, pktlen; 491170273Syongari uint32_t temp32; 492174987Smarius uint16_t cksum; 493170273Syongari 494170273Syongari pktlen = m->m_pkthdr.len; 495170273Syongari if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 496170273Syongari return; 497170273Syongari eh = mtod(m, struct ether_header *); 498170273Syongari if (eh->ether_type != htons(ETHERTYPE_IP)) 499170273Syongari return; 500170273Syongari ip = (struct ip *)(eh + 1); 501170273Syongari if (ip->ip_v != IPVERSION) 502170273Syongari return; 503170273Syongari 504170273Syongari hlen = ip->ip_hl << 2; 505170273Syongari pktlen -= sizeof(struct ether_header); 506170273Syongari if (hlen < sizeof(struct ip)) 507170273Syongari return; 508170273Syongari if (ntohs(ip->ip_len) < hlen) 509170273Syongari return; 510170273Syongari if (ntohs(ip->ip_len) != pktlen) 511170273Syongari return; 512170273Syongari if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 513174987Smarius return; /* Cannot handle fragmented packet. */ 514170273Syongari 515170273Syongari switch (ip->ip_p) { 516170273Syongari case IPPROTO_TCP: 517170273Syongari if (pktlen < (hlen + sizeof(struct tcphdr))) 518170273Syongari return; 519170273Syongari break; 520170273Syongari case IPPROTO_UDP: 521170273Syongari if (pktlen < (hlen + sizeof(struct udphdr))) 522170273Syongari return; 523170273Syongari uh = (struct udphdr *)((uint8_t *)ip + hlen); 524170273Syongari if (uh->uh_sum == 0) 525170273Syongari return; /* no checksum */ 526170273Syongari break; 527170273Syongari default: 528170273Syongari return; 529170273Syongari } 530170273Syongari 531170273Syongari cksum = ~(flags & GEM_RD_CHECKSUM); 532170273Syongari /* checksum fixup for IP options */ 533170273Syongari len = hlen - sizeof(struct ip); 534170273Syongari if (len > 0) { 535170273Syongari opts = (uint16_t *)(ip + 1); 536170273Syongari for (; len > 0; len -= sizeof(uint16_t), opts++) { 537170273Syongari temp32 = cksum - *opts; 538170273Syongari temp32 = (temp32 >> 16) + (temp32 & 65535); 539170273Syongari cksum = temp32 & 65535; 540170273Syongari } 541170273Syongari } 542170273Syongari m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 543170273Syongari m->m_pkthdr.csum_data = cksum; 544170273Syongari} 545170273Syongari 54691398Stmmstatic void 547174987Smariusgem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 54891398Stmm{ 549174987Smarius struct gem_softc *sc = xsc; 55091398Stmm 55191398Stmm if (error != 0) 55291398Stmm return; 553174987Smarius if (nsegs != 1) 554172334Smarius panic("%s: bad control buffer segment count", __func__); 55591398Stmm sc->sc_cddma = segs[0].ds_addr; 55691398Stmm} 55791398Stmm 55891398Stmmstatic void 559174987Smariusgem_tick(void *arg) 56091398Stmm{ 561170273Syongari struct gem_softc *sc = arg; 562194763Smarius struct ifnet *ifp = sc->sc_ifp; 563182060Smarius uint32_t v; 56491398Stmm 565170273Syongari GEM_LOCK_ASSERT(sc, MA_OWNED); 566170273Syongari 567108832Stmm /* 568182060Smarius * Unload collision and error counters. 569108832Stmm */ 570170273Syongari ifp->if_collisions += 571177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 572182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 573182060Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 574177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 575182060Smarius ifp->if_collisions += v; 576182060Smarius ifp->if_oerrors += v; 577182060Smarius ifp->if_ierrors += 578182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 579182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 580182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 581182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 58291398Stmm 58391398Stmm /* 584176996Smarius * Then clear the hardware counters. 58591398Stmm */ 586177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 587177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 588177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 589177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 590182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 591182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 592182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 593182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 594108832Stmm 59591398Stmm mii_tick(sc->sc_mii); 59691398Stmm 597164931Smarius if (gem_watchdog(sc) == EJUSTRETURN) 598164931Smarius return; 599164931Smarius 60091398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 60191398Stmm} 60291398Stmm 60391398Stmmstatic int 604177560Smariusgem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 605177560Smarius uint32_t set) 60691398Stmm{ 60791398Stmm int i; 608174987Smarius uint32_t reg; 60991398Stmm 610194763Smarius for (i = GEM_TRIES; i--; DELAY(100)) { 611177560Smarius reg = GEM_BANKN_READ_M(bank, 4, sc, r); 612170847Smarius if ((reg & clr) == 0 && (reg & set) == set) 61391398Stmm return (1); 61491398Stmm } 61591398Stmm return (0); 61691398Stmm} 61791398Stmm 618172334Smariusstatic void 619194763Smariusgem_reset(struct gem_softc *sc) 62091398Stmm{ 62191398Stmm 622115030Stmm#ifdef GEM_DEBUG 623170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 624115030Stmm#endif 62591398Stmm gem_reset_rx(sc); 62691398Stmm gem_reset_tx(sc); 62791398Stmm 628174987Smarius /* Do a full reset. */ 629177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 630179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 631179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 632177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 63391398Stmm device_printf(sc->sc_dev, "cannot reset device\n"); 63491398Stmm} 63591398Stmm 63691398Stmmstatic void 637174987Smariusgem_rxdrain(struct gem_softc *sc) 63891398Stmm{ 63991398Stmm struct gem_rxsoft *rxs; 64091398Stmm int i; 64191398Stmm 64291398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 64391398Stmm rxs = &sc->sc_rxsoft[i]; 64491398Stmm if (rxs->rxs_mbuf != NULL) { 645109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 646109648Stmm BUS_DMASYNC_POSTREAD); 647108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 64891398Stmm m_freem(rxs->rxs_mbuf); 64991398Stmm rxs->rxs_mbuf = NULL; 65091398Stmm } 65191398Stmm } 65291398Stmm} 65391398Stmm 65491398Stmmstatic void 655174987Smariusgem_stop(struct ifnet *ifp, int disable) 65691398Stmm{ 657174987Smarius struct gem_softc *sc = ifp->if_softc; 65891398Stmm struct gem_txsoft *txs; 65991398Stmm 660115030Stmm#ifdef GEM_DEBUG 661170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 662115030Stmm#endif 66391398Stmm 66491398Stmm callout_stop(&sc->sc_tick_ch); 665150285Smarius#ifdef GEM_RINT_TIMEOUT 666150285Smarius callout_stop(&sc->sc_rx_ch); 667172334Smarius#endif 66891398Stmm 669194763Smarius gem_reset_tx(sc); 670194763Smarius gem_reset_rx(sc); 67191398Stmm 67291398Stmm /* 67391398Stmm * Release any queued transmit buffers. 67491398Stmm */ 67591398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 67691398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 67791398Stmm if (txs->txs_ndescs != 0) { 678109648Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 679109648Stmm BUS_DMASYNC_POSTWRITE); 680108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 68191398Stmm if (txs->txs_mbuf != NULL) { 68291398Stmm m_freem(txs->txs_mbuf); 68391398Stmm txs->txs_mbuf = NULL; 68491398Stmm } 68591398Stmm } 68691398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 68791398Stmm } 68891398Stmm 68991398Stmm if (disable) 69091398Stmm gem_rxdrain(sc); 69191398Stmm 69291398Stmm /* 69391398Stmm * Mark the interface down and cancel the watchdog timer. 69491398Stmm */ 695148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 696172334Smarius sc->sc_flags &= ~GEM_LINK; 697164931Smarius sc->sc_wdog_timer = 0; 69891398Stmm} 69991398Stmm 700172334Smariusstatic int 701174987Smariusgem_reset_rx(struct gem_softc *sc) 70291398Stmm{ 70391398Stmm 70491398Stmm /* 70591398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 70691398Stmm * disable DMA first. 70791398Stmm */ 70891398Stmm gem_disable_rx(sc); 709177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 710179925Smarius GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 711179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 712177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 713172334Smarius device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 71491398Stmm 715176996Smarius /* Finally, reset the ERX. */ 716177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX); 717179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 718179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 719177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 720177560Smarius 0)) { 72191398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 72291398Stmm return (1); 72391398Stmm } 72491398Stmm return (0); 72591398Stmm} 72691398Stmm 727172334Smarius/* 728172334Smarius * Reset the receiver DMA engine. 729172334Smarius * 730172334Smarius * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 731172334Smarius * etc in order to reset the receiver DMA engine only and not do a full 732172334Smarius * reset which amongst others also downs the link and clears the FIFOs. 733172334Smarius */ 734172334Smariusstatic void 735172334Smariusgem_reset_rxdma(struct gem_softc *sc) 736172334Smarius{ 737172334Smarius int i; 73891398Stmm 739172334Smarius if (gem_reset_rx(sc) != 0) 740172334Smarius return (gem_init_locked(sc)); 741172334Smarius for (i = 0; i < GEM_NRXDESC; i++) 742172334Smarius if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 743172334Smarius GEM_UPDATE_RXDESC(sc, i); 744172334Smarius sc->sc_rxptr = 0; 745194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746172334Smarius 747172334Smarius /* NOTE: we use only 32-bit DMA addresses here. */ 748177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 749177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 750177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 751177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 752174987Smarius gem_ringsize(GEM_NRXDESC /* XXX */) | 753172334Smarius ((ETHER_HDR_LEN + sizeof(struct ip)) << 754172334Smarius GEM_RX_CONFIG_CXM_START_SHFT) | 755172334Smarius (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 756194763Smarius (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 757194763Smarius /* Adjust for the SBus clock probably isn't worth the fuzz. */ 758177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 759194763Smarius ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 760194763Smarius GEM_RX_BLANKING_TIME_SHIFT) | 6); 761177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 762174987Smarius (3 * sc->sc_rxfifosize / 256) | 763174987Smarius ((sc->sc_rxfifosize / 256) << 12)); 764177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 765177560Smarius GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 766177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 767172334Smarius GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 768177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 769177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE); 770172334Smarius} 771172334Smarius 77291398Stmmstatic int 773174987Smariusgem_reset_tx(struct gem_softc *sc) 77491398Stmm{ 77591398Stmm 77691398Stmm /* 77791398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 77891398Stmm * disable DMA first. 77991398Stmm */ 78091398Stmm gem_disable_tx(sc); 781177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 782179925Smarius GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 783179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 784177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 785172334Smarius device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 78691398Stmm 787176996Smarius /* Finally, reset the ETX. */ 788177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX); 789179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 790179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 791177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 792177560Smarius 0)) { 793172334Smarius device_printf(sc->sc_dev, "cannot reset transmitter\n"); 79491398Stmm return (1); 79591398Stmm } 79691398Stmm return (0); 79791398Stmm} 79891398Stmm 79991398Stmmstatic int 800174987Smariusgem_disable_rx(struct gem_softc *sc) 80191398Stmm{ 80291398Stmm 803177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 804177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 805179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 806179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 807177560Smarius return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 808177560Smarius 0)); 80991398Stmm} 81091398Stmm 81191398Stmmstatic int 812174987Smariusgem_disable_tx(struct gem_softc *sc) 81391398Stmm{ 81491398Stmm 815177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 816177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 817179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 818179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 819177560Smarius return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 820177560Smarius 0)); 82191398Stmm} 82291398Stmm 82391398Stmmstatic int 824194763Smariusgem_meminit(struct gem_softc *sc) 82591398Stmm{ 82691398Stmm struct gem_rxsoft *rxs; 827174987Smarius int error, i; 82891398Stmm 829194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 830194763Smarius 83191398Stmm /* 83291398Stmm * Initialize the transmit descriptor ring. 83391398Stmm */ 83491398Stmm for (i = 0; i < GEM_NTXDESC; i++) { 83591398Stmm sc->sc_txdescs[i].gd_flags = 0; 83691398Stmm sc->sc_txdescs[i].gd_addr = 0; 83791398Stmm } 838108832Stmm sc->sc_txfree = GEM_MAXTXFREE; 83991398Stmm sc->sc_txnext = 0; 84099726Sbenno sc->sc_txwin = 0; 84191398Stmm 84291398Stmm /* 84391398Stmm * Initialize the receive descriptor and receive job 84491398Stmm * descriptor rings. 84591398Stmm */ 84691398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 84791398Stmm rxs = &sc->sc_rxsoft[i]; 84891398Stmm if (rxs->rxs_mbuf == NULL) { 84991398Stmm if ((error = gem_add_rxbuf(sc, i)) != 0) { 850174987Smarius device_printf(sc->sc_dev, 851174987Smarius "unable to allocate or map RX buffer %d, " 852174987Smarius "error = %d\n", i, error); 85391398Stmm /* 854174987Smarius * XXX we should attempt to run with fewer 855174987Smarius * receive buffers instead of just failing. 85691398Stmm */ 85791398Stmm gem_rxdrain(sc); 85891398Stmm return (1); 85991398Stmm } 86091398Stmm } else 86191398Stmm GEM_INIT_RXDESC(sc, i); 86291398Stmm } 86391398Stmm sc->sc_rxptr = 0; 86491398Stmm 865194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 866194763Smarius 86791398Stmm return (0); 86891398Stmm} 86991398Stmm 870172334Smariusstatic u_int 871174987Smariusgem_ringsize(u_int sz) 87291398Stmm{ 87391398Stmm 87491398Stmm switch (sz) { 87591398Stmm case 32: 876172334Smarius return (GEM_RING_SZ_32); 87791398Stmm case 64: 878172334Smarius return (GEM_RING_SZ_64); 87991398Stmm case 128: 880172334Smarius return (GEM_RING_SZ_128); 88191398Stmm case 256: 882172334Smarius return (GEM_RING_SZ_256); 88391398Stmm case 512: 884172334Smarius return (GEM_RING_SZ_512); 88591398Stmm case 1024: 886172334Smarius return (GEM_RING_SZ_1024); 88791398Stmm case 2048: 888172334Smarius return (GEM_RING_SZ_2048); 88991398Stmm case 4096: 890172334Smarius return (GEM_RING_SZ_4096); 89191398Stmm case 8192: 892172334Smarius return (GEM_RING_SZ_8192); 89391398Stmm default: 894172334Smarius printf("%s: invalid ring size %d\n", __func__, sz); 895172334Smarius return (GEM_RING_SZ_32); 89691398Stmm } 89791398Stmm} 89891398Stmm 899148369Smariusstatic void 900174987Smariusgem_init(void *xsc) 901148369Smarius{ 902174987Smarius struct gem_softc *sc = xsc; 903148369Smarius 904148369Smarius GEM_LOCK(sc); 905148369Smarius gem_init_locked(sc); 906148369Smarius GEM_UNLOCK(sc); 907148369Smarius} 908148369Smarius 90991398Stmm/* 91091398Stmm * Initialization of interface; set up initialization block 91191398Stmm * and transmit/receive descriptor rings. 91291398Stmm */ 91391398Stmmstatic void 914174987Smariusgem_init_locked(struct gem_softc *sc) 91591398Stmm{ 916147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 917174987Smarius uint32_t v; 91891398Stmm 919148369Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 92091398Stmm 921115030Stmm#ifdef GEM_DEBUG 922170273Syongari CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 923170273Syongari __func__); 924115030Stmm#endif 92591398Stmm /* 926174987Smarius * Initialization sequence. The numbered steps below correspond 92791398Stmm * to the sequence outlined in section 6.3.5.1 in the Ethernet 92891398Stmm * Channel Engine manual (part of the PCIO manual). 92991398Stmm * See also the STP2002-STQ document from Sun Microsystems. 93091398Stmm */ 93191398Stmm 932174987Smarius /* step 1 & 2. Reset the Ethernet Channel. */ 933179925Smarius gem_stop(ifp, 0); 93491398Stmm gem_reset(sc); 935115030Stmm#ifdef GEM_DEBUG 936170273Syongari CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 937170273Syongari __func__); 938115030Stmm#endif 93991398Stmm 940212725Smarius if ((sc->sc_flags & GEM_SERDES) == 0) 941212725Smarius /* Re-initialize the MIF. */ 942212725Smarius gem_mifinit(sc); 94391398Stmm 944174987Smarius /* step 3. Setup data structures in host memory. */ 945172334Smarius if (gem_meminit(sc) != 0) 946172334Smarius return; 94791398Stmm 948174987Smarius /* step 4. TX MAC registers & counters */ 94991398Stmm gem_init_regs(sc); 95091398Stmm 951174987Smarius /* step 5. RX MAC registers & counters */ 95291398Stmm gem_setladrf(sc); 95391398Stmm 954174987Smarius /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 95591398Stmm /* NOTE: we use only 32-bit DMA addresses here. */ 956177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 957177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 95891398Stmm 959177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 960177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 961115030Stmm#ifdef GEM_DEBUG 962174987Smarius CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 96391398Stmm GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 964115030Stmm#endif 96591398Stmm 966174987Smarius /* step 8. Global Configuration & Interrupt Mask */ 967194763Smarius 968194763Smarius /* 969194763Smarius * Set the internal arbitration to "infinite" bursts of the 970194763Smarius * maximum length of 31 * 64 bytes so DMA transfers aren't 971194763Smarius * split up in cache line size chunks. This greatly improves 972194763Smarius * RX performance. 973194763Smarius * Enable silicon bug workarounds for the Apple variants. 974194763Smarius */ 975194763Smarius GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 976194763Smarius GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 977194763Smarius ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 978194763Smarius GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 979194763Smarius GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 980194763Smarius 981177560Smarius GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 982172334Smarius ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 983172334Smarius GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 984172334Smarius GEM_INTR_BERR 985172334Smarius#ifdef GEM_DEBUG 986172334Smarius | GEM_INTR_PCS | GEM_INTR_MIF 987172334Smarius#endif 988172334Smarius )); 989177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 990172334Smarius GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 991177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 992194763Smarius GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 993194763Smarius GEM_MAC_TX_PEAK_EXP); 994172334Smarius#ifdef GEM_DEBUG 995177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 996172334Smarius ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 997172334Smarius#else 998177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 999172334Smarius GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1000172334Smarius#endif 100191398Stmm 1002174987Smarius /* step 9. ETX Configuration: use mostly default values. */ 100391398Stmm 1004174987Smarius /* Enable DMA. */ 1005194763Smarius v = gem_ringsize(GEM_NTXDESC); 1006194763Smarius /* Set TX FIFO threshold and enable DMA. */ 1007179925Smarius v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1008179925Smarius GEM_TX_CONFIG_TXFIFO_TH; 1009179925Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 101091398Stmm 1011174987Smarius /* step 10. ERX Configuration */ 101291398Stmm 1013172334Smarius /* Encode Receive Descriptor ring size. */ 1014174987Smarius v = gem_ringsize(GEM_NRXDESC /* XXX */); 1015174987Smarius /* RX TCP/UDP checksum offset */ 1016170273Syongari v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 1017170273Syongari GEM_RX_CONFIG_CXM_START_SHFT); 1018194763Smarius /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1019177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1020174987Smarius v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1021194763Smarius (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1022194763Smarius GEM_RX_CONFIG_RXDMA_EN); 1023172334Smarius 1024194763Smarius /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1025177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1026194763Smarius ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1027194763Smarius GEM_RX_BLANKING_TIME_SHIFT) | 6); 1028172334Smarius 102991398Stmm /* 103099726Sbenno * The following value is for an OFF Threshold of about 3/4 full 103199726Sbenno * and an ON Threshold of 1/4 full. 103291398Stmm */ 1033177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 103499726Sbenno (3 * sc->sc_rxfifosize / 256) | 1035174987Smarius ((sc->sc_rxfifosize / 256) << 12)); 103691398Stmm 1037174987Smarius /* step 11. Configure Media. */ 103891398Stmm 1039174987Smarius /* step 12. RX_MAC Configuration Register */ 1040177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1041179925Smarius v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1042177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 1043179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1044179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1045177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1046179925Smarius device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1047177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 104891398Stmm 1049194763Smarius /* step 13. TX_MAC Configuration Register */ 1050179925Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1051179925Smarius v |= GEM_MAC_TX_ENABLE; 1052179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1053179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1054179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1055179925Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1056179925Smarius device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1057179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1058179925Smarius 1059174987Smarius /* step 14. Issue Transmit Pending command. */ 106091398Stmm 1061174987Smarius /* step 15. Give the reciever a swift kick. */ 1062177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 106391398Stmm 1064172334Smarius ifp->if_drv_flags |= IFF_DRV_RUNNING; 1065172334Smarius ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1066172334Smarius 1067172334Smarius mii_mediachg(sc->sc_mii); 1068172334Smarius 106991398Stmm /* Start the one second timer. */ 1070164931Smarius sc->sc_wdog_timer = 0; 107191398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 107291398Stmm} 107391398Stmm 107491398Stmmstatic int 1075174987Smariusgem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 107691398Stmm{ 1077174987Smarius bus_dma_segment_t txsegs[GEM_NTXSEGS]; 107891398Stmm struct gem_txsoft *txs; 1079179925Smarius struct ip *ip; 1080170273Syongari struct mbuf *m; 1081174987Smarius uint64_t cflags, flags; 1082179925Smarius int error, nexttx, nsegs, offset, seg; 108391398Stmm 1084194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1085194763Smarius 1086108832Stmm /* Get a work queue entry. */ 1087108832Stmm if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1088108832Stmm /* Ran out of descriptors. */ 1089170273Syongari return (ENOBUFS); 1090108832Stmm } 1091179925Smarius 1092179925Smarius cflags = 0; 1093179925Smarius if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1094179925Smarius if (M_WRITABLE(*m_head) == 0) { 1095179925Smarius m = m_dup(*m_head, M_DONTWAIT); 1096179925Smarius m_freem(*m_head); 1097179925Smarius *m_head = m; 1098179925Smarius if (m == NULL) 1099179925Smarius return (ENOBUFS); 1100179925Smarius } 1101179925Smarius offset = sizeof(struct ether_header); 1102179925Smarius m = m_pullup(*m_head, offset + sizeof(struct ip)); 1103179925Smarius if (m == NULL) { 1104179925Smarius *m_head = NULL; 1105179925Smarius return (ENOBUFS); 1106179925Smarius } 1107179925Smarius ip = (struct ip *)(mtod(m, caddr_t) + offset); 1108179925Smarius offset += (ip->ip_hl << 2); 1109179925Smarius cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1110179925Smarius ((offset + m->m_pkthdr.csum_data) << 1111179925Smarius GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1112179925Smarius *m_head = m; 1113179925Smarius } 1114179925Smarius 1115170273Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1116170273Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1117170273Syongari if (error == EFBIG) { 1118175418Sjhb m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 1119170273Syongari if (m == NULL) { 1120170273Syongari m_freem(*m_head); 1121170273Syongari *m_head = NULL; 1122170273Syongari return (ENOBUFS); 1123170273Syongari } 1124170273Syongari *m_head = m; 1125174987Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1126174987Smarius txs->txs_dmamap, *m_head, txsegs, &nsegs, 1127174987Smarius BUS_DMA_NOWAIT); 1128170273Syongari if (error != 0) { 1129170273Syongari m_freem(*m_head); 1130170273Syongari *m_head = NULL; 1131170273Syongari return (error); 1132170273Syongari } 1133170273Syongari } else if (error != 0) 1134170273Syongari return (error); 1135176996Smarius /* If nsegs is wrong then the stack is corrupt. */ 1136176996Smarius KASSERT(nsegs <= GEM_NTXSEGS, 1137176996Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1138170273Syongari if (nsegs == 0) { 1139170273Syongari m_freem(*m_head); 1140170273Syongari *m_head = NULL; 1141170273Syongari return (EIO); 1142170273Syongari } 1143170273Syongari 1144170273Syongari /* 1145170273Syongari * Ensure we have enough descriptors free to describe 1146170273Syongari * the packet. Note, we always reserve one descriptor 1147174987Smarius * at the end of the ring as a termination point, in 1148174987Smarius * order to prevent wrap-around. 1149170273Syongari */ 1150170273Syongari if (nsegs > sc->sc_txfree - 1) { 1151170273Syongari txs->txs_ndescs = 0; 1152170273Syongari bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1153170273Syongari return (ENOBUFS); 1154170273Syongari } 1155170273Syongari 1156170273Syongari txs->txs_ndescs = nsegs; 1157108832Stmm txs->txs_firstdesc = sc->sc_txnext; 1158170273Syongari nexttx = txs->txs_firstdesc; 1159170273Syongari for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1160172334Smarius#ifdef GEM_DEBUG 1161174987Smarius CTR6(KTR_GEM, 1162174987Smarius "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1163174987Smarius __func__, seg, nexttx, txsegs[seg].ds_len, 1164174987Smarius txsegs[seg].ds_addr, 1165170273Syongari GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1166170273Syongari#endif 1167170273Syongari sc->sc_txdescs[nexttx].gd_addr = 1168170273Syongari GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1169170273Syongari KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1170170273Syongari ("%s: segment size too large!", __func__)); 1171170273Syongari flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1172170273Syongari sc->sc_txdescs[nexttx].gd_flags = 1173170273Syongari GEM_DMA_WRITE(sc, flags | cflags); 1174170273Syongari txs->txs_lastdesc = nexttx; 117591398Stmm } 117691398Stmm 1177174987Smarius /* Set EOP on the last descriptor. */ 1178172334Smarius#ifdef GEM_DEBUG 1179174987Smarius CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1180174987Smarius __func__, seg, nexttx); 1181170273Syongari#endif 1182170273Syongari sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1183170273Syongari GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1184170273Syongari 1185174987Smarius /* Lastly set SOP on the first descriptor. */ 1186172334Smarius#ifdef GEM_DEBUG 1187174987Smarius CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1188174987Smarius __func__, seg, nexttx); 1189170273Syongari#endif 1190170273Syongari if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1191170273Syongari sc->sc_txwin = 0; 1192170273Syongari sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1193170273Syongari GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1194170273Syongari GEM_TD_START_OF_PACKET); 1195170273Syongari } else 1196170273Syongari sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1197170273Syongari GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1198170273Syongari 1199108832Stmm /* Sync the DMA map. */ 1200174987Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1201174987Smarius BUS_DMASYNC_PREWRITE); 120291398Stmm 1203115030Stmm#ifdef GEM_DEBUG 1204170273Syongari CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1205174987Smarius __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1206174987Smarius txs->txs_ndescs); 1207115030Stmm#endif 1208108832Stmm STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1209108832Stmm STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1210170273Syongari txs->txs_mbuf = *m_head; 121191398Stmm 1212108832Stmm sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1213108832Stmm sc->sc_txfree -= txs->txs_ndescs; 1214170273Syongari 1215108832Stmm return (0); 121691398Stmm} 121791398Stmm 121891398Stmmstatic void 1219174987Smariusgem_init_regs(struct gem_softc *sc) 122091398Stmm{ 1221152315Sru const u_char *laddr = IF_LLADDR(sc->sc_ifp); 122291398Stmm 1223194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1224194763Smarius 1225174987Smarius /* These registers are not cleared on reset. */ 1226172334Smarius if ((sc->sc_flags & GEM_INITED) == 0) { 1227174987Smarius /* magic values */ 1228177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1229177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1230177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 123191398Stmm 1232194763Smarius /* min frame length */ 1233177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1234194763Smarius /* max frame length and max burst size */ 1235177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1236172334Smarius (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 123799726Sbenno 1238194763Smarius /* more magic values */ 1239177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1240177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1241177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1242177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088); 1243194763Smarius 1244194763Smarius /* random number seed */ 1245177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1246174987Smarius ((laddr[5] << 8) | laddr[4]) & 0x3ff); 124799726Sbenno 1248174987Smarius /* secondary MAC address: 0:0:0:0:0:0 */ 1249177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1250177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1251177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 125299726Sbenno 1253174987Smarius /* MAC control address: 01:80:c2:00:00:01 */ 1254177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1255177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1256177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 125791398Stmm 1258174987Smarius /* MAC filter address: 0:0:0:0:0:0 */ 1259177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1260177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1261177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1262177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1263177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 126491398Stmm 1265172334Smarius sc->sc_flags |= GEM_INITED; 126691398Stmm } 126791398Stmm 1268174987Smarius /* Counters need to be zeroed. */ 1269177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1270177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1271177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1272177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1273177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1274177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1275177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1276177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1277177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1278177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1279177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 128091398Stmm 1281172334Smarius /* Set XOFF PAUSE time. */ 1282177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 128391398Stmm 1284174987Smarius /* Set the station address. */ 1285177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1286177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1287177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 128899726Sbenno 1289172334Smarius /* Enable MII outputs. */ 1290177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 129191398Stmm} 129291398Stmm 129391398Stmmstatic void 1294174987Smariusgem_start(struct ifnet *ifp) 129591398Stmm{ 1296174987Smarius struct gem_softc *sc = ifp->if_softc; 1297148369Smarius 1298148369Smarius GEM_LOCK(sc); 1299148369Smarius gem_start_locked(ifp); 1300148369Smarius GEM_UNLOCK(sc); 1301148369Smarius} 1302148369Smarius 1303194763Smariusstatic inline void 1304194763Smariusgem_txkick(struct gem_softc *sc) 1305194763Smarius{ 1306194763Smarius 1307194763Smarius /* 1308194763Smarius * Update the TX kick register. This register has to point to the 1309194763Smarius * descriptor after the last valid one and for optimum performance 1310194763Smarius * should be incremented in multiples of 4 (the DMA engine fetches/ 1311194763Smarius * updates descriptors in batches of 4). 1312194763Smarius */ 1313194763Smarius#ifdef GEM_DEBUG 1314194763Smarius CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1315194763Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1316194763Smarius#endif 1317194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1318194763Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1319194763Smarius} 1320194763Smarius 1321148369Smariusstatic void 1322174987Smariusgem_start_locked(struct ifnet *ifp) 1323148369Smarius{ 1324174987Smarius struct gem_softc *sc = ifp->if_softc; 1325170273Syongari struct mbuf *m; 1326194763Smarius int kicked, ntx; 132791398Stmm 1328194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1329194763Smarius 1330148887Srwatson if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1331172334Smarius IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 133291398Stmm return; 133391398Stmm 1334115030Stmm#ifdef GEM_DEBUG 1335170273Syongari CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1336172334Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1337172334Smarius sc->sc_txnext); 1338115030Stmm#endif 1339174987Smarius ntx = 0; 1340194763Smarius kicked = 0; 1341170273Syongari for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1342170273Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1343170273Syongari if (m == NULL) 134491398Stmm break; 1345172334Smarius if (gem_load_txmbuf(sc, &m) != 0) { 1346170273Syongari if (m == NULL) 1347170273Syongari break; 1348170273Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1349170273Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m); 135091398Stmm break; 135191398Stmm } 1352194763Smarius if ((sc->sc_txnext % 4) == 0) { 1353194763Smarius gem_txkick(sc); 1354194763Smarius kicked = 1; 1355194763Smarius } else 1356194763Smarius kicked = 0; 1357115030Stmm ntx++; 1358170273Syongari BPF_MTAP(ifp, m); 135991398Stmm } 136091398Stmm 136191398Stmm if (ntx > 0) { 1362194763Smarius if (kicked == 0) 1363194763Smarius gem_txkick(sc); 1364115030Stmm#ifdef GEM_DEBUG 1365108832Stmm CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1366172334Smarius device_get_name(sc->sc_dev), sc->sc_txnext); 1367115030Stmm#endif 136891398Stmm 136991398Stmm /* Set a watchdog timer in case the chip flakes out. */ 1370164931Smarius sc->sc_wdog_timer = 5; 1371115030Stmm#ifdef GEM_DEBUG 1372170273Syongari CTR3(KTR_GEM, "%s: %s: watchdog %d", 1373174987Smarius device_get_name(sc->sc_dev), __func__, 1374174987Smarius sc->sc_wdog_timer); 1375115030Stmm#endif 137691398Stmm } 137791398Stmm} 137891398Stmm 137991398Stmmstatic void 1380174987Smariusgem_tint(struct gem_softc *sc) 138191398Stmm{ 1382147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 138391398Stmm struct gem_txsoft *txs; 1384194763Smarius int progress; 1385194763Smarius uint32_t txlast; 1386174987Smarius#ifdef GEM_DEBUG 1387174987Smarius int i; 138891398Stmm 1389194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1390194763Smarius 1391170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1392115030Stmm#endif 139391398Stmm 139491398Stmm /* 1395174987Smarius * Go through our TX list and free mbufs for those 139691398Stmm * frames that have been transmitted. 139791398Stmm */ 1398174987Smarius progress = 0; 1399109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 140091398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 140191398Stmm#ifdef GEM_DEBUG 1402174987Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 140391398Stmm printf(" txsoft %p transmit chain:\n", txs); 140491398Stmm for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 140591398Stmm printf("descriptor %d: ", i); 1406174987Smarius printf("gd_flags: 0x%016llx\t", 1407174987Smarius (long long)GEM_DMA_READ(sc, 1408174987Smarius sc->sc_txdescs[i].gd_flags)); 1409174987Smarius printf("gd_addr: 0x%016llx\n", 1410174987Smarius (long long)GEM_DMA_READ(sc, 1411174987Smarius sc->sc_txdescs[i].gd_addr)); 141291398Stmm if (i == txs->txs_lastdesc) 141391398Stmm break; 141491398Stmm } 141591398Stmm } 141691398Stmm#endif 141791398Stmm 141891398Stmm /* 1419172334Smarius * In theory, we could harvest some descriptors before 142091398Stmm * the ring is empty, but that's a bit complicated. 142191398Stmm * 142291398Stmm * GEM_TX_COMPLETION points to the last descriptor 1423174987Smarius * processed + 1. 142491398Stmm */ 1425177560Smarius txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1426115030Stmm#ifdef GEM_DEBUG 1427170273Syongari CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 142891398Stmm "txs->txs_lastdesc = %d, txlast = %d", 1429170273Syongari __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1430115030Stmm#endif 143191398Stmm if (txs->txs_firstdesc <= txs->txs_lastdesc) { 143291398Stmm if ((txlast >= txs->txs_firstdesc) && 1433174987Smarius (txlast <= txs->txs_lastdesc)) 143491398Stmm break; 143591398Stmm } else { 1436174987Smarius /* Ick -- this command wraps. */ 143791398Stmm if ((txlast >= txs->txs_firstdesc) || 1438174987Smarius (txlast <= txs->txs_lastdesc)) 143991398Stmm break; 144091398Stmm } 144191398Stmm 1442115030Stmm#ifdef GEM_DEBUG 1443174987Smarius CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1444115030Stmm#endif 144591398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 144691398Stmm 144791398Stmm sc->sc_txfree += txs->txs_ndescs; 144891398Stmm 1449108832Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 145091398Stmm BUS_DMASYNC_POSTWRITE); 1451108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 145291398Stmm if (txs->txs_mbuf != NULL) { 145391398Stmm m_freem(txs->txs_mbuf); 145491398Stmm txs->txs_mbuf = NULL; 145591398Stmm } 145691398Stmm 145791398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 145891398Stmm 145991398Stmm ifp->if_opackets++; 146099726Sbenno progress = 1; 146191398Stmm } 146291398Stmm 1463115030Stmm#ifdef GEM_DEBUG 1464174987Smarius CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1465172334Smarius "GEM_TX_COMPLETION %x", 1466177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1467177560Smarius ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1468177560Smarius GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1469177560Smarius GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1470115030Stmm#endif 147191398Stmm 147299726Sbenno if (progress) { 147399726Sbenno if (sc->sc_txfree == GEM_NTXDESC - 1) 147499726Sbenno sc->sc_txwin = 0; 147591398Stmm 1476174987Smarius /* 1477174987Smarius * We freed some descriptors, so reset IFF_DRV_OACTIVE 1478174987Smarius * and restart. 1479174987Smarius */ 1480148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1481194763Smarius if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1482194763Smarius sc->sc_wdog_timer = 0; 1483179925Smarius gem_start_locked(ifp); 148499726Sbenno } 148599726Sbenno 1486115030Stmm#ifdef GEM_DEBUG 1487170273Syongari CTR3(KTR_GEM, "%s: %s: watchdog %d", 1488170273Syongari device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1489115030Stmm#endif 149091398Stmm} 149191398Stmm 1492148368Smarius#ifdef GEM_RINT_TIMEOUT 149393045Stmmstatic void 1494174987Smariusgem_rint_timeout(void *arg) 149593045Stmm{ 1496174987Smarius struct gem_softc *sc = arg; 149793045Stmm 1498150285Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1499194763Smarius 1500148369Smarius gem_rint(sc); 150193045Stmm} 1502100587Sjake#endif 150393045Stmm 150491398Stmmstatic void 1505174987Smariusgem_rint(struct gem_softc *sc) 150691398Stmm{ 1507147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 150891398Stmm struct mbuf *m; 1509174987Smarius uint64_t rxstat; 1510174987Smarius uint32_t rxcomp; 151191398Stmm 1512194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1513194763Smarius 1514148368Smarius#ifdef GEM_RINT_TIMEOUT 151593045Stmm callout_stop(&sc->sc_rx_ch); 1516148368Smarius#endif 1517115030Stmm#ifdef GEM_DEBUG 1518170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1519115030Stmm#endif 152099726Sbenno 152191398Stmm /* 152299726Sbenno * Read the completion register once. This limits 152399726Sbenno * how long the following loop can execute. 152499726Sbenno */ 1525177560Smarius rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1526115030Stmm#ifdef GEM_DEBUG 1527194763Smarius CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1528170273Syongari __func__, sc->sc_rxptr, rxcomp); 1529115030Stmm#endif 1530194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1531172334Smarius for (; sc->sc_rxptr != rxcomp;) { 1532172334Smarius m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1533172334Smarius rxstat = GEM_DMA_READ(sc, 1534172334Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 153591398Stmm 153691398Stmm if (rxstat & GEM_RD_OWN) { 1537148368Smarius#ifdef GEM_RINT_TIMEOUT 153891398Stmm /* 153993045Stmm * The descriptor is still marked as owned, although 1540174987Smarius * it is supposed to have completed. This has been 1541174987Smarius * observed on some machines. Just exiting here 154293045Stmm * might leave the packet sitting around until another 154393045Stmm * one arrives to trigger a new interrupt, which is 154493045Stmm * generally undesirable, so set up a timeout. 154591398Stmm */ 154693045Stmm callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 154793045Stmm gem_rint_timeout, sc); 154899726Sbenno#endif 1549172334Smarius m = NULL; 1550172334Smarius goto kickit; 155191398Stmm } 155291398Stmm 155391398Stmm if (rxstat & GEM_RD_BAD_CRC) { 155499726Sbenno ifp->if_ierrors++; 155591398Stmm device_printf(sc->sc_dev, "receive error: CRC error\n"); 1556172334Smarius GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1557172334Smarius m = NULL; 1558172334Smarius goto kickit; 155991398Stmm } 156091398Stmm 156191398Stmm#ifdef GEM_DEBUG 1562174987Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 1563172334Smarius printf(" rxsoft %p descriptor %d: ", 1564172334Smarius &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1565174987Smarius printf("gd_flags: 0x%016llx\t", 1566174987Smarius (long long)GEM_DMA_READ(sc, 1567174987Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1568174987Smarius printf("gd_addr: 0x%016llx\n", 1569174987Smarius (long long)GEM_DMA_READ(sc, 1570174987Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 157191398Stmm } 157291398Stmm#endif 157391398Stmm 157491398Stmm /* 157591398Stmm * Allocate a new mbuf cluster. If that fails, we are 157691398Stmm * out of memory, and must drop the packet and recycle 157791398Stmm * the buffer that's already attached to this descriptor. 157891398Stmm */ 1579172334Smarius if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 158091398Stmm ifp->if_ierrors++; 1581172334Smarius GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1582172334Smarius m = NULL; 1583172334Smarius } 1584172334Smarius 1585174987Smarius kickit: 1586174987Smarius /* 1587174987Smarius * Update the RX kick register. This register has to point 1588172334Smarius * to the descriptor after the last valid one (before the 1589194763Smarius * current batch) and for optimum performance should be 1590194763Smarius * incremented in multiples of 4 (the DMA engine fetches/ 1591194763Smarius * updates descriptors in batches of 4). 1592172334Smarius */ 1593172334Smarius sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1594172334Smarius if ((sc->sc_rxptr % 4) == 0) { 1595179925Smarius GEM_CDSYNC(sc, 1596179925Smarius BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1597177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1598172334Smarius (sc->sc_rxptr + GEM_NRXDESC - 4) & 1599172334Smarius GEM_NRXDESC_MASK); 1600172334Smarius } 1601172334Smarius 1602172334Smarius if (m == NULL) { 1603172334Smarius if (rxstat & GEM_RD_OWN) 1604172334Smarius break; 160591398Stmm continue; 160691398Stmm } 1607172334Smarius 1608172334Smarius ifp->if_ipackets++; 1609194763Smarius m->m_data += ETHER_ALIGN; /* first byte offset */ 161091398Stmm m->m_pkthdr.rcvif = ifp; 1611172334Smarius m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 161291398Stmm 1613170273Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1614170273Syongari gem_rxcksum(m, rxstat); 1615170273Syongari 161691398Stmm /* Pass it on. */ 1617148369Smarius GEM_UNLOCK(sc); 1618106937Ssam (*ifp->if_input)(ifp, m); 1619148369Smarius GEM_LOCK(sc); 162091398Stmm } 162191398Stmm 1622115030Stmm#ifdef GEM_DEBUG 1623194763Smarius CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1624177560Smarius sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1625115030Stmm#endif 162691398Stmm} 162791398Stmm 162891398Stmmstatic int 1629174987Smariusgem_add_rxbuf(struct gem_softc *sc, int idx) 163091398Stmm{ 163191398Stmm struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 163291398Stmm struct mbuf *m; 1633148368Smarius bus_dma_segment_t segs[1]; 1634148368Smarius int error, nsegs; 163591398Stmm 1636194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1637194763Smarius 1638111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 163991398Stmm if (m == NULL) 164091398Stmm return (ENOBUFS); 1641108832Stmm m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 164291398Stmm 164391398Stmm#ifdef GEM_DEBUG 1644174987Smarius /* Bzero the packet to check DMA. */ 164591398Stmm memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 164691398Stmm#endif 164791398Stmm 1648109648Stmm if (rxs->rxs_mbuf != NULL) { 1649109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1650109648Stmm BUS_DMASYNC_POSTREAD); 1651108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1652109648Stmm } 165391398Stmm 1654148368Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1655148368Smarius m, segs, &nsegs, BUS_DMA_NOWAIT); 1656148368Smarius if (error != 0) { 1657174987Smarius device_printf(sc->sc_dev, 1658174987Smarius "cannot load RS DMA map %d, error = %d\n", idx, error); 1659148368Smarius m_freem(m); 1660172334Smarius return (error); 166191398Stmm } 1662174987Smarius /* If nsegs is wrong then the stack is corrupt. */ 1663176996Smarius KASSERT(nsegs == 1, 1664176996Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1665172334Smarius rxs->rxs_mbuf = m; 1666148368Smarius rxs->rxs_paddr = segs[0].ds_addr; 166791398Stmm 1668174987Smarius bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1669174987Smarius BUS_DMASYNC_PREREAD); 167091398Stmm 167191398Stmm GEM_INIT_RXDESC(sc, idx); 167291398Stmm 167391398Stmm return (0); 167491398Stmm} 167591398Stmm 167691398Stmmstatic void 1677174987Smariusgem_eint(struct gem_softc *sc, u_int status) 167891398Stmm{ 167991398Stmm 1680172334Smarius sc->sc_ifp->if_ierrors++; 1681172334Smarius if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1682172334Smarius gem_reset_rxdma(sc); 168391398Stmm return; 168491398Stmm } 168591398Stmm 1686194763Smarius device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1687194763Smarius if ((status & GEM_INTR_BERR) != 0) { 1688194763Smarius if ((sc->sc_flags & GEM_PCI) != 0) 1689194763Smarius printf(", PCI bus error 0x%x\n", 1690194763Smarius GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1691194763Smarius else 1692194763Smarius printf(", SBus error 0x%x\n", 1693194763Smarius GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1694194763Smarius } 169591398Stmm} 169691398Stmm 169791398Stmmvoid 1698174987Smariusgem_intr(void *v) 169991398Stmm{ 1700174987Smarius struct gem_softc *sc = v; 1701172334Smarius uint32_t status, status2; 170291398Stmm 1703148369Smarius GEM_LOCK(sc); 1704177560Smarius status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1705172334Smarius 1706115030Stmm#ifdef GEM_DEBUG 1707170273Syongari CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1708194763Smarius device_get_name(sc->sc_dev), __func__, 1709194763Smarius (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1710172334Smarius 1711172334Smarius /* 1712172334Smarius * PCS interrupts must be cleared, otherwise no traffic is passed! 1713172334Smarius */ 1714172334Smarius if ((status & GEM_INTR_PCS) != 0) { 1715174987Smarius status2 = 1716177560Smarius GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1717177560Smarius GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1718172334Smarius if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1719172334Smarius device_printf(sc->sc_dev, 1720172334Smarius "%s: PCS link status changed\n", __func__); 1721172334Smarius } 1722172334Smarius if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1723177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1724172334Smarius if ((status2 & GEM_MAC_PAUSED) != 0) 1725172334Smarius device_printf(sc->sc_dev, 1726172334Smarius "%s: PAUSE received (PAUSE time %d slots)\n", 1727172334Smarius __func__, GEM_MAC_PAUSE_TIME(status2)); 1728172334Smarius if ((status2 & GEM_MAC_PAUSE) != 0) 1729172334Smarius device_printf(sc->sc_dev, 1730172334Smarius "%s: transited to PAUSE state\n", __func__); 1731172334Smarius if ((status2 & GEM_MAC_RESUME) != 0) 1732172334Smarius device_printf(sc->sc_dev, 1733172334Smarius "%s: transited to non-PAUSE state\n", __func__); 1734172334Smarius } 1735172334Smarius if ((status & GEM_INTR_MIF) != 0) 1736172334Smarius device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1737115030Stmm#endif 173891398Stmm 1739194763Smarius if (__predict_false(status & 1740172334Smarius (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 174191398Stmm gem_eint(sc, status); 174291398Stmm 1743172334Smarius if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1744172334Smarius gem_rint(sc); 1745172334Smarius 174691398Stmm if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 174791398Stmm gem_tint(sc); 174891398Stmm 1749194763Smarius if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1750177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1751174987Smarius if ((status2 & 1752194763Smarius ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1753194763Smarius GEM_MAC_TX_PEAK_EXP)) != 0) 1754174987Smarius device_printf(sc->sc_dev, 1755174987Smarius "MAC TX fault, status %x\n", status2); 1756174987Smarius if ((status2 & 1757194763Smarius (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1758194763Smarius sc->sc_ifp->if_oerrors++; 1759148369Smarius gem_init_locked(sc); 1760194763Smarius } 176191398Stmm } 1762194763Smarius if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1763177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1764149552Smarius /* 1765172334Smarius * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1766172334Smarius * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1767174987Smarius * silicon bug so handle them silently. Moreover, it's 1768172334Smarius * likely that the receiver has hung so we reset it. 1769149552Smarius */ 1770174987Smarius if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1771172334Smarius sc->sc_ifp->if_ierrors++; 1772172334Smarius gem_reset_rxdma(sc); 1773174987Smarius } else if ((status2 & 1774174987Smarius ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1775174987Smarius device_printf(sc->sc_dev, 1776174987Smarius "MAC RX fault, status %x\n", status2); 177791398Stmm } 1778148369Smarius GEM_UNLOCK(sc); 177991398Stmm} 178091398Stmm 1781164931Smariusstatic int 1782174987Smariusgem_watchdog(struct gem_softc *sc) 178391398Stmm{ 1784179925Smarius struct ifnet *ifp = sc->sc_ifp; 178591398Stmm 1786164931Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1787164931Smarius 1788115030Stmm#ifdef GEM_DEBUG 1789174987Smarius CTR4(KTR_GEM, 1790174987Smarius "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1791177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1792177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1793177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1794174987Smarius CTR4(KTR_GEM, 1795174987Smarius "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1796177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1797177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1798177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1799115030Stmm#endif 180091398Stmm 1801164931Smarius if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1802164931Smarius return (0); 1803164931Smarius 1804172334Smarius if ((sc->sc_flags & GEM_LINK) != 0) 1805172334Smarius device_printf(sc->sc_dev, "device timeout\n"); 1806172334Smarius else if (bootverbose) 1807172334Smarius device_printf(sc->sc_dev, "device timeout (no link)\n"); 1808179925Smarius ++ifp->if_oerrors; 180991398Stmm 181091398Stmm /* Try to get more packets going. */ 1811148369Smarius gem_init_locked(sc); 1812179925Smarius gem_start_locked(ifp); 1813164931Smarius return (EJUSTRETURN); 181491398Stmm} 181591398Stmm 181691398Stmmstatic void 1817174987Smariusgem_mifinit(struct gem_softc *sc) 181891398Stmm{ 181991398Stmm 1820176996Smarius /* Configure the MIF in frame mode. */ 1821177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1822177560Smarius GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1823212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 1824212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 182591398Stmm} 182691398Stmm 182791398Stmm/* 182891398Stmm * MII interface 182991398Stmm * 1830182060Smarius * The MII interface supports at least three different operating modes: 183191398Stmm * 183291398Stmm * Bitbang mode is implemented using data, clock and output enable registers. 183391398Stmm * 183491398Stmm * Frame mode is implemented by loading a complete frame into the frame 183591398Stmm * register and polling the valid bit for completion. 183691398Stmm * 183791398Stmm * Polling mode uses the frame register but completion is indicated by 183891398Stmm * an interrupt. 183991398Stmm * 184091398Stmm */ 184191398Stmmint 1842174987Smariusgem_mii_readreg(device_t dev, int phy, int reg) 184391398Stmm{ 1844174987Smarius struct gem_softc *sc; 184591398Stmm int n; 1846174987Smarius uint32_t v; 184791398Stmm 184891398Stmm#ifdef GEM_DEBUG_PHY 1849172334Smarius printf("%s: phy %d reg %d\n", __func__, phy, reg); 185091398Stmm#endif 185191398Stmm 1852174987Smarius sc = device_get_softc(dev); 1853172334Smarius if ((sc->sc_flags & GEM_SERDES) != 0) { 1854172334Smarius switch (reg) { 1855172334Smarius case MII_BMCR: 1856172334Smarius reg = GEM_MII_CONTROL; 1857172334Smarius break; 1858172334Smarius case MII_BMSR: 1859172334Smarius reg = GEM_MII_STATUS; 1860172334Smarius break; 1861172334Smarius case MII_PHYIDR1: 1862172334Smarius case MII_PHYIDR2: 1863172334Smarius return (0); 1864172334Smarius case MII_ANAR: 1865172334Smarius reg = GEM_MII_ANAR; 1866172334Smarius break; 1867172334Smarius case MII_ANLPAR: 1868172334Smarius reg = GEM_MII_ANLPAR; 1869172334Smarius break; 1870172334Smarius case MII_EXTSR: 1871172334Smarius return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1872172334Smarius default: 1873172334Smarius device_printf(sc->sc_dev, 1874172334Smarius "%s: unhandled register %d\n", __func__, reg); 1875172334Smarius return (0); 1876172334Smarius } 1877177560Smarius return (GEM_BANK1_READ_4(sc, reg)); 1878172334Smarius } 1879172334Smarius 1880174987Smarius /* Construct the frame command. */ 1881172334Smarius v = GEM_MIF_FRAME_READ | 1882172334Smarius (phy << GEM_MIF_PHY_SHIFT) | 1883172334Smarius (reg << GEM_MIF_REG_SHIFT); 188491398Stmm 1885177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1886179925Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1887179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 188891398Stmm for (n = 0; n < 100; n++) { 188991398Stmm DELAY(1); 1890177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1891150285Smarius if (v & GEM_MIF_FRAME_TA0) 189291398Stmm return (v & GEM_MIF_FRAME_DATA); 189391398Stmm } 189491398Stmm 1895174987Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 189691398Stmm return (0); 189791398Stmm} 189891398Stmm 189991398Stmmint 1900174987Smariusgem_mii_writereg(device_t dev, int phy, int reg, int val) 190191398Stmm{ 1902174987Smarius struct gem_softc *sc; 190391398Stmm int n; 1904174987Smarius uint32_t v; 190591398Stmm 190691398Stmm#ifdef GEM_DEBUG_PHY 1907172334Smarius printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 190891398Stmm#endif 190991398Stmm 1910174987Smarius sc = device_get_softc(dev); 1911172334Smarius if ((sc->sc_flags & GEM_SERDES) != 0) { 1912172334Smarius switch (reg) { 1913172334Smarius case MII_BMSR: 1914172334Smarius reg = GEM_MII_STATUS; 1915172334Smarius break; 1916179925Smarius case MII_BMCR: 1917179925Smarius reg = GEM_MII_CONTROL; 1918179925Smarius if ((val & GEM_MII_CONTROL_RESET) == 0) 1919179925Smarius break; 1920179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1921179925Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1922179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1923179925Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1924179925Smarius GEM_MII_CONTROL_RESET, 0)) 1925179925Smarius device_printf(sc->sc_dev, 1926179925Smarius "cannot reset PCS\n"); 1927179925Smarius /* FALLTHROUGH */ 1928172334Smarius case MII_ANAR: 1929177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1930177560Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1931172334Smarius BUS_SPACE_BARRIER_WRITE); 1932177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1933212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 1934212725Smarius BUS_SPACE_BARRIER_WRITE); 1935177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1936172334Smarius GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1937212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 1938212725Smarius BUS_SPACE_BARRIER_WRITE); 1939177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1940172334Smarius GEM_MII_CONFIG_ENABLE); 1941212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1942212725Smarius BUS_SPACE_BARRIER_WRITE); 1943172334Smarius return (0); 1944172334Smarius case MII_ANLPAR: 1945172334Smarius reg = GEM_MII_ANLPAR; 1946172334Smarius break; 1947172334Smarius default: 1948172334Smarius device_printf(sc->sc_dev, 1949172334Smarius "%s: unhandled register %d\n", __func__, reg); 1950172334Smarius return (0); 1951172334Smarius } 1952177560Smarius GEM_BANK1_WRITE_4(sc, reg, val); 1953212725Smarius GEM_BANK1_BARRIER(sc, reg, 4, 1954212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1955172334Smarius return (0); 1956172334Smarius } 1957172334Smarius 1958174987Smarius /* Construct the frame command. */ 1959172334Smarius v = GEM_MIF_FRAME_WRITE | 1960172334Smarius (phy << GEM_MIF_PHY_SHIFT) | 1961172334Smarius (reg << GEM_MIF_REG_SHIFT) | 196291398Stmm (val & GEM_MIF_FRAME_DATA); 196391398Stmm 1964177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1965179925Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1966179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 196791398Stmm for (n = 0; n < 100; n++) { 196891398Stmm DELAY(1); 1969177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1970150285Smarius if (v & GEM_MIF_FRAME_TA0) 197191398Stmm return (1); 197291398Stmm } 197391398Stmm 1974174987Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 197591398Stmm return (0); 197691398Stmm} 197791398Stmm 197891398Stmmvoid 1979174987Smariusgem_mii_statchg(device_t dev) 198091398Stmm{ 1981174987Smarius struct gem_softc *sc; 1982172334Smarius int gigabit; 1983172334Smarius uint32_t rxcfg, txcfg, v; 198491398Stmm 1985174987Smarius sc = device_get_softc(dev); 1986174987Smarius 1987194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1988194763Smarius 198991398Stmm#ifdef GEM_DEBUG 1990174987Smarius if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1991213893Smarius device_printf(sc->sc_dev, "%s: status change\n", __func__); 199291398Stmm#endif 199391398Stmm 1994172334Smarius if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 1995172334Smarius IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 1996172334Smarius sc->sc_flags |= GEM_LINK; 1997172334Smarius else 1998172334Smarius sc->sc_flags &= ~GEM_LINK; 1999172334Smarius 2000172334Smarius switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2001172334Smarius case IFM_1000_SX: 2002172334Smarius case IFM_1000_LX: 2003172334Smarius case IFM_1000_CX: 2004172334Smarius case IFM_1000_T: 2005172334Smarius gigabit = 1; 2006172334Smarius break; 2007172334Smarius default: 2008172334Smarius gigabit = 0; 200991398Stmm } 201091398Stmm 2011172334Smarius /* 2012172334Smarius * The configuration done here corresponds to the steps F) and 2013172334Smarius * G) and as far as enabling of RX and TX MAC goes also step H) 2014172334Smarius * of the initialization sequence outlined in section 3.2.1 of 2015172334Smarius * the GEM Gigabit Ethernet ASIC Specification. 2016172334Smarius */ 2017172334Smarius 2018177560Smarius rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2019172334Smarius rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2020172334Smarius txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2021172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2022172334Smarius txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2023172334Smarius else if (gigabit != 0) { 2024172334Smarius rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2025172334Smarius txcfg |= GEM_MAC_TX_CARR_EXTEND; 2026172334Smarius } 2027177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 2028179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 2029179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2030177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2031172334Smarius device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2032177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2033177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 2034179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2035179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2036177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2037172334Smarius device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2038177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2039172334Smarius 2040177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2041172334Smarius ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2042172334Smarius#ifdef notyet 2043174987Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2044174987Smarius IFM_ETH_RXPAUSE) != 0) 2045172334Smarius v |= GEM_MAC_CC_RX_PAUSE; 2046174987Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2047174987Smarius IFM_ETH_TXPAUSE) != 0) 2048172334Smarius v |= GEM_MAC_CC_TX_PAUSE; 2049172334Smarius#endif 2050177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2051172334Smarius 2052172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2053172334Smarius gigabit != 0) 2054177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2055172334Smarius GEM_MAC_SLOT_TIME_CARR_EXTEND); 2056172334Smarius else 2057177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2058172334Smarius GEM_MAC_SLOT_TIME_NORMAL); 2059172334Smarius 206091398Stmm /* XIF Configuration */ 206191398Stmm v = GEM_MAC_XIF_LINK_LED; 206291398Stmm v |= GEM_MAC_XIF_TX_MII_ENA; 2063172334Smarius if ((sc->sc_flags & GEM_SERDES) == 0) { 2064177560Smarius if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2065182060Smarius GEM_MIF_CONFIG_PHY_SEL) != 0) { 2066172334Smarius /* External MII needs echo disable if half duplex. */ 2067194763Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2068182060Smarius IFM_FDX) == 0) 2069182060Smarius v |= GEM_MAC_XIF_ECHO_DISABL; 2070182060Smarius } else 2071172334Smarius /* 2072172334Smarius * Internal MII needs buffer enable. 2073172334Smarius * XXX buffer enable makes only sense for an 2074172334Smarius * external PHY. 2075172334Smarius */ 2076172334Smarius v |= GEM_MAC_XIF_MII_BUF_ENA; 2077172334Smarius } 2078172334Smarius if (gigabit != 0) 2079172334Smarius v |= GEM_MAC_XIF_GMII_MODE; 2080172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2081172334Smarius v |= GEM_MAC_XIF_FDPLX_LED; 2082177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 208399726Sbenno 2084172334Smarius if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2085172334Smarius (sc->sc_flags & GEM_LINK) != 0) { 2086177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2087172334Smarius txcfg | GEM_MAC_TX_ENABLE); 2088177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2089172334Smarius rxcfg | GEM_MAC_RX_ENABLE); 209091398Stmm } 209191398Stmm} 209291398Stmm 209391398Stmmint 2094174987Smariusgem_mediachange(struct ifnet *ifp) 209591398Stmm{ 209691398Stmm struct gem_softc *sc = ifp->if_softc; 2097150285Smarius int error; 209891398Stmm 2099174987Smarius /* XXX add support for serial media. */ 210091398Stmm 2101150285Smarius GEM_LOCK(sc); 2102150285Smarius error = mii_mediachg(sc->sc_mii); 2103150285Smarius GEM_UNLOCK(sc); 2104150285Smarius return (error); 210591398Stmm} 210691398Stmm 210791398Stmmvoid 2108174987Smariusgem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 210991398Stmm{ 211091398Stmm struct gem_softc *sc = ifp->if_softc; 211191398Stmm 2112148369Smarius GEM_LOCK(sc); 2113148369Smarius if ((ifp->if_flags & IFF_UP) == 0) { 2114148369Smarius GEM_UNLOCK(sc); 211591398Stmm return; 2116148369Smarius } 211791398Stmm 211891398Stmm mii_pollstat(sc->sc_mii); 211991398Stmm ifmr->ifm_active = sc->sc_mii->mii_media_active; 212091398Stmm ifmr->ifm_status = sc->sc_mii->mii_media_status; 2121148369Smarius GEM_UNLOCK(sc); 212291398Stmm} 212391398Stmm 212491398Stmmstatic int 2125174987Smariusgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 212691398Stmm{ 212791398Stmm struct gem_softc *sc = ifp->if_softc; 212891398Stmm struct ifreq *ifr = (struct ifreq *)data; 2129174987Smarius int error; 213091398Stmm 2131174987Smarius error = 0; 213291398Stmm switch (cmd) { 2133150285Smarius case SIOCSIFFLAGS: 2134148369Smarius GEM_LOCK(sc); 2135174987Smarius if ((ifp->if_flags & IFF_UP) != 0) { 2136172334Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2137172334Smarius ((ifp->if_flags ^ sc->sc_ifflags) & 2138172334Smarius (IFF_ALLMULTI | IFF_PROMISC)) != 0) 213991398Stmm gem_setladrf(sc); 214091398Stmm else 2141148369Smarius gem_init_locked(sc); 2142174987Smarius } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2143174987Smarius gem_stop(ifp, 0); 2144170273Syongari if ((ifp->if_flags & IFF_LINK0) != 0) 2145170273Syongari sc->sc_csum_features |= CSUM_UDP; 2146170273Syongari else 2147170273Syongari sc->sc_csum_features &= ~CSUM_UDP; 2148170273Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2149170273Syongari ifp->if_hwassist = sc->sc_csum_features; 215099726Sbenno sc->sc_ifflags = ifp->if_flags; 2151150285Smarius GEM_UNLOCK(sc); 215291398Stmm break; 215391398Stmm case SIOCADDMULTI: 215491398Stmm case SIOCDELMULTI: 2155150285Smarius GEM_LOCK(sc); 215691398Stmm gem_setladrf(sc); 2157150285Smarius GEM_UNLOCK(sc); 215891398Stmm break; 215991398Stmm case SIOCGIFMEDIA: 216091398Stmm case SIOCSIFMEDIA: 216191398Stmm error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 216291398Stmm break; 2163170273Syongari case SIOCSIFCAP: 2164170273Syongari GEM_LOCK(sc); 2165170273Syongari ifp->if_capenable = ifr->ifr_reqcap; 2166170273Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2167170273Syongari ifp->if_hwassist = sc->sc_csum_features; 2168170273Syongari else 2169170273Syongari ifp->if_hwassist = 0; 2170170273Syongari GEM_UNLOCK(sc); 2171170273Syongari break; 217291398Stmm default: 2173150285Smarius error = ether_ioctl(ifp, cmd, data); 217491398Stmm break; 217591398Stmm } 217691398Stmm 217791398Stmm return (error); 217891398Stmm} 217991398Stmm 218091398Stmmstatic void 2181174987Smariusgem_setladrf(struct gem_softc *sc) 218291398Stmm{ 2183147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 218491398Stmm struct ifmultiaddr *inm; 218599726Sbenno int i; 2186174987Smarius uint32_t hash[16]; 2187174987Smarius uint32_t crc, v; 218891398Stmm 2189148369Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 2190148369Smarius 2191174987Smarius /* Get the current RX configuration. */ 2192177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 219391398Stmm 219499726Sbenno /* 219599726Sbenno * Turn off promiscuous mode, promiscuous group mode (all multicast), 219699726Sbenno * and hash filter. Depending on the case, the right bit will be 219799726Sbenno * enabled. 219899726Sbenno */ 2199174987Smarius v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 220099726Sbenno GEM_MAC_RX_PROMISC_GRP); 220199726Sbenno 2202177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2203179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2204179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2205177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 2206177560Smarius 0)) 2207172334Smarius device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2208172334Smarius 220991398Stmm if ((ifp->if_flags & IFF_PROMISC) != 0) { 221091398Stmm v |= GEM_MAC_RX_PROMISCUOUS; 221191398Stmm goto chipit; 221291398Stmm } 221391398Stmm if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 221499726Sbenno v |= GEM_MAC_RX_PROMISC_GRP; 221591398Stmm goto chipit; 221691398Stmm } 221791398Stmm 221891398Stmm /* 2219174987Smarius * Set up multicast address filter by passing all multicast 2220174987Smarius * addresses through a crc generator, and then using the high 2221174987Smarius * order 8 bits as an index into the 256 bit logical address 2222174987Smarius * filter. The high order 4 bits selects the word, while the 2223174987Smarius * other 4 bits select the bit within the word (where bit 0 2224174987Smarius * is the MSB). 222591398Stmm */ 222691398Stmm 2227174987Smarius /* Clear the hash table. */ 222899726Sbenno memset(hash, 0, sizeof(hash)); 222999726Sbenno 2230195049Srwatson if_maddr_rlock(ifp); 2231147256Sbrooks TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 223291398Stmm if (inm->ifma_addr->sa_family != AF_LINK) 223391398Stmm continue; 2234130288Smarius crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2235130288Smarius inm->ifma_addr), ETHER_ADDR_LEN); 223691398Stmm 2237174987Smarius /* We just want the 8 most significant bits. */ 223891398Stmm crc >>= 24; 223991398Stmm 224091398Stmm /* Set the corresponding bit in the filter. */ 224199726Sbenno hash[crc >> 4] |= 1 << (15 - (crc & 15)); 224291398Stmm } 2243195049Srwatson if_maddr_runlock(ifp); 224491398Stmm 224599726Sbenno v |= GEM_MAC_RX_HASH_FILTER; 224699726Sbenno 2247174987Smarius /* Now load the hash table into the chip (if we are using it). */ 2248174987Smarius for (i = 0; i < 16; i++) 2249177560Smarius GEM_BANK1_WRITE_4(sc, 2250174987Smarius GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 225199726Sbenno hash[i]); 225299726Sbenno 2253174987Smarius chipit: 2254177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 225591398Stmm} 2256