if_gem.c revision 212725
1119418Sobrien/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 3108832Stmm * Copyright (c) 2001-2003 Thomas Moestl 4174987Smarius * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 591398Stmm * All rights reserved. 691398Stmm * 791398Stmm * Redistribution and use in source and binary forms, with or without 891398Stmm * modification, are permitted provided that the following conditions 991398Stmm * are met: 1091398Stmm * 1. Redistributions of source code must retain the above copyright 1191398Stmm * notice, this list of conditions and the following disclaimer. 1291398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1391398Stmm * notice, this list of conditions and the following disclaimer in the 1491398Stmm * documentation and/or other materials provided with the distribution. 1591398Stmm * 1691398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1791398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1891398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1991398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 2091398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2191398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2291398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2391398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2491398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2591398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2691398Stmm * SUCH DAMAGE. 2791398Stmm * 2899726Sbenno * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 2991398Stmm */ 3091398Stmm 31119418Sobrien#include <sys/cdefs.h> 32119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 212725 2010-09-16 09:29:48Z marius $"); 33119418Sobrien 3491398Stmm/* 35172334Smarius * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 3691398Stmm */ 3791398Stmm 38115030Stmm#if 0 3991398Stmm#define GEM_DEBUG 40115030Stmm#endif 4191398Stmm 42148368Smarius#if 0 /* XXX: In case of emergency, re-enable this. */ 43148368Smarius#define GEM_RINT_TIMEOUT 44148368Smarius#endif 45148368Smarius 4691398Stmm#include <sys/param.h> 4791398Stmm#include <sys/systm.h> 4891398Stmm#include <sys/bus.h> 4991398Stmm#include <sys/callout.h> 5095533Smike#include <sys/endian.h> 5191398Stmm#include <sys/mbuf.h> 5291398Stmm#include <sys/malloc.h> 5391398Stmm#include <sys/kernel.h> 54148369Smarius#include <sys/lock.h> 55130026Sphk#include <sys/module.h> 56148369Smarius#include <sys/mutex.h> 5791398Stmm#include <sys/socket.h> 5891398Stmm#include <sys/sockio.h> 59169269Sphk#include <sys/rman.h> 6091398Stmm 61105982Stmm#include <net/bpf.h> 6291398Stmm#include <net/ethernet.h> 6391398Stmm#include <net/if.h> 6491398Stmm#include <net/if_arp.h> 6591398Stmm#include <net/if_dl.h> 6691398Stmm#include <net/if_media.h> 67147256Sbrooks#include <net/if_types.h> 68149552Smarius#include <net/if_vlan_var.h> 6991398Stmm 70170273Syongari#include <netinet/in.h> 71170273Syongari#include <netinet/in_systm.h> 72170273Syongari#include <netinet/ip.h> 73170273Syongari#include <netinet/tcp.h> 74170273Syongari#include <netinet/udp.h> 75170273Syongari 7691398Stmm#include <machine/bus.h> 7791398Stmm 7891398Stmm#include <dev/mii/mii.h> 7991398Stmm#include <dev/mii/miivar.h> 8091398Stmm 81119355Simp#include <dev/gem/if_gemreg.h> 82119355Simp#include <dev/gem/if_gemvar.h> 8391398Stmm 84172334SmariusCTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 85172334SmariusCTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 86172334Smarius 87194763Smarius#define GEM_TRIES 10000 88172334Smarius 89170273Syongari/* 90182060Smarius * The hardware supports basic TCP/UDP checksum offloading. However, 91170273Syongari * the hardware doesn't compensate the checksum for UDP datagram which 92174987Smarius * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 93174987Smarius * by default. It can be reactivated by setting special link option 94170273Syongari * link0 with ifconfig(8). 95170273Syongari */ 96170273Syongari#define GEM_CSUM_FEATURES (CSUM_TCP) 9791398Stmm 98174987Smariusstatic int gem_add_rxbuf(struct gem_softc *sc, int idx); 99177560Smariusstatic int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 100177560Smarius uint32_t clr, uint32_t set); 101174987Smariusstatic void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 102174987Smarius int nsegs, int error); 103174987Smariusstatic int gem_disable_rx(struct gem_softc *sc); 104174987Smariusstatic int gem_disable_tx(struct gem_softc *sc); 105174987Smariusstatic void gem_eint(struct gem_softc *sc, u_int status); 106174987Smariusstatic void gem_init(void *xsc); 107174987Smariusstatic void gem_init_locked(struct gem_softc *sc); 108174987Smariusstatic void gem_init_regs(struct gem_softc *sc); 109174987Smariusstatic int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 110174987Smariusstatic int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 111174987Smariusstatic int gem_meminit(struct gem_softc *sc); 112174987Smariusstatic void gem_mifinit(struct gem_softc *sc); 113174987Smariusstatic void gem_reset(struct gem_softc *sc); 114174987Smariusstatic int gem_reset_rx(struct gem_softc *sc); 115172334Smariusstatic void gem_reset_rxdma(struct gem_softc *sc); 116174987Smariusstatic int gem_reset_tx(struct gem_softc *sc); 117174987Smariusstatic u_int gem_ringsize(u_int sz); 118174987Smariusstatic void gem_rint(struct gem_softc *sc); 119148368Smarius#ifdef GEM_RINT_TIMEOUT 120174987Smariusstatic void gem_rint_timeout(void *arg); 121100587Sjake#endif 122194763Smariusstatic inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 123174987Smariusstatic void gem_rxdrain(struct gem_softc *sc); 124174987Smariusstatic void gem_setladrf(struct gem_softc *sc); 125174987Smariusstatic void gem_start(struct ifnet *ifp); 126174987Smariusstatic void gem_start_locked(struct ifnet *ifp); 127174987Smariusstatic void gem_stop(struct ifnet *ifp, int disable); 128174987Smariusstatic void gem_tick(void *arg); 129174987Smariusstatic void gem_tint(struct gem_softc *sc); 130194763Smariusstatic inline void gem_txkick(struct gem_softc *sc); 131174987Smariusstatic int gem_watchdog(struct gem_softc *sc); 13291398Stmm 13391398Stmmdevclass_t gem_devclass; 13491398StmmDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 13591398StmmMODULE_DEPEND(gem, miibus, 1, 1, 1); 13691398Stmm 13791398Stmm#ifdef GEM_DEBUG 13891398Stmm#include <sys/ktr.h> 139210334Sattilio#define KTR_GEM KTR_SPARE2 14091398Stmm#endif 14191398Stmm 142177560Smarius#define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 143177560Smarius gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 144177560Smarius#define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 145177560Smarius gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 146177560Smarius 14791398Stmmint 148174987Smariusgem_attach(struct gem_softc *sc) 14991398Stmm{ 150174987Smarius struct gem_txsoft *txs; 151147256Sbrooks struct ifnet *ifp; 152174987Smarius int error, i; 153174987Smarius uint32_t v; 15491398Stmm 155194763Smarius if (bootverbose) 156194763Smarius device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 157194763Smarius 158194763Smarius /* Set up ifnet structure. */ 159147256Sbrooks ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 160147256Sbrooks if (ifp == NULL) 161147256Sbrooks return (ENOSPC); 162194763Smarius sc->sc_csum_features = GEM_CSUM_FEATURES; 163194763Smarius ifp->if_softc = sc; 164194763Smarius if_initname(ifp, device_get_name(sc->sc_dev), 165194763Smarius device_get_unit(sc->sc_dev)); 166194763Smarius ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 167194763Smarius ifp->if_start = gem_start; 168194763Smarius ifp->if_ioctl = gem_ioctl; 169194763Smarius ifp->if_init = gem_init; 170194763Smarius IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 171194763Smarius ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 172194763Smarius IFQ_SET_READY(&ifp->if_snd); 173147256Sbrooks 174150285Smarius callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 175150285Smarius#ifdef GEM_RINT_TIMEOUT 176150285Smarius callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 177150285Smarius#endif 178150285Smarius 17991398Stmm /* Make sure the chip is stopped. */ 18091398Stmm gem_reset(sc); 18191398Stmm 182161928Sjmg error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 183161928Sjmg BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 184174987Smarius BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 185174987Smarius NULL, &sc->sc_pdmatag); 186194763Smarius if (error != 0) 187147256Sbrooks goto fail_ifnet; 18891398Stmm 18991398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 190170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 191170273Syongari 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 192194763Smarius if (error != 0) 193108832Stmm goto fail_ptag; 19491398Stmm 195108832Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 196170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 197170273Syongari MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 198117126Sscottl BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 199194763Smarius if (error != 0) 200108832Stmm goto fail_rtag; 201108832Stmm 20291398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 203170273Syongari BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 20491398Stmm sizeof(struct gem_control_data), 1, 205170273Syongari sizeof(struct gem_control_data), 0, 206170273Syongari NULL, NULL, &sc->sc_cdmatag); 207194763Smarius if (error != 0) 208108832Stmm goto fail_ttag; 20991398Stmm 21091398Stmm /* 211174987Smarius * Allocate the control data structures, create and load the 21291398Stmm * DMA map for it. 21391398Stmm */ 21491398Stmm if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 215170273Syongari (void **)&sc->sc_control_data, 216170273Syongari BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 217194763Smarius &sc->sc_cddmamap)) != 0) { 218174987Smarius device_printf(sc->sc_dev, 219174987Smarius "unable to allocate control data, error = %d\n", error); 220108832Stmm goto fail_ctag; 22191398Stmm } 22291398Stmm 22391398Stmm sc->sc_cddma = 0; 22491398Stmm if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 22591398Stmm sc->sc_control_data, sizeof(struct gem_control_data), 22691398Stmm gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 227174987Smarius device_printf(sc->sc_dev, 228174987Smarius "unable to load control data DMA map, error = %d\n", 229174987Smarius error); 230108832Stmm goto fail_cmem; 23191398Stmm } 23291398Stmm 23391398Stmm /* 23491398Stmm * Initialize the transmit job descriptors. 23591398Stmm */ 23691398Stmm STAILQ_INIT(&sc->sc_txfreeq); 23791398Stmm STAILQ_INIT(&sc->sc_txdirtyq); 23891398Stmm 23991398Stmm /* 24091398Stmm * Create the transmit buffer DMA maps. 24191398Stmm */ 24291398Stmm error = ENOMEM; 24391398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 24491398Stmm txs = &sc->sc_txsoft[i]; 24591398Stmm txs->txs_mbuf = NULL; 24691398Stmm txs->txs_ndescs = 0; 247108832Stmm if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 24891398Stmm &txs->txs_dmamap)) != 0) { 249174987Smarius device_printf(sc->sc_dev, 250174987Smarius "unable to create TX DMA map %d, error = %d\n", 251174987Smarius i, error); 252108832Stmm goto fail_txd; 25391398Stmm } 25491398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 25591398Stmm } 25691398Stmm 25791398Stmm /* 25891398Stmm * Create the receive buffer DMA maps. 25991398Stmm */ 26091398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 261108832Stmm if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 26291398Stmm &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263174987Smarius device_printf(sc->sc_dev, 264174987Smarius "unable to create RX DMA map %d, error = %d\n", 265174987Smarius i, error); 266108832Stmm goto fail_rxd; 26791398Stmm } 26891398Stmm sc->sc_rxsoft[i].rxs_mbuf = NULL; 26991398Stmm } 27091398Stmm 271212725Smarius /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 272212725Smarius if ((sc->sc_flags & GEM_SERDES) != 0) 273212725Smarius goto serdes; 274212725Smarius 275172334Smarius /* Bad things will happen when touching this register on ERI. */ 276212725Smarius if (sc->sc_variant != GEM_SUN_ERI) { 277177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 278172334Smarius GEM_MII_DATAPATH_MII); 279212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 280212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 281212725Smarius } 282172334Smarius 28391398Stmm gem_mifinit(sc); 28491398Stmm 285172334Smarius /* 286172334Smarius * Look for an external PHY. 287172334Smarius */ 288172334Smarius error = ENXIO; 289177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 290172334Smarius if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 291172334Smarius v |= GEM_MIF_CONFIG_PHY_SEL; 292177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 293212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 294212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 295172334Smarius switch (sc->sc_variant) { 296172334Smarius case GEM_SUN_ERI: 297172334Smarius sc->sc_phyad = GEM_PHYAD_EXTERNAL; 298172334Smarius break; 299172334Smarius default: 300172334Smarius sc->sc_phyad = -1; 301172334Smarius break; 302172334Smarius } 303172334Smarius error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 304172334Smarius gem_mediachange, gem_mediastatus); 305172334Smarius } 306172334Smarius 307172334Smarius /* 308172334Smarius * Fall back on an internal PHY if no external PHY was found. 309204222Smarius * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 310204222Smarius * trusted when the firmware has powered down the chip. 311172334Smarius */ 312204222Smarius if (error != 0 && 313204222Smarius ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 314172334Smarius v &= ~GEM_MIF_CONFIG_PHY_SEL; 315177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 316212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 317212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 318172334Smarius switch (sc->sc_variant) { 319172334Smarius case GEM_SUN_ERI: 320172334Smarius case GEM_APPLE_K2_GMAC: 321172334Smarius sc->sc_phyad = GEM_PHYAD_INTERNAL; 322172334Smarius break; 323172334Smarius case GEM_APPLE_GMAC: 324172334Smarius sc->sc_phyad = GEM_PHYAD_EXTERNAL; 325172334Smarius break; 326172334Smarius default: 327172334Smarius sc->sc_phyad = -1; 328172334Smarius break; 329172334Smarius } 330172334Smarius error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 331172334Smarius gem_mediachange, gem_mediastatus); 332172334Smarius } 333172334Smarius 334172334Smarius /* 335172334Smarius * Try the external PCS SERDES if we didn't find any PHYs. 336172334Smarius */ 337172334Smarius if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 338212725Smarius serdes: 339177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 340172334Smarius GEM_MII_DATAPATH_SERDES); 341212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 342212725Smarius BUS_SPACE_BARRIER_WRITE); 343177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 344172334Smarius GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 345212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 346212725Smarius BUS_SPACE_BARRIER_WRITE); 347177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 348212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 349212725Smarius BUS_SPACE_BARRIER_WRITE); 350172334Smarius sc->sc_flags |= GEM_SERDES; 351172334Smarius sc->sc_phyad = GEM_PHYAD_EXTERNAL; 352172334Smarius error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 353172334Smarius gem_mediachange, gem_mediastatus); 354172334Smarius } 355172334Smarius if (error != 0) { 356172334Smarius device_printf(sc->sc_dev, "PHY probe failed: %d\n", error); 357108832Stmm goto fail_rxd; 35891398Stmm } 35991398Stmm sc->sc_mii = device_get_softc(sc->sc_miibus); 36091398Stmm 36191398Stmm /* 36291398Stmm * From this point forward, the attachment cannot fail. A failure 36391398Stmm * before this point releases all resources that may have been 36491398Stmm * allocated. 36591398Stmm */ 36691398Stmm 367176996Smarius /* Get RX FIFO size. */ 36899726Sbenno sc->sc_rxfifosize = 64 * 369177560Smarius GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 37099726Sbenno 371176996Smarius /* Get TX FIFO size. */ 372177560Smarius v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 373128588Stmm device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 374128588Stmm sc->sc_rxfifosize / 1024, v / 16); 37599726Sbenno 37691398Stmm /* Attach the interface. */ 377147256Sbrooks ether_ifattach(ifp, sc->sc_enaddr); 37891398Stmm 37991398Stmm /* 380170273Syongari * Tell the upper layer(s) we support long frames/checksum offloads. 381149552Smarius */ 382149552Smarius ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 383170273Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 384170273Syongari ifp->if_hwassist |= sc->sc_csum_features; 385170273Syongari ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 386149552Smarius 38791398Stmm return (0); 38891398Stmm 38991398Stmm /* 39091398Stmm * Free any resources we've allocated during the failed attach 39191398Stmm * attempt. Do this in reverse order and fall through. 39291398Stmm */ 393174987Smarius fail_rxd: 394174987Smarius for (i = 0; i < GEM_NRXDESC; i++) 39591398Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 396108832Stmm bus_dmamap_destroy(sc->sc_rdmatag, 39791398Stmm sc->sc_rxsoft[i].rxs_dmamap); 398174987Smarius fail_txd: 399174987Smarius for (i = 0; i < GEM_TXQUEUELEN; i++) 40091398Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 401108832Stmm bus_dmamap_destroy(sc->sc_tdmatag, 40291398Stmm sc->sc_txsoft[i].txs_dmamap); 403108832Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 404174987Smarius fail_cmem: 40591398Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 40691398Stmm sc->sc_cddmamap); 407174987Smarius fail_ctag: 40891398Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 409174987Smarius fail_ttag: 410108832Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 411174987Smarius fail_rtag: 412108832Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 413174987Smarius fail_ptag: 41491398Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 415174987Smarius fail_ifnet: 416147256Sbrooks if_free(ifp); 41791398Stmm return (error); 41891398Stmm} 41991398Stmm 420108964Stmmvoid 421174987Smariusgem_detach(struct gem_softc *sc) 422108964Stmm{ 423147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 424108964Stmm int i; 425108964Stmm 426194886Smarius ether_ifdetach(ifp); 427148369Smarius GEM_LOCK(sc); 428147317Sbrooks gem_stop(ifp, 1); 429148369Smarius GEM_UNLOCK(sc); 430150285Smarius callout_drain(&sc->sc_tick_ch); 431150285Smarius#ifdef GEM_RINT_TIMEOUT 432150285Smarius callout_drain(&sc->sc_rx_ch); 433150285Smarius#endif 434147256Sbrooks if_free(ifp); 435108964Stmm device_delete_child(sc->sc_dev, sc->sc_miibus); 436108964Stmm 437174987Smarius for (i = 0; i < GEM_NRXDESC; i++) 438108964Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 439108964Stmm bus_dmamap_destroy(sc->sc_rdmatag, 440108964Stmm sc->sc_rxsoft[i].rxs_dmamap); 441174987Smarius for (i = 0; i < GEM_TXQUEUELEN; i++) 442108964Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 443108964Stmm bus_dmamap_destroy(sc->sc_tdmatag, 444108964Stmm sc->sc_txsoft[i].txs_dmamap); 445179925Smarius GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 446108964Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 447108964Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 448108964Stmm sc->sc_cddmamap); 449108964Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 450108964Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 451108964Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 452108964Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 453108964Stmm} 454108964Stmm 455108964Stmmvoid 456174987Smariusgem_suspend(struct gem_softc *sc) 457108964Stmm{ 458147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 459108964Stmm 460148369Smarius GEM_LOCK(sc); 461108964Stmm gem_stop(ifp, 0); 462148369Smarius GEM_UNLOCK(sc); 463108964Stmm} 464108964Stmm 465108964Stmmvoid 466174987Smariusgem_resume(struct gem_softc *sc) 467108964Stmm{ 468147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 469108964Stmm 470148369Smarius GEM_LOCK(sc); 471149552Smarius /* 472149552Smarius * On resume all registers have to be initialized again like 473149552Smarius * after power-on. 474149552Smarius */ 475172334Smarius sc->sc_flags &= ~GEM_INITED; 476108964Stmm if (ifp->if_flags & IFF_UP) 477148369Smarius gem_init_locked(sc); 478148369Smarius GEM_UNLOCK(sc); 479108964Stmm} 480108964Stmm 481194763Smariusstatic inline void 482170273Syongarigem_rxcksum(struct mbuf *m, uint64_t flags) 483170273Syongari{ 484170273Syongari struct ether_header *eh; 485170273Syongari struct ip *ip; 486170273Syongari struct udphdr *uh; 487174987Smarius uint16_t *opts; 488170273Syongari int32_t hlen, len, pktlen; 489170273Syongari uint32_t temp32; 490174987Smarius uint16_t cksum; 491170273Syongari 492170273Syongari pktlen = m->m_pkthdr.len; 493170273Syongari if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 494170273Syongari return; 495170273Syongari eh = mtod(m, struct ether_header *); 496170273Syongari if (eh->ether_type != htons(ETHERTYPE_IP)) 497170273Syongari return; 498170273Syongari ip = (struct ip *)(eh + 1); 499170273Syongari if (ip->ip_v != IPVERSION) 500170273Syongari return; 501170273Syongari 502170273Syongari hlen = ip->ip_hl << 2; 503170273Syongari pktlen -= sizeof(struct ether_header); 504170273Syongari if (hlen < sizeof(struct ip)) 505170273Syongari return; 506170273Syongari if (ntohs(ip->ip_len) < hlen) 507170273Syongari return; 508170273Syongari if (ntohs(ip->ip_len) != pktlen) 509170273Syongari return; 510170273Syongari if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 511174987Smarius return; /* Cannot handle fragmented packet. */ 512170273Syongari 513170273Syongari switch (ip->ip_p) { 514170273Syongari case IPPROTO_TCP: 515170273Syongari if (pktlen < (hlen + sizeof(struct tcphdr))) 516170273Syongari return; 517170273Syongari break; 518170273Syongari case IPPROTO_UDP: 519170273Syongari if (pktlen < (hlen + sizeof(struct udphdr))) 520170273Syongari return; 521170273Syongari uh = (struct udphdr *)((uint8_t *)ip + hlen); 522170273Syongari if (uh->uh_sum == 0) 523170273Syongari return; /* no checksum */ 524170273Syongari break; 525170273Syongari default: 526170273Syongari return; 527170273Syongari } 528170273Syongari 529170273Syongari cksum = ~(flags & GEM_RD_CHECKSUM); 530170273Syongari /* checksum fixup for IP options */ 531170273Syongari len = hlen - sizeof(struct ip); 532170273Syongari if (len > 0) { 533170273Syongari opts = (uint16_t *)(ip + 1); 534170273Syongari for (; len > 0; len -= sizeof(uint16_t), opts++) { 535170273Syongari temp32 = cksum - *opts; 536170273Syongari temp32 = (temp32 >> 16) + (temp32 & 65535); 537170273Syongari cksum = temp32 & 65535; 538170273Syongari } 539170273Syongari } 540170273Syongari m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 541170273Syongari m->m_pkthdr.csum_data = cksum; 542170273Syongari} 543170273Syongari 54491398Stmmstatic void 545174987Smariusgem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 54691398Stmm{ 547174987Smarius struct gem_softc *sc = xsc; 54891398Stmm 54991398Stmm if (error != 0) 55091398Stmm return; 551174987Smarius if (nsegs != 1) 552172334Smarius panic("%s: bad control buffer segment count", __func__); 55391398Stmm sc->sc_cddma = segs[0].ds_addr; 55491398Stmm} 55591398Stmm 55691398Stmmstatic void 557174987Smariusgem_tick(void *arg) 55891398Stmm{ 559170273Syongari struct gem_softc *sc = arg; 560194763Smarius struct ifnet *ifp = sc->sc_ifp; 561182060Smarius uint32_t v; 56291398Stmm 563170273Syongari GEM_LOCK_ASSERT(sc, MA_OWNED); 564170273Syongari 565108832Stmm /* 566182060Smarius * Unload collision and error counters. 567108832Stmm */ 568170273Syongari ifp->if_collisions += 569177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 570182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 571182060Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 572177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 573182060Smarius ifp->if_collisions += v; 574182060Smarius ifp->if_oerrors += v; 575182060Smarius ifp->if_ierrors += 576182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 577182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 578182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 579182060Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 58091398Stmm 58191398Stmm /* 582176996Smarius * Then clear the hardware counters. 58391398Stmm */ 584177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 585177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 586177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 587177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 588182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 589182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 590182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 591182060Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 592108832Stmm 59391398Stmm mii_tick(sc->sc_mii); 59491398Stmm 595164931Smarius if (gem_watchdog(sc) == EJUSTRETURN) 596164931Smarius return; 597164931Smarius 59891398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 59991398Stmm} 60091398Stmm 60191398Stmmstatic int 602177560Smariusgem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 603177560Smarius uint32_t set) 60491398Stmm{ 60591398Stmm int i; 606174987Smarius uint32_t reg; 60791398Stmm 608194763Smarius for (i = GEM_TRIES; i--; DELAY(100)) { 609177560Smarius reg = GEM_BANKN_READ_M(bank, 4, sc, r); 610170847Smarius if ((reg & clr) == 0 && (reg & set) == set) 61191398Stmm return (1); 61291398Stmm } 61391398Stmm return (0); 61491398Stmm} 61591398Stmm 616172334Smariusstatic void 617194763Smariusgem_reset(struct gem_softc *sc) 61891398Stmm{ 61991398Stmm 620115030Stmm#ifdef GEM_DEBUG 621170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 622115030Stmm#endif 62391398Stmm gem_reset_rx(sc); 62491398Stmm gem_reset_tx(sc); 62591398Stmm 626174987Smarius /* Do a full reset. */ 627177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 628179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 629179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 630177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 63191398Stmm device_printf(sc->sc_dev, "cannot reset device\n"); 63291398Stmm} 63391398Stmm 63491398Stmmstatic void 635174987Smariusgem_rxdrain(struct gem_softc *sc) 63691398Stmm{ 63791398Stmm struct gem_rxsoft *rxs; 63891398Stmm int i; 63991398Stmm 64091398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 64191398Stmm rxs = &sc->sc_rxsoft[i]; 64291398Stmm if (rxs->rxs_mbuf != NULL) { 643109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 644109648Stmm BUS_DMASYNC_POSTREAD); 645108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 64691398Stmm m_freem(rxs->rxs_mbuf); 64791398Stmm rxs->rxs_mbuf = NULL; 64891398Stmm } 64991398Stmm } 65091398Stmm} 65191398Stmm 65291398Stmmstatic void 653174987Smariusgem_stop(struct ifnet *ifp, int disable) 65491398Stmm{ 655174987Smarius struct gem_softc *sc = ifp->if_softc; 65691398Stmm struct gem_txsoft *txs; 65791398Stmm 658115030Stmm#ifdef GEM_DEBUG 659170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 660115030Stmm#endif 66191398Stmm 66291398Stmm callout_stop(&sc->sc_tick_ch); 663150285Smarius#ifdef GEM_RINT_TIMEOUT 664150285Smarius callout_stop(&sc->sc_rx_ch); 665172334Smarius#endif 66691398Stmm 667194763Smarius gem_reset_tx(sc); 668194763Smarius gem_reset_rx(sc); 66991398Stmm 67091398Stmm /* 67191398Stmm * Release any queued transmit buffers. 67291398Stmm */ 67391398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 67491398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 67591398Stmm if (txs->txs_ndescs != 0) { 676109648Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 677109648Stmm BUS_DMASYNC_POSTWRITE); 678108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 67991398Stmm if (txs->txs_mbuf != NULL) { 68091398Stmm m_freem(txs->txs_mbuf); 68191398Stmm txs->txs_mbuf = NULL; 68291398Stmm } 68391398Stmm } 68491398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 68591398Stmm } 68691398Stmm 68791398Stmm if (disable) 68891398Stmm gem_rxdrain(sc); 68991398Stmm 69091398Stmm /* 69191398Stmm * Mark the interface down and cancel the watchdog timer. 69291398Stmm */ 693148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 694172334Smarius sc->sc_flags &= ~GEM_LINK; 695164931Smarius sc->sc_wdog_timer = 0; 69691398Stmm} 69791398Stmm 698172334Smariusstatic int 699174987Smariusgem_reset_rx(struct gem_softc *sc) 70091398Stmm{ 70191398Stmm 70291398Stmm /* 70391398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 70491398Stmm * disable DMA first. 70591398Stmm */ 70691398Stmm gem_disable_rx(sc); 707177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 708179925Smarius GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 709179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 710177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 711172334Smarius device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 71291398Stmm 713176996Smarius /* Finally, reset the ERX. */ 714177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX); 715179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 716179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 717177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 718177560Smarius 0)) { 71991398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 72091398Stmm return (1); 72191398Stmm } 72291398Stmm return (0); 72391398Stmm} 72491398Stmm 725172334Smarius/* 726172334Smarius * Reset the receiver DMA engine. 727172334Smarius * 728172334Smarius * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 729172334Smarius * etc in order to reset the receiver DMA engine only and not do a full 730172334Smarius * reset which amongst others also downs the link and clears the FIFOs. 731172334Smarius */ 732172334Smariusstatic void 733172334Smariusgem_reset_rxdma(struct gem_softc *sc) 734172334Smarius{ 735172334Smarius int i; 73691398Stmm 737172334Smarius if (gem_reset_rx(sc) != 0) 738172334Smarius return (gem_init_locked(sc)); 739172334Smarius for (i = 0; i < GEM_NRXDESC; i++) 740172334Smarius if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 741172334Smarius GEM_UPDATE_RXDESC(sc, i); 742172334Smarius sc->sc_rxptr = 0; 743194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 744172334Smarius 745172334Smarius /* NOTE: we use only 32-bit DMA addresses here. */ 746177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 747177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 748177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 749177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 750174987Smarius gem_ringsize(GEM_NRXDESC /* XXX */) | 751172334Smarius ((ETHER_HDR_LEN + sizeof(struct ip)) << 752172334Smarius GEM_RX_CONFIG_CXM_START_SHFT) | 753172334Smarius (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 754194763Smarius (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 755194763Smarius /* Adjust for the SBus clock probably isn't worth the fuzz. */ 756177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 757194763Smarius ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 758194763Smarius GEM_RX_BLANKING_TIME_SHIFT) | 6); 759177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 760174987Smarius (3 * sc->sc_rxfifosize / 256) | 761174987Smarius ((sc->sc_rxfifosize / 256) << 12)); 762177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 763177560Smarius GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 764177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 765172334Smarius GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 766177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 767177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE); 768172334Smarius} 769172334Smarius 77091398Stmmstatic int 771174987Smariusgem_reset_tx(struct gem_softc *sc) 77291398Stmm{ 77391398Stmm 77491398Stmm /* 77591398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 77691398Stmm * disable DMA first. 77791398Stmm */ 77891398Stmm gem_disable_tx(sc); 779177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 780179925Smarius GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 781179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 782177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 783172334Smarius device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 78491398Stmm 785176996Smarius /* Finally, reset the ETX. */ 786177560Smarius GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX); 787179925Smarius GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 788179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 789177560Smarius if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 790177560Smarius 0)) { 791172334Smarius device_printf(sc->sc_dev, "cannot reset transmitter\n"); 79291398Stmm return (1); 79391398Stmm } 79491398Stmm return (0); 79591398Stmm} 79691398Stmm 79791398Stmmstatic int 798174987Smariusgem_disable_rx(struct gem_softc *sc) 79991398Stmm{ 80091398Stmm 801177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 802177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 803179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 804179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 805177560Smarius return (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 806177560Smarius 0)); 80791398Stmm} 80891398Stmm 80991398Stmmstatic int 810174987Smariusgem_disable_tx(struct gem_softc *sc) 81191398Stmm{ 81291398Stmm 813177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 814177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 815179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 816179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 817177560Smarius return (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 818177560Smarius 0)); 81991398Stmm} 82091398Stmm 82191398Stmmstatic int 822194763Smariusgem_meminit(struct gem_softc *sc) 82391398Stmm{ 82491398Stmm struct gem_rxsoft *rxs; 825174987Smarius int error, i; 82691398Stmm 827194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 828194763Smarius 82991398Stmm /* 83091398Stmm * Initialize the transmit descriptor ring. 83191398Stmm */ 83291398Stmm for (i = 0; i < GEM_NTXDESC; i++) { 83391398Stmm sc->sc_txdescs[i].gd_flags = 0; 83491398Stmm sc->sc_txdescs[i].gd_addr = 0; 83591398Stmm } 836108832Stmm sc->sc_txfree = GEM_MAXTXFREE; 83791398Stmm sc->sc_txnext = 0; 83899726Sbenno sc->sc_txwin = 0; 83991398Stmm 84091398Stmm /* 84191398Stmm * Initialize the receive descriptor and receive job 84291398Stmm * descriptor rings. 84391398Stmm */ 84491398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 84591398Stmm rxs = &sc->sc_rxsoft[i]; 84691398Stmm if (rxs->rxs_mbuf == NULL) { 84791398Stmm if ((error = gem_add_rxbuf(sc, i)) != 0) { 848174987Smarius device_printf(sc->sc_dev, 849174987Smarius "unable to allocate or map RX buffer %d, " 850174987Smarius "error = %d\n", i, error); 85191398Stmm /* 852174987Smarius * XXX we should attempt to run with fewer 853174987Smarius * receive buffers instead of just failing. 85491398Stmm */ 85591398Stmm gem_rxdrain(sc); 85691398Stmm return (1); 85791398Stmm } 85891398Stmm } else 85991398Stmm GEM_INIT_RXDESC(sc, i); 86091398Stmm } 86191398Stmm sc->sc_rxptr = 0; 86291398Stmm 863194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 864194763Smarius 86591398Stmm return (0); 86691398Stmm} 86791398Stmm 868172334Smariusstatic u_int 869174987Smariusgem_ringsize(u_int sz) 87091398Stmm{ 87191398Stmm 87291398Stmm switch (sz) { 87391398Stmm case 32: 874172334Smarius return (GEM_RING_SZ_32); 87591398Stmm case 64: 876172334Smarius return (GEM_RING_SZ_64); 87791398Stmm case 128: 878172334Smarius return (GEM_RING_SZ_128); 87991398Stmm case 256: 880172334Smarius return (GEM_RING_SZ_256); 88191398Stmm case 512: 882172334Smarius return (GEM_RING_SZ_512); 88391398Stmm case 1024: 884172334Smarius return (GEM_RING_SZ_1024); 88591398Stmm case 2048: 886172334Smarius return (GEM_RING_SZ_2048); 88791398Stmm case 4096: 888172334Smarius return (GEM_RING_SZ_4096); 88991398Stmm case 8192: 890172334Smarius return (GEM_RING_SZ_8192); 89191398Stmm default: 892172334Smarius printf("%s: invalid ring size %d\n", __func__, sz); 893172334Smarius return (GEM_RING_SZ_32); 89491398Stmm } 89591398Stmm} 89691398Stmm 897148369Smariusstatic void 898174987Smariusgem_init(void *xsc) 899148369Smarius{ 900174987Smarius struct gem_softc *sc = xsc; 901148369Smarius 902148369Smarius GEM_LOCK(sc); 903148369Smarius gem_init_locked(sc); 904148369Smarius GEM_UNLOCK(sc); 905148369Smarius} 906148369Smarius 90791398Stmm/* 90891398Stmm * Initialization of interface; set up initialization block 90991398Stmm * and transmit/receive descriptor rings. 91091398Stmm */ 91191398Stmmstatic void 912174987Smariusgem_init_locked(struct gem_softc *sc) 91391398Stmm{ 914147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 915174987Smarius uint32_t v; 91691398Stmm 917148369Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 91891398Stmm 919115030Stmm#ifdef GEM_DEBUG 920170273Syongari CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 921170273Syongari __func__); 922115030Stmm#endif 92391398Stmm /* 924174987Smarius * Initialization sequence. The numbered steps below correspond 92591398Stmm * to the sequence outlined in section 6.3.5.1 in the Ethernet 92691398Stmm * Channel Engine manual (part of the PCIO manual). 92791398Stmm * See also the STP2002-STQ document from Sun Microsystems. 92891398Stmm */ 92991398Stmm 930174987Smarius /* step 1 & 2. Reset the Ethernet Channel. */ 931179925Smarius gem_stop(ifp, 0); 93291398Stmm gem_reset(sc); 933115030Stmm#ifdef GEM_DEBUG 934170273Syongari CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 935170273Syongari __func__); 936115030Stmm#endif 93791398Stmm 938212725Smarius if ((sc->sc_flags & GEM_SERDES) == 0) 939212725Smarius /* Re-initialize the MIF. */ 940212725Smarius gem_mifinit(sc); 94191398Stmm 942174987Smarius /* step 3. Setup data structures in host memory. */ 943172334Smarius if (gem_meminit(sc) != 0) 944172334Smarius return; 94591398Stmm 946174987Smarius /* step 4. TX MAC registers & counters */ 94791398Stmm gem_init_regs(sc); 94891398Stmm 949174987Smarius /* step 5. RX MAC registers & counters */ 95091398Stmm gem_setladrf(sc); 95191398Stmm 952174987Smarius /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 95391398Stmm /* NOTE: we use only 32-bit DMA addresses here. */ 954177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 955177560Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 95691398Stmm 957177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 958177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 959115030Stmm#ifdef GEM_DEBUG 960174987Smarius CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 96191398Stmm GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 962115030Stmm#endif 96391398Stmm 964174987Smarius /* step 8. Global Configuration & Interrupt Mask */ 965194763Smarius 966194763Smarius /* 967194763Smarius * Set the internal arbitration to "infinite" bursts of the 968194763Smarius * maximum length of 31 * 64 bytes so DMA transfers aren't 969194763Smarius * split up in cache line size chunks. This greatly improves 970194763Smarius * RX performance. 971194763Smarius * Enable silicon bug workarounds for the Apple variants. 972194763Smarius */ 973194763Smarius GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 974194763Smarius GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 975194763Smarius ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 976194763Smarius GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 977194763Smarius GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 978194763Smarius 979177560Smarius GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 980172334Smarius ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 981172334Smarius GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 982172334Smarius GEM_INTR_BERR 983172334Smarius#ifdef GEM_DEBUG 984172334Smarius | GEM_INTR_PCS | GEM_INTR_MIF 985172334Smarius#endif 986172334Smarius )); 987177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 988172334Smarius GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 989177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 990194763Smarius GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 991194763Smarius GEM_MAC_TX_PEAK_EXP); 992172334Smarius#ifdef GEM_DEBUG 993177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 994172334Smarius ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 995172334Smarius#else 996177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 997172334Smarius GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 998172334Smarius#endif 99991398Stmm 1000174987Smarius /* step 9. ETX Configuration: use mostly default values. */ 100191398Stmm 1002174987Smarius /* Enable DMA. */ 1003194763Smarius v = gem_ringsize(GEM_NTXDESC); 1004194763Smarius /* Set TX FIFO threshold and enable DMA. */ 1005179925Smarius v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1006179925Smarius GEM_TX_CONFIG_TXFIFO_TH; 1007179925Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 100891398Stmm 1009174987Smarius /* step 10. ERX Configuration */ 101091398Stmm 1011172334Smarius /* Encode Receive Descriptor ring size. */ 1012174987Smarius v = gem_ringsize(GEM_NRXDESC /* XXX */); 1013174987Smarius /* RX TCP/UDP checksum offset */ 1014170273Syongari v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 1015170273Syongari GEM_RX_CONFIG_CXM_START_SHFT); 1016194763Smarius /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1017177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1018174987Smarius v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1019194763Smarius (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1020194763Smarius GEM_RX_CONFIG_RXDMA_EN); 1021172334Smarius 1022194763Smarius /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1023177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1024194763Smarius ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1025194763Smarius GEM_RX_BLANKING_TIME_SHIFT) | 6); 1026172334Smarius 102791398Stmm /* 102899726Sbenno * The following value is for an OFF Threshold of about 3/4 full 102999726Sbenno * and an ON Threshold of 1/4 full. 103091398Stmm */ 1031177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 103299726Sbenno (3 * sc->sc_rxfifosize / 256) | 1033174987Smarius ((sc->sc_rxfifosize / 256) << 12)); 103491398Stmm 1035174987Smarius /* step 11. Configure Media. */ 103691398Stmm 1037174987Smarius /* step 12. RX_MAC Configuration Register */ 1038177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1039179925Smarius v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1040177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 1041179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 1042179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1043177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 1044179925Smarius device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1045177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 104691398Stmm 1047194763Smarius /* step 13. TX_MAC Configuration Register */ 1048179925Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1049179925Smarius v |= GEM_MAC_TX_ENABLE; 1050179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 1051179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 1052179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1053179925Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 1054179925Smarius device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1055179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1056179925Smarius 1057174987Smarius /* step 14. Issue Transmit Pending command. */ 105891398Stmm 1059174987Smarius /* step 15. Give the reciever a swift kick. */ 1060177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 106191398Stmm 1062172334Smarius ifp->if_drv_flags |= IFF_DRV_RUNNING; 1063172334Smarius ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1064172334Smarius 1065172334Smarius mii_mediachg(sc->sc_mii); 1066172334Smarius 106791398Stmm /* Start the one second timer. */ 1068164931Smarius sc->sc_wdog_timer = 0; 106991398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 107091398Stmm} 107191398Stmm 107291398Stmmstatic int 1073174987Smariusgem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 107491398Stmm{ 1075174987Smarius bus_dma_segment_t txsegs[GEM_NTXSEGS]; 107691398Stmm struct gem_txsoft *txs; 1077179925Smarius struct ip *ip; 1078170273Syongari struct mbuf *m; 1079174987Smarius uint64_t cflags, flags; 1080179925Smarius int error, nexttx, nsegs, offset, seg; 108191398Stmm 1082194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1083194763Smarius 1084108832Stmm /* Get a work queue entry. */ 1085108832Stmm if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1086108832Stmm /* Ran out of descriptors. */ 1087170273Syongari return (ENOBUFS); 1088108832Stmm } 1089179925Smarius 1090179925Smarius cflags = 0; 1091179925Smarius if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1092179925Smarius if (M_WRITABLE(*m_head) == 0) { 1093179925Smarius m = m_dup(*m_head, M_DONTWAIT); 1094179925Smarius m_freem(*m_head); 1095179925Smarius *m_head = m; 1096179925Smarius if (m == NULL) 1097179925Smarius return (ENOBUFS); 1098179925Smarius } 1099179925Smarius offset = sizeof(struct ether_header); 1100179925Smarius m = m_pullup(*m_head, offset + sizeof(struct ip)); 1101179925Smarius if (m == NULL) { 1102179925Smarius *m_head = NULL; 1103179925Smarius return (ENOBUFS); 1104179925Smarius } 1105179925Smarius ip = (struct ip *)(mtod(m, caddr_t) + offset); 1106179925Smarius offset += (ip->ip_hl << 2); 1107179925Smarius cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1108179925Smarius ((offset + m->m_pkthdr.csum_data) << 1109179925Smarius GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1110179925Smarius *m_head = m; 1111179925Smarius } 1112179925Smarius 1113170273Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1114170273Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1115170273Syongari if (error == EFBIG) { 1116175418Sjhb m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 1117170273Syongari if (m == NULL) { 1118170273Syongari m_freem(*m_head); 1119170273Syongari *m_head = NULL; 1120170273Syongari return (ENOBUFS); 1121170273Syongari } 1122170273Syongari *m_head = m; 1123174987Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1124174987Smarius txs->txs_dmamap, *m_head, txsegs, &nsegs, 1125174987Smarius BUS_DMA_NOWAIT); 1126170273Syongari if (error != 0) { 1127170273Syongari m_freem(*m_head); 1128170273Syongari *m_head = NULL; 1129170273Syongari return (error); 1130170273Syongari } 1131170273Syongari } else if (error != 0) 1132170273Syongari return (error); 1133176996Smarius /* If nsegs is wrong then the stack is corrupt. */ 1134176996Smarius KASSERT(nsegs <= GEM_NTXSEGS, 1135176996Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1136170273Syongari if (nsegs == 0) { 1137170273Syongari m_freem(*m_head); 1138170273Syongari *m_head = NULL; 1139170273Syongari return (EIO); 1140170273Syongari } 1141170273Syongari 1142170273Syongari /* 1143170273Syongari * Ensure we have enough descriptors free to describe 1144170273Syongari * the packet. Note, we always reserve one descriptor 1145174987Smarius * at the end of the ring as a termination point, in 1146174987Smarius * order to prevent wrap-around. 1147170273Syongari */ 1148170273Syongari if (nsegs > sc->sc_txfree - 1) { 1149170273Syongari txs->txs_ndescs = 0; 1150170273Syongari bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1151170273Syongari return (ENOBUFS); 1152170273Syongari } 1153170273Syongari 1154170273Syongari txs->txs_ndescs = nsegs; 1155108832Stmm txs->txs_firstdesc = sc->sc_txnext; 1156170273Syongari nexttx = txs->txs_firstdesc; 1157170273Syongari for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1158172334Smarius#ifdef GEM_DEBUG 1159174987Smarius CTR6(KTR_GEM, 1160174987Smarius "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1161174987Smarius __func__, seg, nexttx, txsegs[seg].ds_len, 1162174987Smarius txsegs[seg].ds_addr, 1163170273Syongari GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1164170273Syongari#endif 1165170273Syongari sc->sc_txdescs[nexttx].gd_addr = 1166170273Syongari GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1167170273Syongari KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1168170273Syongari ("%s: segment size too large!", __func__)); 1169170273Syongari flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1170170273Syongari sc->sc_txdescs[nexttx].gd_flags = 1171170273Syongari GEM_DMA_WRITE(sc, flags | cflags); 1172170273Syongari txs->txs_lastdesc = nexttx; 117391398Stmm } 117491398Stmm 1175174987Smarius /* Set EOP on the last descriptor. */ 1176172334Smarius#ifdef GEM_DEBUG 1177174987Smarius CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1178174987Smarius __func__, seg, nexttx); 1179170273Syongari#endif 1180170273Syongari sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1181170273Syongari GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1182170273Syongari 1183174987Smarius /* Lastly set SOP on the first descriptor. */ 1184172334Smarius#ifdef GEM_DEBUG 1185174987Smarius CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1186174987Smarius __func__, seg, nexttx); 1187170273Syongari#endif 1188170273Syongari if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1189170273Syongari sc->sc_txwin = 0; 1190170273Syongari sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1191170273Syongari GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1192170273Syongari GEM_TD_START_OF_PACKET); 1193170273Syongari } else 1194170273Syongari sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1195170273Syongari GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1196170273Syongari 1197108832Stmm /* Sync the DMA map. */ 1198174987Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1199174987Smarius BUS_DMASYNC_PREWRITE); 120091398Stmm 1201115030Stmm#ifdef GEM_DEBUG 1202170273Syongari CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1203174987Smarius __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1204174987Smarius txs->txs_ndescs); 1205115030Stmm#endif 1206108832Stmm STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1207108832Stmm STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1208170273Syongari txs->txs_mbuf = *m_head; 120991398Stmm 1210108832Stmm sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1211108832Stmm sc->sc_txfree -= txs->txs_ndescs; 1212170273Syongari 1213108832Stmm return (0); 121491398Stmm} 121591398Stmm 121691398Stmmstatic void 1217174987Smariusgem_init_regs(struct gem_softc *sc) 121891398Stmm{ 1219152315Sru const u_char *laddr = IF_LLADDR(sc->sc_ifp); 122091398Stmm 1221194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1222194763Smarius 1223174987Smarius /* These registers are not cleared on reset. */ 1224172334Smarius if ((sc->sc_flags & GEM_INITED) == 0) { 1225174987Smarius /* magic values */ 1226177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1227177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1228177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 122991398Stmm 1230194763Smarius /* min frame length */ 1231177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1232194763Smarius /* max frame length and max burst size */ 1233177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1234172334Smarius (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 123599726Sbenno 1236194763Smarius /* more magic values */ 1237177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1238177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1239177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1240177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8088); 1241194763Smarius 1242194763Smarius /* random number seed */ 1243177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1244174987Smarius ((laddr[5] << 8) | laddr[4]) & 0x3ff); 124599726Sbenno 1246174987Smarius /* secondary MAC address: 0:0:0:0:0:0 */ 1247177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1248177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1249177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 125099726Sbenno 1251174987Smarius /* MAC control address: 01:80:c2:00:00:01 */ 1252177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1253177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1254177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 125591398Stmm 1256174987Smarius /* MAC filter address: 0:0:0:0:0:0 */ 1257177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1258177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1259177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1260177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1261177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 126291398Stmm 1263172334Smarius sc->sc_flags |= GEM_INITED; 126491398Stmm } 126591398Stmm 1266174987Smarius /* Counters need to be zeroed. */ 1267177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1268177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1269177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1270177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1271177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1272177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1273177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1274177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1275177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1276177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1277177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 127891398Stmm 1279172334Smarius /* Set XOFF PAUSE time. */ 1280177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 128191398Stmm 1282174987Smarius /* Set the station address. */ 1283177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1284177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1285177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 128699726Sbenno 1287172334Smarius /* Enable MII outputs. */ 1288177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 128991398Stmm} 129091398Stmm 129191398Stmmstatic void 1292174987Smariusgem_start(struct ifnet *ifp) 129391398Stmm{ 1294174987Smarius struct gem_softc *sc = ifp->if_softc; 1295148369Smarius 1296148369Smarius GEM_LOCK(sc); 1297148369Smarius gem_start_locked(ifp); 1298148369Smarius GEM_UNLOCK(sc); 1299148369Smarius} 1300148369Smarius 1301194763Smariusstatic inline void 1302194763Smariusgem_txkick(struct gem_softc *sc) 1303194763Smarius{ 1304194763Smarius 1305194763Smarius /* 1306194763Smarius * Update the TX kick register. This register has to point to the 1307194763Smarius * descriptor after the last valid one and for optimum performance 1308194763Smarius * should be incremented in multiples of 4 (the DMA engine fetches/ 1309194763Smarius * updates descriptors in batches of 4). 1310194763Smarius */ 1311194763Smarius#ifdef GEM_DEBUG 1312194763Smarius CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1313194763Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1314194763Smarius#endif 1315194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1316194763Smarius GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1317194763Smarius} 1318194763Smarius 1319148369Smariusstatic void 1320174987Smariusgem_start_locked(struct ifnet *ifp) 1321148369Smarius{ 1322174987Smarius struct gem_softc *sc = ifp->if_softc; 1323170273Syongari struct mbuf *m; 1324194763Smarius int kicked, ntx; 132591398Stmm 1326194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1327194763Smarius 1328148887Srwatson if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1329172334Smarius IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 133091398Stmm return; 133191398Stmm 1332115030Stmm#ifdef GEM_DEBUG 1333170273Syongari CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1334172334Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1335172334Smarius sc->sc_txnext); 1336115030Stmm#endif 1337174987Smarius ntx = 0; 1338194763Smarius kicked = 0; 1339170273Syongari for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1340170273Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1341170273Syongari if (m == NULL) 134291398Stmm break; 1343172334Smarius if (gem_load_txmbuf(sc, &m) != 0) { 1344170273Syongari if (m == NULL) 1345170273Syongari break; 1346170273Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1347170273Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m); 134891398Stmm break; 134991398Stmm } 1350194763Smarius if ((sc->sc_txnext % 4) == 0) { 1351194763Smarius gem_txkick(sc); 1352194763Smarius kicked = 1; 1353194763Smarius } else 1354194763Smarius kicked = 0; 1355115030Stmm ntx++; 1356170273Syongari BPF_MTAP(ifp, m); 135791398Stmm } 135891398Stmm 135991398Stmm if (ntx > 0) { 1360194763Smarius if (kicked == 0) 1361194763Smarius gem_txkick(sc); 1362115030Stmm#ifdef GEM_DEBUG 1363108832Stmm CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1364172334Smarius device_get_name(sc->sc_dev), sc->sc_txnext); 1365115030Stmm#endif 136691398Stmm 136791398Stmm /* Set a watchdog timer in case the chip flakes out. */ 1368164931Smarius sc->sc_wdog_timer = 5; 1369115030Stmm#ifdef GEM_DEBUG 1370170273Syongari CTR3(KTR_GEM, "%s: %s: watchdog %d", 1371174987Smarius device_get_name(sc->sc_dev), __func__, 1372174987Smarius sc->sc_wdog_timer); 1373115030Stmm#endif 137491398Stmm } 137591398Stmm} 137691398Stmm 137791398Stmmstatic void 1378174987Smariusgem_tint(struct gem_softc *sc) 137991398Stmm{ 1380147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 138191398Stmm struct gem_txsoft *txs; 1382194763Smarius int progress; 1383194763Smarius uint32_t txlast; 1384174987Smarius#ifdef GEM_DEBUG 1385174987Smarius int i; 138691398Stmm 1387194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1388194763Smarius 1389170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1390115030Stmm#endif 139191398Stmm 139291398Stmm /* 1393174987Smarius * Go through our TX list and free mbufs for those 139491398Stmm * frames that have been transmitted. 139591398Stmm */ 1396174987Smarius progress = 0; 1397109648Stmm GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 139891398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 139991398Stmm#ifdef GEM_DEBUG 1400174987Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 140191398Stmm printf(" txsoft %p transmit chain:\n", txs); 140291398Stmm for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 140391398Stmm printf("descriptor %d: ", i); 1404174987Smarius printf("gd_flags: 0x%016llx\t", 1405174987Smarius (long long)GEM_DMA_READ(sc, 1406174987Smarius sc->sc_txdescs[i].gd_flags)); 1407174987Smarius printf("gd_addr: 0x%016llx\n", 1408174987Smarius (long long)GEM_DMA_READ(sc, 1409174987Smarius sc->sc_txdescs[i].gd_addr)); 141091398Stmm if (i == txs->txs_lastdesc) 141191398Stmm break; 141291398Stmm } 141391398Stmm } 141491398Stmm#endif 141591398Stmm 141691398Stmm /* 1417172334Smarius * In theory, we could harvest some descriptors before 141891398Stmm * the ring is empty, but that's a bit complicated. 141991398Stmm * 142091398Stmm * GEM_TX_COMPLETION points to the last descriptor 1421174987Smarius * processed + 1. 142291398Stmm */ 1423177560Smarius txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1424115030Stmm#ifdef GEM_DEBUG 1425170273Syongari CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 142691398Stmm "txs->txs_lastdesc = %d, txlast = %d", 1427170273Syongari __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1428115030Stmm#endif 142991398Stmm if (txs->txs_firstdesc <= txs->txs_lastdesc) { 143091398Stmm if ((txlast >= txs->txs_firstdesc) && 1431174987Smarius (txlast <= txs->txs_lastdesc)) 143291398Stmm break; 143391398Stmm } else { 1434174987Smarius /* Ick -- this command wraps. */ 143591398Stmm if ((txlast >= txs->txs_firstdesc) || 1436174987Smarius (txlast <= txs->txs_lastdesc)) 143791398Stmm break; 143891398Stmm } 143991398Stmm 1440115030Stmm#ifdef GEM_DEBUG 1441174987Smarius CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1442115030Stmm#endif 144391398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 144491398Stmm 144591398Stmm sc->sc_txfree += txs->txs_ndescs; 144691398Stmm 1447108832Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 144891398Stmm BUS_DMASYNC_POSTWRITE); 1449108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 145091398Stmm if (txs->txs_mbuf != NULL) { 145191398Stmm m_freem(txs->txs_mbuf); 145291398Stmm txs->txs_mbuf = NULL; 145391398Stmm } 145491398Stmm 145591398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 145691398Stmm 145791398Stmm ifp->if_opackets++; 145899726Sbenno progress = 1; 145991398Stmm } 146091398Stmm 1461115030Stmm#ifdef GEM_DEBUG 1462174987Smarius CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1463172334Smarius "GEM_TX_COMPLETION %x", 1464177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1465177560Smarius ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1466177560Smarius GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1467177560Smarius GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1468115030Stmm#endif 146991398Stmm 147099726Sbenno if (progress) { 147199726Sbenno if (sc->sc_txfree == GEM_NTXDESC - 1) 147299726Sbenno sc->sc_txwin = 0; 147391398Stmm 1474174987Smarius /* 1475174987Smarius * We freed some descriptors, so reset IFF_DRV_OACTIVE 1476174987Smarius * and restart. 1477174987Smarius */ 1478148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1479194763Smarius if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1480194763Smarius sc->sc_wdog_timer = 0; 1481179925Smarius gem_start_locked(ifp); 148299726Sbenno } 148399726Sbenno 1484115030Stmm#ifdef GEM_DEBUG 1485170273Syongari CTR3(KTR_GEM, "%s: %s: watchdog %d", 1486170273Syongari device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1487115030Stmm#endif 148891398Stmm} 148991398Stmm 1490148368Smarius#ifdef GEM_RINT_TIMEOUT 149193045Stmmstatic void 1492174987Smariusgem_rint_timeout(void *arg) 149393045Stmm{ 1494174987Smarius struct gem_softc *sc = arg; 149593045Stmm 1496150285Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1497194763Smarius 1498148369Smarius gem_rint(sc); 149993045Stmm} 1500100587Sjake#endif 150193045Stmm 150291398Stmmstatic void 1503174987Smariusgem_rint(struct gem_softc *sc) 150491398Stmm{ 1505147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 150691398Stmm struct mbuf *m; 1507174987Smarius uint64_t rxstat; 1508174987Smarius uint32_t rxcomp; 150991398Stmm 1510194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1511194763Smarius 1512148368Smarius#ifdef GEM_RINT_TIMEOUT 151393045Stmm callout_stop(&sc->sc_rx_ch); 1514148368Smarius#endif 1515115030Stmm#ifdef GEM_DEBUG 1516170273Syongari CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1517115030Stmm#endif 151899726Sbenno 151991398Stmm /* 152099726Sbenno * Read the completion register once. This limits 152199726Sbenno * how long the following loop can execute. 152299726Sbenno */ 1523177560Smarius rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1524115030Stmm#ifdef GEM_DEBUG 1525194763Smarius CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1526170273Syongari __func__, sc->sc_rxptr, rxcomp); 1527115030Stmm#endif 1528194763Smarius GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1529172334Smarius for (; sc->sc_rxptr != rxcomp;) { 1530172334Smarius m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1531172334Smarius rxstat = GEM_DMA_READ(sc, 1532172334Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 153391398Stmm 153491398Stmm if (rxstat & GEM_RD_OWN) { 1535148368Smarius#ifdef GEM_RINT_TIMEOUT 153691398Stmm /* 153793045Stmm * The descriptor is still marked as owned, although 1538174987Smarius * it is supposed to have completed. This has been 1539174987Smarius * observed on some machines. Just exiting here 154093045Stmm * might leave the packet sitting around until another 154193045Stmm * one arrives to trigger a new interrupt, which is 154293045Stmm * generally undesirable, so set up a timeout. 154391398Stmm */ 154493045Stmm callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 154593045Stmm gem_rint_timeout, sc); 154699726Sbenno#endif 1547172334Smarius m = NULL; 1548172334Smarius goto kickit; 154991398Stmm } 155091398Stmm 155191398Stmm if (rxstat & GEM_RD_BAD_CRC) { 155299726Sbenno ifp->if_ierrors++; 155391398Stmm device_printf(sc->sc_dev, "receive error: CRC error\n"); 1554172334Smarius GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1555172334Smarius m = NULL; 1556172334Smarius goto kickit; 155791398Stmm } 155891398Stmm 155991398Stmm#ifdef GEM_DEBUG 1560174987Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 1561172334Smarius printf(" rxsoft %p descriptor %d: ", 1562172334Smarius &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1563174987Smarius printf("gd_flags: 0x%016llx\t", 1564174987Smarius (long long)GEM_DMA_READ(sc, 1565174987Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1566174987Smarius printf("gd_addr: 0x%016llx\n", 1567174987Smarius (long long)GEM_DMA_READ(sc, 1568174987Smarius sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 156991398Stmm } 157091398Stmm#endif 157191398Stmm 157291398Stmm /* 157391398Stmm * Allocate a new mbuf cluster. If that fails, we are 157491398Stmm * out of memory, and must drop the packet and recycle 157591398Stmm * the buffer that's already attached to this descriptor. 157691398Stmm */ 1577172334Smarius if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 157891398Stmm ifp->if_ierrors++; 1579172334Smarius GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1580172334Smarius m = NULL; 1581172334Smarius } 1582172334Smarius 1583174987Smarius kickit: 1584174987Smarius /* 1585174987Smarius * Update the RX kick register. This register has to point 1586172334Smarius * to the descriptor after the last valid one (before the 1587194763Smarius * current batch) and for optimum performance should be 1588194763Smarius * incremented in multiples of 4 (the DMA engine fetches/ 1589194763Smarius * updates descriptors in batches of 4). 1590172334Smarius */ 1591172334Smarius sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1592172334Smarius if ((sc->sc_rxptr % 4) == 0) { 1593179925Smarius GEM_CDSYNC(sc, 1594179925Smarius BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1595177560Smarius GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1596172334Smarius (sc->sc_rxptr + GEM_NRXDESC - 4) & 1597172334Smarius GEM_NRXDESC_MASK); 1598172334Smarius } 1599172334Smarius 1600172334Smarius if (m == NULL) { 1601172334Smarius if (rxstat & GEM_RD_OWN) 1602172334Smarius break; 160391398Stmm continue; 160491398Stmm } 1605172334Smarius 1606172334Smarius ifp->if_ipackets++; 1607194763Smarius m->m_data += ETHER_ALIGN; /* first byte offset */ 160891398Stmm m->m_pkthdr.rcvif = ifp; 1609172334Smarius m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 161091398Stmm 1611170273Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1612170273Syongari gem_rxcksum(m, rxstat); 1613170273Syongari 161491398Stmm /* Pass it on. */ 1615148369Smarius GEM_UNLOCK(sc); 1616106937Ssam (*ifp->if_input)(ifp, m); 1617148369Smarius GEM_LOCK(sc); 161891398Stmm } 161991398Stmm 1620115030Stmm#ifdef GEM_DEBUG 1621194763Smarius CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1622177560Smarius sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1623115030Stmm#endif 162491398Stmm} 162591398Stmm 162691398Stmmstatic int 1627174987Smariusgem_add_rxbuf(struct gem_softc *sc, int idx) 162891398Stmm{ 162991398Stmm struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 163091398Stmm struct mbuf *m; 1631148368Smarius bus_dma_segment_t segs[1]; 1632148368Smarius int error, nsegs; 163391398Stmm 1634194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1635194763Smarius 1636111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 163791398Stmm if (m == NULL) 163891398Stmm return (ENOBUFS); 1639108832Stmm m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 164091398Stmm 164191398Stmm#ifdef GEM_DEBUG 1642174987Smarius /* Bzero the packet to check DMA. */ 164391398Stmm memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 164491398Stmm#endif 164591398Stmm 1646109648Stmm if (rxs->rxs_mbuf != NULL) { 1647109648Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1648109648Stmm BUS_DMASYNC_POSTREAD); 1649108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1650109648Stmm } 165191398Stmm 1652148368Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1653148368Smarius m, segs, &nsegs, BUS_DMA_NOWAIT); 1654148368Smarius if (error != 0) { 1655174987Smarius device_printf(sc->sc_dev, 1656174987Smarius "cannot load RS DMA map %d, error = %d\n", idx, error); 1657148368Smarius m_freem(m); 1658172334Smarius return (error); 165991398Stmm } 1660174987Smarius /* If nsegs is wrong then the stack is corrupt. */ 1661176996Smarius KASSERT(nsegs == 1, 1662176996Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1663172334Smarius rxs->rxs_mbuf = m; 1664148368Smarius rxs->rxs_paddr = segs[0].ds_addr; 166591398Stmm 1666174987Smarius bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1667174987Smarius BUS_DMASYNC_PREREAD); 166891398Stmm 166991398Stmm GEM_INIT_RXDESC(sc, idx); 167091398Stmm 167191398Stmm return (0); 167291398Stmm} 167391398Stmm 167491398Stmmstatic void 1675174987Smariusgem_eint(struct gem_softc *sc, u_int status) 167691398Stmm{ 167791398Stmm 1678172334Smarius sc->sc_ifp->if_ierrors++; 1679172334Smarius if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1680172334Smarius gem_reset_rxdma(sc); 168191398Stmm return; 168291398Stmm } 168391398Stmm 1684194763Smarius device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1685194763Smarius if ((status & GEM_INTR_BERR) != 0) { 1686194763Smarius if ((sc->sc_flags & GEM_PCI) != 0) 1687194763Smarius printf(", PCI bus error 0x%x\n", 1688194763Smarius GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1689194763Smarius else 1690194763Smarius printf(", SBus error 0x%x\n", 1691194763Smarius GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1692194763Smarius } 169391398Stmm} 169491398Stmm 169591398Stmmvoid 1696174987Smariusgem_intr(void *v) 169791398Stmm{ 1698174987Smarius struct gem_softc *sc = v; 1699172334Smarius uint32_t status, status2; 170091398Stmm 1701148369Smarius GEM_LOCK(sc); 1702177560Smarius status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1703172334Smarius 1704115030Stmm#ifdef GEM_DEBUG 1705170273Syongari CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1706194763Smarius device_get_name(sc->sc_dev), __func__, 1707194763Smarius (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1708172334Smarius 1709172334Smarius /* 1710172334Smarius * PCS interrupts must be cleared, otherwise no traffic is passed! 1711172334Smarius */ 1712172334Smarius if ((status & GEM_INTR_PCS) != 0) { 1713174987Smarius status2 = 1714177560Smarius GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1715177560Smarius GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1716172334Smarius if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1717172334Smarius device_printf(sc->sc_dev, 1718172334Smarius "%s: PCS link status changed\n", __func__); 1719172334Smarius } 1720172334Smarius if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1721177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1722172334Smarius if ((status2 & GEM_MAC_PAUSED) != 0) 1723172334Smarius device_printf(sc->sc_dev, 1724172334Smarius "%s: PAUSE received (PAUSE time %d slots)\n", 1725172334Smarius __func__, GEM_MAC_PAUSE_TIME(status2)); 1726172334Smarius if ((status2 & GEM_MAC_PAUSE) != 0) 1727172334Smarius device_printf(sc->sc_dev, 1728172334Smarius "%s: transited to PAUSE state\n", __func__); 1729172334Smarius if ((status2 & GEM_MAC_RESUME) != 0) 1730172334Smarius device_printf(sc->sc_dev, 1731172334Smarius "%s: transited to non-PAUSE state\n", __func__); 1732172334Smarius } 1733172334Smarius if ((status & GEM_INTR_MIF) != 0) 1734172334Smarius device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1735115030Stmm#endif 173691398Stmm 1737194763Smarius if (__predict_false(status & 1738172334Smarius (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 173991398Stmm gem_eint(sc, status); 174091398Stmm 1741172334Smarius if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1742172334Smarius gem_rint(sc); 1743172334Smarius 174491398Stmm if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 174591398Stmm gem_tint(sc); 174691398Stmm 1747194763Smarius if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1748177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1749174987Smarius if ((status2 & 1750194763Smarius ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1751194763Smarius GEM_MAC_TX_PEAK_EXP)) != 0) 1752174987Smarius device_printf(sc->sc_dev, 1753174987Smarius "MAC TX fault, status %x\n", status2); 1754174987Smarius if ((status2 & 1755194763Smarius (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1756194763Smarius sc->sc_ifp->if_oerrors++; 1757148369Smarius gem_init_locked(sc); 1758194763Smarius } 175991398Stmm } 1760194763Smarius if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1761177560Smarius status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1762149552Smarius /* 1763172334Smarius * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1764172334Smarius * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1765174987Smarius * silicon bug so handle them silently. Moreover, it's 1766172334Smarius * likely that the receiver has hung so we reset it. 1767149552Smarius */ 1768174987Smarius if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1769172334Smarius sc->sc_ifp->if_ierrors++; 1770172334Smarius gem_reset_rxdma(sc); 1771174987Smarius } else if ((status2 & 1772174987Smarius ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1773174987Smarius device_printf(sc->sc_dev, 1774174987Smarius "MAC RX fault, status %x\n", status2); 177591398Stmm } 1776148369Smarius GEM_UNLOCK(sc); 177791398Stmm} 177891398Stmm 1779164931Smariusstatic int 1780174987Smariusgem_watchdog(struct gem_softc *sc) 178191398Stmm{ 1782179925Smarius struct ifnet *ifp = sc->sc_ifp; 178391398Stmm 1784164931Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1785164931Smarius 1786115030Stmm#ifdef GEM_DEBUG 1787174987Smarius CTR4(KTR_GEM, 1788174987Smarius "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1789177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1790177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1791177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1792174987Smarius CTR4(KTR_GEM, 1793174987Smarius "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1794177560Smarius __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1795177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1796177560Smarius GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1797115030Stmm#endif 179891398Stmm 1799164931Smarius if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1800164931Smarius return (0); 1801164931Smarius 1802172334Smarius if ((sc->sc_flags & GEM_LINK) != 0) 1803172334Smarius device_printf(sc->sc_dev, "device timeout\n"); 1804172334Smarius else if (bootverbose) 1805172334Smarius device_printf(sc->sc_dev, "device timeout (no link)\n"); 1806179925Smarius ++ifp->if_oerrors; 180791398Stmm 180891398Stmm /* Try to get more packets going. */ 1809148369Smarius gem_init_locked(sc); 1810179925Smarius gem_start_locked(ifp); 1811164931Smarius return (EJUSTRETURN); 181291398Stmm} 181391398Stmm 181491398Stmmstatic void 1815174987Smariusgem_mifinit(struct gem_softc *sc) 181691398Stmm{ 181791398Stmm 1818176996Smarius /* Configure the MIF in frame mode. */ 1819177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1820177560Smarius GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1821212725Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 1822212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 182391398Stmm} 182491398Stmm 182591398Stmm/* 182691398Stmm * MII interface 182791398Stmm * 1828182060Smarius * The MII interface supports at least three different operating modes: 182991398Stmm * 183091398Stmm * Bitbang mode is implemented using data, clock and output enable registers. 183191398Stmm * 183291398Stmm * Frame mode is implemented by loading a complete frame into the frame 183391398Stmm * register and polling the valid bit for completion. 183491398Stmm * 183591398Stmm * Polling mode uses the frame register but completion is indicated by 183691398Stmm * an interrupt. 183791398Stmm * 183891398Stmm */ 183991398Stmmint 1840174987Smariusgem_mii_readreg(device_t dev, int phy, int reg) 184191398Stmm{ 1842174987Smarius struct gem_softc *sc; 184391398Stmm int n; 1844174987Smarius uint32_t v; 184591398Stmm 184691398Stmm#ifdef GEM_DEBUG_PHY 1847172334Smarius printf("%s: phy %d reg %d\n", __func__, phy, reg); 184891398Stmm#endif 184991398Stmm 1850174987Smarius sc = device_get_softc(dev); 1851172334Smarius if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 1852172334Smarius return (0); 185391398Stmm 1854172334Smarius if ((sc->sc_flags & GEM_SERDES) != 0) { 1855172334Smarius switch (reg) { 1856172334Smarius case MII_BMCR: 1857172334Smarius reg = GEM_MII_CONTROL; 1858172334Smarius break; 1859172334Smarius case MII_BMSR: 1860172334Smarius reg = GEM_MII_STATUS; 1861172334Smarius break; 1862172334Smarius case MII_PHYIDR1: 1863172334Smarius case MII_PHYIDR2: 1864172334Smarius return (0); 1865172334Smarius case MII_ANAR: 1866172334Smarius reg = GEM_MII_ANAR; 1867172334Smarius break; 1868172334Smarius case MII_ANLPAR: 1869172334Smarius reg = GEM_MII_ANLPAR; 1870172334Smarius break; 1871172334Smarius case MII_EXTSR: 1872172334Smarius return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1873172334Smarius default: 1874172334Smarius device_printf(sc->sc_dev, 1875172334Smarius "%s: unhandled register %d\n", __func__, reg); 1876172334Smarius return (0); 1877172334Smarius } 1878177560Smarius return (GEM_BANK1_READ_4(sc, reg)); 1879172334Smarius } 1880172334Smarius 1881174987Smarius /* Construct the frame command. */ 1882172334Smarius v = GEM_MIF_FRAME_READ | 1883172334Smarius (phy << GEM_MIF_PHY_SHIFT) | 1884172334Smarius (reg << GEM_MIF_REG_SHIFT); 188591398Stmm 1886177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1887179925Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1888179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 188991398Stmm for (n = 0; n < 100; n++) { 189091398Stmm DELAY(1); 1891177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1892150285Smarius if (v & GEM_MIF_FRAME_TA0) 189391398Stmm return (v & GEM_MIF_FRAME_DATA); 189491398Stmm } 189591398Stmm 1896174987Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 189791398Stmm return (0); 189891398Stmm} 189991398Stmm 190091398Stmmint 1901174987Smariusgem_mii_writereg(device_t dev, int phy, int reg, int val) 190291398Stmm{ 1903174987Smarius struct gem_softc *sc; 190491398Stmm int n; 1905174987Smarius uint32_t v; 190691398Stmm 190791398Stmm#ifdef GEM_DEBUG_PHY 1908172334Smarius printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 190991398Stmm#endif 191091398Stmm 1911174987Smarius sc = device_get_softc(dev); 1912172334Smarius if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 1913172334Smarius return (0); 1914172334Smarius 1915172334Smarius if ((sc->sc_flags & GEM_SERDES) != 0) { 1916172334Smarius switch (reg) { 1917172334Smarius case MII_BMSR: 1918172334Smarius reg = GEM_MII_STATUS; 1919172334Smarius break; 1920179925Smarius case MII_BMCR: 1921179925Smarius reg = GEM_MII_CONTROL; 1922179925Smarius if ((val & GEM_MII_CONTROL_RESET) == 0) 1923179925Smarius break; 1924179925Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1925179925Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1926179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1927179925Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1928179925Smarius GEM_MII_CONTROL_RESET, 0)) 1929179925Smarius device_printf(sc->sc_dev, 1930179925Smarius "cannot reset PCS\n"); 1931179925Smarius /* FALLTHROUGH */ 1932172334Smarius case MII_ANAR: 1933177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1934177560Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1935172334Smarius BUS_SPACE_BARRIER_WRITE); 1936177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1937212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 1938212725Smarius BUS_SPACE_BARRIER_WRITE); 1939177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1940172334Smarius GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1941212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 1942212725Smarius BUS_SPACE_BARRIER_WRITE); 1943177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1944172334Smarius GEM_MII_CONFIG_ENABLE); 1945212725Smarius GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1946212725Smarius BUS_SPACE_BARRIER_WRITE); 1947172334Smarius return (0); 1948172334Smarius case MII_ANLPAR: 1949172334Smarius reg = GEM_MII_ANLPAR; 1950172334Smarius break; 1951172334Smarius default: 1952172334Smarius device_printf(sc->sc_dev, 1953172334Smarius "%s: unhandled register %d\n", __func__, reg); 1954172334Smarius return (0); 1955172334Smarius } 1956177560Smarius GEM_BANK1_WRITE_4(sc, reg, val); 1957212725Smarius GEM_BANK1_BARRIER(sc, reg, 4, 1958212725Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1959172334Smarius return (0); 1960172334Smarius } 1961172334Smarius 1962174987Smarius /* Construct the frame command. */ 1963172334Smarius v = GEM_MIF_FRAME_WRITE | 1964172334Smarius (phy << GEM_MIF_PHY_SHIFT) | 1965172334Smarius (reg << GEM_MIF_REG_SHIFT) | 196691398Stmm (val & GEM_MIF_FRAME_DATA); 196791398Stmm 1968177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1969179925Smarius GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1970179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 197191398Stmm for (n = 0; n < 100; n++) { 197291398Stmm DELAY(1); 1973177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1974150285Smarius if (v & GEM_MIF_FRAME_TA0) 197591398Stmm return (1); 197691398Stmm } 197791398Stmm 1978174987Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 197991398Stmm return (0); 198091398Stmm} 198191398Stmm 198291398Stmmvoid 1983174987Smariusgem_mii_statchg(device_t dev) 198491398Stmm{ 1985174987Smarius struct gem_softc *sc; 1986172334Smarius int gigabit; 1987172334Smarius uint32_t rxcfg, txcfg, v; 198891398Stmm 1989174987Smarius sc = device_get_softc(dev); 1990174987Smarius 1991194763Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 1992194763Smarius 199391398Stmm#ifdef GEM_DEBUG 1994174987Smarius if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 1995172334Smarius device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", 1996172334Smarius __func__, sc->sc_phyad); 199791398Stmm#endif 199891398Stmm 1999172334Smarius if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2000172334Smarius IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2001172334Smarius sc->sc_flags |= GEM_LINK; 2002172334Smarius else 2003172334Smarius sc->sc_flags &= ~GEM_LINK; 2004172334Smarius 2005172334Smarius switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2006172334Smarius case IFM_1000_SX: 2007172334Smarius case IFM_1000_LX: 2008172334Smarius case IFM_1000_CX: 2009172334Smarius case IFM_1000_T: 2010172334Smarius gigabit = 1; 2011172334Smarius break; 2012172334Smarius default: 2013172334Smarius gigabit = 0; 201491398Stmm } 201591398Stmm 2016172334Smarius /* 2017172334Smarius * The configuration done here corresponds to the steps F) and 2018172334Smarius * G) and as far as enabling of RX and TX MAC goes also step H) 2019172334Smarius * of the initialization sequence outlined in section 3.2.1 of 2020172334Smarius * the GEM Gigabit Ethernet ASIC Specification. 2021172334Smarius */ 2022172334Smarius 2023177560Smarius rxcfg = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 2024172334Smarius rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2025172334Smarius txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2026172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2027172334Smarius txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2028172334Smarius else if (gigabit != 0) { 2029172334Smarius rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2030172334Smarius txcfg |= GEM_MAC_TX_CARR_EXTEND; 2031172334Smarius } 2032177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 0); 2033179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 2034179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2035177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2036172334Smarius device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2037177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2038177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 0); 2039179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2040179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2041177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2042172334Smarius device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2043177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2044172334Smarius 2045177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2046172334Smarius ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2047172334Smarius#ifdef notyet 2048174987Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2049174987Smarius IFM_ETH_RXPAUSE) != 0) 2050172334Smarius v |= GEM_MAC_CC_RX_PAUSE; 2051174987Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2052174987Smarius IFM_ETH_TXPAUSE) != 0) 2053172334Smarius v |= GEM_MAC_CC_TX_PAUSE; 2054172334Smarius#endif 2055177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2056172334Smarius 2057172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2058172334Smarius gigabit != 0) 2059177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2060172334Smarius GEM_MAC_SLOT_TIME_CARR_EXTEND); 2061172334Smarius else 2062177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2063172334Smarius GEM_MAC_SLOT_TIME_NORMAL); 2064172334Smarius 206591398Stmm /* XIF Configuration */ 206691398Stmm v = GEM_MAC_XIF_LINK_LED; 206791398Stmm v |= GEM_MAC_XIF_TX_MII_ENA; 2068172334Smarius if ((sc->sc_flags & GEM_SERDES) == 0) { 2069177560Smarius if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2070182060Smarius GEM_MIF_CONFIG_PHY_SEL) != 0) { 2071172334Smarius /* External MII needs echo disable if half duplex. */ 2072194763Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2073182060Smarius IFM_FDX) == 0) 2074182060Smarius v |= GEM_MAC_XIF_ECHO_DISABL; 2075182060Smarius } else 2076172334Smarius /* 2077172334Smarius * Internal MII needs buffer enable. 2078172334Smarius * XXX buffer enable makes only sense for an 2079172334Smarius * external PHY. 2080172334Smarius */ 2081172334Smarius v |= GEM_MAC_XIF_MII_BUF_ENA; 2082172334Smarius } 2083172334Smarius if (gigabit != 0) 2084172334Smarius v |= GEM_MAC_XIF_GMII_MODE; 2085172334Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2086172334Smarius v |= GEM_MAC_XIF_FDPLX_LED; 2087177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 208899726Sbenno 2089172334Smarius if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2090172334Smarius (sc->sc_flags & GEM_LINK) != 0) { 2091177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2092172334Smarius txcfg | GEM_MAC_TX_ENABLE); 2093177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2094172334Smarius rxcfg | GEM_MAC_RX_ENABLE); 209591398Stmm } 209691398Stmm} 209791398Stmm 209891398Stmmint 2099174987Smariusgem_mediachange(struct ifnet *ifp) 210091398Stmm{ 210191398Stmm struct gem_softc *sc = ifp->if_softc; 2102150285Smarius int error; 210391398Stmm 2104174987Smarius /* XXX add support for serial media. */ 210591398Stmm 2106150285Smarius GEM_LOCK(sc); 2107150285Smarius error = mii_mediachg(sc->sc_mii); 2108150285Smarius GEM_UNLOCK(sc); 2109150285Smarius return (error); 211091398Stmm} 211191398Stmm 211291398Stmmvoid 2113174987Smariusgem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 211491398Stmm{ 211591398Stmm struct gem_softc *sc = ifp->if_softc; 211691398Stmm 2117148369Smarius GEM_LOCK(sc); 2118148369Smarius if ((ifp->if_flags & IFF_UP) == 0) { 2119148369Smarius GEM_UNLOCK(sc); 212091398Stmm return; 2121148369Smarius } 212291398Stmm 212391398Stmm mii_pollstat(sc->sc_mii); 212491398Stmm ifmr->ifm_active = sc->sc_mii->mii_media_active; 212591398Stmm ifmr->ifm_status = sc->sc_mii->mii_media_status; 2126148369Smarius GEM_UNLOCK(sc); 212791398Stmm} 212891398Stmm 212991398Stmmstatic int 2130174987Smariusgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 213191398Stmm{ 213291398Stmm struct gem_softc *sc = ifp->if_softc; 213391398Stmm struct ifreq *ifr = (struct ifreq *)data; 2134174987Smarius int error; 213591398Stmm 2136174987Smarius error = 0; 213791398Stmm switch (cmd) { 2138150285Smarius case SIOCSIFFLAGS: 2139148369Smarius GEM_LOCK(sc); 2140174987Smarius if ((ifp->if_flags & IFF_UP) != 0) { 2141172334Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2142172334Smarius ((ifp->if_flags ^ sc->sc_ifflags) & 2143172334Smarius (IFF_ALLMULTI | IFF_PROMISC)) != 0) 214491398Stmm gem_setladrf(sc); 214591398Stmm else 2146148369Smarius gem_init_locked(sc); 2147174987Smarius } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2148174987Smarius gem_stop(ifp, 0); 2149170273Syongari if ((ifp->if_flags & IFF_LINK0) != 0) 2150170273Syongari sc->sc_csum_features |= CSUM_UDP; 2151170273Syongari else 2152170273Syongari sc->sc_csum_features &= ~CSUM_UDP; 2153170273Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2154170273Syongari ifp->if_hwassist = sc->sc_csum_features; 215599726Sbenno sc->sc_ifflags = ifp->if_flags; 2156150285Smarius GEM_UNLOCK(sc); 215791398Stmm break; 215891398Stmm case SIOCADDMULTI: 215991398Stmm case SIOCDELMULTI: 2160150285Smarius GEM_LOCK(sc); 216191398Stmm gem_setladrf(sc); 2162150285Smarius GEM_UNLOCK(sc); 216391398Stmm break; 216491398Stmm case SIOCGIFMEDIA: 216591398Stmm case SIOCSIFMEDIA: 216691398Stmm error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 216791398Stmm break; 2168170273Syongari case SIOCSIFCAP: 2169170273Syongari GEM_LOCK(sc); 2170170273Syongari ifp->if_capenable = ifr->ifr_reqcap; 2171170273Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2172170273Syongari ifp->if_hwassist = sc->sc_csum_features; 2173170273Syongari else 2174170273Syongari ifp->if_hwassist = 0; 2175170273Syongari GEM_UNLOCK(sc); 2176170273Syongari break; 217791398Stmm default: 2178150285Smarius error = ether_ioctl(ifp, cmd, data); 217991398Stmm break; 218091398Stmm } 218191398Stmm 218291398Stmm return (error); 218391398Stmm} 218491398Stmm 218591398Stmmstatic void 2186174987Smariusgem_setladrf(struct gem_softc *sc) 218791398Stmm{ 2188147256Sbrooks struct ifnet *ifp = sc->sc_ifp; 218991398Stmm struct ifmultiaddr *inm; 219099726Sbenno int i; 2191174987Smarius uint32_t hash[16]; 2192174987Smarius uint32_t crc, v; 219391398Stmm 2194148369Smarius GEM_LOCK_ASSERT(sc, MA_OWNED); 2195148369Smarius 2196174987Smarius /* Get the current RX configuration. */ 2197177560Smarius v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 219891398Stmm 219999726Sbenno /* 220099726Sbenno * Turn off promiscuous mode, promiscuous group mode (all multicast), 220199726Sbenno * and hash filter. Depending on the case, the right bit will be 220299726Sbenno * enabled. 220399726Sbenno */ 2204174987Smarius v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 220599726Sbenno GEM_MAC_RX_PROMISC_GRP); 220699726Sbenno 2207177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2208179925Smarius GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2209179925Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2210177560Smarius if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER, 2211177560Smarius 0)) 2212172334Smarius device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2213172334Smarius 221491398Stmm if ((ifp->if_flags & IFF_PROMISC) != 0) { 221591398Stmm v |= GEM_MAC_RX_PROMISCUOUS; 221691398Stmm goto chipit; 221791398Stmm } 221891398Stmm if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 221999726Sbenno v |= GEM_MAC_RX_PROMISC_GRP; 222091398Stmm goto chipit; 222191398Stmm } 222291398Stmm 222391398Stmm /* 2224174987Smarius * Set up multicast address filter by passing all multicast 2225174987Smarius * addresses through a crc generator, and then using the high 2226174987Smarius * order 8 bits as an index into the 256 bit logical address 2227174987Smarius * filter. The high order 4 bits selects the word, while the 2228174987Smarius * other 4 bits select the bit within the word (where bit 0 2229174987Smarius * is the MSB). 223091398Stmm */ 223191398Stmm 2232174987Smarius /* Clear the hash table. */ 223399726Sbenno memset(hash, 0, sizeof(hash)); 223499726Sbenno 2235195049Srwatson if_maddr_rlock(ifp); 2236147256Sbrooks TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 223791398Stmm if (inm->ifma_addr->sa_family != AF_LINK) 223891398Stmm continue; 2239130288Smarius crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2240130288Smarius inm->ifma_addr), ETHER_ADDR_LEN); 224191398Stmm 2242174987Smarius /* We just want the 8 most significant bits. */ 224391398Stmm crc >>= 24; 224491398Stmm 224591398Stmm /* Set the corresponding bit in the filter. */ 224699726Sbenno hash[crc >> 4] |= 1 << (15 - (crc & 15)); 224791398Stmm } 2248195049Srwatson if_maddr_runlock(ifp); 224991398Stmm 225099726Sbenno v |= GEM_MAC_RX_HASH_FILTER; 225199726Sbenno 2252174987Smarius /* Now load the hash table into the chip (if we are using it). */ 2253174987Smarius for (i = 0; i < 16; i++) 2254177560Smarius GEM_BANK1_WRITE_4(sc, 2255174987Smarius GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 225699726Sbenno hash[i]); 225799726Sbenno 2258174987Smarius chipit: 2259177560Smarius GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 226091398Stmm} 2261