if_gem.c revision 161928
11556Srgrimes/*- 21556Srgrimes * Copyright (C) 2001 Eduardo Horvath. 31556Srgrimes * Copyright (c) 2001-2003 Thomas Moestl 41556Srgrimes * All rights reserved. 51556Srgrimes * 61556Srgrimes * Redistribution and use in source and binary forms, with or without 71556Srgrimes * modification, are permitted provided that the following conditions 81556Srgrimes * are met: 91556Srgrimes * 1. Redistributions of source code must retain the above copyright 101556Srgrimes * notice, this list of conditions and the following disclaimer. 111556Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 121556Srgrimes * notice, this list of conditions and the following disclaimer in the 131556Srgrimes * documentation and/or other materials provided with the distribution. 141556Srgrimes * 151556Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 161556Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 171556Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 181556Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 191556Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 201556Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 211556Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 221556Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 231556Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 241556Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 251556Srgrimes * SUCH DAMAGE. 261556Srgrimes * 271556Srgrimes * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 281556Srgrimes */ 291556Srgrimes 301556Srgrimes#include <sys/cdefs.h> 311556Srgrimes__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 161928 2006-09-03 00:27:42Z jmg $"); 321556Srgrimes 331556Srgrimes/* 3436150Scharnier * Driver for Sun GEM ethernet controllers. 3536150Scharnier */ 3636150Scharnier 371556Srgrimes#if 0 3899110Sobrien#define GEM_DEBUG 3999110Sobrien#endif 401556Srgrimes 4117987Speter#if 0 /* XXX: In case of emergency, re-enable this. */ 4217987Speter#define GEM_RINT_TIMEOUT 43114763Sobrien#endif 4417987Speter 451556Srgrimes#include <sys/param.h> 461556Srgrimes#include <sys/systm.h> 471556Srgrimes#include <sys/bus.h> 481556Srgrimes#include <sys/callout.h> 4917525Sache#include <sys/endian.h> 50221559Sjilles#include <sys/mbuf.h> 5117525Sache#include <sys/malloc.h> 521556Srgrimes#include <sys/kernel.h> 531556Srgrimes#include <sys/lock.h> 541556Srgrimes#include <sys/module.h> 551556Srgrimes#include <sys/mutex.h> 561556Srgrimes#include <sys/socket.h> 571556Srgrimes#include <sys/sockio.h> 581556Srgrimes 591556Srgrimes#include <net/bpf.h> 601556Srgrimes#include <net/ethernet.h> 611556Srgrimes#include <net/if.h> 621556Srgrimes#include <net/if_arp.h> 631556Srgrimes#include <net/if_dl.h> 641556Srgrimes#include <net/if_media.h> 6520425Ssteve#include <net/if_types.h> 66223060Sjilles#include <net/if_vlan_var.h> 6717987Speter 6817987Speter#include <machine/bus.h> 6917987Speter 701556Srgrimes#include <dev/mii/mii.h> 711556Srgrimes#include <dev/mii/miivar.h> 721556Srgrimes 731556Srgrimes#include <dev/gem/if_gemreg.h> 741556Srgrimes#include <dev/gem/if_gemvar.h> 751556Srgrimes 761556Srgrimes#define TRIES 10000 771556Srgrimes 78201056Sjillesstatic void gem_start(struct ifnet *); 7990111Simpstatic void gem_start_locked(struct ifnet *); 801556Srgrimesstatic void gem_stop(struct ifnet *, int); 811556Srgrimesstatic int gem_ioctl(struct ifnet *, u_long, caddr_t); 821556Srgrimesstatic void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); 8317987Speterstatic void gem_txdma_callback(void *, bus_dma_segment_t *, int, 841556Srgrimes bus_size_t, int); 85208755Sjillesstatic void gem_tick(void *); 8617987Speterstatic void gem_watchdog(struct ifnet *); 871556Srgrimesstatic void gem_init(void *); 881556Srgrimesstatic void gem_init_locked(struct gem_softc *sc); 891556Srgrimesstatic void gem_init_regs(struct gem_softc *sc); 901556Srgrimesstatic int gem_ringsize(int sz); 911556Srgrimesstatic int gem_meminit(struct gem_softc *); 921556Srgrimesstatic int gem_load_txmbuf(struct gem_softc *, struct mbuf *); 93159632Sstefanfstatic void gem_mifinit(struct gem_softc *); 94213760Sobrienstatic int gem_bitwait(struct gem_softc *sc, bus_addr_t r, 95230998Sjilles u_int32_t clr, u_int32_t set); 961556Srgrimesstatic int gem_reset_rx(struct gem_softc *); 97223024Sjillesstatic int gem_reset_tx(struct gem_softc *); 98223024Sjillesstatic int gem_disable_rx(struct gem_softc *); 99213760Sobrienstatic int gem_disable_tx(struct gem_softc *); 10017987Speterstatic void gem_rxdrain(struct gem_softc *); 101201056Sjillesstatic int gem_add_rxbuf(struct gem_softc *, int); 10220425Sstevestatic void gem_setladrf(struct gem_softc *); 10317987Speter 104201056Sjillesstruct mbuf *gem_get(struct gem_softc *, int, int); 10520425Sstevestatic void gem_eint(struct gem_softc *, u_int); 106201056Sjillesstatic void gem_rint(struct gem_softc *); 10720425Ssteve#ifdef GEM_RINT_TIMEOUT 108201056Sjillesstatic void gem_rint_timeout(void *); 10920425Ssteve#endif 110201056Sjillesstatic void gem_tint(struct gem_softc *); 11120425Ssteve#ifdef notyet 1128855Srgrimesstatic void gem_power(int, void *); 1131556Srgrimes#endif 1141556Srgrimes 115201056Sjillesdevclass_t gem_devclass; 11620425SsteveDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 117201056SjillesMODULE_DEPEND(gem, miibus, 1, 1, 1); 118159632Sstefanf 119208755Sjilles#ifdef GEM_DEBUG 120208755Sjilles#include <sys/ktr.h> 121208755Sjilles#define KTR_GEM KTR_CT2 122208755Sjilles#endif 123201056Sjilles 12420425Ssteve#define GEM_NSEGS GEM_NTXDESC 125230998Sjilles 126230998Sjilles/* 12720425Ssteve * gem_attach: 12820425Ssteve * 1291556Srgrimes * Attach a Gem interface to the system. 1301556Srgrimes */ 131213760Sobrienint 1321556Srgrimesgem_attach(sc) 133213760Sobrien struct gem_softc *sc; 134207678Sjilles{ 135207678Sjilles struct ifnet *ifp; 136207678Sjilles struct mii_softc *child; 137213760Sobrien int i, error; 138207678Sjilles u_int32_t v; 139207678Sjilles 140207678Sjilles ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 141213811Sobrien if (ifp == NULL) 142221668Sjilles return (ENOSPC); 143213811Sobrien 1441556Srgrimes callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 145245689Sjilles#ifdef GEM_RINT_TIMEOUT 1461556Srgrimes callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 1471556Srgrimes#endif 148245689Sjilles 149245689Sjilles /* Make sure the chip is stopped. */ 1501556Srgrimes ifp->if_softc = sc; 1511556Srgrimes GEM_LOCK(sc); 1521556Srgrimes gem_stop(ifp, 0); 15390111Simp gem_reset(sc); 15490111Simp GEM_UNLOCK(sc); 15597689Stjr 1561556Srgrimes error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1571556Srgrimes BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1581556Srgrimes MCLBYTES, GEM_NSEGS, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 159245689Sjilles &sc->sc_pdmatag); 1601556Srgrimes if (error) 1611556Srgrimes goto fail_ifnet; 162221668Sjilles 163221668Sjilles error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 164221668Sjilles BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE, 165221668Sjilles 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL, 166221668Sjilles &sc->sc_rdmatag); 167221668Sjilles if (error) 168221668Sjilles goto fail_ptag; 1691556Srgrimes 1701556Srgrimes error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 1711556Srgrimes BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1721556Srgrimes GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT, 173221668Sjilles BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 1741556Srgrimes if (error) 1751556Srgrimes goto fail_rtag; 176201056Sjilles 1771556Srgrimes error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 1781556Srgrimes BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 179262951Sjmmv sizeof(struct gem_control_data), 1, 180262951Sjmmv sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW, 181245689Sjilles busdma_lock_mutex, &sc->sc_mtx, &sc->sc_cdmatag); 182245689Sjilles if (error) 183245689Sjilles goto fail_ttag; 184245689Sjilles 185245689Sjilles /* 186262951Sjmmv * Allocate the control data structures, and create and load the 1871556Srgrimes * DMA map for it. 1881556Srgrimes */ 1891556Srgrimes if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 19020425Ssteve (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) { 19120425Ssteve device_printf(sc->sc_dev, "unable to allocate control data," 19220425Ssteve " error = %d\n", error); 19320425Ssteve goto fail_ctag; 194200956Sjilles } 19520425Ssteve 19620425Ssteve sc->sc_cddma = 0; 197194765Sjilles if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 19820425Ssteve sc->sc_control_data, sizeof(struct gem_control_data), 199199660Sjilles gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 20020425Ssteve device_printf(sc->sc_dev, "unable to load control data DMA " 201199660Sjilles "map, error = %d\n", error); 20220425Ssteve goto fail_cmem; 20320425Ssteve } 20420425Ssteve 20520425Ssteve /* 20620425Ssteve * Initialize the transmit job descriptors. 20720425Ssteve */ 20820425Ssteve STAILQ_INIT(&sc->sc_txfreeq); 209199660Sjilles STAILQ_INIT(&sc->sc_txdirtyq); 21020425Ssteve 21120425Ssteve /* 21220425Ssteve * Create the transmit buffer DMA maps. 21320425Ssteve */ 214155302Sschweikh error = ENOMEM; 2151556Srgrimes for (i = 0; i < GEM_TXQUEUELEN; i++) { 2161556Srgrimes struct gem_txsoft *txs; 2171556Srgrimes 2181556Srgrimes txs = &sc->sc_txsoft[i]; 219200956Sjilles txs->txs_mbuf = NULL; 22017987Speter txs->txs_ndescs = 0; 221200956Sjilles if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 222262951Sjmmv &txs->txs_dmamap)) != 0) { 223262951Sjmmv device_printf(sc->sc_dev, "unable to create tx DMA map " 224262951Sjmmv "%d, error = %d\n", i, error); 2251556Srgrimes goto fail_txd; 2261556Srgrimes } 2271556Srgrimes STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2281556Srgrimes } 2291556Srgrimes 23017525Sache /* 2311556Srgrimes * Create the receive buffer DMA maps. 23217525Sache */ 2331556Srgrimes for (i = 0; i < GEM_NRXDESC; i++) { 2341556Srgrimes if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 2351556Srgrimes &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 2361556Srgrimes device_printf(sc->sc_dev, "unable to create rx DMA map " 2371556Srgrimes "%d, error = %d\n", i, error); 2381556Srgrimes goto fail_rxd; 2391556Srgrimes } 2401556Srgrimes sc->sc_rxsoft[i].rxs_mbuf = NULL; 2411556Srgrimes } 2421556Srgrimes 243262951Sjmmv gem_mifinit(sc); 2441556Srgrimes 2451556Srgrimes if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange, 2461556Srgrimes gem_mediastatus)) != 0) { 247262951Sjmmv device_printf(sc->sc_dev, "phy probe failed: %d\n", error); 2481556Srgrimes goto fail_rxd; 249262951Sjmmv } 250262951Sjmmv sc->sc_mii = device_get_softc(sc->sc_miibus); 2511556Srgrimes 252264478Sjilles /* 253200956Sjilles * From this point forward, the attachment cannot fail. A failure 254200956Sjilles * before this point releases all resources that may have been 255200956Sjilles * allocated. 2561556Srgrimes */ 257262951Sjmmv 258200956Sjilles /* Get RX FIFO size */ 259200956Sjilles sc->sc_rxfifosize = 64 * 2601556Srgrimes bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 261264478Sjilles 2621556Srgrimes /* Get TX FIFO size */ 2631556Srgrimes v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 264213811Sobrien device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 265200956Sjilles sc->sc_rxfifosize / 1024, v / 16); 26690111Simp 267207678Sjilles /* Initialize ifnet structure. */ 2681556Srgrimes ifp->if_softc = sc; 26917525Sache if_initname(ifp, device_get_name(sc->sc_dev), 27017525Sache device_get_unit(sc->sc_dev)); 27117525Sache ifp->if_mtu = ETHERMTU; 27217525Sache ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 27317525Sache ifp->if_start = gem_start; 27417525Sache ifp->if_ioctl = gem_ioctl; 275207678Sjilles ifp->if_watchdog = gem_watchdog; 276207678Sjilles ifp->if_init = gem_init; 277207678Sjilles ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN; 278207678Sjilles /* 27917525Sache * Walk along the list of attached MII devices and 28017525Sache * establish an `MII instance' to `phy number' 28117525Sache * mapping. We'll use this mapping in media change 2821556Srgrimes * requests to determine which phy to use to program 283171268Sscf * the MIF configuration register. 2841556Srgrimes */ 285171268Sscf for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL; 286171268Sscf child = LIST_NEXT(child, mii_list)) { 287171268Sscf /* 288213811Sobrien * Note: we support just two PHYs: the built-in 289200956Sjilles * internal device and an external on the MII 290171268Sscf * connector. 291171268Sscf */ 292171268Sscf if (child->mii_phy > 1 || child->mii_inst > 1) { 293171268Sscf device_printf(sc->sc_dev, "cannot accomodate " 294264478Sjilles "MII device %s at phy %d, instance %d\n", 295171268Sscf device_get_name(child->mii_dev), 296171268Sscf child->mii_phy, child->mii_inst); 297171268Sscf continue; 298171268Sscf } 299171268Sscf 300171268Sscf sc->sc_phys[child->mii_inst] = child->mii_phy; 301171268Sscf } 302171268Sscf 303264478Sjilles /* 304171268Sscf * Now select and activate the PHY we will use. 305171268Sscf * 306171268Sscf * The order of preference is External (MDI1), 307171268Sscf * Internal (MDI0), Serial Link (no MII). 308171268Sscf */ 309171268Sscf if (sc->sc_phys[1]) { 3101556Srgrimes#ifdef GEM_DEBUG 3111556Srgrimes printf("using external phy\n"); 3121556Srgrimes#endif 3131556Srgrimes sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 3141556Srgrimes } else { 3151556Srgrimes#ifdef GEM_DEBUG 3161556Srgrimes printf("using internal phy\n"); 31790111Simp#endif 31817987Speter sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 3191556Srgrimes } 320221668Sjilles bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 3211556Srgrimes sc->sc_mif_config); 32245263Scracauer /* Attach the interface. */ 32345263Scracauer ether_ifattach(ifp, sc->sc_enaddr); 324223024Sjilles 325223024Sjilles#ifdef notyet 326221668Sjilles /* 327221668Sjilles * Add a suspend hook to make sure we come back up after a 328264512Sjilles * resume. 329264512Sjilles */ 330264512Sjilles sc->sc_powerhook = powerhook_establish(gem_power, sc); 331292664Sjilles if (sc->sc_powerhook == NULL) 332264512Sjilles device_printf(sc->sc_dev, "WARNING: unable to establish power " 333264513Sjilles "hook\n"); 334264513Sjilles#endif 335264513Sjilles 336221668Sjilles /* 337264513Sjilles * Tell the upper layer(s) we support long frames. 338221668Sjilles */ 33920425Ssteve ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 340221668Sjilles ifp->if_capabilities |= IFCAP_VLAN_MTU; 341221668Sjilles ifp->if_capenable |= IFCAP_VLAN_MTU; 34220425Ssteve 343221668Sjilles return (0); 344221668Sjilles 34520425Ssteve /* 346221668Sjilles * Free any resources we've allocated during the failed attach 347221668Sjilles * attempt. Do this in reverse order and fall through. 348221668Sjilles */ 34920425Sstevefail_rxd: 350221668Sjilles for (i = 0; i < GEM_NRXDESC; i++) { 351221668Sjilles if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 352221668Sjilles bus_dmamap_destroy(sc->sc_rdmatag, 353221668Sjilles sc->sc_rxsoft[i].rxs_dmamap); 354221668Sjilles } 355245689Sjillesfail_txd: 356221668Sjilles for (i = 0; i < GEM_TXQUEUELEN; i++) { 357221668Sjilles if (sc->sc_txsoft[i].txs_dmamap != NULL) 358221668Sjilles bus_dmamap_destroy(sc->sc_tdmatag, 359221668Sjilles sc->sc_txsoft[i].txs_dmamap); 360221668Sjilles } 361221668Sjilles bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 362221668Sjillesfail_cmem: 363221668Sjilles bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 364221668Sjilles sc->sc_cddmamap); 3651556Srgrimesfail_ctag: 366221668Sjilles bus_dma_tag_destroy(sc->sc_cdmatag); 367221668Sjillesfail_ttag: 3681556Srgrimes bus_dma_tag_destroy(sc->sc_tdmatag); 3691556Srgrimesfail_rtag: 370264513Sjilles bus_dma_tag_destroy(sc->sc_rdmatag); 371264513Sjillesfail_ptag: 372264513Sjilles bus_dma_tag_destroy(sc->sc_pdmatag); 373216870Sjillesfail_ifnet: 374264513Sjilles if_free(ifp); 375264478Sjilles return (error); 3761556Srgrimes} 3771556Srgrimes 3781556Srgrimesvoid 379221668Sjillesgem_detach(sc) 3801556Srgrimes struct gem_softc *sc; 38120425Ssteve{ 3821556Srgrimes struct ifnet *ifp = sc->sc_ifp; 38317525Sache int i; 384171268Sscf 38517525Sache GEM_LOCK(sc); 386221559Sjilles gem_stop(ifp, 1); 38717525Sache GEM_UNLOCK(sc); 38817525Sache callout_drain(&sc->sc_tick_ch); 3891556Srgrimes#ifdef GEM_RINT_TIMEOUT 3901556Srgrimes callout_drain(&sc->sc_rx_ch); 3911556Srgrimes#endif 3921556Srgrimes ether_ifdetach(ifp); 3931556Srgrimes if_free(ifp); 3941556Srgrimes device_delete_child(sc->sc_dev, sc->sc_miibus); 3951556Srgrimes 3961556Srgrimes for (i = 0; i < GEM_NRXDESC; i++) { 3971556Srgrimes if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 398216870Sjilles bus_dmamap_destroy(sc->sc_rdmatag, 39990111Simp sc->sc_rxsoft[i].rxs_dmamap); 4001556Srgrimes } 4011556Srgrimes for (i = 0; i < GEM_TXQUEUELEN; i++) { 4021556Srgrimes if (sc->sc_txsoft[i].txs_dmamap != NULL) 4031556Srgrimes bus_dmamap_destroy(sc->sc_tdmatag, 404216870Sjilles sc->sc_txsoft[i].txs_dmamap); 4051556Srgrimes } 4061556Srgrimes GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 4071556Srgrimes GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE); 4081556Srgrimes bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 4091556Srgrimes bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 4101556Srgrimes sc->sc_cddmamap); 4111556Srgrimes bus_dma_tag_destroy(sc->sc_cdmatag); 4121556Srgrimes bus_dma_tag_destroy(sc->sc_tdmatag); 4131556Srgrimes bus_dma_tag_destroy(sc->sc_rdmatag); 4141556Srgrimes bus_dma_tag_destroy(sc->sc_pdmatag); 4151556Srgrimes} 416200956Sjilles 41790111Simpvoid 4181556Srgrimesgem_suspend(sc) 4191556Srgrimes struct gem_softc *sc; 420221668Sjilles{ 421221668Sjilles struct ifnet *ifp = sc->sc_ifp; 422221668Sjilles 423221668Sjilles GEM_LOCK(sc); 4241556Srgrimes gem_stop(ifp, 0); 4251556Srgrimes GEM_UNLOCK(sc); 4261556Srgrimes} 4271556Srgrimes 4281556Srgrimesvoid 4291556Srgrimesgem_resume(sc) 4301556Srgrimes struct gem_softc *sc; 4311556Srgrimes{ 4321556Srgrimes struct ifnet *ifp = sc->sc_ifp; 4331556Srgrimes 4341556Srgrimes GEM_LOCK(sc); 435200956Sjilles /* 43617987Speter * On resume all registers have to be initialized again like 4371556Srgrimes * after power-on. 4381556Srgrimes */ 439212467Sjilles sc->sc_inited = 0; 4401556Srgrimes if (ifp->if_flags & IFF_UP) 441212467Sjilles gem_init_locked(sc); 4421556Srgrimes GEM_UNLOCK(sc); 4431556Srgrimes} 444212467Sjilles 4451556Srgrimesstatic void 446212467Sjillesgem_cddma_callback(xsc, segs, nsegs, error) 447212467Sjilles void *xsc; 448221668Sjilles bus_dma_segment_t *segs; 449221668Sjilles int nsegs; 450221668Sjilles int error; 451221668Sjilles{ 452221668Sjilles struct gem_softc *sc = (struct gem_softc *)xsc; 453221668Sjilles 4541556Srgrimes if (error != 0) 4551556Srgrimes return; 4561556Srgrimes if (nsegs != 1) { 457207678Sjilles /* can't happen... */ 458207678Sjilles panic("gem_cddma_callback: bad control buffer segment count"); 459207678Sjilles } 460207678Sjilles sc->sc_cddma = segs[0].ds_addr; 461207678Sjilles} 462207678Sjilles 463207678Sjillesstatic void 464207678Sjillesgem_txdma_callback(xsc, segs, nsegs, totsz, error) 465207678Sjilles void *xsc; 466207678Sjilles bus_dma_segment_t *segs; 4671556Srgrimes int nsegs; 468207678Sjilles bus_size_t totsz; 469207678Sjilles int error; 470207678Sjilles{ 471207678Sjilles struct gem_txdma *txd = (struct gem_txdma *)xsc; 472207678Sjilles struct gem_softc *sc = txd->txd_sc; 473207678Sjilles struct gem_txsoft *txs = txd->txd_txs; 474207678Sjilles bus_size_t len = 0; 475207678Sjilles uint64_t flags = 0; 476207678Sjilles int seg, nexttx; 477207678Sjilles 478207678Sjilles if (error != 0) 479207678Sjilles return; 480207678Sjilles /* 481221559Sjilles * Ensure we have enough descriptors free to describe 482207678Sjilles * the packet. Note, we always reserve one descriptor 483207678Sjilles * at the end of the ring as a termination point, to 484207678Sjilles * prevent wrap-around. 485207678Sjilles */ 486207678Sjilles if (nsegs > sc->sc_txfree - 1) { 487207678Sjilles txs->txs_ndescs = -1; 488207678Sjilles return; 489207678Sjilles } 490207678Sjilles txs->txs_ndescs = nsegs; 491207678Sjilles 492207678Sjilles nexttx = txs->txs_firstdesc; 493221559Sjilles /* 494207678Sjilles * Initialize the transmit descriptors. 495207678Sjilles */ 4961556Srgrimes for (seg = 0; seg < nsegs; 497207678Sjilles seg++, nexttx = GEM_NEXTTX(nexttx)) { 498207678Sjilles#ifdef GEM_DEBUG 499207678Sjilles CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len " 500207678Sjilles "%lx, addr %#lx (%#lx)", seg, nexttx, 501207678Sjilles segs[seg].ds_len, segs[seg].ds_addr, 502207678Sjilles GEM_DMA_WRITE(sc, segs[seg].ds_addr)); 503207678Sjilles#endif 504207678Sjilles 505207678Sjilles if (segs[seg].ds_len == 0) 506207678Sjilles continue; 507207678Sjilles sc->sc_txdescs[nexttx].gd_addr = 508221559Sjilles GEM_DMA_WRITE(sc, segs[seg].ds_addr); 509207678Sjilles KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE, 510207678Sjilles ("gem_txdma_callback: segment size too large!")); 511207678Sjilles flags = segs[seg].ds_len & GEM_TD_BUFSIZE; 512207678Sjilles if (len == 0) { 513207678Sjilles#ifdef GEM_DEBUG 514207678Sjilles CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, " 515221559Sjilles "tx %d", seg, nexttx); 516221559Sjilles#endif 517221559Sjilles flags |= GEM_TD_START_OF_PACKET; 518221559Sjilles if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 519221559Sjilles sc->sc_txwin = 0; 520221559Sjilles flags |= GEM_TD_INTERRUPT_ME; 521221559Sjilles } 522207678Sjilles } 523221559Sjilles if (len + segs[seg].ds_len == totsz) { 524221559Sjilles#ifdef GEM_DEBUG 525221559Sjilles CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, " 526221559Sjilles "tx %d", seg, nexttx); 527221669Sjilles#endif 528221669Sjilles flags |= GEM_TD_END_OF_PACKET; 529221669Sjilles } 530221669Sjilles sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags); 531221669Sjilles txs->txs_lastdesc = nexttx; 532221669Sjilles len += segs[seg].ds_len; 533221669Sjilles } 534207678Sjilles KASSERT((flags & GEM_TD_END_OF_PACKET) != 0, 5351556Srgrimes ("gem_txdma_callback: missed end of packet!")); 5361556Srgrimes} 5371556Srgrimes 5381556Srgrimesstatic void 5391556Srgrimesgem_tick(arg) 54090111Simp void *arg; 54190111Simp{ 5421556Srgrimes struct gem_softc *sc = arg; 5431556Srgrimes 5441556Srgrimes GEM_LOCK_ASSERT(sc, MA_OWNED); 5451556Srgrimes mii_tick(sc->sc_mii); 5461556Srgrimes 5471556Srgrimes callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 5481556Srgrimes} 5491556Srgrimes 5501556Srgrimesstatic int 5511556Srgrimesgem_bitwait(sc, r, clr, set) 5521556Srgrimes struct gem_softc *sc; 5531556Srgrimes bus_addr_t r; 5541556Srgrimes u_int32_t clr; 5551556Srgrimes u_int32_t set; 5561556Srgrimes{ 5571556Srgrimes int i; 5581556Srgrimes u_int32_t reg; 5591556Srgrimes 5601556Srgrimes for (i = TRIES; i--; DELAY(100)) { 5611556Srgrimes reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 5621556Srgrimes if ((r & clr) == 0 && (r & set) == set) 5631556Srgrimes return (1); 564213811Sobrien } 565158145Sstefanf return (0); 566158145Sstefanf} 567158145Sstefanf 5681556Srgrimesvoid 569158145Sstefanfgem_reset(sc) 570158145Sstefanf struct gem_softc *sc; 571158145Sstefanf{ 572158145Sstefanf bus_space_tag_t t = sc->sc_bustag; 573158145Sstefanf bus_space_handle_t h = sc->sc_h; 574158145Sstefanf 575158145Sstefanf#ifdef GEM_DEBUG 576158145Sstefanf CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 577158145Sstefanf#endif 578158145Sstefanf gem_reset_rx(sc); 579158145Sstefanf gem_reset_tx(sc); 5801556Srgrimes 581217847Sjilles /* Do a full reset */ 582217847Sjilles bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 5831556Srgrimes if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 5841556Srgrimes device_printf(sc->sc_dev, "cannot reset device\n"); 5851556Srgrimes} 58690111Simp 58717987Speter 5881556Srgrimes/* 5891556Srgrimes * gem_rxdrain: 59097915Stjr * 591158145Sstefanf * Drain the receive queue. 592158145Sstefanf */ 5931556Srgrimesstatic void 594158145Sstefanfgem_rxdrain(sc) 595158145Sstefanf struct gem_softc *sc; 596158145Sstefanf{ 597158145Sstefanf struct gem_rxsoft *rxs; 598158145Sstefanf int i; 599158145Sstefanf 600158145Sstefanf for (i = 0; i < GEM_NRXDESC; i++) { 601158145Sstefanf rxs = &sc->sc_rxsoft[i]; 6021556Srgrimes if (rxs->rxs_mbuf != NULL) { 6031556Srgrimes bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 604158145Sstefanf BUS_DMASYNC_POSTREAD); 605231001Sjilles bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 606158145Sstefanf m_freem(rxs->rxs_mbuf); 607158145Sstefanf rxs->rxs_mbuf = NULL; 608158145Sstefanf } 609158145Sstefanf } 610158145Sstefanf} 611158145Sstefanf 612158145Sstefanf/* 613158145Sstefanf * Reset the whole thing. 614158145Sstefanf */ 615158145Sstefanfstatic void 616158145Sstefanfgem_stop(ifp, disable) 617223183Sjilles struct ifnet *ifp; 618223183Sjilles int disable; 619223183Sjilles{ 620223183Sjilles struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 621223183Sjilles struct gem_txsoft *txs; 622223183Sjilles 623215567Sjilles#ifdef GEM_DEBUG 624215567Sjilles CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev)); 625215567Sjilles#endif 626215567Sjilles 627158145Sstefanf callout_stop(&sc->sc_tick_ch); 628158145Sstefanf#ifdef GEM_RINT_TIMEOUT 629158145Sstefanf callout_stop(&sc->sc_rx_ch); 630231001Sjilles#endif 631158145Sstefanf 6321556Srgrimes /* XXX - Should we reset these instead? */ 6331556Srgrimes gem_disable_tx(sc); 6341556Srgrimes gem_disable_rx(sc); 6351556Srgrimes 6361556Srgrimes /* 6371556Srgrimes * Release any queued transmit buffers. 6381556Srgrimes */ 6391556Srgrimes while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 6401556Srgrimes STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 6411556Srgrimes if (txs->txs_ndescs != 0) { 642240541Sjilles bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 64317987Speter BUS_DMASYNC_POSTWRITE); 6441556Srgrimes bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 6451556Srgrimes if (txs->txs_mbuf != NULL) { 646240541Sjilles m_freem(txs->txs_mbuf); 6471556Srgrimes txs->txs_mbuf = NULL; 6481556Srgrimes } 64997914Stjr } 65097914Stjr STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 6511556Srgrimes } 6521556Srgrimes 65397914Stjr if (disable) 65497914Stjr gem_rxdrain(sc); 655240541Sjilles 65697914Stjr /* 65797914Stjr * Mark the interface down and cancel the watchdog timer. 65897914Stjr */ 65997914Stjr ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 66097914Stjr ifp->if_timer = 0; 66197914Stjr} 66297914Stjr 663240541Sjilles/* 664149919Sstefanf * Reset the receiver 665240541Sjilles */ 666240541Sjillesint 6671556Srgrimesgem_reset_rx(sc) 6681556Srgrimes struct gem_softc *sc; 6691556Srgrimes{ 670221668Sjilles bus_space_tag_t t = sc->sc_bustag; 671221668Sjilles bus_space_handle_t h = sc->sc_h; 672221668Sjilles 673221668Sjilles /* 674221668Sjilles * Resetting while DMA is in progress can cause a bus hang, so we 675221668Sjilles * disable DMA first. 676221668Sjilles */ 6771556Srgrimes gem_disable_rx(sc); 678221668Sjilles bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 6791556Srgrimes /* Wait till it finishes */ 6801556Srgrimes if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 6811556Srgrimes device_printf(sc->sc_dev, "cannot disable read dma\n"); 6821556Srgrimes 6831556Srgrimes /* Wait 5ms extra. */ 6841556Srgrimes DELAY(5000); 6851556Srgrimes 6861556Srgrimes /* Finally, reset the ERX */ 68797914Stjr bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 688223183Sjilles /* Wait till it finishes */ 689223183Sjilles if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 690223183Sjilles device_printf(sc->sc_dev, "cannot reset receiver\n"); 691223183Sjilles return (1); 692223183Sjilles } 693223183Sjilles return (0); 694223183Sjilles} 69597914Stjr 69697914Stjr 69797914Stjr/* 69897914Stjr * Reset the transmitter 699221975Sjilles */ 700221975Sjillesstatic int 701221975Sjillesgem_reset_tx(sc) 702221975Sjilles struct gem_softc *sc; 703215567Sjilles{ 704221975Sjilles bus_space_tag_t t = sc->sc_bustag; 705215567Sjilles bus_space_handle_t h = sc->sc_h; 7061556Srgrimes int i; 7071556Srgrimes 7081556Srgrimes /* 7091556Srgrimes * Resetting while DMA is in progress can cause a bus hang, so we 7101556Srgrimes * disable DMA first. 7111556Srgrimes */ 7121556Srgrimes gem_disable_tx(sc); 7131556Srgrimes bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 7141556Srgrimes /* Wait till it finishes */ 7151556Srgrimes if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 7161556Srgrimes device_printf(sc->sc_dev, "cannot disable read dma\n"); 7171556Srgrimes 7181556Srgrimes /* Wait 5ms extra. */ 71917987Speter DELAY(5000); 72090111Simp 72117987Speter /* Finally, reset the ETX */ 7221556Srgrimes bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 7231556Srgrimes /* Wait till it finishes */ 724254339Sjilles for (i = TRIES; i--; DELAY(100)) 7251556Srgrimes if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 7261556Srgrimes break; 7271556Srgrimes if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 7281556Srgrimes device_printf(sc->sc_dev, "cannot reset receiver\n"); 7291556Srgrimes return (1); 7301556Srgrimes } 7311556Srgrimes return (0); 7321556Srgrimes} 7331556Srgrimes 7341556Srgrimes/* 7351556Srgrimes * disable receiver. 7361556Srgrimes */ 7371556Srgrimesstatic int 7381556Srgrimesgem_disable_rx(sc) 7391556Srgrimes struct gem_softc *sc; 7401556Srgrimes{ 7411556Srgrimes bus_space_tag_t t = sc->sc_bustag; 74290111Simp bus_space_handle_t h = sc->sc_h; 74390111Simp u_int32_t cfg; 7441556Srgrimes 7451556Srgrimes /* Flip the enable bit */ 7461556Srgrimes cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 7471556Srgrimes cfg &= ~GEM_MAC_RX_ENABLE; 7481556Srgrimes bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 7491556Srgrimes 7501556Srgrimes /* Wait for it to finish */ 7511556Srgrimes return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 75217987Speter} 7531556Srgrimes 7541556Srgrimes/* 755221668Sjilles * disable transmitter. 7561556Srgrimes */ 7571556Srgrimesstatic int 758223024Sjillesgem_disable_tx(sc) 7591556Srgrimes struct gem_softc *sc; 760223024Sjilles{ 7611556Srgrimes bus_space_tag_t t = sc->sc_bustag; 7621556Srgrimes bus_space_handle_t h = sc->sc_h; 7631556Srgrimes u_int32_t cfg; 7641556Srgrimes 7651556Srgrimes /* Flip the enable bit */ 7661556Srgrimes cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 7671556Srgrimes cfg &= ~GEM_MAC_TX_ENABLE; 768221668Sjilles bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 769223024Sjilles 7701556Srgrimes /* Wait for it to finish */ 7711556Srgrimes return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 7721556Srgrimes} 7731556Srgrimes 7741556Srgrimes/* 7751556Srgrimes * Initialize interface. 7761556Srgrimes */ 7771556Srgrimesstatic int 7781556Srgrimesgem_meminit(sc) 7791556Srgrimes struct gem_softc *sc; 7801556Srgrimes{ 7811556Srgrimes struct gem_rxsoft *rxs; 7821556Srgrimes int i, error; 7831556Srgrimes 78490111Simp /* 78590111Simp * Initialize the transmit descriptor ring. 7861556Srgrimes */ 7871556Srgrimes for (i = 0; i < GEM_NTXDESC; i++) { 7881556Srgrimes sc->sc_txdescs[i].gd_flags = 0; 789264478Sjilles sc->sc_txdescs[i].gd_addr = 0; 7901556Srgrimes } 7911556Srgrimes sc->sc_txfree = GEM_MAXTXFREE; 7921556Srgrimes sc->sc_txnext = 0; 7931556Srgrimes sc->sc_txwin = 0; 79417987Speter 7951556Srgrimes /* 796215266Sjilles * Initialize the receive descriptor and receive job 7971556Srgrimes * descriptor rings. 7981556Srgrimes */ 7991556Srgrimes for (i = 0; i < GEM_NRXDESC; i++) { 8001556Srgrimes rxs = &sc->sc_rxsoft[i]; 8011556Srgrimes if (rxs->rxs_mbuf == NULL) { 8021556Srgrimes if ((error = gem_add_rxbuf(sc, i)) != 0) { 8031556Srgrimes device_printf(sc->sc_dev, "unable to " 8041556Srgrimes "allocate or map rx buffer %d, error = " 8051556Srgrimes "%d\n", i, error); 8061556Srgrimes /* 807264478Sjilles * XXX Should attempt to run with fewer receive 8081556Srgrimes * XXX buffers instead of just failing. 8091556Srgrimes */ 8101556Srgrimes gem_rxdrain(sc); 81117987Speter return (1); 81290111Simp } 81317987Speter } else 8141556Srgrimes GEM_INIT_RXDESC(sc, i); 8151556Srgrimes } 8161556Srgrimes sc->sc_rxptr = 0; 8171556Srgrimes GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 8181556Srgrimes GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 819214538Sjilles 8201556Srgrimes return (0); 8211556Srgrimes} 8221556Srgrimes 8231556Srgrimesstatic int 8241556Srgrimesgem_ringsize(sz) 825217847Sjilles int sz; 8261556Srgrimes{ 8271556Srgrimes int v = 0; 82817987Speter 82990111Simp switch (sz) { 83017987Speter case 32: 8311556Srgrimes v = GEM_RING_SZ_32; 8321556Srgrimes break; 8331556Srgrimes case 64: 8341556Srgrimes v = GEM_RING_SZ_64; 8351556Srgrimes break; 8361556Srgrimes case 128: 8371556Srgrimes v = GEM_RING_SZ_128; 8381556Srgrimes break; 8391556Srgrimes case 256: 8401556Srgrimes v = GEM_RING_SZ_256; 8411556Srgrimes break; 8421556Srgrimes case 512: 8431556Srgrimes v = GEM_RING_SZ_512; 8441556Srgrimes break; 8458855Srgrimes case 1024: 846264478Sjilles v = GEM_RING_SZ_1024; 8471556Srgrimes break; 8481556Srgrimes case 2048: 8491556Srgrimes v = GEM_RING_SZ_2048; 8501556Srgrimes break; 8511556Srgrimes case 4096: 8521556Srgrimes v = GEM_RING_SZ_4096; 853264478Sjilles break; 8541556Srgrimes case 8192: 8551556Srgrimes v = GEM_RING_SZ_8192; 8561556Srgrimes break; 8571556Srgrimes default: 8581556Srgrimes printf("gem: invalid Receive Descriptor ring size\n"); 8591556Srgrimes break; 860264478Sjilles } 8611556Srgrimes return (v); 8621556Srgrimes} 86320425Ssteve 864200956Sjillesstatic void 86590111Simpgem_init(xsc) 8661556Srgrimes void *xsc; 8671556Srgrimes{ 8681556Srgrimes struct gem_softc *sc = (struct gem_softc *)xsc; 869221668Sjilles 870221668Sjilles GEM_LOCK(sc); 871221668Sjilles gem_init_locked(sc); 872221668Sjilles GEM_UNLOCK(sc); 873221668Sjilles} 874221668Sjilles 875221668Sjilles/* 876221668Sjilles * Initialization of interface; set up initialization block 877221668Sjilles * and transmit/receive descriptor rings. 878221668Sjilles */ 879221668Sjillesstatic void 8801556Srgrimesgem_init_locked(sc) 881221668Sjilles struct gem_softc *sc; 882221668Sjilles{ 883221668Sjilles struct ifnet *ifp = sc->sc_ifp; 884221668Sjilles bus_space_tag_t t = sc->sc_bustag; 885221668Sjilles bus_space_handle_t h = sc->sc_h; 886221668Sjilles u_int32_t v; 887221668Sjilles 888221668Sjilles GEM_LOCK_ASSERT(sc, MA_OWNED); 889135856Sdes 8901556Srgrimes#ifdef GEM_DEBUG 8911556Srgrimes CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 8921556Srgrimes#endif 8931556Srgrimes /* 8941556Srgrimes * Initialization sequence. The numbered steps below correspond 895250422Seadler * to the sequence outlined in section 6.3.5.1 in the Ethernet 8961556Srgrimes * Channel Engine manual (part of the PCIO manual). 8971556Srgrimes * See also the STP2002-STQ document from Sun Microsystems. 8981556Srgrimes */ 8991556Srgrimes 900213811Sobrien /* step 1 & 2. Reset the Ethernet Channel */ 901200956Sjilles gem_stop(sc->sc_ifp, 0); 90290111Simp gem_reset(sc); 9031556Srgrimes#ifdef GEM_DEBUG 9041556Srgrimes CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev)); 9051556Srgrimes#endif 9061556Srgrimes 9071556Srgrimes /* Re-initialize the MIF */ 9081556Srgrimes gem_mifinit(sc); 9091556Srgrimes 9101556Srgrimes /* step 3. Setup data structures in host memory */ 911221668Sjilles gem_meminit(sc); 912221668Sjilles 913221668Sjilles /* step 4. TX MAC registers & counters */ 914221668Sjilles gem_init_regs(sc); 915221668Sjilles 916250422Seadler /* step 5. RX MAC registers & counters */ 917221668Sjilles gem_setladrf(sc); 918221668Sjilles 919221668Sjilles /* step 6 & 7. Program Descriptor Ring Base Addresses */ 920221668Sjilles /* NOTE: we use only 32-bit DMA addresses here. */ 921221668Sjilles bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 922221668Sjilles bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 923221668Sjilles 924221668Sjilles bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 925221668Sjilles bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 926221668Sjilles#ifdef GEM_DEBUG 927221668Sjilles CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 928221668Sjilles GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 929221668Sjilles#endif 930221668Sjilles 931221668Sjilles /* step 8. Global Configuration & Interrupt Mask */ 932221668Sjilles bus_space_write_4(t, h, GEM_INTMASK, 933221668Sjilles ~(GEM_INTR_TX_INTME| 934221668Sjilles GEM_INTR_TX_EMPTY| 935221668Sjilles GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 936221668Sjilles GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 937221668Sjilles GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 938221668Sjilles GEM_INTR_BERR)); 939221668Sjilles bus_space_write_4(t, h, GEM_MAC_RX_MASK, 940221668Sjilles GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 941221668Sjilles bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 942221668Sjilles bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 943221668Sjilles 944221668Sjilles /* step 9. ETX Configuration: use mostly default values */ 945221668Sjilles 946221668Sjilles /* Enable DMA */ 947221668Sjilles v = gem_ringsize(GEM_NTXDESC /*XXX*/); 948221668Sjilles bus_space_write_4(t, h, GEM_TX_CONFIG, 949 v|GEM_TX_CONFIG_TXDMA_EN| 950 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 951 952 /* step 10. ERX Configuration */ 953 954 /* Encode Receive Descriptor ring size: four possible values */ 955 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 956 957 /* Enable DMA */ 958 bus_space_write_4(t, h, GEM_RX_CONFIG, 959 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 960 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 961 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 962 /* 963 * The following value is for an OFF Threshold of about 3/4 full 964 * and an ON Threshold of 1/4 full. 965 */ 966 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 967 (3 * sc->sc_rxfifosize / 256) | 968 ( (sc->sc_rxfifosize / 256) << 12)); 969 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 970 971 /* step 11. Configure Media */ 972 mii_mediachg(sc->sc_mii); 973 974 /* step 12. RX_MAC Configuration Register */ 975 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 976 v |= GEM_MAC_RX_ENABLE; 977 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 978 979 /* step 14. Issue Transmit Pending command */ 980 981 /* step 15. Give the reciever a swift kick */ 982 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 983 984 /* Start the one second timer. */ 985 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 986 987 ifp->if_drv_flags |= IFF_DRV_RUNNING; 988 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 989 ifp->if_timer = 0; 990 sc->sc_ifflags = ifp->if_flags; 991} 992 993static int 994gem_load_txmbuf(sc, m0) 995 struct gem_softc *sc; 996 struct mbuf *m0; 997{ 998 struct gem_txdma txd; 999 struct gem_txsoft *txs; 1000 int error; 1001 1002 /* Get a work queue entry. */ 1003 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1004 /* Ran out of descriptors. */ 1005 return (-1); 1006 } 1007 txd.txd_sc = sc; 1008 txd.txd_txs = txs; 1009 txs->txs_firstdesc = sc->sc_txnext; 1010 error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0, 1011 gem_txdma_callback, &txd, BUS_DMA_NOWAIT); 1012 if (error != 0) 1013 goto fail; 1014 if (txs->txs_ndescs == -1) { 1015 error = -1; 1016 goto fail; 1017 } 1018 1019 /* Sync the DMA map. */ 1020 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1021 BUS_DMASYNC_PREWRITE); 1022 1023#ifdef GEM_DEBUG 1024 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, " 1025 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc, 1026 txs->txs_ndescs); 1027#endif 1028 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1029 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1030 txs->txs_mbuf = m0; 1031 1032 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1033 sc->sc_txfree -= txs->txs_ndescs; 1034 return (0); 1035 1036fail: 1037#ifdef GEM_DEBUG 1038 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error); 1039#endif 1040 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1041 return (error); 1042} 1043 1044static void 1045gem_init_regs(sc) 1046 struct gem_softc *sc; 1047{ 1048 bus_space_tag_t t = sc->sc_bustag; 1049 bus_space_handle_t h = sc->sc_h; 1050 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1051 u_int32_t v; 1052 1053 /* These regs are not cleared on reset */ 1054 if (!sc->sc_inited) { 1055 1056 /* Wooo. Magic values. */ 1057 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 1058 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 1059 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 1060 1061 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1062 /* Max frame and max burst size */ 1063 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1064 (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) | 1065 (0x2000 << 16)); 1066 1067 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 1068 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 1069 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1070 /* Dunno.... */ 1071 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1072 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1073 ((laddr[5]<<8)|laddr[4])&0x3ff); 1074 1075 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1076 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1077 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1078 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1079 1080 /* MAC control addr set to 01:80:c2:00:00:01 */ 1081 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1082 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1083 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1084 1085 /* MAC filter addr set to 0:0:0:0:0:0 */ 1086 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1087 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1088 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1089 1090 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1091 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1092 1093 sc->sc_inited = 1; 1094 } 1095 1096 /* Counters need to be zeroed */ 1097 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1098 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1099 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1100 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1101 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1102 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1103 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1104 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1105 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1106 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1107 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1108 1109 /* Un-pause stuff */ 1110#if 0 1111 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1112#else 1113 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 1114#endif 1115 1116 /* 1117 * Set the station address. 1118 */ 1119 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1120 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1121 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1122 1123 /* 1124 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1125 */ 1126 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1127 v = GEM_MAC_XIF_TX_MII_ENA; 1128 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1129 v |= GEM_MAC_XIF_FDPLX_LED; 1130 if (sc->sc_flags & GEM_GIGABIT) 1131 v |= GEM_MAC_XIF_GMII_MODE; 1132 } 1133 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1134} 1135 1136static void 1137gem_start(ifp) 1138 struct ifnet *ifp; 1139{ 1140 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1141 1142 GEM_LOCK(sc); 1143 gem_start_locked(ifp); 1144 GEM_UNLOCK(sc); 1145} 1146 1147static void 1148gem_start_locked(ifp) 1149 struct ifnet *ifp; 1150{ 1151 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1152 struct mbuf *m0 = NULL; 1153 int firsttx, ntx = 0, ofree, txmfail; 1154 1155 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1156 IFF_DRV_RUNNING) 1157 return; 1158 1159 /* 1160 * Remember the previous number of free descriptors and 1161 * the first descriptor we'll use. 1162 */ 1163 ofree = sc->sc_txfree; 1164 firsttx = sc->sc_txnext; 1165 1166#ifdef GEM_DEBUG 1167 CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d", 1168 device_get_name(sc->sc_dev), ofree, firsttx); 1169#endif 1170 1171 /* 1172 * Loop through the send queue, setting up transmit descriptors 1173 * until we drain the queue, or use up all available transmit 1174 * descriptors. 1175 */ 1176 txmfail = 0; 1177 do { 1178 /* 1179 * Grab a packet off the queue. 1180 */ 1181 IF_DEQUEUE(&ifp->if_snd, m0); 1182 if (m0 == NULL) 1183 break; 1184 1185 txmfail = gem_load_txmbuf(sc, m0); 1186 if (txmfail > 0) { 1187 /* Drop the mbuf and complain. */ 1188 printf("gem_start: error %d while loading mbuf dma " 1189 "map\n", txmfail); 1190 continue; 1191 } 1192 /* Not enough descriptors. */ 1193 if (txmfail == -1) { 1194 if (sc->sc_txfree == GEM_MAXTXFREE) 1195 panic("gem_start: mbuf chain too long!"); 1196 IF_PREPEND(&ifp->if_snd, m0); 1197 break; 1198 } 1199 1200 ntx++; 1201 /* Kick the transmitter. */ 1202#ifdef GEM_DEBUG 1203 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d", 1204 device_get_name(sc->sc_dev), sc->sc_txnext); 1205#endif 1206 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1207 sc->sc_txnext); 1208 1209 BPF_MTAP(ifp, m0); 1210 } while (1); 1211 1212 if (txmfail == -1 || sc->sc_txfree == 0) { 1213 /* No more slots left; notify upper layer. */ 1214 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1215 } 1216 1217 if (ntx > 0) { 1218 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1219 1220#ifdef GEM_DEBUG 1221 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1222 device_get_name(sc->sc_dev), firsttx); 1223#endif 1224 1225 /* Set a watchdog timer in case the chip flakes out. */ 1226 ifp->if_timer = 5; 1227#ifdef GEM_DEBUG 1228 CTR2(KTR_GEM, "%s: gem_start: watchdog %d", 1229 device_get_name(sc->sc_dev), ifp->if_timer); 1230#endif 1231 } 1232} 1233 1234/* 1235 * Transmit interrupt. 1236 */ 1237static void 1238gem_tint(sc) 1239 struct gem_softc *sc; 1240{ 1241 struct ifnet *ifp = sc->sc_ifp; 1242 bus_space_tag_t t = sc->sc_bustag; 1243 bus_space_handle_t mac = sc->sc_h; 1244 struct gem_txsoft *txs; 1245 int txlast; 1246 int progress = 0; 1247 1248 1249#ifdef GEM_DEBUG 1250 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 1251#endif 1252 1253 /* 1254 * Unload collision counters 1255 */ 1256 ifp->if_collisions += 1257 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1258 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1259 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1260 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1261 1262 /* 1263 * then clear the hardware counters. 1264 */ 1265 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1266 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1267 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1268 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1269 1270 /* 1271 * Go through our Tx list and free mbufs for those 1272 * frames that have been transmitted. 1273 */ 1274 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1275 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1276 1277#ifdef GEM_DEBUG 1278 if (ifp->if_flags & IFF_DEBUG) { 1279 int i; 1280 printf(" txsoft %p transmit chain:\n", txs); 1281 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1282 printf("descriptor %d: ", i); 1283 printf("gd_flags: 0x%016llx\t", (long long) 1284 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1285 printf("gd_addr: 0x%016llx\n", (long long) 1286 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1287 if (i == txs->txs_lastdesc) 1288 break; 1289 } 1290 } 1291#endif 1292 1293 /* 1294 * In theory, we could harveast some descriptors before 1295 * the ring is empty, but that's a bit complicated. 1296 * 1297 * GEM_TX_COMPLETION points to the last descriptor 1298 * processed +1. 1299 */ 1300 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1301#ifdef GEM_DEBUG 1302 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 1303 "txs->txs_lastdesc = %d, txlast = %d", 1304 txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1305#endif 1306 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1307 if ((txlast >= txs->txs_firstdesc) && 1308 (txlast <= txs->txs_lastdesc)) 1309 break; 1310 } else { 1311 /* Ick -- this command wraps */ 1312 if ((txlast >= txs->txs_firstdesc) || 1313 (txlast <= txs->txs_lastdesc)) 1314 break; 1315 } 1316 1317#ifdef GEM_DEBUG 1318 CTR0(KTR_GEM, "gem_tint: releasing a desc"); 1319#endif 1320 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1321 1322 sc->sc_txfree += txs->txs_ndescs; 1323 1324 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1325 BUS_DMASYNC_POSTWRITE); 1326 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1327 if (txs->txs_mbuf != NULL) { 1328 m_freem(txs->txs_mbuf); 1329 txs->txs_mbuf = NULL; 1330 } 1331 1332 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1333 1334 ifp->if_opackets++; 1335 progress = 1; 1336 } 1337 1338#ifdef GEM_DEBUG 1339 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 1340 "GEM_TX_DATA_PTR %llx " 1341 "GEM_TX_COMPLETION %x", 1342 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1343 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1344 GEM_TX_DATA_PTR_HI) << 32) | 1345 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1346 GEM_TX_DATA_PTR_LO), 1347 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION)); 1348#endif 1349 1350 if (progress) { 1351 if (sc->sc_txfree == GEM_NTXDESC - 1) 1352 sc->sc_txwin = 0; 1353 1354 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */ 1355 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1356 gem_start_locked(ifp); 1357 1358 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1359 ifp->if_timer = 0; 1360 } 1361 1362#ifdef GEM_DEBUG 1363 CTR2(KTR_GEM, "%s: gem_tint: watchdog %d", 1364 device_get_name(sc->sc_dev), ifp->if_timer); 1365#endif 1366} 1367 1368#ifdef GEM_RINT_TIMEOUT 1369static void 1370gem_rint_timeout(arg) 1371 void *arg; 1372{ 1373 struct gem_softc *sc = (struct gem_softc *)arg; 1374 1375 GEM_LOCK_ASSERT(sc, MA_OWNED); 1376 gem_rint(sc); 1377} 1378#endif 1379 1380/* 1381 * Receive interrupt. 1382 */ 1383static void 1384gem_rint(sc) 1385 struct gem_softc *sc; 1386{ 1387 struct ifnet *ifp = sc->sc_ifp; 1388 bus_space_tag_t t = sc->sc_bustag; 1389 bus_space_handle_t h = sc->sc_h; 1390 struct gem_rxsoft *rxs; 1391 struct mbuf *m; 1392 u_int64_t rxstat; 1393 u_int32_t rxcomp; 1394 int i, len, progress = 0; 1395 1396#ifdef GEM_RINT_TIMEOUT 1397 callout_stop(&sc->sc_rx_ch); 1398#endif 1399#ifdef GEM_DEBUG 1400 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 1401#endif 1402 1403 /* 1404 * Read the completion register once. This limits 1405 * how long the following loop can execute. 1406 */ 1407 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1408 1409#ifdef GEM_DEBUG 1410 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 1411 sc->sc_rxptr, rxcomp); 1412#endif 1413 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1414 for (i = sc->sc_rxptr; i != rxcomp; 1415 i = GEM_NEXTRX(i)) { 1416 rxs = &sc->sc_rxsoft[i]; 1417 1418 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1419 1420 if (rxstat & GEM_RD_OWN) { 1421#ifdef GEM_RINT_TIMEOUT 1422 /* 1423 * The descriptor is still marked as owned, although 1424 * it is supposed to have completed. This has been 1425 * observed on some machines. Just exiting here 1426 * might leave the packet sitting around until another 1427 * one arrives to trigger a new interrupt, which is 1428 * generally undesirable, so set up a timeout. 1429 */ 1430 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1431 gem_rint_timeout, sc); 1432#endif 1433 break; 1434 } 1435 1436 progress++; 1437 ifp->if_ipackets++; 1438 1439 if (rxstat & GEM_RD_BAD_CRC) { 1440 ifp->if_ierrors++; 1441 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1442 GEM_INIT_RXDESC(sc, i); 1443 continue; 1444 } 1445 1446#ifdef GEM_DEBUG 1447 if (ifp->if_flags & IFF_DEBUG) { 1448 printf(" rxsoft %p descriptor %d: ", rxs, i); 1449 printf("gd_flags: 0x%016llx\t", (long long) 1450 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1451 printf("gd_addr: 0x%016llx\n", (long long) 1452 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1453 } 1454#endif 1455 1456 /* 1457 * No errors; receive the packet. Note the Gem 1458 * includes the CRC with every packet. 1459 */ 1460 len = GEM_RD_BUFLEN(rxstat); 1461 1462 /* 1463 * Allocate a new mbuf cluster. If that fails, we are 1464 * out of memory, and must drop the packet and recycle 1465 * the buffer that's already attached to this descriptor. 1466 */ 1467 m = rxs->rxs_mbuf; 1468 if (gem_add_rxbuf(sc, i) != 0) { 1469 ifp->if_ierrors++; 1470 GEM_INIT_RXDESC(sc, i); 1471 continue; 1472 } 1473 m->m_data += 2; /* We're already off by two */ 1474 1475 m->m_pkthdr.rcvif = ifp; 1476 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN; 1477 1478 /* Pass it on. */ 1479 GEM_UNLOCK(sc); 1480 (*ifp->if_input)(ifp, m); 1481 GEM_LOCK(sc); 1482 } 1483 1484 if (progress) { 1485 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1486 /* Update the receive pointer. */ 1487 if (i == sc->sc_rxptr) { 1488 device_printf(sc->sc_dev, "rint: ring wrap\n"); 1489 } 1490 sc->sc_rxptr = i; 1491 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1492 } 1493 1494#ifdef GEM_DEBUG 1495 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", 1496 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 1497#endif 1498} 1499 1500 1501/* 1502 * gem_add_rxbuf: 1503 * 1504 * Add a receive buffer to the indicated descriptor. 1505 */ 1506static int 1507gem_add_rxbuf(sc, idx) 1508 struct gem_softc *sc; 1509 int idx; 1510{ 1511 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1512 struct mbuf *m; 1513 bus_dma_segment_t segs[1]; 1514 int error, nsegs; 1515 1516 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1517 if (m == NULL) 1518 return (ENOBUFS); 1519 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1520 1521#ifdef GEM_DEBUG 1522 /* bzero the packet to check dma */ 1523 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1524#endif 1525 1526 if (rxs->rxs_mbuf != NULL) { 1527 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1528 BUS_DMASYNC_POSTREAD); 1529 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1530 } 1531 1532 rxs->rxs_mbuf = m; 1533 1534 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1535 m, segs, &nsegs, BUS_DMA_NOWAIT); 1536 /* If nsegs is wrong then the stack is corrupt. */ 1537 KASSERT(nsegs == 1, ("Too many segments returned!")); 1538 if (error != 0) { 1539 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " 1540 "%d\n", idx, error); 1541 m_freem(m); 1542 return (ENOBUFS); 1543 } 1544 rxs->rxs_paddr = segs[0].ds_addr; 1545 1546 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1547 1548 GEM_INIT_RXDESC(sc, idx); 1549 1550 return (0); 1551} 1552 1553 1554static void 1555gem_eint(sc, status) 1556 struct gem_softc *sc; 1557 u_int status; 1558{ 1559 1560 if ((status & GEM_INTR_MIF) != 0) { 1561 device_printf(sc->sc_dev, "XXXlink status changed\n"); 1562 return; 1563 } 1564 1565 device_printf(sc->sc_dev, "status=%x\n", status); 1566} 1567 1568 1569void 1570gem_intr(v) 1571 void *v; 1572{ 1573 struct gem_softc *sc = (struct gem_softc *)v; 1574 bus_space_tag_t t = sc->sc_bustag; 1575 bus_space_handle_t seb = sc->sc_h; 1576 u_int32_t status; 1577 1578 GEM_LOCK(sc); 1579 status = bus_space_read_4(t, seb, GEM_STATUS); 1580#ifdef GEM_DEBUG 1581 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 1582 device_get_name(sc->sc_dev), (status>>19), 1583 (u_int)status); 1584#endif 1585 1586 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1587 gem_eint(sc, status); 1588 1589 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1590 gem_tint(sc); 1591 1592 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1593 gem_rint(sc); 1594 1595 /* We should eventually do more than just print out error stats. */ 1596 if (status & GEM_INTR_TX_MAC) { 1597 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1598 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1599 device_printf(sc->sc_dev, "MAC tx fault, status %x\n", 1600 txstat); 1601 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1602 gem_init_locked(sc); 1603 } 1604 if (status & GEM_INTR_RX_MAC) { 1605 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1606 /* 1607 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1608 * due to a silicon bug so handle them silently. 1609 */ 1610 if (rxstat & GEM_MAC_RX_OVERFLOW) 1611 gem_init_locked(sc); 1612 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1613 device_printf(sc->sc_dev, "MAC rx fault, status %x\n", 1614 rxstat); 1615 } 1616 GEM_UNLOCK(sc); 1617} 1618 1619 1620static void 1621gem_watchdog(ifp) 1622 struct ifnet *ifp; 1623{ 1624 struct gem_softc *sc = ifp->if_softc; 1625 1626 GEM_LOCK(sc); 1627#ifdef GEM_DEBUG 1628 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1629 "GEM_MAC_RX_CONFIG %x", 1630 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1631 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1632 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)); 1633 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 1634 "GEM_MAC_TX_CONFIG %x", 1635 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 1636 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS), 1637 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 1638#endif 1639 1640 device_printf(sc->sc_dev, "device timeout\n"); 1641 ++ifp->if_oerrors; 1642 1643 /* Try to get more packets going. */ 1644 gem_init_locked(sc); 1645 GEM_UNLOCK(sc); 1646} 1647 1648/* 1649 * Initialize the MII Management Interface 1650 */ 1651static void 1652gem_mifinit(sc) 1653 struct gem_softc *sc; 1654{ 1655 bus_space_tag_t t = sc->sc_bustag; 1656 bus_space_handle_t mif = sc->sc_h; 1657 1658 /* Configure the MIF in frame mode */ 1659 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1660 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1661 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1662} 1663 1664/* 1665 * MII interface 1666 * 1667 * The GEM MII interface supports at least three different operating modes: 1668 * 1669 * Bitbang mode is implemented using data, clock and output enable registers. 1670 * 1671 * Frame mode is implemented by loading a complete frame into the frame 1672 * register and polling the valid bit for completion. 1673 * 1674 * Polling mode uses the frame register but completion is indicated by 1675 * an interrupt. 1676 * 1677 */ 1678int 1679gem_mii_readreg(dev, phy, reg) 1680 device_t dev; 1681 int phy, reg; 1682{ 1683 struct gem_softc *sc = device_get_softc(dev); 1684 bus_space_tag_t t = sc->sc_bustag; 1685 bus_space_handle_t mif = sc->sc_h; 1686 int n; 1687 u_int32_t v; 1688 1689#ifdef GEM_DEBUG_PHY 1690 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1691#endif 1692 1693#if 0 1694 /* Select the desired PHY in the MIF configuration register */ 1695 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1696 /* Clear PHY select bit */ 1697 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1698 if (phy == GEM_PHYAD_EXTERNAL) 1699 /* Set PHY select bit to get at external device */ 1700 v |= GEM_MIF_CONFIG_PHY_SEL; 1701 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1702#endif 1703 1704 /* Construct the frame command */ 1705 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1706 GEM_MIF_FRAME_READ; 1707 1708 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1709 for (n = 0; n < 100; n++) { 1710 DELAY(1); 1711 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1712 if (v & GEM_MIF_FRAME_TA0) 1713 return (v & GEM_MIF_FRAME_DATA); 1714 } 1715 1716 device_printf(sc->sc_dev, "mii_read timeout\n"); 1717 return (0); 1718} 1719 1720int 1721gem_mii_writereg(dev, phy, reg, val) 1722 device_t dev; 1723 int phy, reg, val; 1724{ 1725 struct gem_softc *sc = device_get_softc(dev); 1726 bus_space_tag_t t = sc->sc_bustag; 1727 bus_space_handle_t mif = sc->sc_h; 1728 int n; 1729 u_int32_t v; 1730 1731#ifdef GEM_DEBUG_PHY 1732 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 1733#endif 1734 1735#if 0 1736 /* Select the desired PHY in the MIF configuration register */ 1737 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1738 /* Clear PHY select bit */ 1739 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1740 if (phy == GEM_PHYAD_EXTERNAL) 1741 /* Set PHY select bit to get at external device */ 1742 v |= GEM_MIF_CONFIG_PHY_SEL; 1743 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1744#endif 1745 /* Construct the frame command */ 1746 v = GEM_MIF_FRAME_WRITE | 1747 (phy << GEM_MIF_PHY_SHIFT) | 1748 (reg << GEM_MIF_REG_SHIFT) | 1749 (val & GEM_MIF_FRAME_DATA); 1750 1751 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1752 for (n = 0; n < 100; n++) { 1753 DELAY(1); 1754 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1755 if (v & GEM_MIF_FRAME_TA0) 1756 return (1); 1757 } 1758 1759 device_printf(sc->sc_dev, "mii_write timeout\n"); 1760 return (0); 1761} 1762 1763void 1764gem_mii_statchg(dev) 1765 device_t dev; 1766{ 1767 struct gem_softc *sc = device_get_softc(dev); 1768#ifdef GEM_DEBUG 1769 int instance; 1770#endif 1771 bus_space_tag_t t = sc->sc_bustag; 1772 bus_space_handle_t mac = sc->sc_h; 1773 u_int32_t v; 1774 1775#ifdef GEM_DEBUG 1776 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 1777 if (sc->sc_debug) 1778 printf("gem_mii_statchg: status change: phy = %d\n", 1779 sc->sc_phys[instance]); 1780#endif 1781 1782 /* Set tx full duplex options */ 1783 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1784 DELAY(10000); /* reg must be cleared and delay before changing. */ 1785 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1786 GEM_MAC_TX_ENABLE; 1787 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 1788 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1789 } 1790 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1791 1792 /* XIF Configuration */ 1793 v = GEM_MAC_XIF_LINK_LED; 1794 v |= GEM_MAC_XIF_TX_MII_ENA; 1795 1796 /* If an external transceiver is connected, enable its MII drivers */ 1797 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1798 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1799 /* External MII needs echo disable if half duplex. */ 1800 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 1801 /* turn on full duplex LED */ 1802 v |= GEM_MAC_XIF_FDPLX_LED; 1803 else 1804 /* half duplex -- disable echo */ 1805 v |= GEM_MAC_XIF_ECHO_DISABL; 1806 1807 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T) 1808 v |= GEM_MAC_XIF_GMII_MODE; 1809 else 1810 v &= ~GEM_MAC_XIF_GMII_MODE; 1811 } else { 1812 /* Internal MII needs buf enable */ 1813 v |= GEM_MAC_XIF_MII_BUF_ENA; 1814 } 1815 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1816} 1817 1818int 1819gem_mediachange(ifp) 1820 struct ifnet *ifp; 1821{ 1822 struct gem_softc *sc = ifp->if_softc; 1823 int error; 1824 1825 /* XXX Add support for serial media. */ 1826 1827 GEM_LOCK(sc); 1828 error = mii_mediachg(sc->sc_mii); 1829 GEM_UNLOCK(sc); 1830 return (error); 1831} 1832 1833void 1834gem_mediastatus(ifp, ifmr) 1835 struct ifnet *ifp; 1836 struct ifmediareq *ifmr; 1837{ 1838 struct gem_softc *sc = ifp->if_softc; 1839 1840 GEM_LOCK(sc); 1841 if ((ifp->if_flags & IFF_UP) == 0) { 1842 GEM_UNLOCK(sc); 1843 return; 1844 } 1845 1846 mii_pollstat(sc->sc_mii); 1847 ifmr->ifm_active = sc->sc_mii->mii_media_active; 1848 ifmr->ifm_status = sc->sc_mii->mii_media_status; 1849 GEM_UNLOCK(sc); 1850} 1851 1852/* 1853 * Process an ioctl request. 1854 */ 1855static int 1856gem_ioctl(ifp, cmd, data) 1857 struct ifnet *ifp; 1858 u_long cmd; 1859 caddr_t data; 1860{ 1861 struct gem_softc *sc = ifp->if_softc; 1862 struct ifreq *ifr = (struct ifreq *)data; 1863 int error = 0; 1864 1865 switch (cmd) { 1866 case SIOCSIFFLAGS: 1867 GEM_LOCK(sc); 1868 if (ifp->if_flags & IFF_UP) { 1869 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC) 1870 gem_setladrf(sc); 1871 else 1872 gem_init_locked(sc); 1873 } else { 1874 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1875 gem_stop(ifp, 0); 1876 } 1877 sc->sc_ifflags = ifp->if_flags; 1878 GEM_UNLOCK(sc); 1879 break; 1880 case SIOCADDMULTI: 1881 case SIOCDELMULTI: 1882 GEM_LOCK(sc); 1883 gem_setladrf(sc); 1884 GEM_UNLOCK(sc); 1885 break; 1886 case SIOCGIFMEDIA: 1887 case SIOCSIFMEDIA: 1888 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 1889 break; 1890 default: 1891 error = ether_ioctl(ifp, cmd, data); 1892 break; 1893 } 1894 1895 /* Try to get things going again */ 1896 GEM_LOCK(sc); 1897 if (ifp->if_flags & IFF_UP) 1898 gem_start_locked(ifp); 1899 GEM_UNLOCK(sc); 1900 return (error); 1901} 1902 1903/* 1904 * Set up the logical address filter. 1905 */ 1906static void 1907gem_setladrf(sc) 1908 struct gem_softc *sc; 1909{ 1910 struct ifnet *ifp = sc->sc_ifp; 1911 struct ifmultiaddr *inm; 1912 bus_space_tag_t t = sc->sc_bustag; 1913 bus_space_handle_t h = sc->sc_h; 1914 u_int32_t crc; 1915 u_int32_t hash[16]; 1916 u_int32_t v; 1917 int i; 1918 1919 GEM_LOCK_ASSERT(sc, MA_OWNED); 1920 1921 /* Get current RX configuration */ 1922 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1923 1924 /* 1925 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1926 * and hash filter. Depending on the case, the right bit will be 1927 * enabled. 1928 */ 1929 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1930 GEM_MAC_RX_PROMISC_GRP); 1931 1932 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1933 /* Turn on promiscuous mode */ 1934 v |= GEM_MAC_RX_PROMISCUOUS; 1935 goto chipit; 1936 } 1937 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 1938 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1939 ifp->if_flags |= IFF_ALLMULTI; 1940 v |= GEM_MAC_RX_PROMISC_GRP; 1941 goto chipit; 1942 } 1943 1944 /* 1945 * Set up multicast address filter by passing all multicast addresses 1946 * through a crc generator, and then using the high order 8 bits as an 1947 * index into the 256 bit logical address filter. The high order 4 1948 * bits selects the word, while the other 4 bits select the bit within 1949 * the word (where bit 0 is the MSB). 1950 */ 1951 1952 /* Clear hash table */ 1953 memset(hash, 0, sizeof(hash)); 1954 1955 IF_ADDR_LOCK(ifp); 1956 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 1957 if (inm->ifma_addr->sa_family != AF_LINK) 1958 continue; 1959 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1960 inm->ifma_addr), ETHER_ADDR_LEN); 1961 1962 /* Just want the 8 most significant bits. */ 1963 crc >>= 24; 1964 1965 /* Set the corresponding bit in the filter. */ 1966 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1967 } 1968 IF_ADDR_UNLOCK(ifp); 1969 1970 v |= GEM_MAC_RX_HASH_FILTER; 1971 ifp->if_flags &= ~IFF_ALLMULTI; 1972 1973 /* Now load the hash table into the chip (if we are using it) */ 1974 for (i = 0; i < 16; i++) { 1975 bus_space_write_4(t, h, 1976 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1977 hash[i]); 1978 } 1979 1980chipit: 1981 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1982} 1983