if_gem.c revision 109648
191398Stmm/*
291398Stmm * Copyright (C) 2001 Eduardo Horvath.
3108832Stmm * Copyright (c) 2001-2003 Thomas Moestl
491398Stmm * All rights reserved.
591398Stmm *
691398Stmm * Redistribution and use in source and binary forms, with or without
791398Stmm * modification, are permitted provided that the following conditions
891398Stmm * are met:
991398Stmm * 1. Redistributions of source code must retain the above copyright
1091398Stmm *    notice, this list of conditions and the following disclaimer.
1191398Stmm * 2. Redistributions in binary form must reproduce the above copyright
1291398Stmm *    notice, this list of conditions and the following disclaimer in the
1391398Stmm *    documentation and/or other materials provided with the distribution.
1491398Stmm *
1591398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
1691398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1791398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1891398Stmm * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
1991398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2091398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2191398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2291398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2391398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2491398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2591398Stmm * SUCH DAMAGE.
2691398Stmm *
2799726Sbenno *	from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
2891398Stmm *
2991398Stmm * $FreeBSD: head/sys/dev/gem/if_gem.c 109648 2003-01-21 17:17:01Z tmm $
3091398Stmm */
3191398Stmm
3291398Stmm/*
3391398Stmm * Driver for Sun GEM ethernet controllers.
3491398Stmm */
3591398Stmm
3691398Stmm#define	GEM_DEBUG
3791398Stmm
3891398Stmm#include <sys/param.h>
3991398Stmm#include <sys/systm.h>
4091398Stmm#include <sys/bus.h>
4191398Stmm#include <sys/callout.h>
4295533Smike#include <sys/endian.h>
4391398Stmm#include <sys/mbuf.h>
4491398Stmm#include <sys/malloc.h>
4591398Stmm#include <sys/kernel.h>
4691398Stmm#include <sys/socket.h>
4791398Stmm#include <sys/sockio.h>
4891398Stmm
49105982Stmm#include <net/bpf.h>
5091398Stmm#include <net/ethernet.h>
5191398Stmm#include <net/if.h>
5291398Stmm#include <net/if_arp.h>
5391398Stmm#include <net/if_dl.h>
5491398Stmm#include <net/if_media.h>
5591398Stmm
5691398Stmm#include <machine/bus.h>
5791398Stmm
5891398Stmm#include <dev/mii/mii.h>
5991398Stmm#include <dev/mii/miivar.h>
6091398Stmm
6191398Stmm#include <gem/if_gemreg.h>
6291398Stmm#include <gem/if_gemvar.h>
6391398Stmm
6491398Stmm#define TRIES	10000
6591398Stmm
6692739Salfredstatic void	gem_start(struct ifnet *);
6792739Salfredstatic void	gem_stop(struct ifnet *, int);
6892739Salfredstatic int	gem_ioctl(struct ifnet *, u_long, caddr_t);
6992739Salfredstatic void	gem_cddma_callback(void *, bus_dma_segment_t *, int, int);
70108832Stmmstatic void	gem_rxdma_callback(void *, bus_dma_segment_t *, int,
71108832Stmm    bus_size_t, int);
72108832Stmmstatic void	gem_txdma_callback(void *, bus_dma_segment_t *, int,
73108832Stmm    bus_size_t, int);
7492739Salfredstatic void	gem_tick(void *);
7592739Salfredstatic void	gem_watchdog(struct ifnet *);
7692739Salfredstatic void	gem_init(void *);
7792739Salfredstatic void	gem_init_regs(struct gem_softc *sc);
7892739Salfredstatic int	gem_ringsize(int sz);
7992739Salfredstatic int	gem_meminit(struct gem_softc *);
80108832Stmmstatic int	gem_load_txmbuf(struct gem_softc *, struct mbuf *);
8192739Salfredstatic void	gem_mifinit(struct gem_softc *);
8292739Salfredstatic int	gem_bitwait(struct gem_softc *sc, bus_addr_t r,
8392739Salfred    u_int32_t clr, u_int32_t set);
8492739Salfredstatic int	gem_reset_rx(struct gem_softc *);
8592739Salfredstatic int	gem_reset_tx(struct gem_softc *);
8692739Salfredstatic int	gem_disable_rx(struct gem_softc *);
8792739Salfredstatic int	gem_disable_tx(struct gem_softc *);
8892739Salfredstatic void	gem_rxdrain(struct gem_softc *);
8992739Salfredstatic int	gem_add_rxbuf(struct gem_softc *, int);
9092739Salfredstatic void	gem_setladrf(struct gem_softc *);
9191398Stmm
9292739Salfredstruct mbuf	*gem_get(struct gem_softc *, int, int);
9392739Salfredstatic void	gem_eint(struct gem_softc *, u_int);
9492739Salfredstatic void	gem_rint(struct gem_softc *);
95100587Sjake#if 0
9693045Stmmstatic void	gem_rint_timeout(void *);
97100587Sjake#endif
9892739Salfredstatic void	gem_tint(struct gem_softc *);
9991398Stmm#ifdef notyet
10092739Salfredstatic void	gem_power(int, void *);
10191398Stmm#endif
10291398Stmm
10391398Stmmdevclass_t gem_devclass;
10491398StmmDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
10591398StmmMODULE_DEPEND(gem, miibus, 1, 1, 1);
10691398Stmm
10791398Stmm#ifdef GEM_DEBUG
10891398Stmm#include <sys/ktr.h>
10991398Stmm#define	KTR_GEM		KTR_CT2
11091398Stmm#endif
11191398Stmm
11291398Stmm#define	GEM_NSEGS GEM_NTXSEGS
11391398Stmm
11491398Stmm/*
11591398Stmm * gem_attach:
11691398Stmm *
11791398Stmm *	Attach a Gem interface to the system.
11891398Stmm */
11991398Stmmint
12091398Stmmgem_attach(sc)
12191398Stmm	struct gem_softc *sc;
12291398Stmm{
12391398Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
12491398Stmm	struct mii_softc *child;
12591398Stmm	int i, error;
12699726Sbenno	u_int32_t v;
12791398Stmm
12891398Stmm	/* Make sure the chip is stopped. */
12991398Stmm	ifp->if_softc = sc;
13091398Stmm	gem_reset(sc);
13191398Stmm
13291398Stmm	error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
13391398Stmm	    BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS,
13491398Stmm	    BUS_SPACE_MAXSIZE_32BIT, 0, &sc->sc_pdmatag);
13591398Stmm	if (error)
13691398Stmm		return (error);
13791398Stmm
13891398Stmm	error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
13991398Stmm	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE,
140108832Stmm	    1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW,
141108832Stmm	    &sc->sc_rdmatag);
14291398Stmm	if (error)
143108832Stmm		goto fail_ptag;
14491398Stmm
145108832Stmm	error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
146108832Stmm	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
147108832Stmm	    GEM_TD_BUFSIZE, GEM_NTXSEGS, BUS_SPACE_MAXSIZE_32BIT,
148108832Stmm	    BUS_DMA_ALLOCNOW, &sc->sc_tdmatag);
149108832Stmm	if (error)
150108832Stmm		goto fail_rtag;
151108832Stmm
15291398Stmm	error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0,
15391398Stmm	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
15491398Stmm	    sizeof(struct gem_control_data), 1,
15591398Stmm	    sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW,
15691398Stmm	    &sc->sc_cdmatag);
15791398Stmm	if (error)
158108832Stmm		goto fail_ttag;
15991398Stmm
16091398Stmm	/*
16191398Stmm	 * Allocate the control data structures, and create and load the
16291398Stmm	 * DMA map for it.
16391398Stmm	 */
16491398Stmm	if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
16591398Stmm	    (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) {
16691398Stmm		device_printf(sc->sc_dev, "unable to allocate control data,"
16791398Stmm		    " error = %d\n", error);
168108832Stmm		goto fail_ctag;
16991398Stmm	}
17091398Stmm
17191398Stmm	sc->sc_cddma = 0;
17291398Stmm	if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
17391398Stmm	    sc->sc_control_data, sizeof(struct gem_control_data),
17491398Stmm	    gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
17591398Stmm		device_printf(sc->sc_dev, "unable to load control data DMA "
17691398Stmm		    "map, error = %d\n", error);
177108832Stmm		goto fail_cmem;
17891398Stmm	}
17991398Stmm
18091398Stmm	/*
18191398Stmm	 * Initialize the transmit job descriptors.
18291398Stmm	 */
18391398Stmm	STAILQ_INIT(&sc->sc_txfreeq);
18491398Stmm	STAILQ_INIT(&sc->sc_txdirtyq);
18591398Stmm
18691398Stmm	/*
18791398Stmm	 * Create the transmit buffer DMA maps.
18891398Stmm	 */
18991398Stmm	error = ENOMEM;
19091398Stmm	for (i = 0; i < GEM_TXQUEUELEN; i++) {
19191398Stmm		struct gem_txsoft *txs;
19291398Stmm
19391398Stmm		txs = &sc->sc_txsoft[i];
19491398Stmm		txs->txs_mbuf = NULL;
19591398Stmm		txs->txs_ndescs = 0;
196108832Stmm		if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
19791398Stmm		    &txs->txs_dmamap)) != 0) {
19891398Stmm			device_printf(sc->sc_dev, "unable to create tx DMA map "
19991398Stmm			    "%d, error = %d\n", i, error);
200108832Stmm			goto fail_txd;
20191398Stmm		}
20291398Stmm		STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
20391398Stmm	}
20491398Stmm
20591398Stmm	/*
20691398Stmm	 * Create the receive buffer DMA maps.
20791398Stmm	 */
20891398Stmm	for (i = 0; i < GEM_NRXDESC; i++) {
209108832Stmm		if ((error = bus_dmamap_create(sc->sc_rdmatag, 0,
21091398Stmm		    &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
21191398Stmm			device_printf(sc->sc_dev, "unable to create rx DMA map "
21291398Stmm			    "%d, error = %d\n", i, error);
213108832Stmm			goto fail_rxd;
21491398Stmm		}
21591398Stmm		sc->sc_rxsoft[i].rxs_mbuf = NULL;
21691398Stmm	}
21791398Stmm
21891398Stmm
21991398Stmm	gem_mifinit(sc);
22091398Stmm
22191398Stmm	if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange,
22291398Stmm	    gem_mediastatus)) != 0) {
22391398Stmm		device_printf(sc->sc_dev, "phy probe failed: %d\n", error);
224108832Stmm		goto fail_rxd;
22591398Stmm	}
22691398Stmm	sc->sc_mii = device_get_softc(sc->sc_miibus);
22791398Stmm
22891398Stmm	/*
22991398Stmm	 * From this point forward, the attachment cannot fail.  A failure
23091398Stmm	 * before this point releases all resources that may have been
23191398Stmm	 * allocated.
23291398Stmm	 */
23391398Stmm
23491398Stmm	/* Announce ourselves. */
23591398Stmm	device_printf(sc->sc_dev, "Ethernet address:");
23691398Stmm	for (i = 0; i < 6; i++)
23791398Stmm		printf("%c%02x", i > 0 ? ':' : ' ', sc->sc_arpcom.ac_enaddr[i]);
23891398Stmm
23999726Sbenno	/* Get RX FIFO size */
24099726Sbenno	sc->sc_rxfifosize = 64 *
24199726Sbenno	    bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
24299726Sbenno	printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024);
24399726Sbenno
24499726Sbenno	/* Get TX FIFO size */
24599726Sbenno	v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
24699726Sbenno	printf(", %uKB TX fifo\n", v / 16);
24799726Sbenno
24891398Stmm	/* Initialize ifnet structure. */
24991398Stmm	ifp->if_softc = sc;
25091398Stmm	ifp->if_unit = device_get_unit(sc->sc_dev);
25191398Stmm	ifp->if_name = "gem";
25291398Stmm	ifp->if_mtu = ETHERMTU;
25391398Stmm	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
25491398Stmm	ifp->if_start = gem_start;
25591398Stmm	ifp->if_ioctl = gem_ioctl;
25691398Stmm	ifp->if_watchdog = gem_watchdog;
25791398Stmm	ifp->if_init = gem_init;
25891398Stmm	ifp->if_output = ether_output;
25991398Stmm	ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN;
26091398Stmm	/*
26191398Stmm	 * Walk along the list of attached MII devices and
26291398Stmm	 * establish an `MII instance' to `phy number'
26391398Stmm	 * mapping. We'll use this mapping in media change
26491398Stmm	 * requests to determine which phy to use to program
26591398Stmm	 * the MIF configuration register.
26691398Stmm	 */
26791398Stmm	for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL;
26891398Stmm	     child = LIST_NEXT(child, mii_list)) {
26991398Stmm		/*
27091398Stmm		 * Note: we support just two PHYs: the built-in
27191398Stmm		 * internal device and an external on the MII
27291398Stmm		 * connector.
27391398Stmm		 */
27491398Stmm		if (child->mii_phy > 1 || child->mii_inst > 1) {
27591398Stmm			device_printf(sc->sc_dev, "cannot accomodate "
27691398Stmm			    "MII device %s at phy %d, instance %d\n",
27791398Stmm			    device_get_name(child->mii_dev),
27891398Stmm			    child->mii_phy, child->mii_inst);
27991398Stmm			continue;
28091398Stmm		}
28191398Stmm
28291398Stmm		sc->sc_phys[child->mii_inst] = child->mii_phy;
28391398Stmm	}
28491398Stmm
28591398Stmm	/*
28691398Stmm	 * Now select and activate the PHY we will use.
28791398Stmm	 *
28891398Stmm	 * The order of preference is External (MDI1),
28991398Stmm	 * Internal (MDI0), Serial Link (no MII).
29091398Stmm	 */
29191398Stmm	if (sc->sc_phys[1]) {
29291398Stmm#ifdef GEM_DEBUG
29391398Stmm		printf("using external phy\n");
29491398Stmm#endif
29591398Stmm		sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
29691398Stmm	} else {
29791398Stmm#ifdef GEM_DEBUG
29891398Stmm		printf("using internal phy\n");
29991398Stmm#endif
30091398Stmm		sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
30191398Stmm	}
30291398Stmm	bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG,
30391398Stmm	    sc->sc_mif_config);
30491398Stmm	/* Attach the interface. */
305106937Ssam	ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr);
30691398Stmm
30791398Stmm#if notyet
30891398Stmm	/*
30991398Stmm	 * Add a suspend hook to make sure we come back up after a
31091398Stmm	 * resume.
31191398Stmm	 */
31291398Stmm	sc->sc_powerhook = powerhook_establish(gem_power, sc);
31391398Stmm	if (sc->sc_powerhook == NULL)
31491398Stmm		device_printf(sc->sc_dev, "WARNING: unable to establish power "
31591398Stmm		    "hook\n");
31691398Stmm#endif
31791398Stmm
31891398Stmm	callout_init(&sc->sc_tick_ch, 0);
31993045Stmm	callout_init(&sc->sc_rx_ch, 0);
32091398Stmm	return (0);
32191398Stmm
32291398Stmm	/*
32391398Stmm	 * Free any resources we've allocated during the failed attach
32491398Stmm	 * attempt.  Do this in reverse order and fall through.
32591398Stmm	 */
326108832Stmmfail_rxd:
32791398Stmm	for (i = 0; i < GEM_NRXDESC; i++) {
32891398Stmm		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
329108832Stmm			bus_dmamap_destroy(sc->sc_rdmatag,
33091398Stmm			    sc->sc_rxsoft[i].rxs_dmamap);
33191398Stmm	}
332108832Stmmfail_txd:
33391398Stmm	for (i = 0; i < GEM_TXQUEUELEN; i++) {
33491398Stmm		if (sc->sc_txsoft[i].txs_dmamap != NULL)
335108832Stmm			bus_dmamap_destroy(sc->sc_tdmatag,
33691398Stmm			    sc->sc_txsoft[i].txs_dmamap);
33791398Stmm	}
338108832Stmm	bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
339108832Stmmfail_cmem:
34091398Stmm	bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
34191398Stmm	    sc->sc_cddmamap);
342108832Stmmfail_ctag:
34391398Stmm	bus_dma_tag_destroy(sc->sc_cdmatag);
344108832Stmmfail_ttag:
345108832Stmm	bus_dma_tag_destroy(sc->sc_tdmatag);
346108832Stmmfail_rtag:
347108832Stmm	bus_dma_tag_destroy(sc->sc_rdmatag);
348108832Stmmfail_ptag:
34991398Stmm	bus_dma_tag_destroy(sc->sc_pdmatag);
35091398Stmm	return (error);
35191398Stmm}
35291398Stmm
353108964Stmmvoid
354108964Stmmgem_detach(sc)
355108964Stmm	struct gem_softc *sc;
356108964Stmm{
357108964Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
358108964Stmm	int i;
359108964Stmm
360108964Stmm	ether_ifdetach(ifp);
361108964Stmm	gem_stop(ifp, 1);
362108964Stmm	device_delete_child(sc->sc_dev, sc->sc_miibus);
363108964Stmm
364108964Stmm	for (i = 0; i < GEM_NRXDESC; i++) {
365108964Stmm		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
366108964Stmm			bus_dmamap_destroy(sc->sc_rdmatag,
367108964Stmm			    sc->sc_rxsoft[i].rxs_dmamap);
368108964Stmm	}
369108964Stmm	for (i = 0; i < GEM_TXQUEUELEN; i++) {
370108964Stmm		if (sc->sc_txsoft[i].txs_dmamap != NULL)
371108964Stmm			bus_dmamap_destroy(sc->sc_tdmatag,
372108964Stmm			    sc->sc_txsoft[i].txs_dmamap);
373108964Stmm	}
374109648Stmm	GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
375109648Stmm	GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE);
376108964Stmm	bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
377108964Stmm	bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
378108964Stmm	    sc->sc_cddmamap);
379108964Stmm	bus_dma_tag_destroy(sc->sc_cdmatag);
380108964Stmm	bus_dma_tag_destroy(sc->sc_tdmatag);
381108964Stmm	bus_dma_tag_destroy(sc->sc_rdmatag);
382108964Stmm	bus_dma_tag_destroy(sc->sc_pdmatag);
383108964Stmm}
384108964Stmm
385108964Stmmvoid
386108964Stmmgem_suspend(sc)
387108964Stmm	struct gem_softc *sc;
388108964Stmm{
389108964Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
390108964Stmm
391108964Stmm	gem_stop(ifp, 0);
392108964Stmm}
393108964Stmm
394108964Stmmvoid
395108964Stmmgem_resume(sc)
396108964Stmm	struct gem_softc *sc;
397108964Stmm{
398108964Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
399108964Stmm
400108964Stmm	if (ifp->if_flags & IFF_UP)
401108964Stmm		gem_init(ifp);
402108964Stmm}
403108964Stmm
40491398Stmmstatic void
40591398Stmmgem_cddma_callback(xsc, segs, nsegs, error)
40691398Stmm	void *xsc;
40791398Stmm	bus_dma_segment_t *segs;
40891398Stmm	int nsegs;
40991398Stmm	int error;
41091398Stmm{
41191398Stmm	struct gem_softc *sc = (struct gem_softc *)xsc;
41291398Stmm
41391398Stmm	if (error != 0)
41491398Stmm		return;
41591398Stmm	if (nsegs != 1) {
41691398Stmm		/* can't happen... */
41791398Stmm		panic("gem_cddma_callback: bad control buffer segment count");
41891398Stmm	}
41991398Stmm	sc->sc_cddma = segs[0].ds_addr;
42091398Stmm}
42191398Stmm
42291398Stmmstatic void
423108832Stmmgem_rxdma_callback(xsc, segs, nsegs, totsz, error)
42491398Stmm	void *xsc;
42591398Stmm	bus_dma_segment_t *segs;
42691398Stmm	int nsegs;
427108832Stmm	bus_size_t totsz;
42891398Stmm	int error;
42991398Stmm{
43091398Stmm	struct gem_rxsoft *rxs = (struct gem_rxsoft *)xsc;
43191398Stmm
43291398Stmm	if (error != 0)
43391398Stmm		return;
434108832Stmm	KASSERT(nsegs == 1, ("gem_rxdma_callback: bad dma segment count"));
43591398Stmm	rxs->rxs_paddr = segs[0].ds_addr;
43691398Stmm}
43791398Stmm
43891398Stmmstatic void
439108832Stmmgem_txdma_callback(xsc, segs, nsegs, totsz, error)
44091398Stmm	void *xsc;
44191398Stmm	bus_dma_segment_t *segs;
44291398Stmm	int nsegs;
443108832Stmm	bus_size_t totsz;
44491398Stmm	int error;
44591398Stmm{
446108832Stmm	struct gem_txdma *txd = (struct gem_txdma *)xsc;
447108832Stmm	struct gem_softc *sc = txd->txd_sc;
448108832Stmm	struct gem_txsoft *txs = txd->txd_txs;
449108832Stmm	bus_size_t len = 0;
450108832Stmm	uint64_t flags = 0;
451108832Stmm	int seg, nexttx;
45291398Stmm
45391398Stmm	if (error != 0)
45491398Stmm		return;
455108832Stmm	/*
456108832Stmm	 * Ensure we have enough descriptors free to describe
457108832Stmm	 * the packet.  Note, we always reserve one descriptor
458108832Stmm	 * at the end of the ring as a termination point, to
459108832Stmm	 * prevent wrap-around.
460108832Stmm	 */
461108832Stmm	if (nsegs > sc->sc_txfree - 1) {
462108832Stmm		txs->txs_ndescs = -1;
463108832Stmm		return;
464108832Stmm	}
465108832Stmm	txs->txs_ndescs = nsegs;
46691398Stmm
467108832Stmm	nexttx = txs->txs_firstdesc;
46891398Stmm	/*
46991398Stmm	 * Initialize the transmit descriptors.
47091398Stmm	 */
47191398Stmm	for (seg = 0; seg < nsegs;
472108832Stmm	     seg++, nexttx = GEM_NEXTTX(nexttx)) {
47391398Stmm		CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len "
474108832Stmm		    "%lx, addr %#lx (%#lx)",  seg, nexttx,
47591398Stmm		    segs[seg].ds_len, segs[seg].ds_addr,
476108832Stmm		    GEM_DMA_WRITE(sc, segs[seg].ds_addr));
477108832Stmm
478108832Stmm		if (segs[seg].ds_len == 0)
479108832Stmm			continue;
480108832Stmm		sc->sc_txdescs[nexttx].gd_addr =
481108832Stmm		    GEM_DMA_WRITE(sc, segs[seg].ds_addr);
482108832Stmm		KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE,
483108832Stmm		    ("gem_txdma_callback: segment size too large!"));
48491398Stmm		flags = segs[seg].ds_len & GEM_TD_BUFSIZE;
485108832Stmm		if (len == 0) {
48691398Stmm			CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, "
487108832Stmm			    "tx %d", seg, nexttx);
48891398Stmm			flags |= GEM_TD_START_OF_PACKET;
489108832Stmm			if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
490108832Stmm				sc->sc_txwin = 0;
49199726Sbenno				flags |= GEM_TD_INTERRUPT_ME;
49299726Sbenno			}
49391398Stmm		}
494108832Stmm		if (len + segs[seg].ds_len == totsz) {
49591398Stmm			CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, "
496108832Stmm			    "tx %d", seg, nexttx);
49791398Stmm			flags |= GEM_TD_END_OF_PACKET;
49891398Stmm		}
499108832Stmm		sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags);
500108832Stmm		txs->txs_lastdesc = nexttx;
501108832Stmm		len += segs[seg].ds_len;
50291398Stmm	}
503108832Stmm	KASSERT((flags & GEM_TD_END_OF_PACKET) != 0,
504108832Stmm	    ("gem_txdma_callback: missed end of packet!"));
50591398Stmm}
50691398Stmm
50791398Stmmstatic void
50891398Stmmgem_tick(arg)
50991398Stmm	void *arg;
51091398Stmm{
51191398Stmm	struct gem_softc *sc = arg;
51291398Stmm	int s;
51391398Stmm
51491398Stmm	s = splnet();
51591398Stmm	mii_tick(sc->sc_mii);
51691398Stmm	splx(s);
51791398Stmm
51891398Stmm	callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
51991398Stmm}
52091398Stmm
52191398Stmmstatic int
52291398Stmmgem_bitwait(sc, r, clr, set)
52391398Stmm	struct gem_softc *sc;
52491398Stmm	bus_addr_t r;
52591398Stmm	u_int32_t clr;
52691398Stmm	u_int32_t set;
52791398Stmm{
52891398Stmm	int i;
52991398Stmm	u_int32_t reg;
53091398Stmm
53191398Stmm	for (i = TRIES; i--; DELAY(100)) {
53291398Stmm		reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r);
53391398Stmm		if ((r & clr) == 0 && (r & set) == set)
53491398Stmm			return (1);
53591398Stmm	}
53691398Stmm	return (0);
53791398Stmm}
53891398Stmm
53991398Stmmvoid
54091398Stmmgem_reset(sc)
54191398Stmm	struct gem_softc *sc;
54291398Stmm{
54391398Stmm	bus_space_tag_t t = sc->sc_bustag;
54491398Stmm	bus_space_handle_t h = sc->sc_h;
54591398Stmm	int s;
54691398Stmm
54791398Stmm	s = splnet();
54891398Stmm	CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev));
54991398Stmm	gem_reset_rx(sc);
55091398Stmm	gem_reset_tx(sc);
55191398Stmm
55291398Stmm	/* Do a full reset */
55391398Stmm	bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
55491398Stmm	if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
55591398Stmm		device_printf(sc->sc_dev, "cannot reset device\n");
55691398Stmm	splx(s);
55791398Stmm}
55891398Stmm
55991398Stmm
56091398Stmm/*
56191398Stmm * gem_rxdrain:
56291398Stmm *
56391398Stmm *	Drain the receive queue.
56491398Stmm */
56591398Stmmstatic void
56691398Stmmgem_rxdrain(sc)
56791398Stmm	struct gem_softc *sc;
56891398Stmm{
56991398Stmm	struct gem_rxsoft *rxs;
57091398Stmm	int i;
57191398Stmm
57291398Stmm	for (i = 0; i < GEM_NRXDESC; i++) {
57391398Stmm		rxs = &sc->sc_rxsoft[i];
57491398Stmm		if (rxs->rxs_mbuf != NULL) {
575109648Stmm			bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
576109648Stmm			    BUS_DMASYNC_POSTREAD);
577108832Stmm			bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
57891398Stmm			m_freem(rxs->rxs_mbuf);
57991398Stmm			rxs->rxs_mbuf = NULL;
58091398Stmm		}
58191398Stmm	}
58291398Stmm}
58391398Stmm
58491398Stmm/*
58591398Stmm * Reset the whole thing.
58691398Stmm */
58791398Stmmstatic void
58891398Stmmgem_stop(ifp, disable)
58991398Stmm	struct ifnet *ifp;
59091398Stmm	int disable;
59191398Stmm{
59291398Stmm	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
59391398Stmm	struct gem_txsoft *txs;
59491398Stmm
59591398Stmm	CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev));
59691398Stmm
59791398Stmm	callout_stop(&sc->sc_tick_ch);
59891398Stmm
59991398Stmm	/* XXX - Should we reset these instead? */
60091398Stmm	gem_disable_tx(sc);
60191398Stmm	gem_disable_rx(sc);
60291398Stmm
60391398Stmm	/*
60491398Stmm	 * Release any queued transmit buffers.
60591398Stmm	 */
60691398Stmm	while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
60791398Stmm		STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
60891398Stmm		if (txs->txs_ndescs != 0) {
609109648Stmm			bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
610109648Stmm			    BUS_DMASYNC_POSTWRITE);
611108832Stmm			bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
61291398Stmm			if (txs->txs_mbuf != NULL) {
61391398Stmm				m_freem(txs->txs_mbuf);
61491398Stmm				txs->txs_mbuf = NULL;
61591398Stmm			}
61691398Stmm		}
61791398Stmm		STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
61891398Stmm	}
61991398Stmm
62091398Stmm	if (disable)
62191398Stmm		gem_rxdrain(sc);
62291398Stmm
62391398Stmm	/*
62491398Stmm	 * Mark the interface down and cancel the watchdog timer.
62591398Stmm	 */
62691398Stmm	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
62791398Stmm	ifp->if_timer = 0;
62891398Stmm}
62991398Stmm
63091398Stmm/*
63191398Stmm * Reset the receiver
63291398Stmm */
63391398Stmmint
63491398Stmmgem_reset_rx(sc)
63591398Stmm	struct gem_softc *sc;
63691398Stmm{
63791398Stmm	bus_space_tag_t t = sc->sc_bustag;
63891398Stmm	bus_space_handle_t h = sc->sc_h;
63991398Stmm
64091398Stmm	/*
64191398Stmm	 * Resetting while DMA is in progress can cause a bus hang, so we
64291398Stmm	 * disable DMA first.
64391398Stmm	 */
64491398Stmm	gem_disable_rx(sc);
64591398Stmm	bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
64691398Stmm	/* Wait till it finishes */
64791398Stmm	if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
64891398Stmm		device_printf(sc->sc_dev, "cannot disable read dma\n");
64991398Stmm
65091398Stmm	/* Wait 5ms extra. */
65191398Stmm	DELAY(5000);
65291398Stmm
65391398Stmm	/* Finally, reset the ERX */
65491398Stmm	bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX);
65591398Stmm	/* Wait till it finishes */
65691398Stmm	if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
65791398Stmm		device_printf(sc->sc_dev, "cannot reset receiver\n");
65891398Stmm		return (1);
65991398Stmm	}
66091398Stmm	return (0);
66191398Stmm}
66291398Stmm
66391398Stmm
66491398Stmm/*
66591398Stmm * Reset the transmitter
66691398Stmm */
66791398Stmmstatic int
66891398Stmmgem_reset_tx(sc)
66991398Stmm	struct gem_softc *sc;
67091398Stmm{
67191398Stmm	bus_space_tag_t t = sc->sc_bustag;
67291398Stmm	bus_space_handle_t h = sc->sc_h;
67391398Stmm	int i;
67491398Stmm
67591398Stmm	/*
67691398Stmm	 * Resetting while DMA is in progress can cause a bus hang, so we
67791398Stmm	 * disable DMA first.
67891398Stmm	 */
67991398Stmm	gem_disable_tx(sc);
68091398Stmm	bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
68191398Stmm	/* Wait till it finishes */
68291398Stmm	if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
68391398Stmm		device_printf(sc->sc_dev, "cannot disable read dma\n");
68491398Stmm
68591398Stmm	/* Wait 5ms extra. */
68691398Stmm	DELAY(5000);
68791398Stmm
68891398Stmm	/* Finally, reset the ETX */
68991398Stmm	bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX);
69091398Stmm	/* Wait till it finishes */
69191398Stmm	for (i = TRIES; i--; DELAY(100))
69291398Stmm		if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0)
69391398Stmm			break;
69491398Stmm	if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
69591398Stmm		device_printf(sc->sc_dev, "cannot reset receiver\n");
69691398Stmm		return (1);
69791398Stmm	}
69891398Stmm	return (0);
69991398Stmm}
70091398Stmm
70191398Stmm/*
70291398Stmm * disable receiver.
70391398Stmm */
70491398Stmmstatic int
70591398Stmmgem_disable_rx(sc)
70691398Stmm	struct gem_softc *sc;
70791398Stmm{
70891398Stmm	bus_space_tag_t t = sc->sc_bustag;
70991398Stmm	bus_space_handle_t h = sc->sc_h;
71091398Stmm	u_int32_t cfg;
71191398Stmm
71291398Stmm	/* Flip the enable bit */
71391398Stmm	cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
71491398Stmm	cfg &= ~GEM_MAC_RX_ENABLE;
71591398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
71691398Stmm
71791398Stmm	/* Wait for it to finish */
71891398Stmm	return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
71991398Stmm}
72091398Stmm
72191398Stmm/*
72291398Stmm * disable transmitter.
72391398Stmm */
72491398Stmmstatic int
72591398Stmmgem_disable_tx(sc)
72691398Stmm	struct gem_softc *sc;
72791398Stmm{
72891398Stmm	bus_space_tag_t t = sc->sc_bustag;
72991398Stmm	bus_space_handle_t h = sc->sc_h;
73091398Stmm	u_int32_t cfg;
73191398Stmm
73291398Stmm	/* Flip the enable bit */
73391398Stmm	cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
73491398Stmm	cfg &= ~GEM_MAC_TX_ENABLE;
73591398Stmm	bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
73691398Stmm
73791398Stmm	/* Wait for it to finish */
73891398Stmm	return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
73991398Stmm}
74091398Stmm
74191398Stmm/*
74291398Stmm * Initialize interface.
74391398Stmm */
74491398Stmmstatic int
74591398Stmmgem_meminit(sc)
74691398Stmm	struct gem_softc *sc;
74791398Stmm{
74891398Stmm	struct gem_rxsoft *rxs;
74991398Stmm	int i, error;
75091398Stmm
75191398Stmm	/*
75291398Stmm	 * Initialize the transmit descriptor ring.
75391398Stmm	 */
75491398Stmm	memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
75591398Stmm	for (i = 0; i < GEM_NTXDESC; i++) {
75691398Stmm		sc->sc_txdescs[i].gd_flags = 0;
75791398Stmm		sc->sc_txdescs[i].gd_addr = 0;
75891398Stmm	}
759108832Stmm	sc->sc_txfree = GEM_MAXTXFREE;
76091398Stmm	sc->sc_txnext = 0;
76199726Sbenno	sc->sc_txwin = 0;
76291398Stmm
76391398Stmm	/*
76491398Stmm	 * Initialize the receive descriptor and receive job
76591398Stmm	 * descriptor rings.
76691398Stmm	 */
76791398Stmm	for (i = 0; i < GEM_NRXDESC; i++) {
76891398Stmm		rxs = &sc->sc_rxsoft[i];
76991398Stmm		if (rxs->rxs_mbuf == NULL) {
77091398Stmm			if ((error = gem_add_rxbuf(sc, i)) != 0) {
77191398Stmm				device_printf(sc->sc_dev, "unable to "
77291398Stmm				    "allocate or map rx buffer %d, error = "
77391398Stmm				    "%d\n", i, error);
77491398Stmm				/*
77591398Stmm				 * XXX Should attempt to run with fewer receive
77691398Stmm				 * XXX buffers instead of just failing.
77791398Stmm				 */
77891398Stmm				gem_rxdrain(sc);
77991398Stmm				return (1);
78091398Stmm			}
78191398Stmm		} else
78291398Stmm			GEM_INIT_RXDESC(sc, i);
78391398Stmm	}
78491398Stmm	sc->sc_rxptr = 0;
785109648Stmm	GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
786109648Stmm	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
78791398Stmm
78891398Stmm	return (0);
78991398Stmm}
79091398Stmm
79191398Stmmstatic int
79291398Stmmgem_ringsize(sz)
79391398Stmm	int sz;
79491398Stmm{
79591398Stmm	int v = 0;
79691398Stmm
79791398Stmm	switch (sz) {
79891398Stmm	case 32:
79991398Stmm		v = GEM_RING_SZ_32;
80091398Stmm		break;
80191398Stmm	case 64:
80291398Stmm		v = GEM_RING_SZ_64;
80391398Stmm		break;
80491398Stmm	case 128:
80591398Stmm		v = GEM_RING_SZ_128;
80691398Stmm		break;
80791398Stmm	case 256:
80891398Stmm		v = GEM_RING_SZ_256;
80991398Stmm		break;
81091398Stmm	case 512:
81191398Stmm		v = GEM_RING_SZ_512;
81291398Stmm		break;
81391398Stmm	case 1024:
81491398Stmm		v = GEM_RING_SZ_1024;
81591398Stmm		break;
81691398Stmm	case 2048:
81791398Stmm		v = GEM_RING_SZ_2048;
81891398Stmm		break;
81991398Stmm	case 4096:
82091398Stmm		v = GEM_RING_SZ_4096;
82191398Stmm		break;
82291398Stmm	case 8192:
82391398Stmm		v = GEM_RING_SZ_8192;
82491398Stmm		break;
82591398Stmm	default:
82691398Stmm		printf("gem: invalid Receive Descriptor ring size\n");
82791398Stmm		break;
82891398Stmm	}
82991398Stmm	return (v);
83091398Stmm}
83191398Stmm
83291398Stmm/*
83391398Stmm * Initialization of interface; set up initialization block
83491398Stmm * and transmit/receive descriptor rings.
83591398Stmm */
83691398Stmmstatic void
83791398Stmmgem_init(xsc)
83891398Stmm	void *xsc;
83991398Stmm{
84091398Stmm	struct gem_softc *sc = (struct gem_softc *)xsc;
84191398Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
84291398Stmm	bus_space_tag_t t = sc->sc_bustag;
84391398Stmm	bus_space_handle_t h = sc->sc_h;
84491398Stmm	int s;
84591398Stmm	u_int32_t v;
84691398Stmm
84791398Stmm	s = splnet();
84891398Stmm
84991398Stmm	CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev));
85091398Stmm	/*
85191398Stmm	 * Initialization sequence. The numbered steps below correspond
85291398Stmm	 * to the sequence outlined in section 6.3.5.1 in the Ethernet
85391398Stmm	 * Channel Engine manual (part of the PCIO manual).
85491398Stmm	 * See also the STP2002-STQ document from Sun Microsystems.
85591398Stmm	 */
85691398Stmm
85791398Stmm	/* step 1 & 2. Reset the Ethernet Channel */
85891398Stmm	gem_stop(&sc->sc_arpcom.ac_if, 0);
85991398Stmm	gem_reset(sc);
86091398Stmm	CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev));
86191398Stmm
86291398Stmm	/* Re-initialize the MIF */
86391398Stmm	gem_mifinit(sc);
86491398Stmm
86591398Stmm	/* step 3. Setup data structures in host memory */
86691398Stmm	gem_meminit(sc);
86791398Stmm
86891398Stmm	/* step 4. TX MAC registers & counters */
86991398Stmm	gem_init_regs(sc);
87091398Stmm	/* XXX: VLAN code from NetBSD temporarily removed. */
87191398Stmm	bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
87291398Stmm            (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16));
87391398Stmm
87491398Stmm	/* step 5. RX MAC registers & counters */
87591398Stmm	gem_setladrf(sc);
87691398Stmm
87791398Stmm	/* step 6 & 7. Program Descriptor Ring Base Addresses */
87891398Stmm	/* NOTE: we use only 32-bit DMA addresses here. */
87991398Stmm	bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
88091398Stmm	bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
88191398Stmm
88291398Stmm	bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
88391398Stmm	bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
88491398Stmm	CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
88591398Stmm	    GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
88691398Stmm
88791398Stmm	/* step 8. Global Configuration & Interrupt Mask */
88891398Stmm	bus_space_write_4(t, h, GEM_INTMASK,
88991398Stmm		      ~(GEM_INTR_TX_INTME|
89091398Stmm			GEM_INTR_TX_EMPTY|
89191398Stmm			GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
89291398Stmm			GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
89391398Stmm			GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
89491398Stmm			GEM_INTR_BERR));
89599726Sbenno	bus_space_write_4(t, h, GEM_MAC_RX_MASK,
89699726Sbenno			GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
89791398Stmm	bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
89891398Stmm	bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
89991398Stmm
90091398Stmm	/* step 9. ETX Configuration: use mostly default values */
90191398Stmm
90291398Stmm	/* Enable DMA */
90391398Stmm	v = gem_ringsize(GEM_NTXDESC /*XXX*/);
90491398Stmm	bus_space_write_4(t, h, GEM_TX_CONFIG,
90591398Stmm		v|GEM_TX_CONFIG_TXDMA_EN|
90691398Stmm		((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
90791398Stmm
90891398Stmm	/* step 10. ERX Configuration */
90991398Stmm
91091398Stmm	/* Encode Receive Descriptor ring size: four possible values */
91191398Stmm	v = gem_ringsize(GEM_NRXDESC /*XXX*/);
91291398Stmm
91391398Stmm	/* Enable DMA */
91491398Stmm	bus_space_write_4(t, h, GEM_RX_CONFIG,
91591398Stmm		v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
91691398Stmm		(2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
91791398Stmm		(0<<GEM_RX_CONFIG_CXM_START_SHFT));
91891398Stmm	/*
91999726Sbenno	 * The following value is for an OFF Threshold of about 3/4 full
92099726Sbenno	 * and an ON Threshold of 1/4 full.
92191398Stmm	 */
92299726Sbenno	bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
92399726Sbenno	    (3 * sc->sc_rxfifosize / 256) |
92499726Sbenno	    (   (sc->sc_rxfifosize / 256) << 12));
92599726Sbenno	bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
92691398Stmm
92791398Stmm	/* step 11. Configure Media */
92899726Sbenno	mii_mediachg(sc->sc_mii);
92991398Stmm
93091398Stmm	/* step 12. RX_MAC Configuration Register */
93191398Stmm	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
93291398Stmm	v |= GEM_MAC_RX_ENABLE;
93391398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
93491398Stmm
93591398Stmm	/* step 14. Issue Transmit Pending command */
93691398Stmm
93791398Stmm	/* step 15.  Give the reciever a swift kick */
93891398Stmm	bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
93991398Stmm
94091398Stmm	/* Start the one second timer. */
94191398Stmm	callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
94291398Stmm
94391398Stmm	ifp->if_flags |= IFF_RUNNING;
94491398Stmm	ifp->if_flags &= ~IFF_OACTIVE;
94591398Stmm	ifp->if_timer = 0;
94699726Sbenno	sc->sc_ifflags = ifp->if_flags;
94791398Stmm	splx(s);
94891398Stmm}
94991398Stmm
95091398Stmmstatic int
951108832Stmmgem_load_txmbuf(sc, m0)
95291398Stmm	struct gem_softc *sc;
95391398Stmm	struct mbuf *m0;
95491398Stmm{
95591398Stmm	struct gem_txdma txd;
95691398Stmm	struct gem_txsoft *txs;
957108832Stmm	int error;
95891398Stmm
959108832Stmm	/* Get a work queue entry. */
960108832Stmm	if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
961108832Stmm		/* Ran out of descriptors. */
962108832Stmm		return (-1);
963108832Stmm	}
96491398Stmm	txd.txd_sc = sc;
965108832Stmm	txd.txd_txs = txs;
966108832Stmm	txs->txs_mbuf = m0;
967108832Stmm	txs->txs_firstdesc = sc->sc_txnext;
968108832Stmm	error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0,
969108832Stmm	    gem_txdma_callback, &txd, BUS_DMA_NOWAIT);
970108832Stmm	if (error != 0)
971108832Stmm		goto fail;
972108832Stmm	if (txs->txs_ndescs == -1) {
973108832Stmm		error = -1;
974108832Stmm		goto fail;
97591398Stmm	}
97691398Stmm
977108832Stmm	/* Sync the DMA map. */
978108832Stmm	bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
979108832Stmm	    BUS_DMASYNC_PREWRITE);
98091398Stmm
981108832Stmm	CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, "
982108832Stmm	    "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc,
983108832Stmm	    txs->txs_ndescs);
984108832Stmm	STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
985108832Stmm	STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
98691398Stmm
987108832Stmm	sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
988108832Stmm	sc->sc_txfree -= txs->txs_ndescs;
989108832Stmm	return (0);
99091398Stmm
991108832Stmmfail:
992108832Stmm	CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error);
993108832Stmm	bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
994108832Stmm	return (error);
99591398Stmm}
99691398Stmm
99791398Stmmstatic void
99891398Stmmgem_init_regs(sc)
99991398Stmm	struct gem_softc *sc;
100091398Stmm{
100191398Stmm	bus_space_tag_t t = sc->sc_bustag;
100291398Stmm	bus_space_handle_t h = sc->sc_h;
100399726Sbenno	const u_char *laddr = sc->sc_arpcom.ac_enaddr;
100499726Sbenno	u_int32_t v;
100591398Stmm
100691398Stmm	/* These regs are not cleared on reset */
100791398Stmm	if (!sc->sc_inited) {
100891398Stmm
100991398Stmm		/* Wooo.  Magic values. */
101091398Stmm		bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
101191398Stmm		bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
101291398Stmm		bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
101391398Stmm
101491398Stmm		bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
101591398Stmm		/* Max frame and max burst size */
101691398Stmm		bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
101799726Sbenno		    ETHER_MAX_LEN | (0x2000<<16));
101899726Sbenno
101991398Stmm		bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
102091398Stmm		bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
102191398Stmm		bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
102291398Stmm		/* Dunno.... */
102391398Stmm		bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
102491398Stmm		bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
102599726Sbenno		    ((laddr[5]<<8)|laddr[4])&0x3ff);
102699726Sbenno
102791398Stmm		/* Secondary MAC addr set to 0:0:0:0:0:0 */
102891398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
102991398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
103091398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
103199726Sbenno
103299726Sbenno		/* MAC control addr set to 01:80:c2:00:00:01 */
103391398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
103491398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
103591398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
103691398Stmm
103791398Stmm		/* MAC filter addr set to 0:0:0:0:0:0 */
103891398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
103991398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
104091398Stmm		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
104191398Stmm
104291398Stmm		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
104391398Stmm		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
104491398Stmm
104591398Stmm		sc->sc_inited = 1;
104691398Stmm	}
104791398Stmm
104891398Stmm	/* Counters need to be zeroed */
104991398Stmm	bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
105091398Stmm	bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
105191398Stmm	bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
105291398Stmm	bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
105391398Stmm	bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
105491398Stmm	bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
105591398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
105691398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
105791398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
105891398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
105991398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
106091398Stmm
106191398Stmm	/* Un-pause stuff */
106291398Stmm#if 0
106391398Stmm	bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
106491398Stmm#else
106591398Stmm	bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
106691398Stmm#endif
106791398Stmm
106891398Stmm	/*
106991398Stmm	 * Set the station address.
107091398Stmm	 */
107199726Sbenno	bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
107299726Sbenno	bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
107399726Sbenno	bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
107499726Sbenno
107599726Sbenno	/*
107699726Sbenno	 * Enable MII outputs.  Enable GMII if there is a gigabit PHY.
107799726Sbenno	 */
107899726Sbenno	sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
107999726Sbenno	v = GEM_MAC_XIF_TX_MII_ENA;
108099726Sbenno	if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
108199726Sbenno		v |= GEM_MAC_XIF_FDPLX_LED;
108299726Sbenno		if (sc->sc_flags & GEM_GIGABIT)
108399726Sbenno			v |= GEM_MAC_XIF_GMII_MODE;
108499726Sbenno	}
108599726Sbenno	bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
108691398Stmm}
108791398Stmm
108891398Stmmstatic void
108991398Stmmgem_start(ifp)
109091398Stmm	struct ifnet *ifp;
109191398Stmm{
109291398Stmm	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1093108832Stmm	struct mbuf *m0 = NULL;
1094108832Stmm	int firsttx, ntx, ofree, txmfail;
109591398Stmm
109691398Stmm	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
109791398Stmm		return;
109891398Stmm
109991398Stmm	/*
110091398Stmm	 * Remember the previous number of free descriptors and
110191398Stmm	 * the first descriptor we'll use.
110291398Stmm	 */
110391398Stmm	ofree = sc->sc_txfree;
110491398Stmm	firsttx = sc->sc_txnext;
110591398Stmm
110691398Stmm	CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d",
110791398Stmm	    device_get_name(sc->sc_dev), ofree, firsttx);
110891398Stmm
110991398Stmm	/*
111091398Stmm	 * Loop through the send queue, setting up transmit descriptors
111191398Stmm	 * until we drain the queue, or use up all available transmit
111291398Stmm	 * descriptors.
111391398Stmm	 */
111491398Stmm	txmfail = 0;
111591398Stmm	for (ntx = 0;; ntx++) {
111691398Stmm		/*
111791398Stmm		 * Grab a packet off the queue.
111891398Stmm		 */
111991398Stmm		IF_DEQUEUE(&ifp->if_snd, m0);
112091398Stmm		if (m0 == NULL)
112191398Stmm			break;
112291398Stmm
1123108832Stmm		txmfail = gem_load_txmbuf(sc, m0);
112491398Stmm		if (txmfail > 0) {
1125108832Stmm			/* Drop the mbuf and complain. */
1126108832Stmm			printf("gem_start: error %d while loading mbuf dma "
1127108832Stmm			    "map\n", txmfail);
1128108832Stmm			continue;
112991398Stmm		}
1130108832Stmm		/* Not enough descriptors. */
1131108832Stmm		if (txmfail == -1) {
1132108832Stmm			if (sc->sc_txfree == GEM_MAXTXFREE)
1133108832Stmm				panic("gem_start: mbuf chain too long!");
113491398Stmm			IF_PREPEND(&ifp->if_snd, m0);
113591398Stmm			break;
113691398Stmm		}
113791398Stmm
1138108832Stmm		/* Kick the transmitter. */
1139108832Stmm		CTR2(KTR_GEM, "%s: gem_start: kicking tx %d",
1140108832Stmm		    device_get_name(sc->sc_dev), sc->sc_txnext);
1141108832Stmm		bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK,
1142108832Stmm			sc->sc_txnext);
1143108832Stmm
1144105982Stmm		if (ifp->if_bpf != NULL)
1145106950Smux			bpf_mtap(ifp->if_bpf, m0);
114691398Stmm	}
114791398Stmm
114891398Stmm	if (txmfail == -1 || sc->sc_txfree == 0) {
1149108832Stmm		/* No more slots left; notify upper layer. */
115091398Stmm		ifp->if_flags |= IFF_OACTIVE;
115191398Stmm	}
115291398Stmm
115391398Stmm	if (ntx > 0) {
1154109648Stmm		GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1155109648Stmm
1156108832Stmm		CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1157108832Stmm		    device_get_name(sc->sc_dev), firsttx);
115891398Stmm
115991398Stmm		/* Set a watchdog timer in case the chip flakes out. */
116091398Stmm		ifp->if_timer = 5;
116191398Stmm		CTR2(KTR_GEM, "%s: gem_start: watchdog %d",
116291398Stmm			device_get_name(sc->sc_dev), ifp->if_timer);
116391398Stmm	}
116491398Stmm}
116591398Stmm
116691398Stmm/*
116791398Stmm * Transmit interrupt.
116891398Stmm */
116991398Stmmstatic void
117091398Stmmgem_tint(sc)
117191398Stmm	struct gem_softc *sc;
117291398Stmm{
117391398Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
117491398Stmm	bus_space_tag_t t = sc->sc_bustag;
117591398Stmm	bus_space_handle_t mac = sc->sc_h;
117691398Stmm	struct gem_txsoft *txs;
117791398Stmm	int txlast;
117899726Sbenno	int progress = 0;
117991398Stmm
118091398Stmm
118191398Stmm	CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev));
118291398Stmm
118391398Stmm	/*
118491398Stmm	 * Unload collision counters
118591398Stmm	 */
118691398Stmm	ifp->if_collisions +=
118791398Stmm		bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
118891398Stmm		bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
118991398Stmm		bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
119091398Stmm		bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
119191398Stmm
119291398Stmm	/*
119391398Stmm	 * then clear the hardware counters.
119491398Stmm	 */
119591398Stmm	bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
119691398Stmm	bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
119791398Stmm	bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
119891398Stmm	bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
119991398Stmm
120091398Stmm	/*
120191398Stmm	 * Go through our Tx list and free mbufs for those
120291398Stmm	 * frames that have been transmitted.
120391398Stmm	 */
1204109648Stmm	GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
120591398Stmm	while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
120691398Stmm
120791398Stmm#ifdef GEM_DEBUG
120891398Stmm		if (ifp->if_flags & IFF_DEBUG) {
120991398Stmm			int i;
121091398Stmm			printf("    txsoft %p transmit chain:\n", txs);
121191398Stmm			for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
121291398Stmm				printf("descriptor %d: ", i);
121391398Stmm				printf("gd_flags: 0x%016llx\t", (long long)
121491398Stmm					GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
121591398Stmm				printf("gd_addr: 0x%016llx\n", (long long)
121691398Stmm					GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
121791398Stmm				if (i == txs->txs_lastdesc)
121891398Stmm					break;
121991398Stmm			}
122091398Stmm		}
122191398Stmm#endif
122291398Stmm
122391398Stmm		/*
122491398Stmm		 * In theory, we could harveast some descriptors before
122591398Stmm		 * the ring is empty, but that's a bit complicated.
122691398Stmm		 *
122791398Stmm		 * GEM_TX_COMPLETION points to the last descriptor
122891398Stmm		 * processed +1.
122991398Stmm		 */
123091398Stmm		txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
123191398Stmm		CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, "
123291398Stmm		    "txs->txs_lastdesc = %d, txlast = %d",
123391398Stmm		    txs->txs_firstdesc, txs->txs_lastdesc, txlast);
123491398Stmm		if (txs->txs_firstdesc <= txs->txs_lastdesc) {
123591398Stmm			if ((txlast >= txs->txs_firstdesc) &&
123691398Stmm				(txlast <= txs->txs_lastdesc))
123791398Stmm				break;
123891398Stmm		} else {
123991398Stmm			/* Ick -- this command wraps */
124091398Stmm			if ((txlast >= txs->txs_firstdesc) ||
124191398Stmm				(txlast <= txs->txs_lastdesc))
124291398Stmm				break;
124391398Stmm		}
124491398Stmm
124591398Stmm		CTR0(KTR_GEM, "gem_tint: releasing a desc");
124691398Stmm		STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
124791398Stmm
124891398Stmm		sc->sc_txfree += txs->txs_ndescs;
124991398Stmm
1250108832Stmm		bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
125191398Stmm		    BUS_DMASYNC_POSTWRITE);
1252108832Stmm		bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
125391398Stmm		if (txs->txs_mbuf != NULL) {
125491398Stmm			m_freem(txs->txs_mbuf);
125591398Stmm			txs->txs_mbuf = NULL;
125691398Stmm		}
125791398Stmm
125891398Stmm		STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
125991398Stmm
126091398Stmm		ifp->if_opackets++;
126199726Sbenno		progress = 1;
126291398Stmm	}
126391398Stmm
126491398Stmm	CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x "
126591398Stmm		"GEM_TX_DATA_PTR %llx "
126691398Stmm		"GEM_TX_COMPLETION %x",
126791398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE),
126891398Stmm		((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h,
126991398Stmm			GEM_TX_DATA_PTR_HI) << 32) |
127091398Stmm			     bus_space_read_4(sc->sc_bustag, sc->sc_h,
127191398Stmm			GEM_TX_DATA_PTR_LO),
127291398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION));
127391398Stmm
127499726Sbenno	if (progress) {
127599726Sbenno		if (sc->sc_txfree == GEM_NTXDESC - 1)
127699726Sbenno			sc->sc_txwin = 0;
127791398Stmm
127899726Sbenno		/* Freed some descriptors, so reset IFF_OACTIVE and restart. */
127999726Sbenno		ifp->if_flags &= ~IFF_OACTIVE;
128099726Sbenno		gem_start(ifp);
128191398Stmm
128299726Sbenno		if (STAILQ_EMPTY(&sc->sc_txdirtyq))
128399726Sbenno			ifp->if_timer = 0;
128499726Sbenno	}
128599726Sbenno
128691398Stmm	CTR2(KTR_GEM, "%s: gem_tint: watchdog %d",
128791398Stmm		device_get_name(sc->sc_dev), ifp->if_timer);
128891398Stmm}
128991398Stmm
1290100587Sjake#if 0
129193045Stmmstatic void
129293045Stmmgem_rint_timeout(arg)
129393045Stmm	void *arg;
129493045Stmm{
129593045Stmm
129693045Stmm	gem_rint((struct gem_softc *)arg);
129793045Stmm}
1298100587Sjake#endif
129993045Stmm
130091398Stmm/*
130191398Stmm * Receive interrupt.
130291398Stmm */
130391398Stmmstatic void
130491398Stmmgem_rint(sc)
130591398Stmm	struct gem_softc *sc;
130691398Stmm{
130791398Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
130891398Stmm	bus_space_tag_t t = sc->sc_bustag;
130991398Stmm	bus_space_handle_t h = sc->sc_h;
131091398Stmm	struct gem_rxsoft *rxs;
131191398Stmm	struct mbuf *m;
131291398Stmm	u_int64_t rxstat;
131399726Sbenno	u_int32_t rxcomp;
131499726Sbenno	int i, len, progress = 0;
131591398Stmm
131693045Stmm	callout_stop(&sc->sc_rx_ch);
131791398Stmm	CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev));
131899726Sbenno
131991398Stmm	/*
132099726Sbenno	 * Read the completion register once.  This limits
132199726Sbenno	 * how long the following loop can execute.
132299726Sbenno	 */
132399726Sbenno	rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
132499726Sbenno
132591398Stmm	CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
132699726Sbenno	    sc->sc_rxptr, rxcomp);
1327109648Stmm	GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
132899726Sbenno	for (i = sc->sc_rxptr; i != rxcomp;
132991398Stmm	     i = GEM_NEXTRX(i)) {
133091398Stmm		rxs = &sc->sc_rxsoft[i];
133191398Stmm
133291398Stmm		rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
133391398Stmm
133491398Stmm		if (rxstat & GEM_RD_OWN) {
133599726Sbenno#if 0 /* XXX: In case of emergency, re-enable this. */
133691398Stmm			/*
133793045Stmm			 * The descriptor is still marked as owned, although
133893045Stmm			 * it is supposed to have completed. This has been
133993045Stmm			 * observed on some machines. Just exiting here
134093045Stmm			 * might leave the packet sitting around until another
134193045Stmm			 * one arrives to trigger a new interrupt, which is
134293045Stmm			 * generally undesirable, so set up a timeout.
134391398Stmm			 */
134493045Stmm			callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
134593045Stmm			    gem_rint_timeout, sc);
134699726Sbenno#endif
134791398Stmm			break;
134891398Stmm		}
134991398Stmm
135099726Sbenno		progress++;
135199726Sbenno		ifp->if_ipackets++;
135299726Sbenno
135391398Stmm		if (rxstat & GEM_RD_BAD_CRC) {
135499726Sbenno			ifp->if_ierrors++;
135591398Stmm			device_printf(sc->sc_dev, "receive error: CRC error\n");
135691398Stmm			GEM_INIT_RXDESC(sc, i);
135791398Stmm			continue;
135891398Stmm		}
135991398Stmm
136091398Stmm#ifdef GEM_DEBUG
136191398Stmm		if (ifp->if_flags & IFF_DEBUG) {
136291398Stmm			printf("    rxsoft %p descriptor %d: ", rxs, i);
136391398Stmm			printf("gd_flags: 0x%016llx\t", (long long)
136491398Stmm				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
136591398Stmm			printf("gd_addr: 0x%016llx\n", (long long)
136691398Stmm				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
136791398Stmm		}
136891398Stmm#endif
136991398Stmm
137091398Stmm		/*
137191398Stmm		 * No errors; receive the packet.  Note the Gem
137291398Stmm		 * includes the CRC with every packet.
137391398Stmm		 */
137491398Stmm		len = GEM_RD_BUFLEN(rxstat);
137591398Stmm
137691398Stmm		/*
137791398Stmm		 * Allocate a new mbuf cluster.  If that fails, we are
137891398Stmm		 * out of memory, and must drop the packet and recycle
137991398Stmm		 * the buffer that's already attached to this descriptor.
138091398Stmm		 */
138191398Stmm		m = rxs->rxs_mbuf;
138291398Stmm		if (gem_add_rxbuf(sc, i) != 0) {
138391398Stmm			ifp->if_ierrors++;
138491398Stmm			GEM_INIT_RXDESC(sc, i);
138591398Stmm			continue;
138691398Stmm		}
138791398Stmm		m->m_data += 2; /* We're already off by two */
138891398Stmm
138991398Stmm		m->m_pkthdr.rcvif = ifp;
139091398Stmm		m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN;
139191398Stmm
139291398Stmm		/* Pass it on. */
1393106937Ssam		(*ifp->if_input)(ifp, m);
139491398Stmm	}
139591398Stmm
139699726Sbenno	if (progress) {
1397109648Stmm		GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
139899726Sbenno		/* Update the receive pointer. */
139999726Sbenno		if (i == sc->sc_rxptr) {
140099726Sbenno			device_printf(sc->sc_dev, "rint: ring wrap\n");
140199726Sbenno		}
140299726Sbenno		sc->sc_rxptr = i;
140399726Sbenno		bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
140499726Sbenno	}
140591398Stmm
140691398Stmm	CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d",
140791398Stmm		sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
140891398Stmm}
140991398Stmm
141091398Stmm
141191398Stmm/*
141291398Stmm * gem_add_rxbuf:
141391398Stmm *
141491398Stmm *	Add a receive buffer to the indicated descriptor.
141591398Stmm */
141691398Stmmstatic int
141791398Stmmgem_add_rxbuf(sc, idx)
141891398Stmm	struct gem_softc *sc;
141991398Stmm	int idx;
142091398Stmm{
142191398Stmm	struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
142291398Stmm	struct mbuf *m;
142391398Stmm	int error;
142491398Stmm
1425109623Salfred	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
142691398Stmm	if (m == NULL)
142791398Stmm		return (ENOBUFS);
1428108832Stmm	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
142991398Stmm
143091398Stmm#ifdef GEM_DEBUG
143191398Stmm	/* bzero the packet to check dma */
143291398Stmm	memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
143391398Stmm#endif
143491398Stmm
1435109648Stmm	if (rxs->rxs_mbuf != NULL) {
1436109648Stmm		bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1437109648Stmm		    BUS_DMASYNC_POSTREAD);
1438108832Stmm		bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1439109648Stmm	}
144091398Stmm
144191398Stmm	rxs->rxs_mbuf = m;
144291398Stmm
1443108832Stmm	error = bus_dmamap_load_mbuf(sc->sc_rdmatag, rxs->rxs_dmamap,
1444108832Stmm	    m, gem_rxdma_callback, rxs, BUS_DMA_NOWAIT);
144591398Stmm	if (error != 0 || rxs->rxs_paddr == 0) {
144691398Stmm		device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
144791398Stmm		    "%d\n", idx, error);
144891398Stmm		panic("gem_add_rxbuf");	/* XXX */
144991398Stmm	}
145091398Stmm
1451108832Stmm	bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
145291398Stmm
145391398Stmm	GEM_INIT_RXDESC(sc, idx);
145491398Stmm
145591398Stmm	return (0);
145691398Stmm}
145791398Stmm
145891398Stmm
145991398Stmmstatic void
146091398Stmmgem_eint(sc, status)
146191398Stmm	struct gem_softc *sc;
146291398Stmm	u_int status;
146391398Stmm{
146491398Stmm
146591398Stmm	if ((status & GEM_INTR_MIF) != 0) {
146691398Stmm		device_printf(sc->sc_dev, "XXXlink status changed\n");
146791398Stmm		return;
146891398Stmm	}
146991398Stmm
147091398Stmm	device_printf(sc->sc_dev, "status=%x\n", status);
147191398Stmm}
147291398Stmm
147391398Stmm
147491398Stmmvoid
147591398Stmmgem_intr(v)
147691398Stmm	void *v;
147791398Stmm{
147891398Stmm	struct gem_softc *sc = (struct gem_softc *)v;
147991398Stmm	bus_space_tag_t t = sc->sc_bustag;
148091398Stmm	bus_space_handle_t seb = sc->sc_h;
148191398Stmm	u_int32_t status;
148291398Stmm
148391398Stmm	status = bus_space_read_4(t, seb, GEM_STATUS);
148491398Stmm	CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x",
148591398Stmm		device_get_name(sc->sc_dev), (status>>19),
148691398Stmm		(u_int)status);
148791398Stmm
148891398Stmm	if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
148991398Stmm		gem_eint(sc, status);
149091398Stmm
149191398Stmm	if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
149291398Stmm		gem_tint(sc);
149391398Stmm
149491398Stmm	if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
149591398Stmm		gem_rint(sc);
149691398Stmm
149791398Stmm	/* We should eventually do more than just print out error stats. */
149891398Stmm	if (status & GEM_INTR_TX_MAC) {
149991398Stmm		int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
150091398Stmm		if (txstat & ~GEM_MAC_TX_XMIT_DONE)
150199726Sbenno			device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
150299726Sbenno			    txstat);
150397240Stmm		if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
150497240Stmm			gem_init(sc);
150591398Stmm	}
150691398Stmm	if (status & GEM_INTR_RX_MAC) {
150791398Stmm		int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
150891398Stmm		if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
150999726Sbenno			device_printf(sc->sc_dev, "MAC rx fault, status %x\n",
151099726Sbenno			    rxstat);
151197240Stmm		if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0)
151297240Stmm			gem_init(sc);
151391398Stmm	}
151491398Stmm}
151591398Stmm
151691398Stmm
151791398Stmmstatic void
151891398Stmmgem_watchdog(ifp)
151991398Stmm	struct ifnet *ifp;
152091398Stmm{
152191398Stmm	struct gem_softc *sc = ifp->if_softc;
152291398Stmm
152391398Stmm	CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
152491398Stmm		"GEM_MAC_RX_CONFIG %x",
152591398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG),
152691398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS),
152791398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG));
152891398Stmm	CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x "
152991398Stmm		"GEM_MAC_TX_CONFIG %x",
153091398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG),
153191398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS),
153291398Stmm		bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG));
153391398Stmm
153491398Stmm	device_printf(sc->sc_dev, "device timeout\n");
153591398Stmm	++ifp->if_oerrors;
153691398Stmm
153791398Stmm	/* Try to get more packets going. */
153891398Stmm	gem_start(ifp);
153991398Stmm}
154091398Stmm
154191398Stmm/*
154291398Stmm * Initialize the MII Management Interface
154391398Stmm */
154491398Stmmstatic void
154591398Stmmgem_mifinit(sc)
154691398Stmm	struct gem_softc *sc;
154791398Stmm{
154891398Stmm	bus_space_tag_t t = sc->sc_bustag;
154991398Stmm	bus_space_handle_t mif = sc->sc_h;
155091398Stmm
155191398Stmm	/* Configure the MIF in frame mode */
155291398Stmm	sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
155391398Stmm	sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
155491398Stmm	bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
155591398Stmm}
155691398Stmm
155791398Stmm/*
155891398Stmm * MII interface
155991398Stmm *
156091398Stmm * The GEM MII interface supports at least three different operating modes:
156191398Stmm *
156291398Stmm * Bitbang mode is implemented using data, clock and output enable registers.
156391398Stmm *
156491398Stmm * Frame mode is implemented by loading a complete frame into the frame
156591398Stmm * register and polling the valid bit for completion.
156691398Stmm *
156791398Stmm * Polling mode uses the frame register but completion is indicated by
156891398Stmm * an interrupt.
156991398Stmm *
157091398Stmm */
157191398Stmmint
157291398Stmmgem_mii_readreg(dev, phy, reg)
157391398Stmm	device_t dev;
157491398Stmm	int phy, reg;
157591398Stmm{
157691398Stmm	struct gem_softc *sc = device_get_softc(dev);
157791398Stmm	bus_space_tag_t t = sc->sc_bustag;
157891398Stmm	bus_space_handle_t mif = sc->sc_h;
157991398Stmm	int n;
158091398Stmm	u_int32_t v;
158191398Stmm
158291398Stmm#ifdef GEM_DEBUG_PHY
158391398Stmm	printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
158491398Stmm#endif
158591398Stmm
158691398Stmm#if 0
158791398Stmm	/* Select the desired PHY in the MIF configuration register */
158891398Stmm	v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
158991398Stmm	/* Clear PHY select bit */
159091398Stmm	v &= ~GEM_MIF_CONFIG_PHY_SEL;
159191398Stmm	if (phy == GEM_PHYAD_EXTERNAL)
159291398Stmm		/* Set PHY select bit to get at external device */
159391398Stmm		v |= GEM_MIF_CONFIG_PHY_SEL;
159491398Stmm	bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
159591398Stmm#endif
159691398Stmm
159791398Stmm	/* Construct the frame command */
159891398Stmm	v = (reg << GEM_MIF_REG_SHIFT)	| (phy << GEM_MIF_PHY_SHIFT) |
159991398Stmm		GEM_MIF_FRAME_READ;
160091398Stmm
160191398Stmm	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
160291398Stmm	for (n = 0; n < 100; n++) {
160391398Stmm		DELAY(1);
160491398Stmm		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
160591398Stmm		if (v & GEM_MIF_FRAME_TA0)
160691398Stmm			return (v & GEM_MIF_FRAME_DATA);
160791398Stmm	}
160891398Stmm
160991398Stmm	device_printf(sc->sc_dev, "mii_read timeout\n");
161091398Stmm	return (0);
161191398Stmm}
161291398Stmm
161391398Stmmint
161491398Stmmgem_mii_writereg(dev, phy, reg, val)
161591398Stmm	device_t dev;
161691398Stmm	int phy, reg, val;
161791398Stmm{
161891398Stmm	struct gem_softc *sc = device_get_softc(dev);
161991398Stmm	bus_space_tag_t t = sc->sc_bustag;
162091398Stmm	bus_space_handle_t mif = sc->sc_h;
162191398Stmm	int n;
162291398Stmm	u_int32_t v;
162391398Stmm
162491398Stmm#ifdef GEM_DEBUG_PHY
162591398Stmm	printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val);
162691398Stmm#endif
162791398Stmm
162891398Stmm#if 0
162991398Stmm	/* Select the desired PHY in the MIF configuration register */
163091398Stmm	v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
163191398Stmm	/* Clear PHY select bit */
163291398Stmm	v &= ~GEM_MIF_CONFIG_PHY_SEL;
163391398Stmm	if (phy == GEM_PHYAD_EXTERNAL)
163491398Stmm		/* Set PHY select bit to get at external device */
163591398Stmm		v |= GEM_MIF_CONFIG_PHY_SEL;
163691398Stmm	bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
163791398Stmm#endif
163891398Stmm	/* Construct the frame command */
163991398Stmm	v = GEM_MIF_FRAME_WRITE			|
164091398Stmm	    (phy << GEM_MIF_PHY_SHIFT)		|
164191398Stmm	    (reg << GEM_MIF_REG_SHIFT)		|
164291398Stmm	    (val & GEM_MIF_FRAME_DATA);
164391398Stmm
164491398Stmm	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
164591398Stmm	for (n = 0; n < 100; n++) {
164691398Stmm		DELAY(1);
164791398Stmm		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
164891398Stmm		if (v & GEM_MIF_FRAME_TA0)
164991398Stmm			return (1);
165091398Stmm	}
165191398Stmm
165291398Stmm	device_printf(sc->sc_dev, "mii_write timeout\n");
165391398Stmm	return (0);
165491398Stmm}
165591398Stmm
165691398Stmmvoid
165791398Stmmgem_mii_statchg(dev)
165891398Stmm	device_t dev;
165991398Stmm{
166091398Stmm	struct gem_softc *sc = device_get_softc(dev);
166191398Stmm#ifdef GEM_DEBUG
166291398Stmm	int instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media);
166391398Stmm#endif
166491398Stmm	bus_space_tag_t t = sc->sc_bustag;
166591398Stmm	bus_space_handle_t mac = sc->sc_h;
166691398Stmm	u_int32_t v;
166791398Stmm
166891398Stmm#ifdef GEM_DEBUG
166991398Stmm	if (sc->sc_debug)
167091398Stmm		printf("gem_mii_statchg: status change: phy = %d\n",
167191398Stmm			sc->sc_phys[instance]);
167291398Stmm#endif
167391398Stmm
167491398Stmm	/* Set tx full duplex options */
167591398Stmm	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
167691398Stmm	DELAY(10000); /* reg must be cleared and delay before changing. */
167791398Stmm	v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
167891398Stmm		GEM_MAC_TX_ENABLE;
167991398Stmm	if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
168091398Stmm		v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
168191398Stmm	}
168291398Stmm	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
168391398Stmm
168491398Stmm	/* XIF Configuration */
168591398Stmm /* We should really calculate all this rather than rely on defaults */
168691398Stmm	v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG);
168791398Stmm	v = GEM_MAC_XIF_LINK_LED;
168891398Stmm	v |= GEM_MAC_XIF_TX_MII_ENA;
168999726Sbenno
169091398Stmm	/* If an external transceiver is connected, enable its MII drivers */
169191398Stmm	sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
169291398Stmm	if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
169391398Stmm		/* External MII needs echo disable if half duplex. */
169491398Stmm		if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
169591398Stmm			/* turn on full duplex LED */
169691398Stmm			v |= GEM_MAC_XIF_FDPLX_LED;
169799726Sbenno		else
169899726Sbenno	 		/* half duplex -- disable echo */
169999726Sbenno	 		v |= GEM_MAC_XIF_ECHO_DISABL;
170099726Sbenno
170199726Sbenno		if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
170299726Sbenno			v |= GEM_MAC_XIF_GMII_MODE;
170399726Sbenno		else
170499726Sbenno			v &= ~GEM_MAC_XIF_GMII_MODE;
170591398Stmm	} else {
170691398Stmm		/* Internal MII needs buf enable */
170791398Stmm		v |= GEM_MAC_XIF_MII_BUF_ENA;
170891398Stmm	}
170991398Stmm	bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
171091398Stmm}
171191398Stmm
171291398Stmmint
171391398Stmmgem_mediachange(ifp)
171491398Stmm	struct ifnet *ifp;
171591398Stmm{
171691398Stmm	struct gem_softc *sc = ifp->if_softc;
171791398Stmm
171891398Stmm	/* XXX Add support for serial media. */
171991398Stmm
172091398Stmm	return (mii_mediachg(sc->sc_mii));
172191398Stmm}
172291398Stmm
172391398Stmmvoid
172491398Stmmgem_mediastatus(ifp, ifmr)
172591398Stmm	struct ifnet *ifp;
172691398Stmm	struct ifmediareq *ifmr;
172791398Stmm{
172891398Stmm	struct gem_softc *sc = ifp->if_softc;
172991398Stmm
173091398Stmm	if ((ifp->if_flags & IFF_UP) == 0)
173191398Stmm		return;
173291398Stmm
173391398Stmm	mii_pollstat(sc->sc_mii);
173491398Stmm	ifmr->ifm_active = sc->sc_mii->mii_media_active;
173591398Stmm	ifmr->ifm_status = sc->sc_mii->mii_media_status;
173691398Stmm}
173791398Stmm
173891398Stmm/*
173991398Stmm * Process an ioctl request.
174091398Stmm */
174191398Stmmstatic int
174291398Stmmgem_ioctl(ifp, cmd, data)
174391398Stmm	struct ifnet *ifp;
174491398Stmm	u_long cmd;
174591398Stmm	caddr_t data;
174691398Stmm{
174791398Stmm	struct gem_softc *sc = ifp->if_softc;
174891398Stmm	struct ifreq *ifr = (struct ifreq *)data;
174991398Stmm	int s, error = 0;
175091398Stmm
175191398Stmm	switch (cmd) {
175291398Stmm	case SIOCSIFADDR:
175391398Stmm	case SIOCGIFADDR:
175491398Stmm	case SIOCSIFMTU:
175591398Stmm		error = ether_ioctl(ifp, cmd, data);
175691398Stmm		break;
175791398Stmm	case SIOCSIFFLAGS:
175891398Stmm		if (ifp->if_flags & IFF_UP) {
175999726Sbenno			if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC)
176091398Stmm				gem_setladrf(sc);
176191398Stmm			else
176291398Stmm				gem_init(sc);
176391398Stmm		} else {
176491398Stmm			if (ifp->if_flags & IFF_RUNNING)
176591398Stmm				gem_stop(ifp, 0);
176691398Stmm		}
176799726Sbenno		sc->sc_ifflags = ifp->if_flags;
176891398Stmm		error = 0;
176991398Stmm		break;
177091398Stmm	case SIOCADDMULTI:
177191398Stmm	case SIOCDELMULTI:
177291398Stmm		gem_setladrf(sc);
177391398Stmm		error = 0;
177491398Stmm		break;
177591398Stmm	case SIOCGIFMEDIA:
177691398Stmm	case SIOCSIFMEDIA:
177791398Stmm		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
177891398Stmm		break;
177991398Stmm	default:
1780108832Stmm		error = ENOTTY;
178191398Stmm		break;
178291398Stmm	}
178391398Stmm
178491398Stmm	/* Try to get things going again */
178591398Stmm	if (ifp->if_flags & IFF_UP)
178691398Stmm		gem_start(ifp);
178791398Stmm	splx(s);
178891398Stmm	return (error);
178991398Stmm}
179091398Stmm
179191398Stmm/*
179291398Stmm * Set up the logical address filter.
179391398Stmm */
179491398Stmmstatic void
179591398Stmmgem_setladrf(sc)
179691398Stmm	struct gem_softc *sc;
179791398Stmm{
179891398Stmm	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
179991398Stmm	struct ifmultiaddr *inm;
180091398Stmm	struct sockaddr_dl *sdl;
180191398Stmm	bus_space_tag_t t = sc->sc_bustag;
180291398Stmm	bus_space_handle_t h = sc->sc_h;
180391398Stmm	u_char *cp;
180491398Stmm	u_int32_t crc;
180591398Stmm	u_int32_t hash[16];
180691398Stmm	u_int32_t v;
180791398Stmm	int len;
180899726Sbenno	int i;
180991398Stmm
181091398Stmm	/* Get current RX configuration */
181191398Stmm	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
181291398Stmm
181399726Sbenno	/*
181499726Sbenno	 * Turn off promiscuous mode, promiscuous group mode (all multicast),
181599726Sbenno	 * and hash filter.  Depending on the case, the right bit will be
181699726Sbenno	 * enabled.
181799726Sbenno	 */
181899726Sbenno	v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
181999726Sbenno	    GEM_MAC_RX_PROMISC_GRP);
182099726Sbenno
182191398Stmm	if ((ifp->if_flags & IFF_PROMISC) != 0) {
182299726Sbenno		/* Turn on promiscuous mode */
182391398Stmm		v |= GEM_MAC_RX_PROMISCUOUS;
182491398Stmm		goto chipit;
182591398Stmm	}
182691398Stmm	if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
182791398Stmm		hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
182891398Stmm		ifp->if_flags |= IFF_ALLMULTI;
182999726Sbenno		v |= GEM_MAC_RX_PROMISC_GRP;
183091398Stmm		goto chipit;
183191398Stmm	}
183291398Stmm
183391398Stmm	/*
183491398Stmm	 * Set up multicast address filter by passing all multicast addresses
183599726Sbenno	 * through a crc generator, and then using the high order 8 bits as an
183699726Sbenno	 * index into the 256 bit logical address filter.  The high order 4
183799726Sbenno	 * bits selects the word, while the other 4 bits select the bit within
183899726Sbenno	 * the word (where bit 0 is the MSB).
183991398Stmm	 */
184091398Stmm
184199726Sbenno	/* Clear hash table */
184299726Sbenno	memset(hash, 0, sizeof(hash));
184399726Sbenno
184491398Stmm	TAILQ_FOREACH(inm, &sc->sc_arpcom.ac_if.if_multiaddrs, ifma_link) {
184591398Stmm		if (inm->ifma_addr->sa_family != AF_LINK)
184691398Stmm			continue;
184791398Stmm		sdl = (struct sockaddr_dl *)inm->ifma_addr;
184891398Stmm		cp = LLADDR(sdl);
184991398Stmm		crc = 0xffffffff;
185091398Stmm		for (len = sdl->sdl_alen; --len >= 0;) {
185191398Stmm			int octet = *cp++;
185291398Stmm			int i;
185391398Stmm
185491398Stmm#define MC_POLY_LE	0xedb88320UL	/* mcast crc, little endian */
185591398Stmm			for (i = 0; i < 8; i++) {
185691398Stmm				if ((crc & 1) ^ (octet & 1)) {
185791398Stmm					crc >>= 1;
185891398Stmm					crc ^= MC_POLY_LE;
185991398Stmm				} else {
186091398Stmm					crc >>= 1;
186191398Stmm				}
186291398Stmm				octet >>= 1;
186391398Stmm			}
186491398Stmm		}
186591398Stmm		/* Just want the 8 most significant bits. */
186691398Stmm		crc >>= 24;
186791398Stmm
186891398Stmm		/* Set the corresponding bit in the filter. */
186999726Sbenno		hash[crc >> 4] |= 1 << (15 - (crc & 15));
187091398Stmm	}
187191398Stmm
187299726Sbenno	v |= GEM_MAC_RX_HASH_FILTER;
187399726Sbenno	ifp->if_flags &= ~IFF_ALLMULTI;
187499726Sbenno
187599726Sbenno	/* Now load the hash table into the chip (if we are using it) */
187699726Sbenno	for (i = 0; i < 16; i++) {
187799726Sbenno		bus_space_write_4(t, h,
187899726Sbenno		    GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
187999726Sbenno		    hash[i]);
188099726Sbenno	}
188199726Sbenno
188291398Stmmchipit:
188391398Stmm	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
188491398Stmm}
1885