if_gem.c revision 108832
191398Stmm/* 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 3108832Stmm * Copyright (c) 2001-2003 Thomas Moestl 491398Stmm * All rights reserved. 591398Stmm * 691398Stmm * Redistribution and use in source and binary forms, with or without 791398Stmm * modification, are permitted provided that the following conditions 891398Stmm * are met: 991398Stmm * 1. Redistributions of source code must retain the above copyright 1091398Stmm * notice, this list of conditions and the following disclaimer. 1191398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1291398Stmm * notice, this list of conditions and the following disclaimer in the 1391398Stmm * documentation and/or other materials provided with the distribution. 1491398Stmm * 1591398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1691398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1791398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1891398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1991398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2091398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2191398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2291398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2391398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2491398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2591398Stmm * SUCH DAMAGE. 2691398Stmm * 2799726Sbenno * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 2891398Stmm * 2991398Stmm * $FreeBSD: head/sys/dev/gem/if_gem.c 108832 2003-01-06 22:09:01Z tmm $ 3091398Stmm */ 3191398Stmm 3291398Stmm/* 3391398Stmm * Driver for Sun GEM ethernet controllers. 3491398Stmm */ 3591398Stmm 3691398Stmm#define GEM_DEBUG 3791398Stmm 3891398Stmm#include <sys/param.h> 3991398Stmm#include <sys/systm.h> 4091398Stmm#include <sys/bus.h> 4191398Stmm#include <sys/callout.h> 4295533Smike#include <sys/endian.h> 4391398Stmm#include <sys/mbuf.h> 4491398Stmm#include <sys/malloc.h> 4591398Stmm#include <sys/kernel.h> 4691398Stmm#include <sys/socket.h> 4791398Stmm#include <sys/sockio.h> 4891398Stmm 49105982Stmm#include <net/bpf.h> 5091398Stmm#include <net/ethernet.h> 5191398Stmm#include <net/if.h> 5291398Stmm#include <net/if_arp.h> 5391398Stmm#include <net/if_dl.h> 5491398Stmm#include <net/if_media.h> 5591398Stmm 5691398Stmm#include <machine/bus.h> 5791398Stmm 5891398Stmm#include <dev/mii/mii.h> 5991398Stmm#include <dev/mii/miivar.h> 6091398Stmm 6191398Stmm#include <gem/if_gemreg.h> 6291398Stmm#include <gem/if_gemvar.h> 6391398Stmm 6491398Stmm#define TRIES 10000 6591398Stmm 6692739Salfredstatic void gem_start(struct ifnet *); 6792739Salfredstatic void gem_stop(struct ifnet *, int); 6892739Salfredstatic int gem_ioctl(struct ifnet *, u_long, caddr_t); 6992739Salfredstatic void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); 70108832Stmmstatic void gem_rxdma_callback(void *, bus_dma_segment_t *, int, 71108832Stmm bus_size_t, int); 72108832Stmmstatic void gem_txdma_callback(void *, bus_dma_segment_t *, int, 73108832Stmm bus_size_t, int); 7492739Salfredstatic void gem_tick(void *); 7592739Salfredstatic void gem_watchdog(struct ifnet *); 7692739Salfredstatic void gem_init(void *); 7792739Salfredstatic void gem_init_regs(struct gem_softc *sc); 7892739Salfredstatic int gem_ringsize(int sz); 7992739Salfredstatic int gem_meminit(struct gem_softc *); 80108832Stmmstatic int gem_load_txmbuf(struct gem_softc *, struct mbuf *); 8192739Salfredstatic void gem_mifinit(struct gem_softc *); 8292739Salfredstatic int gem_bitwait(struct gem_softc *sc, bus_addr_t r, 8392739Salfred u_int32_t clr, u_int32_t set); 8492739Salfredstatic int gem_reset_rx(struct gem_softc *); 8592739Salfredstatic int gem_reset_tx(struct gem_softc *); 8692739Salfredstatic int gem_disable_rx(struct gem_softc *); 8792739Salfredstatic int gem_disable_tx(struct gem_softc *); 8892739Salfredstatic void gem_rxdrain(struct gem_softc *); 8992739Salfredstatic int gem_add_rxbuf(struct gem_softc *, int); 9092739Salfredstatic void gem_setladrf(struct gem_softc *); 9191398Stmm 9292739Salfredstruct mbuf *gem_get(struct gem_softc *, int, int); 9392739Salfredstatic void gem_eint(struct gem_softc *, u_int); 9492739Salfredstatic void gem_rint(struct gem_softc *); 95100587Sjake#if 0 9693045Stmmstatic void gem_rint_timeout(void *); 97100587Sjake#endif 9892739Salfredstatic void gem_tint(struct gem_softc *); 9991398Stmm#ifdef notyet 10092739Salfredstatic void gem_power(int, void *); 10191398Stmm#endif 10291398Stmm 10391398Stmmdevclass_t gem_devclass; 10491398StmmDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 10591398StmmMODULE_DEPEND(gem, miibus, 1, 1, 1); 10691398Stmm 10791398Stmm#ifdef GEM_DEBUG 10891398Stmm#include <sys/ktr.h> 10991398Stmm#define KTR_GEM KTR_CT2 11091398Stmm#endif 11191398Stmm 11291398Stmm#define GEM_NSEGS GEM_NTXSEGS 11391398Stmm 11491398Stmm/* 11591398Stmm * gem_attach: 11691398Stmm * 11791398Stmm * Attach a Gem interface to the system. 11891398Stmm */ 11991398Stmmint 12091398Stmmgem_attach(sc) 12191398Stmm struct gem_softc *sc; 12291398Stmm{ 12391398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 12491398Stmm struct mii_softc *child; 12591398Stmm int i, error; 12699726Sbenno u_int32_t v; 12791398Stmm 12891398Stmm /* Make sure the chip is stopped. */ 12991398Stmm ifp->if_softc = sc; 13091398Stmm gem_reset(sc); 13191398Stmm 13291398Stmm error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 13391398Stmm BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS, 13491398Stmm BUS_SPACE_MAXSIZE_32BIT, 0, &sc->sc_pdmatag); 13591398Stmm if (error) 13691398Stmm return (error); 13791398Stmm 13891398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 13991398Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE, 140108832Stmm 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, 141108832Stmm &sc->sc_rdmatag); 14291398Stmm if (error) 143108832Stmm goto fail_ptag; 14491398Stmm 145108832Stmm error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 146108832Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 147108832Stmm GEM_TD_BUFSIZE, GEM_NTXSEGS, BUS_SPACE_MAXSIZE_32BIT, 148108832Stmm BUS_DMA_ALLOCNOW, &sc->sc_tdmatag); 149108832Stmm if (error) 150108832Stmm goto fail_rtag; 151108832Stmm 15291398Stmm error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 15391398Stmm BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 15491398Stmm sizeof(struct gem_control_data), 1, 15591398Stmm sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW, 15691398Stmm &sc->sc_cdmatag); 15791398Stmm if (error) 158108832Stmm goto fail_ttag; 15991398Stmm 16091398Stmm /* 16191398Stmm * Allocate the control data structures, and create and load the 16291398Stmm * DMA map for it. 16391398Stmm */ 16491398Stmm if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 16591398Stmm (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) { 16691398Stmm device_printf(sc->sc_dev, "unable to allocate control data," 16791398Stmm " error = %d\n", error); 168108832Stmm goto fail_ctag; 16991398Stmm } 17091398Stmm 17191398Stmm sc->sc_cddma = 0; 17291398Stmm if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 17391398Stmm sc->sc_control_data, sizeof(struct gem_control_data), 17491398Stmm gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 17591398Stmm device_printf(sc->sc_dev, "unable to load control data DMA " 17691398Stmm "map, error = %d\n", error); 177108832Stmm goto fail_cmem; 17891398Stmm } 17991398Stmm 18091398Stmm /* 18191398Stmm * Initialize the transmit job descriptors. 18291398Stmm */ 18391398Stmm STAILQ_INIT(&sc->sc_txfreeq); 18491398Stmm STAILQ_INIT(&sc->sc_txdirtyq); 18591398Stmm 18691398Stmm /* 18791398Stmm * Create the transmit buffer DMA maps. 18891398Stmm */ 18991398Stmm error = ENOMEM; 19091398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 19191398Stmm struct gem_txsoft *txs; 19291398Stmm 19391398Stmm txs = &sc->sc_txsoft[i]; 19491398Stmm txs->txs_mbuf = NULL; 19591398Stmm txs->txs_ndescs = 0; 196108832Stmm if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 19791398Stmm &txs->txs_dmamap)) != 0) { 19891398Stmm device_printf(sc->sc_dev, "unable to create tx DMA map " 19991398Stmm "%d, error = %d\n", i, error); 200108832Stmm goto fail_txd; 20191398Stmm } 20291398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 20391398Stmm } 20491398Stmm 20591398Stmm /* 20691398Stmm * Create the receive buffer DMA maps. 20791398Stmm */ 20891398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 209108832Stmm if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 21091398Stmm &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 21191398Stmm device_printf(sc->sc_dev, "unable to create rx DMA map " 21291398Stmm "%d, error = %d\n", i, error); 213108832Stmm goto fail_rxd; 21491398Stmm } 21591398Stmm sc->sc_rxsoft[i].rxs_mbuf = NULL; 21691398Stmm } 21791398Stmm 21891398Stmm 21991398Stmm gem_mifinit(sc); 22091398Stmm 22191398Stmm if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange, 22291398Stmm gem_mediastatus)) != 0) { 22391398Stmm device_printf(sc->sc_dev, "phy probe failed: %d\n", error); 224108832Stmm goto fail_rxd; 22591398Stmm } 22691398Stmm sc->sc_mii = device_get_softc(sc->sc_miibus); 22791398Stmm 22891398Stmm /* 22991398Stmm * From this point forward, the attachment cannot fail. A failure 23091398Stmm * before this point releases all resources that may have been 23191398Stmm * allocated. 23291398Stmm */ 23391398Stmm 23491398Stmm /* Announce ourselves. */ 23591398Stmm device_printf(sc->sc_dev, "Ethernet address:"); 23691398Stmm for (i = 0; i < 6; i++) 23791398Stmm printf("%c%02x", i > 0 ? ':' : ' ', sc->sc_arpcom.ac_enaddr[i]); 23891398Stmm 23999726Sbenno /* Get RX FIFO size */ 24099726Sbenno sc->sc_rxfifosize = 64 * 24199726Sbenno bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 24299726Sbenno printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 24399726Sbenno 24499726Sbenno /* Get TX FIFO size */ 24599726Sbenno v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 24699726Sbenno printf(", %uKB TX fifo\n", v / 16); 24799726Sbenno 24891398Stmm /* Initialize ifnet structure. */ 24991398Stmm ifp->if_softc = sc; 25091398Stmm ifp->if_unit = device_get_unit(sc->sc_dev); 25191398Stmm ifp->if_name = "gem"; 25291398Stmm ifp->if_mtu = ETHERMTU; 25391398Stmm ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 25491398Stmm ifp->if_start = gem_start; 25591398Stmm ifp->if_ioctl = gem_ioctl; 25691398Stmm ifp->if_watchdog = gem_watchdog; 25791398Stmm ifp->if_init = gem_init; 25891398Stmm ifp->if_output = ether_output; 25991398Stmm ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN; 26091398Stmm /* 26191398Stmm * Walk along the list of attached MII devices and 26291398Stmm * establish an `MII instance' to `phy number' 26391398Stmm * mapping. We'll use this mapping in media change 26491398Stmm * requests to determine which phy to use to program 26591398Stmm * the MIF configuration register. 26691398Stmm */ 26791398Stmm for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL; 26891398Stmm child = LIST_NEXT(child, mii_list)) { 26991398Stmm /* 27091398Stmm * Note: we support just two PHYs: the built-in 27191398Stmm * internal device and an external on the MII 27291398Stmm * connector. 27391398Stmm */ 27491398Stmm if (child->mii_phy > 1 || child->mii_inst > 1) { 27591398Stmm device_printf(sc->sc_dev, "cannot accomodate " 27691398Stmm "MII device %s at phy %d, instance %d\n", 27791398Stmm device_get_name(child->mii_dev), 27891398Stmm child->mii_phy, child->mii_inst); 27991398Stmm continue; 28091398Stmm } 28191398Stmm 28291398Stmm sc->sc_phys[child->mii_inst] = child->mii_phy; 28391398Stmm } 28491398Stmm 28591398Stmm /* 28691398Stmm * Now select and activate the PHY we will use. 28791398Stmm * 28891398Stmm * The order of preference is External (MDI1), 28991398Stmm * Internal (MDI0), Serial Link (no MII). 29091398Stmm */ 29191398Stmm if (sc->sc_phys[1]) { 29291398Stmm#ifdef GEM_DEBUG 29391398Stmm printf("using external phy\n"); 29491398Stmm#endif 29591398Stmm sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 29691398Stmm } else { 29791398Stmm#ifdef GEM_DEBUG 29891398Stmm printf("using internal phy\n"); 29991398Stmm#endif 30091398Stmm sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 30191398Stmm } 30291398Stmm bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 30391398Stmm sc->sc_mif_config); 30491398Stmm /* Attach the interface. */ 305106937Ssam ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr); 30691398Stmm 30791398Stmm#if notyet 30891398Stmm /* 30991398Stmm * Add a suspend hook to make sure we come back up after a 31091398Stmm * resume. 31191398Stmm */ 31291398Stmm sc->sc_powerhook = powerhook_establish(gem_power, sc); 31391398Stmm if (sc->sc_powerhook == NULL) 31491398Stmm device_printf(sc->sc_dev, "WARNING: unable to establish power " 31591398Stmm "hook\n"); 31691398Stmm#endif 31791398Stmm 31891398Stmm callout_init(&sc->sc_tick_ch, 0); 31993045Stmm callout_init(&sc->sc_rx_ch, 0); 32091398Stmm return (0); 32191398Stmm 32291398Stmm /* 32391398Stmm * Free any resources we've allocated during the failed attach 32491398Stmm * attempt. Do this in reverse order and fall through. 32591398Stmm */ 326108832Stmmfail_rxd: 32791398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 32891398Stmm if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 329108832Stmm bus_dmamap_destroy(sc->sc_rdmatag, 33091398Stmm sc->sc_rxsoft[i].rxs_dmamap); 33191398Stmm } 332108832Stmmfail_txd: 33391398Stmm for (i = 0; i < GEM_TXQUEUELEN; i++) { 33491398Stmm if (sc->sc_txsoft[i].txs_dmamap != NULL) 335108832Stmm bus_dmamap_destroy(sc->sc_tdmatag, 33691398Stmm sc->sc_txsoft[i].txs_dmamap); 33791398Stmm } 338108832Stmm bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 339108832Stmmfail_cmem: 34091398Stmm bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 34191398Stmm sc->sc_cddmamap); 342108832Stmmfail_ctag: 34391398Stmm bus_dma_tag_destroy(sc->sc_cdmatag); 344108832Stmmfail_ttag: 345108832Stmm bus_dma_tag_destroy(sc->sc_tdmatag); 346108832Stmmfail_rtag: 347108832Stmm bus_dma_tag_destroy(sc->sc_rdmatag); 348108832Stmmfail_ptag: 34991398Stmm bus_dma_tag_destroy(sc->sc_pdmatag); 35091398Stmm return (error); 35191398Stmm} 35291398Stmm 35391398Stmmstatic void 35491398Stmmgem_cddma_callback(xsc, segs, nsegs, error) 35591398Stmm void *xsc; 35691398Stmm bus_dma_segment_t *segs; 35791398Stmm int nsegs; 35891398Stmm int error; 35991398Stmm{ 36091398Stmm struct gem_softc *sc = (struct gem_softc *)xsc; 36191398Stmm 36291398Stmm if (error != 0) 36391398Stmm return; 36491398Stmm if (nsegs != 1) { 36591398Stmm /* can't happen... */ 36691398Stmm panic("gem_cddma_callback: bad control buffer segment count"); 36791398Stmm } 36891398Stmm sc->sc_cddma = segs[0].ds_addr; 36991398Stmm} 37091398Stmm 37191398Stmmstatic void 372108832Stmmgem_rxdma_callback(xsc, segs, nsegs, totsz, error) 37391398Stmm void *xsc; 37491398Stmm bus_dma_segment_t *segs; 37591398Stmm int nsegs; 376108832Stmm bus_size_t totsz; 37791398Stmm int error; 37891398Stmm{ 37991398Stmm struct gem_rxsoft *rxs = (struct gem_rxsoft *)xsc; 38091398Stmm 38191398Stmm if (error != 0) 38291398Stmm return; 383108832Stmm KASSERT(nsegs == 1, ("gem_rxdma_callback: bad dma segment count")); 38491398Stmm rxs->rxs_paddr = segs[0].ds_addr; 38591398Stmm} 38691398Stmm 38791398Stmmstatic void 388108832Stmmgem_txdma_callback(xsc, segs, nsegs, totsz, error) 38991398Stmm void *xsc; 39091398Stmm bus_dma_segment_t *segs; 39191398Stmm int nsegs; 392108832Stmm bus_size_t totsz; 39391398Stmm int error; 39491398Stmm{ 395108832Stmm struct gem_txdma *txd = (struct gem_txdma *)xsc; 396108832Stmm struct gem_softc *sc = txd->txd_sc; 397108832Stmm struct gem_txsoft *txs = txd->txd_txs; 398108832Stmm bus_size_t len = 0; 399108832Stmm uint64_t flags = 0; 400108832Stmm int seg, nexttx; 40191398Stmm 40291398Stmm if (error != 0) 40391398Stmm return; 404108832Stmm /* 405108832Stmm * Ensure we have enough descriptors free to describe 406108832Stmm * the packet. Note, we always reserve one descriptor 407108832Stmm * at the end of the ring as a termination point, to 408108832Stmm * prevent wrap-around. 409108832Stmm */ 410108832Stmm if (nsegs > sc->sc_txfree - 1) { 411108832Stmm txs->txs_ndescs = -1; 412108832Stmm return; 413108832Stmm } 414108832Stmm txs->txs_ndescs = nsegs; 41591398Stmm 416108832Stmm nexttx = txs->txs_firstdesc; 41791398Stmm /* 41891398Stmm * Initialize the transmit descriptors. 41991398Stmm */ 42091398Stmm for (seg = 0; seg < nsegs; 421108832Stmm seg++, nexttx = GEM_NEXTTX(nexttx)) { 42291398Stmm CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len " 423108832Stmm "%lx, addr %#lx (%#lx)", seg, nexttx, 42491398Stmm segs[seg].ds_len, segs[seg].ds_addr, 425108832Stmm GEM_DMA_WRITE(sc, segs[seg].ds_addr)); 426108832Stmm 427108832Stmm if (segs[seg].ds_len == 0) 428108832Stmm continue; 429108832Stmm sc->sc_txdescs[nexttx].gd_addr = 430108832Stmm GEM_DMA_WRITE(sc, segs[seg].ds_addr); 431108832Stmm KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE, 432108832Stmm ("gem_txdma_callback: segment size too large!")); 43391398Stmm flags = segs[seg].ds_len & GEM_TD_BUFSIZE; 434108832Stmm if (len == 0) { 43591398Stmm CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, " 436108832Stmm "tx %d", seg, nexttx); 43791398Stmm flags |= GEM_TD_START_OF_PACKET; 438108832Stmm if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 439108832Stmm sc->sc_txwin = 0; 44099726Sbenno flags |= GEM_TD_INTERRUPT_ME; 44199726Sbenno } 44291398Stmm } 443108832Stmm if (len + segs[seg].ds_len == totsz) { 44491398Stmm CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, " 445108832Stmm "tx %d", seg, nexttx); 44691398Stmm flags |= GEM_TD_END_OF_PACKET; 44791398Stmm } 448108832Stmm sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags); 449108832Stmm txs->txs_lastdesc = nexttx; 450108832Stmm len += segs[seg].ds_len; 45191398Stmm } 452108832Stmm KASSERT((flags & GEM_TD_END_OF_PACKET) != 0, 453108832Stmm ("gem_txdma_callback: missed end of packet!")); 45491398Stmm} 45591398Stmm 45691398Stmmstatic void 45791398Stmmgem_tick(arg) 45891398Stmm void *arg; 45991398Stmm{ 46091398Stmm struct gem_softc *sc = arg; 46191398Stmm int s; 46291398Stmm 46391398Stmm s = splnet(); 46491398Stmm mii_tick(sc->sc_mii); 46591398Stmm splx(s); 46691398Stmm 46791398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 46891398Stmm} 46991398Stmm 47091398Stmmstatic int 47191398Stmmgem_bitwait(sc, r, clr, set) 47291398Stmm struct gem_softc *sc; 47391398Stmm bus_addr_t r; 47491398Stmm u_int32_t clr; 47591398Stmm u_int32_t set; 47691398Stmm{ 47791398Stmm int i; 47891398Stmm u_int32_t reg; 47991398Stmm 48091398Stmm for (i = TRIES; i--; DELAY(100)) { 48191398Stmm reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 48291398Stmm if ((r & clr) == 0 && (r & set) == set) 48391398Stmm return (1); 48491398Stmm } 48591398Stmm return (0); 48691398Stmm} 48791398Stmm 48891398Stmmvoid 48991398Stmmgem_reset(sc) 49091398Stmm struct gem_softc *sc; 49191398Stmm{ 49291398Stmm bus_space_tag_t t = sc->sc_bustag; 49391398Stmm bus_space_handle_t h = sc->sc_h; 49491398Stmm int s; 49591398Stmm 49691398Stmm s = splnet(); 49791398Stmm CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 49891398Stmm gem_reset_rx(sc); 49991398Stmm gem_reset_tx(sc); 50091398Stmm 50191398Stmm /* Do a full reset */ 50291398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 50391398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 50491398Stmm device_printf(sc->sc_dev, "cannot reset device\n"); 50591398Stmm splx(s); 50691398Stmm} 50791398Stmm 50891398Stmm 50991398Stmm/* 51091398Stmm * gem_rxdrain: 51191398Stmm * 51291398Stmm * Drain the receive queue. 51391398Stmm */ 51491398Stmmstatic void 51591398Stmmgem_rxdrain(sc) 51691398Stmm struct gem_softc *sc; 51791398Stmm{ 51891398Stmm struct gem_rxsoft *rxs; 51991398Stmm int i; 52091398Stmm 52191398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 52291398Stmm rxs = &sc->sc_rxsoft[i]; 52391398Stmm if (rxs->rxs_mbuf != NULL) { 524108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 52591398Stmm m_freem(rxs->rxs_mbuf); 52691398Stmm rxs->rxs_mbuf = NULL; 52791398Stmm } 52891398Stmm } 52991398Stmm} 53091398Stmm 53191398Stmm/* 53291398Stmm * Reset the whole thing. 53391398Stmm */ 53491398Stmmstatic void 53591398Stmmgem_stop(ifp, disable) 53691398Stmm struct ifnet *ifp; 53791398Stmm int disable; 53891398Stmm{ 53991398Stmm struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 54091398Stmm struct gem_txsoft *txs; 54191398Stmm 54291398Stmm CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev)); 54391398Stmm 54491398Stmm callout_stop(&sc->sc_tick_ch); 54591398Stmm 54691398Stmm /* XXX - Should we reset these instead? */ 54791398Stmm gem_disable_tx(sc); 54891398Stmm gem_disable_rx(sc); 54991398Stmm 55091398Stmm /* 55191398Stmm * Release any queued transmit buffers. 55291398Stmm */ 55391398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 55491398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 55591398Stmm if (txs->txs_ndescs != 0) { 556108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 55791398Stmm if (txs->txs_mbuf != NULL) { 55891398Stmm m_freem(txs->txs_mbuf); 55991398Stmm txs->txs_mbuf = NULL; 56091398Stmm } 56191398Stmm } 56291398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 56391398Stmm } 56491398Stmm 56591398Stmm if (disable) 56691398Stmm gem_rxdrain(sc); 56791398Stmm 56891398Stmm /* 56991398Stmm * Mark the interface down and cancel the watchdog timer. 57091398Stmm */ 57191398Stmm ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 57291398Stmm ifp->if_timer = 0; 57391398Stmm} 57491398Stmm 57591398Stmm/* 57691398Stmm * Reset the receiver 57791398Stmm */ 57891398Stmmint 57991398Stmmgem_reset_rx(sc) 58091398Stmm struct gem_softc *sc; 58191398Stmm{ 58291398Stmm bus_space_tag_t t = sc->sc_bustag; 58391398Stmm bus_space_handle_t h = sc->sc_h; 58491398Stmm 58591398Stmm /* 58691398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 58791398Stmm * disable DMA first. 58891398Stmm */ 58991398Stmm gem_disable_rx(sc); 59091398Stmm bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 59191398Stmm /* Wait till it finishes */ 59291398Stmm if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 59391398Stmm device_printf(sc->sc_dev, "cannot disable read dma\n"); 59491398Stmm 59591398Stmm /* Wait 5ms extra. */ 59691398Stmm DELAY(5000); 59791398Stmm 59891398Stmm /* Finally, reset the ERX */ 59991398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 60091398Stmm /* Wait till it finishes */ 60191398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 60291398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 60391398Stmm return (1); 60491398Stmm } 60591398Stmm return (0); 60691398Stmm} 60791398Stmm 60891398Stmm 60991398Stmm/* 61091398Stmm * Reset the transmitter 61191398Stmm */ 61291398Stmmstatic int 61391398Stmmgem_reset_tx(sc) 61491398Stmm struct gem_softc *sc; 61591398Stmm{ 61691398Stmm bus_space_tag_t t = sc->sc_bustag; 61791398Stmm bus_space_handle_t h = sc->sc_h; 61891398Stmm int i; 61991398Stmm 62091398Stmm /* 62191398Stmm * Resetting while DMA is in progress can cause a bus hang, so we 62291398Stmm * disable DMA first. 62391398Stmm */ 62491398Stmm gem_disable_tx(sc); 62591398Stmm bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 62691398Stmm /* Wait till it finishes */ 62791398Stmm if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 62891398Stmm device_printf(sc->sc_dev, "cannot disable read dma\n"); 62991398Stmm 63091398Stmm /* Wait 5ms extra. */ 63191398Stmm DELAY(5000); 63291398Stmm 63391398Stmm /* Finally, reset the ETX */ 63491398Stmm bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 63591398Stmm /* Wait till it finishes */ 63691398Stmm for (i = TRIES; i--; DELAY(100)) 63791398Stmm if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 63891398Stmm break; 63991398Stmm if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 64091398Stmm device_printf(sc->sc_dev, "cannot reset receiver\n"); 64191398Stmm return (1); 64291398Stmm } 64391398Stmm return (0); 64491398Stmm} 64591398Stmm 64691398Stmm/* 64791398Stmm * disable receiver. 64891398Stmm */ 64991398Stmmstatic int 65091398Stmmgem_disable_rx(sc) 65191398Stmm struct gem_softc *sc; 65291398Stmm{ 65391398Stmm bus_space_tag_t t = sc->sc_bustag; 65491398Stmm bus_space_handle_t h = sc->sc_h; 65591398Stmm u_int32_t cfg; 65691398Stmm 65791398Stmm /* Flip the enable bit */ 65891398Stmm cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 65991398Stmm cfg &= ~GEM_MAC_RX_ENABLE; 66091398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 66191398Stmm 66291398Stmm /* Wait for it to finish */ 66391398Stmm return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 66491398Stmm} 66591398Stmm 66691398Stmm/* 66791398Stmm * disable transmitter. 66891398Stmm */ 66991398Stmmstatic int 67091398Stmmgem_disable_tx(sc) 67191398Stmm struct gem_softc *sc; 67291398Stmm{ 67391398Stmm bus_space_tag_t t = sc->sc_bustag; 67491398Stmm bus_space_handle_t h = sc->sc_h; 67591398Stmm u_int32_t cfg; 67691398Stmm 67791398Stmm /* Flip the enable bit */ 67891398Stmm cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 67991398Stmm cfg &= ~GEM_MAC_TX_ENABLE; 68091398Stmm bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 68191398Stmm 68291398Stmm /* Wait for it to finish */ 68391398Stmm return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 68491398Stmm} 68591398Stmm 68691398Stmm/* 68791398Stmm * Initialize interface. 68891398Stmm */ 68991398Stmmstatic int 69091398Stmmgem_meminit(sc) 69191398Stmm struct gem_softc *sc; 69291398Stmm{ 69391398Stmm struct gem_rxsoft *rxs; 69491398Stmm int i, error; 69591398Stmm 69691398Stmm /* 69791398Stmm * Initialize the transmit descriptor ring. 69891398Stmm */ 69991398Stmm memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 70091398Stmm for (i = 0; i < GEM_NTXDESC; i++) { 70191398Stmm sc->sc_txdescs[i].gd_flags = 0; 70291398Stmm sc->sc_txdescs[i].gd_addr = 0; 70391398Stmm } 70491398Stmm GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 70591398Stmm BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 706108832Stmm sc->sc_txfree = GEM_MAXTXFREE; 70791398Stmm sc->sc_txnext = 0; 70899726Sbenno sc->sc_txwin = 0; 70991398Stmm 71091398Stmm /* 71191398Stmm * Initialize the receive descriptor and receive job 71291398Stmm * descriptor rings. 71391398Stmm */ 71491398Stmm for (i = 0; i < GEM_NRXDESC; i++) { 71591398Stmm rxs = &sc->sc_rxsoft[i]; 71691398Stmm if (rxs->rxs_mbuf == NULL) { 71791398Stmm if ((error = gem_add_rxbuf(sc, i)) != 0) { 71891398Stmm device_printf(sc->sc_dev, "unable to " 71991398Stmm "allocate or map rx buffer %d, error = " 72091398Stmm "%d\n", i, error); 72191398Stmm /* 72291398Stmm * XXX Should attempt to run with fewer receive 72391398Stmm * XXX buffers instead of just failing. 72491398Stmm */ 72591398Stmm gem_rxdrain(sc); 72691398Stmm return (1); 72791398Stmm } 72891398Stmm } else 72991398Stmm GEM_INIT_RXDESC(sc, i); 73091398Stmm } 73191398Stmm sc->sc_rxptr = 0; 73291398Stmm 73391398Stmm return (0); 73491398Stmm} 73591398Stmm 73691398Stmmstatic int 73791398Stmmgem_ringsize(sz) 73891398Stmm int sz; 73991398Stmm{ 74091398Stmm int v = 0; 74191398Stmm 74291398Stmm switch (sz) { 74391398Stmm case 32: 74491398Stmm v = GEM_RING_SZ_32; 74591398Stmm break; 74691398Stmm case 64: 74791398Stmm v = GEM_RING_SZ_64; 74891398Stmm break; 74991398Stmm case 128: 75091398Stmm v = GEM_RING_SZ_128; 75191398Stmm break; 75291398Stmm case 256: 75391398Stmm v = GEM_RING_SZ_256; 75491398Stmm break; 75591398Stmm case 512: 75691398Stmm v = GEM_RING_SZ_512; 75791398Stmm break; 75891398Stmm case 1024: 75991398Stmm v = GEM_RING_SZ_1024; 76091398Stmm break; 76191398Stmm case 2048: 76291398Stmm v = GEM_RING_SZ_2048; 76391398Stmm break; 76491398Stmm case 4096: 76591398Stmm v = GEM_RING_SZ_4096; 76691398Stmm break; 76791398Stmm case 8192: 76891398Stmm v = GEM_RING_SZ_8192; 76991398Stmm break; 77091398Stmm default: 77191398Stmm printf("gem: invalid Receive Descriptor ring size\n"); 77291398Stmm break; 77391398Stmm } 77491398Stmm return (v); 77591398Stmm} 77691398Stmm 77791398Stmm/* 77891398Stmm * Initialization of interface; set up initialization block 77991398Stmm * and transmit/receive descriptor rings. 78091398Stmm */ 78191398Stmmstatic void 78291398Stmmgem_init(xsc) 78391398Stmm void *xsc; 78491398Stmm{ 78591398Stmm struct gem_softc *sc = (struct gem_softc *)xsc; 78691398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 78791398Stmm bus_space_tag_t t = sc->sc_bustag; 78891398Stmm bus_space_handle_t h = sc->sc_h; 78991398Stmm int s; 79091398Stmm u_int32_t v; 79191398Stmm 79291398Stmm s = splnet(); 79391398Stmm 79491398Stmm CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 79591398Stmm /* 79691398Stmm * Initialization sequence. The numbered steps below correspond 79791398Stmm * to the sequence outlined in section 6.3.5.1 in the Ethernet 79891398Stmm * Channel Engine manual (part of the PCIO manual). 79991398Stmm * See also the STP2002-STQ document from Sun Microsystems. 80091398Stmm */ 80191398Stmm 80291398Stmm /* step 1 & 2. Reset the Ethernet Channel */ 80391398Stmm gem_stop(&sc->sc_arpcom.ac_if, 0); 80491398Stmm gem_reset(sc); 80591398Stmm CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev)); 80691398Stmm 80791398Stmm /* Re-initialize the MIF */ 80891398Stmm gem_mifinit(sc); 80991398Stmm 81091398Stmm /* step 3. Setup data structures in host memory */ 81191398Stmm gem_meminit(sc); 81291398Stmm 81391398Stmm /* step 4. TX MAC registers & counters */ 81491398Stmm gem_init_regs(sc); 81591398Stmm /* XXX: VLAN code from NetBSD temporarily removed. */ 81691398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 81791398Stmm (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 81891398Stmm 81991398Stmm /* step 5. RX MAC registers & counters */ 82091398Stmm gem_setladrf(sc); 82191398Stmm 82291398Stmm /* step 6 & 7. Program Descriptor Ring Base Addresses */ 82391398Stmm /* NOTE: we use only 32-bit DMA addresses here. */ 82491398Stmm bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 82591398Stmm bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 82691398Stmm 82791398Stmm bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 82891398Stmm bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 82991398Stmm CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 83091398Stmm GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 83191398Stmm 83291398Stmm /* step 8. Global Configuration & Interrupt Mask */ 83391398Stmm bus_space_write_4(t, h, GEM_INTMASK, 83491398Stmm ~(GEM_INTR_TX_INTME| 83591398Stmm GEM_INTR_TX_EMPTY| 83691398Stmm GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 83791398Stmm GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 83891398Stmm GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 83991398Stmm GEM_INTR_BERR)); 84099726Sbenno bus_space_write_4(t, h, GEM_MAC_RX_MASK, 84199726Sbenno GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 84291398Stmm bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 84391398Stmm bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 84491398Stmm 84591398Stmm /* step 9. ETX Configuration: use mostly default values */ 84691398Stmm 84791398Stmm /* Enable DMA */ 84891398Stmm v = gem_ringsize(GEM_NTXDESC /*XXX*/); 84991398Stmm bus_space_write_4(t, h, GEM_TX_CONFIG, 85091398Stmm v|GEM_TX_CONFIG_TXDMA_EN| 85191398Stmm ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 85291398Stmm 85391398Stmm /* step 10. ERX Configuration */ 85491398Stmm 85591398Stmm /* Encode Receive Descriptor ring size: four possible values */ 85691398Stmm v = gem_ringsize(GEM_NRXDESC /*XXX*/); 85791398Stmm 85891398Stmm /* Enable DMA */ 85991398Stmm bus_space_write_4(t, h, GEM_RX_CONFIG, 86091398Stmm v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 86191398Stmm (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 86291398Stmm (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 86391398Stmm /* 86499726Sbenno * The following value is for an OFF Threshold of about 3/4 full 86599726Sbenno * and an ON Threshold of 1/4 full. 86691398Stmm */ 86799726Sbenno bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 86899726Sbenno (3 * sc->sc_rxfifosize / 256) | 86999726Sbenno ( (sc->sc_rxfifosize / 256) << 12)); 87099726Sbenno bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 87191398Stmm 87291398Stmm /* step 11. Configure Media */ 87399726Sbenno mii_mediachg(sc->sc_mii); 87491398Stmm 87591398Stmm /* step 12. RX_MAC Configuration Register */ 87691398Stmm v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 87791398Stmm v |= GEM_MAC_RX_ENABLE; 87891398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 87991398Stmm 88091398Stmm /* step 14. Issue Transmit Pending command */ 88191398Stmm 88291398Stmm /* step 15. Give the reciever a swift kick */ 88391398Stmm bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 88491398Stmm 88591398Stmm /* Start the one second timer. */ 88691398Stmm callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 88791398Stmm 88891398Stmm ifp->if_flags |= IFF_RUNNING; 88991398Stmm ifp->if_flags &= ~IFF_OACTIVE; 89091398Stmm ifp->if_timer = 0; 89199726Sbenno sc->sc_ifflags = ifp->if_flags; 89291398Stmm splx(s); 89391398Stmm} 89491398Stmm 89591398Stmmstatic int 896108832Stmmgem_load_txmbuf(sc, m0) 89791398Stmm struct gem_softc *sc; 89891398Stmm struct mbuf *m0; 89991398Stmm{ 90091398Stmm struct gem_txdma txd; 90191398Stmm struct gem_txsoft *txs; 902108832Stmm int error; 90391398Stmm 904108832Stmm /* Get a work queue entry. */ 905108832Stmm if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 906108832Stmm /* Ran out of descriptors. */ 907108832Stmm return (-1); 908108832Stmm } 90991398Stmm txd.txd_sc = sc; 910108832Stmm txd.txd_txs = txs; 911108832Stmm txs->txs_mbuf = m0; 912108832Stmm txs->txs_firstdesc = sc->sc_txnext; 913108832Stmm error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0, 914108832Stmm gem_txdma_callback, &txd, BUS_DMA_NOWAIT); 915108832Stmm if (error != 0) 916108832Stmm goto fail; 917108832Stmm if (txs->txs_ndescs == -1) { 918108832Stmm error = -1; 919108832Stmm goto fail; 92091398Stmm } 92191398Stmm 922108832Stmm /* Sync the DMA map. */ 923108832Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 924108832Stmm BUS_DMASYNC_PREWRITE); 92591398Stmm 926108832Stmm CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, " 927108832Stmm "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc, 928108832Stmm txs->txs_ndescs); 929108832Stmm STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 930108832Stmm STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 93191398Stmm 932108832Stmm /* Sync the descriptors we're using. */ 933108832Stmm GEM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndescs, 934108832Stmm BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 93591398Stmm 936108832Stmm sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 937108832Stmm sc->sc_txfree -= txs->txs_ndescs; 938108832Stmm return (0); 93991398Stmm 940108832Stmmfail: 941108832Stmm CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error); 942108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 943108832Stmm return (error); 94491398Stmm} 94591398Stmm 94691398Stmmstatic void 94791398Stmmgem_init_regs(sc) 94891398Stmm struct gem_softc *sc; 94991398Stmm{ 95091398Stmm bus_space_tag_t t = sc->sc_bustag; 95191398Stmm bus_space_handle_t h = sc->sc_h; 95299726Sbenno const u_char *laddr = sc->sc_arpcom.ac_enaddr; 95399726Sbenno u_int32_t v; 95491398Stmm 95591398Stmm /* These regs are not cleared on reset */ 95691398Stmm if (!sc->sc_inited) { 95791398Stmm 95891398Stmm /* Wooo. Magic values. */ 95991398Stmm bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 96091398Stmm bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 96191398Stmm bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 96291398Stmm 96391398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 96491398Stmm /* Max frame and max burst size */ 96591398Stmm bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 96699726Sbenno ETHER_MAX_LEN | (0x2000<<16)); 96799726Sbenno 96891398Stmm bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 96991398Stmm bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 97091398Stmm bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 97191398Stmm /* Dunno.... */ 97291398Stmm bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 97391398Stmm bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 97499726Sbenno ((laddr[5]<<8)|laddr[4])&0x3ff); 97599726Sbenno 97691398Stmm /* Secondary MAC addr set to 0:0:0:0:0:0 */ 97791398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 97891398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 97991398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 98099726Sbenno 98199726Sbenno /* MAC control addr set to 01:80:c2:00:00:01 */ 98291398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 98391398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 98491398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 98591398Stmm 98691398Stmm /* MAC filter addr set to 0:0:0:0:0:0 */ 98791398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 98891398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 98991398Stmm bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 99091398Stmm 99191398Stmm bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 99291398Stmm bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 99391398Stmm 99491398Stmm sc->sc_inited = 1; 99591398Stmm } 99691398Stmm 99791398Stmm /* Counters need to be zeroed */ 99891398Stmm bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 99991398Stmm bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 100091398Stmm bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 100191398Stmm bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 100291398Stmm bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 100391398Stmm bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 100491398Stmm bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 100591398Stmm bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 100691398Stmm bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 100791398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 100891398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 100991398Stmm 101091398Stmm /* Un-pause stuff */ 101191398Stmm#if 0 101291398Stmm bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 101391398Stmm#else 101491398Stmm bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 101591398Stmm#endif 101691398Stmm 101791398Stmm /* 101891398Stmm * Set the station address. 101991398Stmm */ 102099726Sbenno bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 102199726Sbenno bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 102299726Sbenno bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 102399726Sbenno 102499726Sbenno /* 102599726Sbenno * Enable MII outputs. Enable GMII if there is a gigabit PHY. 102699726Sbenno */ 102799726Sbenno sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 102899726Sbenno v = GEM_MAC_XIF_TX_MII_ENA; 102999726Sbenno if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 103099726Sbenno v |= GEM_MAC_XIF_FDPLX_LED; 103199726Sbenno if (sc->sc_flags & GEM_GIGABIT) 103299726Sbenno v |= GEM_MAC_XIF_GMII_MODE; 103399726Sbenno } 103499726Sbenno bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 103591398Stmm} 103691398Stmm 103791398Stmmstatic void 103891398Stmmgem_start(ifp) 103991398Stmm struct ifnet *ifp; 104091398Stmm{ 104191398Stmm struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1042108832Stmm struct mbuf *m0 = NULL; 1043108832Stmm int firsttx, ntx, ofree, txmfail; 104491398Stmm 104591398Stmm if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 104691398Stmm return; 104791398Stmm 104891398Stmm /* 104991398Stmm * Remember the previous number of free descriptors and 105091398Stmm * the first descriptor we'll use. 105191398Stmm */ 105291398Stmm ofree = sc->sc_txfree; 105391398Stmm firsttx = sc->sc_txnext; 105491398Stmm 105591398Stmm CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d", 105691398Stmm device_get_name(sc->sc_dev), ofree, firsttx); 105791398Stmm 105891398Stmm /* 105991398Stmm * Loop through the send queue, setting up transmit descriptors 106091398Stmm * until we drain the queue, or use up all available transmit 106191398Stmm * descriptors. 106291398Stmm */ 106391398Stmm txmfail = 0; 106491398Stmm for (ntx = 0;; ntx++) { 106591398Stmm /* 106691398Stmm * Grab a packet off the queue. 106791398Stmm */ 106891398Stmm IF_DEQUEUE(&ifp->if_snd, m0); 106991398Stmm if (m0 == NULL) 107091398Stmm break; 107191398Stmm 1072108832Stmm txmfail = gem_load_txmbuf(sc, m0); 107391398Stmm if (txmfail > 0) { 1074108832Stmm /* Drop the mbuf and complain. */ 1075108832Stmm printf("gem_start: error %d while loading mbuf dma " 1076108832Stmm "map\n", txmfail); 1077108832Stmm continue; 107891398Stmm } 1079108832Stmm /* Not enough descriptors. */ 1080108832Stmm if (txmfail == -1) { 1081108832Stmm if (sc->sc_txfree == GEM_MAXTXFREE) 1082108832Stmm panic("gem_start: mbuf chain too long!"); 108391398Stmm IF_PREPEND(&ifp->if_snd, m0); 108491398Stmm break; 108591398Stmm } 108691398Stmm 1087108832Stmm /* Kick the transmitter. */ 1088108832Stmm CTR2(KTR_GEM, "%s: gem_start: kicking tx %d", 1089108832Stmm device_get_name(sc->sc_dev), sc->sc_txnext); 1090108832Stmm bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1091108832Stmm sc->sc_txnext); 1092108832Stmm 1093105982Stmm if (ifp->if_bpf != NULL) 1094106950Smux bpf_mtap(ifp->if_bpf, m0); 109591398Stmm } 109691398Stmm 109791398Stmm if (txmfail == -1 || sc->sc_txfree == 0) { 1098108832Stmm /* No more slots left; notify upper layer. */ 109991398Stmm ifp->if_flags |= IFF_OACTIVE; 110091398Stmm } 110191398Stmm 110291398Stmm if (ntx > 0) { 1103108832Stmm CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1104108832Stmm device_get_name(sc->sc_dev), firsttx); 110591398Stmm 110691398Stmm /* Set a watchdog timer in case the chip flakes out. */ 110791398Stmm ifp->if_timer = 5; 110891398Stmm CTR2(KTR_GEM, "%s: gem_start: watchdog %d", 110991398Stmm device_get_name(sc->sc_dev), ifp->if_timer); 111091398Stmm } 111191398Stmm} 111291398Stmm 111391398Stmm/* 111491398Stmm * Transmit interrupt. 111591398Stmm */ 111691398Stmmstatic void 111791398Stmmgem_tint(sc) 111891398Stmm struct gem_softc *sc; 111991398Stmm{ 112091398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 112191398Stmm bus_space_tag_t t = sc->sc_bustag; 112291398Stmm bus_space_handle_t mac = sc->sc_h; 112391398Stmm struct gem_txsoft *txs; 112491398Stmm int txlast; 112599726Sbenno int progress = 0; 112691398Stmm 112791398Stmm 112891398Stmm CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 112991398Stmm 113091398Stmm /* 113191398Stmm * Unload collision counters 113291398Stmm */ 113391398Stmm ifp->if_collisions += 113491398Stmm bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 113591398Stmm bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 113691398Stmm bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 113791398Stmm bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 113891398Stmm 113991398Stmm /* 114091398Stmm * then clear the hardware counters. 114191398Stmm */ 114291398Stmm bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 114391398Stmm bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 114491398Stmm bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 114591398Stmm bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 114691398Stmm 114791398Stmm /* 114891398Stmm * Go through our Tx list and free mbufs for those 114991398Stmm * frames that have been transmitted. 115091398Stmm */ 115191398Stmm while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 115291398Stmm GEM_CDTXSYNC(sc, txs->txs_lastdesc, 115391398Stmm txs->txs_ndescs, 115491398Stmm BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 115591398Stmm 115691398Stmm#ifdef GEM_DEBUG 115791398Stmm if (ifp->if_flags & IFF_DEBUG) { 115891398Stmm int i; 115991398Stmm printf(" txsoft %p transmit chain:\n", txs); 116091398Stmm for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 116191398Stmm printf("descriptor %d: ", i); 116291398Stmm printf("gd_flags: 0x%016llx\t", (long long) 116391398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 116491398Stmm printf("gd_addr: 0x%016llx\n", (long long) 116591398Stmm GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 116691398Stmm if (i == txs->txs_lastdesc) 116791398Stmm break; 116891398Stmm } 116991398Stmm } 117091398Stmm#endif 117191398Stmm 117291398Stmm /* 117391398Stmm * In theory, we could harveast some descriptors before 117491398Stmm * the ring is empty, but that's a bit complicated. 117591398Stmm * 117691398Stmm * GEM_TX_COMPLETION points to the last descriptor 117791398Stmm * processed +1. 117891398Stmm */ 117991398Stmm txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 118091398Stmm CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 118191398Stmm "txs->txs_lastdesc = %d, txlast = %d", 118291398Stmm txs->txs_firstdesc, txs->txs_lastdesc, txlast); 118391398Stmm if (txs->txs_firstdesc <= txs->txs_lastdesc) { 118491398Stmm if ((txlast >= txs->txs_firstdesc) && 118591398Stmm (txlast <= txs->txs_lastdesc)) 118691398Stmm break; 118791398Stmm } else { 118891398Stmm /* Ick -- this command wraps */ 118991398Stmm if ((txlast >= txs->txs_firstdesc) || 119091398Stmm (txlast <= txs->txs_lastdesc)) 119191398Stmm break; 119291398Stmm } 119391398Stmm 119491398Stmm CTR0(KTR_GEM, "gem_tint: releasing a desc"); 119591398Stmm STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 119691398Stmm 119791398Stmm sc->sc_txfree += txs->txs_ndescs; 119891398Stmm 1199108832Stmm bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 120091398Stmm BUS_DMASYNC_POSTWRITE); 1201108832Stmm bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 120291398Stmm if (txs->txs_mbuf != NULL) { 120391398Stmm m_freem(txs->txs_mbuf); 120491398Stmm txs->txs_mbuf = NULL; 120591398Stmm } 120691398Stmm 120791398Stmm STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 120891398Stmm 120991398Stmm ifp->if_opackets++; 121099726Sbenno progress = 1; 121191398Stmm } 121291398Stmm 121391398Stmm CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 121491398Stmm "GEM_TX_DATA_PTR %llx " 121591398Stmm "GEM_TX_COMPLETION %x", 121691398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 121791398Stmm ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 121891398Stmm GEM_TX_DATA_PTR_HI) << 32) | 121991398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, 122091398Stmm GEM_TX_DATA_PTR_LO), 122191398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION)); 122291398Stmm 122399726Sbenno if (progress) { 122499726Sbenno if (sc->sc_txfree == GEM_NTXDESC - 1) 122599726Sbenno sc->sc_txwin = 0; 122691398Stmm 122799726Sbenno /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 122899726Sbenno ifp->if_flags &= ~IFF_OACTIVE; 122999726Sbenno gem_start(ifp); 123091398Stmm 123199726Sbenno if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 123299726Sbenno ifp->if_timer = 0; 123399726Sbenno } 123499726Sbenno 123591398Stmm CTR2(KTR_GEM, "%s: gem_tint: watchdog %d", 123691398Stmm device_get_name(sc->sc_dev), ifp->if_timer); 123791398Stmm} 123891398Stmm 1239100587Sjake#if 0 124093045Stmmstatic void 124193045Stmmgem_rint_timeout(arg) 124293045Stmm void *arg; 124393045Stmm{ 124493045Stmm 124593045Stmm gem_rint((struct gem_softc *)arg); 124693045Stmm} 1247100587Sjake#endif 124893045Stmm 124991398Stmm/* 125091398Stmm * Receive interrupt. 125191398Stmm */ 125291398Stmmstatic void 125391398Stmmgem_rint(sc) 125491398Stmm struct gem_softc *sc; 125591398Stmm{ 125691398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 125791398Stmm bus_space_tag_t t = sc->sc_bustag; 125891398Stmm bus_space_handle_t h = sc->sc_h; 125991398Stmm struct gem_rxsoft *rxs; 126091398Stmm struct mbuf *m; 126191398Stmm u_int64_t rxstat; 126299726Sbenno u_int32_t rxcomp; 126399726Sbenno int i, len, progress = 0; 126491398Stmm 126593045Stmm callout_stop(&sc->sc_rx_ch); 126691398Stmm CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 126799726Sbenno 126891398Stmm /* 126999726Sbenno * Read the completion register once. This limits 127099726Sbenno * how long the following loop can execute. 127199726Sbenno */ 127299726Sbenno rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 127399726Sbenno 127491398Stmm CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 127599726Sbenno sc->sc_rxptr, rxcomp); 127699726Sbenno for (i = sc->sc_rxptr; i != rxcomp; 127791398Stmm i = GEM_NEXTRX(i)) { 127891398Stmm rxs = &sc->sc_rxsoft[i]; 127991398Stmm 128091398Stmm GEM_CDRXSYNC(sc, i, 128191398Stmm BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 128291398Stmm 128391398Stmm rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 128491398Stmm 128591398Stmm if (rxstat & GEM_RD_OWN) { 128699726Sbenno#if 0 /* XXX: In case of emergency, re-enable this. */ 128791398Stmm /* 128893045Stmm * The descriptor is still marked as owned, although 128993045Stmm * it is supposed to have completed. This has been 129093045Stmm * observed on some machines. Just exiting here 129193045Stmm * might leave the packet sitting around until another 129293045Stmm * one arrives to trigger a new interrupt, which is 129393045Stmm * generally undesirable, so set up a timeout. 129491398Stmm */ 129593045Stmm callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 129693045Stmm gem_rint_timeout, sc); 129799726Sbenno#endif 129891398Stmm break; 129991398Stmm } 130091398Stmm 130199726Sbenno progress++; 130299726Sbenno ifp->if_ipackets++; 130399726Sbenno 130491398Stmm if (rxstat & GEM_RD_BAD_CRC) { 130599726Sbenno ifp->if_ierrors++; 130691398Stmm device_printf(sc->sc_dev, "receive error: CRC error\n"); 130791398Stmm GEM_INIT_RXDESC(sc, i); 130891398Stmm continue; 130991398Stmm } 131091398Stmm 1311108832Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 131291398Stmm BUS_DMASYNC_POSTREAD); 131391398Stmm#ifdef GEM_DEBUG 131491398Stmm if (ifp->if_flags & IFF_DEBUG) { 131591398Stmm printf(" rxsoft %p descriptor %d: ", rxs, i); 131691398Stmm printf("gd_flags: 0x%016llx\t", (long long) 131791398Stmm GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 131891398Stmm printf("gd_addr: 0x%016llx\n", (long long) 131991398Stmm GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 132091398Stmm } 132191398Stmm#endif 132291398Stmm 132391398Stmm /* 132491398Stmm * No errors; receive the packet. Note the Gem 132591398Stmm * includes the CRC with every packet. 132691398Stmm */ 132791398Stmm len = GEM_RD_BUFLEN(rxstat); 132891398Stmm 132991398Stmm /* 133091398Stmm * Allocate a new mbuf cluster. If that fails, we are 133191398Stmm * out of memory, and must drop the packet and recycle 133291398Stmm * the buffer that's already attached to this descriptor. 133391398Stmm */ 133491398Stmm m = rxs->rxs_mbuf; 133591398Stmm if (gem_add_rxbuf(sc, i) != 0) { 133691398Stmm ifp->if_ierrors++; 133791398Stmm GEM_INIT_RXDESC(sc, i); 1338108832Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 133991398Stmm BUS_DMASYNC_PREREAD); 134091398Stmm continue; 134191398Stmm } 134291398Stmm m->m_data += 2; /* We're already off by two */ 134391398Stmm 134491398Stmm m->m_pkthdr.rcvif = ifp; 134591398Stmm m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN; 134691398Stmm 134791398Stmm /* Pass it on. */ 1348106937Ssam (*ifp->if_input)(ifp, m); 134991398Stmm } 135091398Stmm 135199726Sbenno if (progress) { 135299726Sbenno /* Update the receive pointer. */ 135399726Sbenno if (i == sc->sc_rxptr) { 135499726Sbenno device_printf(sc->sc_dev, "rint: ring wrap\n"); 135599726Sbenno } 135699726Sbenno sc->sc_rxptr = i; 135799726Sbenno bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 135899726Sbenno } 135991398Stmm 136091398Stmm CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", 136191398Stmm sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 136291398Stmm} 136391398Stmm 136491398Stmm 136591398Stmm/* 136691398Stmm * gem_add_rxbuf: 136791398Stmm * 136891398Stmm * Add a receive buffer to the indicated descriptor. 136991398Stmm */ 137091398Stmmstatic int 137191398Stmmgem_add_rxbuf(sc, idx) 137291398Stmm struct gem_softc *sc; 137391398Stmm int idx; 137491398Stmm{ 137591398Stmm struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 137691398Stmm struct mbuf *m; 137791398Stmm int error; 137891398Stmm 1379108832Stmm m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 138091398Stmm if (m == NULL) 138191398Stmm return (ENOBUFS); 1382108832Stmm m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 138391398Stmm 138491398Stmm#ifdef GEM_DEBUG 138591398Stmm /* bzero the packet to check dma */ 138691398Stmm memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 138791398Stmm#endif 138891398Stmm 138991398Stmm if (rxs->rxs_mbuf != NULL) 1390108832Stmm bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 139191398Stmm 139291398Stmm rxs->rxs_mbuf = m; 139391398Stmm 1394108832Stmm error = bus_dmamap_load_mbuf(sc->sc_rdmatag, rxs->rxs_dmamap, 1395108832Stmm m, gem_rxdma_callback, rxs, BUS_DMA_NOWAIT); 139691398Stmm if (error != 0 || rxs->rxs_paddr == 0) { 139791398Stmm device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " 139891398Stmm "%d\n", idx, error); 139991398Stmm panic("gem_add_rxbuf"); /* XXX */ 140091398Stmm } 140191398Stmm 1402108832Stmm bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 140391398Stmm 140491398Stmm GEM_INIT_RXDESC(sc, idx); 140591398Stmm 140691398Stmm return (0); 140791398Stmm} 140891398Stmm 140991398Stmm 141091398Stmmstatic void 141191398Stmmgem_eint(sc, status) 141291398Stmm struct gem_softc *sc; 141391398Stmm u_int status; 141491398Stmm{ 141591398Stmm 141691398Stmm if ((status & GEM_INTR_MIF) != 0) { 141791398Stmm device_printf(sc->sc_dev, "XXXlink status changed\n"); 141891398Stmm return; 141991398Stmm } 142091398Stmm 142191398Stmm device_printf(sc->sc_dev, "status=%x\n", status); 142291398Stmm} 142391398Stmm 142491398Stmm 142591398Stmmvoid 142691398Stmmgem_intr(v) 142791398Stmm void *v; 142891398Stmm{ 142991398Stmm struct gem_softc *sc = (struct gem_softc *)v; 143091398Stmm bus_space_tag_t t = sc->sc_bustag; 143191398Stmm bus_space_handle_t seb = sc->sc_h; 143291398Stmm u_int32_t status; 143391398Stmm 143491398Stmm status = bus_space_read_4(t, seb, GEM_STATUS); 143591398Stmm CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 143691398Stmm device_get_name(sc->sc_dev), (status>>19), 143791398Stmm (u_int)status); 143891398Stmm 143991398Stmm if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 144091398Stmm gem_eint(sc, status); 144191398Stmm 144291398Stmm if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 144391398Stmm gem_tint(sc); 144491398Stmm 144591398Stmm if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 144691398Stmm gem_rint(sc); 144791398Stmm 144891398Stmm /* We should eventually do more than just print out error stats. */ 144991398Stmm if (status & GEM_INTR_TX_MAC) { 145091398Stmm int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 145191398Stmm if (txstat & ~GEM_MAC_TX_XMIT_DONE) 145299726Sbenno device_printf(sc->sc_dev, "MAC tx fault, status %x\n", 145399726Sbenno txstat); 145497240Stmm if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 145597240Stmm gem_init(sc); 145691398Stmm } 145791398Stmm if (status & GEM_INTR_RX_MAC) { 145891398Stmm int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 145991398Stmm if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 146099726Sbenno device_printf(sc->sc_dev, "MAC rx fault, status %x\n", 146199726Sbenno rxstat); 146297240Stmm if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0) 146397240Stmm gem_init(sc); 146491398Stmm } 146591398Stmm} 146691398Stmm 146791398Stmm 146891398Stmmstatic void 146991398Stmmgem_watchdog(ifp) 147091398Stmm struct ifnet *ifp; 147191398Stmm{ 147291398Stmm struct gem_softc *sc = ifp->if_softc; 147391398Stmm 147491398Stmm CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 147591398Stmm "GEM_MAC_RX_CONFIG %x", 147691398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 147791398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 147891398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)); 147991398Stmm CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 148091398Stmm "GEM_MAC_TX_CONFIG %x", 148191398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 148291398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS), 148391398Stmm bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 148491398Stmm 148591398Stmm device_printf(sc->sc_dev, "device timeout\n"); 148691398Stmm ++ifp->if_oerrors; 148791398Stmm 148891398Stmm /* Try to get more packets going. */ 148991398Stmm gem_start(ifp); 149091398Stmm} 149191398Stmm 149291398Stmm/* 149391398Stmm * Initialize the MII Management Interface 149491398Stmm */ 149591398Stmmstatic void 149691398Stmmgem_mifinit(sc) 149791398Stmm struct gem_softc *sc; 149891398Stmm{ 149991398Stmm bus_space_tag_t t = sc->sc_bustag; 150091398Stmm bus_space_handle_t mif = sc->sc_h; 150191398Stmm 150291398Stmm /* Configure the MIF in frame mode */ 150391398Stmm sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 150491398Stmm sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 150591398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 150691398Stmm} 150791398Stmm 150891398Stmm/* 150991398Stmm * MII interface 151091398Stmm * 151191398Stmm * The GEM MII interface supports at least three different operating modes: 151291398Stmm * 151391398Stmm * Bitbang mode is implemented using data, clock and output enable registers. 151491398Stmm * 151591398Stmm * Frame mode is implemented by loading a complete frame into the frame 151691398Stmm * register and polling the valid bit for completion. 151791398Stmm * 151891398Stmm * Polling mode uses the frame register but completion is indicated by 151991398Stmm * an interrupt. 152091398Stmm * 152191398Stmm */ 152291398Stmmint 152391398Stmmgem_mii_readreg(dev, phy, reg) 152491398Stmm device_t dev; 152591398Stmm int phy, reg; 152691398Stmm{ 152791398Stmm struct gem_softc *sc = device_get_softc(dev); 152891398Stmm bus_space_tag_t t = sc->sc_bustag; 152991398Stmm bus_space_handle_t mif = sc->sc_h; 153091398Stmm int n; 153191398Stmm u_int32_t v; 153291398Stmm 153391398Stmm#ifdef GEM_DEBUG_PHY 153491398Stmm printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 153591398Stmm#endif 153691398Stmm 153791398Stmm#if 0 153891398Stmm /* Select the desired PHY in the MIF configuration register */ 153991398Stmm v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 154091398Stmm /* Clear PHY select bit */ 154191398Stmm v &= ~GEM_MIF_CONFIG_PHY_SEL; 154291398Stmm if (phy == GEM_PHYAD_EXTERNAL) 154391398Stmm /* Set PHY select bit to get at external device */ 154491398Stmm v |= GEM_MIF_CONFIG_PHY_SEL; 154591398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 154691398Stmm#endif 154791398Stmm 154891398Stmm /* Construct the frame command */ 154991398Stmm v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 155091398Stmm GEM_MIF_FRAME_READ; 155191398Stmm 155291398Stmm bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 155391398Stmm for (n = 0; n < 100; n++) { 155491398Stmm DELAY(1); 155591398Stmm v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 155691398Stmm if (v & GEM_MIF_FRAME_TA0) 155791398Stmm return (v & GEM_MIF_FRAME_DATA); 155891398Stmm } 155991398Stmm 156091398Stmm device_printf(sc->sc_dev, "mii_read timeout\n"); 156191398Stmm return (0); 156291398Stmm} 156391398Stmm 156491398Stmmint 156591398Stmmgem_mii_writereg(dev, phy, reg, val) 156691398Stmm device_t dev; 156791398Stmm int phy, reg, val; 156891398Stmm{ 156991398Stmm struct gem_softc *sc = device_get_softc(dev); 157091398Stmm bus_space_tag_t t = sc->sc_bustag; 157191398Stmm bus_space_handle_t mif = sc->sc_h; 157291398Stmm int n; 157391398Stmm u_int32_t v; 157491398Stmm 157591398Stmm#ifdef GEM_DEBUG_PHY 157691398Stmm printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 157791398Stmm#endif 157891398Stmm 157991398Stmm#if 0 158091398Stmm /* Select the desired PHY in the MIF configuration register */ 158191398Stmm v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 158291398Stmm /* Clear PHY select bit */ 158391398Stmm v &= ~GEM_MIF_CONFIG_PHY_SEL; 158491398Stmm if (phy == GEM_PHYAD_EXTERNAL) 158591398Stmm /* Set PHY select bit to get at external device */ 158691398Stmm v |= GEM_MIF_CONFIG_PHY_SEL; 158791398Stmm bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 158891398Stmm#endif 158991398Stmm /* Construct the frame command */ 159091398Stmm v = GEM_MIF_FRAME_WRITE | 159191398Stmm (phy << GEM_MIF_PHY_SHIFT) | 159291398Stmm (reg << GEM_MIF_REG_SHIFT) | 159391398Stmm (val & GEM_MIF_FRAME_DATA); 159491398Stmm 159591398Stmm bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 159691398Stmm for (n = 0; n < 100; n++) { 159791398Stmm DELAY(1); 159891398Stmm v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 159991398Stmm if (v & GEM_MIF_FRAME_TA0) 160091398Stmm return (1); 160191398Stmm } 160291398Stmm 160391398Stmm device_printf(sc->sc_dev, "mii_write timeout\n"); 160491398Stmm return (0); 160591398Stmm} 160691398Stmm 160791398Stmmvoid 160891398Stmmgem_mii_statchg(dev) 160991398Stmm device_t dev; 161091398Stmm{ 161191398Stmm struct gem_softc *sc = device_get_softc(dev); 161291398Stmm#ifdef GEM_DEBUG 161391398Stmm int instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 161491398Stmm#endif 161591398Stmm bus_space_tag_t t = sc->sc_bustag; 161691398Stmm bus_space_handle_t mac = sc->sc_h; 161791398Stmm u_int32_t v; 161891398Stmm 161991398Stmm#ifdef GEM_DEBUG 162091398Stmm if (sc->sc_debug) 162191398Stmm printf("gem_mii_statchg: status change: phy = %d\n", 162291398Stmm sc->sc_phys[instance]); 162391398Stmm#endif 162491398Stmm 162591398Stmm /* Set tx full duplex options */ 162691398Stmm bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 162791398Stmm DELAY(10000); /* reg must be cleared and delay before changing. */ 162891398Stmm v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 162991398Stmm GEM_MAC_TX_ENABLE; 163091398Stmm if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 163191398Stmm v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 163291398Stmm } 163391398Stmm bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 163491398Stmm 163591398Stmm /* XIF Configuration */ 163691398Stmm /* We should really calculate all this rather than rely on defaults */ 163791398Stmm v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 163891398Stmm v = GEM_MAC_XIF_LINK_LED; 163991398Stmm v |= GEM_MAC_XIF_TX_MII_ENA; 164099726Sbenno 164191398Stmm /* If an external transceiver is connected, enable its MII drivers */ 164291398Stmm sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 164391398Stmm if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 164491398Stmm /* External MII needs echo disable if half duplex. */ 164591398Stmm if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 164691398Stmm /* turn on full duplex LED */ 164791398Stmm v |= GEM_MAC_XIF_FDPLX_LED; 164899726Sbenno else 164999726Sbenno /* half duplex -- disable echo */ 165099726Sbenno v |= GEM_MAC_XIF_ECHO_DISABL; 165199726Sbenno 165299726Sbenno if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T) 165399726Sbenno v |= GEM_MAC_XIF_GMII_MODE; 165499726Sbenno else 165599726Sbenno v &= ~GEM_MAC_XIF_GMII_MODE; 165691398Stmm } else { 165791398Stmm /* Internal MII needs buf enable */ 165891398Stmm v |= GEM_MAC_XIF_MII_BUF_ENA; 165991398Stmm } 166091398Stmm bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 166191398Stmm} 166291398Stmm 166391398Stmmint 166491398Stmmgem_mediachange(ifp) 166591398Stmm struct ifnet *ifp; 166691398Stmm{ 166791398Stmm struct gem_softc *sc = ifp->if_softc; 166891398Stmm 166991398Stmm /* XXX Add support for serial media. */ 167091398Stmm 167191398Stmm return (mii_mediachg(sc->sc_mii)); 167291398Stmm} 167391398Stmm 167491398Stmmvoid 167591398Stmmgem_mediastatus(ifp, ifmr) 167691398Stmm struct ifnet *ifp; 167791398Stmm struct ifmediareq *ifmr; 167891398Stmm{ 167991398Stmm struct gem_softc *sc = ifp->if_softc; 168091398Stmm 168191398Stmm if ((ifp->if_flags & IFF_UP) == 0) 168291398Stmm return; 168391398Stmm 168491398Stmm mii_pollstat(sc->sc_mii); 168591398Stmm ifmr->ifm_active = sc->sc_mii->mii_media_active; 168691398Stmm ifmr->ifm_status = sc->sc_mii->mii_media_status; 168791398Stmm} 168891398Stmm 168991398Stmm/* 169091398Stmm * Process an ioctl request. 169191398Stmm */ 169291398Stmmstatic int 169391398Stmmgem_ioctl(ifp, cmd, data) 169491398Stmm struct ifnet *ifp; 169591398Stmm u_long cmd; 169691398Stmm caddr_t data; 169791398Stmm{ 169891398Stmm struct gem_softc *sc = ifp->if_softc; 169991398Stmm struct ifreq *ifr = (struct ifreq *)data; 170091398Stmm int s, error = 0; 170191398Stmm 170291398Stmm switch (cmd) { 170391398Stmm case SIOCSIFADDR: 170491398Stmm case SIOCGIFADDR: 170591398Stmm case SIOCSIFMTU: 170691398Stmm error = ether_ioctl(ifp, cmd, data); 170791398Stmm break; 170891398Stmm case SIOCSIFFLAGS: 170991398Stmm if (ifp->if_flags & IFF_UP) { 171099726Sbenno if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC) 171191398Stmm gem_setladrf(sc); 171291398Stmm else 171391398Stmm gem_init(sc); 171491398Stmm } else { 171591398Stmm if (ifp->if_flags & IFF_RUNNING) 171691398Stmm gem_stop(ifp, 0); 171791398Stmm } 171899726Sbenno sc->sc_ifflags = ifp->if_flags; 171991398Stmm error = 0; 172091398Stmm break; 172191398Stmm case SIOCADDMULTI: 172291398Stmm case SIOCDELMULTI: 172391398Stmm gem_setladrf(sc); 172491398Stmm error = 0; 172591398Stmm break; 172691398Stmm case SIOCGIFMEDIA: 172791398Stmm case SIOCSIFMEDIA: 172891398Stmm error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 172991398Stmm break; 173091398Stmm default: 1731108832Stmm error = ENOTTY; 173291398Stmm break; 173391398Stmm } 173491398Stmm 173591398Stmm /* Try to get things going again */ 173691398Stmm if (ifp->if_flags & IFF_UP) 173791398Stmm gem_start(ifp); 173891398Stmm splx(s); 173991398Stmm return (error); 174091398Stmm} 174191398Stmm 174291398Stmm/* 174391398Stmm * Set up the logical address filter. 174491398Stmm */ 174591398Stmmstatic void 174691398Stmmgem_setladrf(sc) 174791398Stmm struct gem_softc *sc; 174891398Stmm{ 174991398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 175091398Stmm struct ifmultiaddr *inm; 175191398Stmm struct sockaddr_dl *sdl; 175291398Stmm bus_space_tag_t t = sc->sc_bustag; 175391398Stmm bus_space_handle_t h = sc->sc_h; 175491398Stmm u_char *cp; 175591398Stmm u_int32_t crc; 175691398Stmm u_int32_t hash[16]; 175791398Stmm u_int32_t v; 175891398Stmm int len; 175999726Sbenno int i; 176091398Stmm 176191398Stmm /* Get current RX configuration */ 176291398Stmm v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 176391398Stmm 176499726Sbenno /* 176599726Sbenno * Turn off promiscuous mode, promiscuous group mode (all multicast), 176699726Sbenno * and hash filter. Depending on the case, the right bit will be 176799726Sbenno * enabled. 176899726Sbenno */ 176999726Sbenno v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 177099726Sbenno GEM_MAC_RX_PROMISC_GRP); 177199726Sbenno 177291398Stmm if ((ifp->if_flags & IFF_PROMISC) != 0) { 177399726Sbenno /* Turn on promiscuous mode */ 177491398Stmm v |= GEM_MAC_RX_PROMISCUOUS; 177591398Stmm goto chipit; 177691398Stmm } 177791398Stmm if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 177891398Stmm hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 177991398Stmm ifp->if_flags |= IFF_ALLMULTI; 178099726Sbenno v |= GEM_MAC_RX_PROMISC_GRP; 178191398Stmm goto chipit; 178291398Stmm } 178391398Stmm 178491398Stmm /* 178591398Stmm * Set up multicast address filter by passing all multicast addresses 178699726Sbenno * through a crc generator, and then using the high order 8 bits as an 178799726Sbenno * index into the 256 bit logical address filter. The high order 4 178899726Sbenno * bits selects the word, while the other 4 bits select the bit within 178999726Sbenno * the word (where bit 0 is the MSB). 179091398Stmm */ 179191398Stmm 179299726Sbenno /* Clear hash table */ 179399726Sbenno memset(hash, 0, sizeof(hash)); 179499726Sbenno 179591398Stmm TAILQ_FOREACH(inm, &sc->sc_arpcom.ac_if.if_multiaddrs, ifma_link) { 179691398Stmm if (inm->ifma_addr->sa_family != AF_LINK) 179791398Stmm continue; 179891398Stmm sdl = (struct sockaddr_dl *)inm->ifma_addr; 179991398Stmm cp = LLADDR(sdl); 180091398Stmm crc = 0xffffffff; 180191398Stmm for (len = sdl->sdl_alen; --len >= 0;) { 180291398Stmm int octet = *cp++; 180391398Stmm int i; 180491398Stmm 180591398Stmm#define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 180691398Stmm for (i = 0; i < 8; i++) { 180791398Stmm if ((crc & 1) ^ (octet & 1)) { 180891398Stmm crc >>= 1; 180991398Stmm crc ^= MC_POLY_LE; 181091398Stmm } else { 181191398Stmm crc >>= 1; 181291398Stmm } 181391398Stmm octet >>= 1; 181491398Stmm } 181591398Stmm } 181691398Stmm /* Just want the 8 most significant bits. */ 181791398Stmm crc >>= 24; 181891398Stmm 181991398Stmm /* Set the corresponding bit in the filter. */ 182099726Sbenno hash[crc >> 4] |= 1 << (15 - (crc & 15)); 182191398Stmm } 182291398Stmm 182399726Sbenno v |= GEM_MAC_RX_HASH_FILTER; 182499726Sbenno ifp->if_flags &= ~IFF_ALLMULTI; 182599726Sbenno 182699726Sbenno /* Now load the hash table into the chip (if we are using it) */ 182799726Sbenno for (i = 0; i < 16; i++) { 182899726Sbenno bus_space_write_4(t, h, 182999726Sbenno GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 183099726Sbenno hash[i]); 183199726Sbenno } 183299726Sbenno 183391398Stmmchipit: 183491398Stmm bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 183591398Stmm} 183691398Stmm 183791398Stmm#if notyet 183891398Stmm 183991398Stmm/* 184091398Stmm * gem_power: 184191398Stmm * 184291398Stmm * Power management (suspend/resume) hook. 184391398Stmm */ 184491398Stmmvoid 184591398Stmmstatic gem_power(why, arg) 184691398Stmm int why; 184791398Stmm void *arg; 184891398Stmm{ 184991398Stmm struct gem_softc *sc = arg; 185091398Stmm struct ifnet *ifp = &sc->sc_arpcom.ac_if; 185191398Stmm int s; 185291398Stmm 185391398Stmm s = splnet(); 185491398Stmm switch (why) { 185591398Stmm case PWR_SUSPEND: 185691398Stmm case PWR_STANDBY: 185791398Stmm gem_stop(ifp, 1); 185891398Stmm if (sc->sc_power != NULL) 185991398Stmm (*sc->sc_power)(sc, why); 186091398Stmm break; 186191398Stmm case PWR_RESUME: 186291398Stmm if (ifp->if_flags & IFF_UP) { 186391398Stmm if (sc->sc_power != NULL) 186491398Stmm (*sc->sc_power)(sc, why); 186591398Stmm gem_init(ifp); 186691398Stmm } 186791398Stmm break; 186891398Stmm case PWR_SOFTSUSPEND: 186991398Stmm case PWR_SOFTSTANDBY: 187091398Stmm case PWR_SOFTRESUME: 187191398Stmm break; 187291398Stmm } 187391398Stmm splx(s); 187491398Stmm} 187591398Stmm#endif 1876