ncr53c9x.c revision 130424
1/*- 2 * Copyright (c) 2004 Scott Long 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28/* $NetBSD: ncr53c9x.c,v 1.106 2003/04/16 18:53:50 petrov Exp $ */ 29 30/*- 31 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Charles M. Hannum. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the NetBSD 48 * Foundation, Inc. and its contributors. 49 * 4. Neither the name of The NetBSD Foundation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 63 * POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66/* 67 * Copyright (c) 1994 Peter Galbavy 68 * Copyright (c) 1995 Paul Kranenburg 69 * All rights reserved. 70 * 71 * Redistribution and use in source and binary forms, with or without 72 * modification, are permitted provided that the following conditions 73 * are met: 74 * 1. Redistributions of source code must retain the above copyright 75 * notice, this list of conditions and the following disclaimer. 76 * 2. Redistributions in binary form must reproduce the above copyright 77 * notice, this list of conditions and the following disclaimer in the 78 * documentation and/or other materials provided with the distribution. 79 * 3. All advertising materials mentioning features or use of this software 80 * must display the following acknowledgement: 81 * This product includes software developed by Peter Galbavy 82 * 4. The name of the author may not be used to endorse or promote products 83 * derived from this software without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 86 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 87 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 88 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 93 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 94 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 95 * POSSIBILITY OF SUCH DAMAGE. 96 */ 97 98/* 99 * Based on aic6360 by Jarle Greipsland 100 * 101 * Acknowledgements: Many of the algorithms used in this driver are 102 * inspired by the work of Julian Elischer (julian@tfs.com) and 103 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 104 */ 105 106#include <sys/cdefs.h> 107__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 130424 2004-06-13 18:45:57Z scottl $"); 108 109#include <sys/param.h> 110#include <sys/systm.h> 111#include <sys/bus.h> 112#include <sys/kernel.h> 113#include <sys/malloc.h> 114#include <sys/resource.h> 115#include <sys/lock.h> 116#include <sys/mutex.h> 117#include <sys/queue.h> 118#include <sys/time.h> 119#include <sys/callout.h> 120 121#include <cam/cam.h> 122#include <cam/cam_ccb.h> 123#include <cam/cam_debug.h> 124#include <cam/cam_sim.h> 125#include <cam/cam_xpt_sim.h> 126#include <cam/scsi/scsi_all.h> 127#include <cam/scsi/scsi_message.h> 128 129#include <dev/esp/ncr53c9xreg.h> 130#include <dev/esp/ncr53c9xvar.h> 131 132int ncr53c9x_debug = NCR_SHOWMISC /*|NCR_SHOWPHASE|NCR_SHOWTRAC|NCR_SHOWCMDS*/; 133#ifdef DEBUG 134int ncr53c9x_notag = 0; 135#endif 136 137static void ncr53c9x_select(struct ncr53c9x_softc *, struct ncr53c9x_ecb *); 138static int ncr53c9x_reselect(struct ncr53c9x_softc *, int, int, int); 139static void ncr53c9x_scsi_reset(struct ncr53c9x_softc *); 140static void ncr53c9x_poll(struct cam_sim *); 141static void ncr53c9x_sched(struct ncr53c9x_softc *); 142static void ncr53c9x_done(struct ncr53c9x_softc *, struct ncr53c9x_ecb *); 143static void ncr53c9x_msgin(struct ncr53c9x_softc *); 144static void ncr53c9x_msgout(struct ncr53c9x_softc *); 145static void ncr53c9x_timeout(void *arg); 146static void ncr53c9x_watch(void *arg); 147static void ncr53c9x_abort(struct ncr53c9x_softc *, struct ncr53c9x_ecb *); 148static void ncr53c9x_dequeue(struct ncr53c9x_softc *, 149 struct ncr53c9x_ecb *); 150static void ncr53c9x_sense(struct ncr53c9x_softc *, struct ncr53c9x_ecb *); 151static void ncr53c9x_free_ecb(struct ncr53c9x_softc *, 152 struct ncr53c9x_ecb *); 153static void ncr53c9x_wrfifo(struct ncr53c9x_softc *, u_char *, int); 154static int ncr53c9x_rdfifo(struct ncr53c9x_softc *, int); 155 156static struct ncr53c9x_ecb *ncr53c9x_get_ecb(struct ncr53c9x_softc *); 157static struct ncr53c9x_linfo *ncr53c9x_lunsearch(struct ncr53c9x_tinfo *, 158 int64_t lun); 159 160static __inline void ncr53c9x_readregs(struct ncr53c9x_softc *); 161static __inline int ncr53c9x_stp2cpb(struct ncr53c9x_softc *, int); 162static __inline void ncr53c9x_setsync(struct ncr53c9x_softc *, 163 struct ncr53c9x_tinfo *); 164 165#define NCR_RDFIFO_START 0 166#define NCR_RDFIFO_CONTINUE 1 167 168#define NCR_SET_COUNT(sc, size) do { \ 169 NCR_WRITE_REG((sc), NCR_TCL, (size)); \ 170 NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \ 171 if ((sc->sc_cfg2 & NCRCFG2_FE) || \ 172 (sc->sc_rev == NCR_VARIANT_FAS366)) { \ 173 NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \ 174 } \ 175 if (sc->sc_rev == NCR_VARIANT_FAS366) { \ 176 NCR_WRITE_REG(sc, NCR_RCH, 0); \ 177 } \ 178} while (0) 179 180#ifndef mstohz 181#define mstohz(ms) \ 182 (((ms) < 0x20000) ? \ 183 ((ms +0u) / 1000u) * hz : \ 184 ((ms +0u) * hz) /1000u) 185#endif 186 187/* 188 * Names for the NCR53c9x variants, correspnding to the variant tags 189 * in ncr53c9xvar.h. 190 */ 191static const char *ncr53c9x_variant_names[] = { 192 "ESP100", 193 "ESP100A", 194 "ESP200", 195 "NCR53C94", 196 "NCR53C96", 197 "ESP406", 198 "FAS408", 199 "FAS216", 200 "AM53C974", 201 "FAS366/HME", 202 "NCR53C90 (86C01)", 203}; 204 205/* 206 * Search linked list for LUN info by LUN id. 207 */ 208static struct ncr53c9x_linfo * 209ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun) 210{ 211 struct ncr53c9x_linfo *li; 212 LIST_FOREACH(li, &ti->luns, link) 213 if (li->lun == lun) 214 return (li); 215 return (NULL); 216} 217 218/* 219 * Attach this instance, and then all the sub-devices 220 */ 221int 222ncr53c9x_attach(struct ncr53c9x_softc *sc) 223{ 224 struct cam_devq *devq; 225 struct cam_sim *sim; 226 struct cam_path *path; 227 struct ncr53c9x_ecb *ecb; 228 int i; 229 230 mtx_init(&sc->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF); 231 232 /* 233 * Note, the front-end has set us up to print the chip variation. 234 */ 235 if (sc->sc_rev >= NCR_VARIANT_MAX) { 236 device_printf(sc->sc_dev, "unknown variant %d, devices not " 237 "attached\n", sc->sc_rev); 238 return (EINVAL); 239 } 240 241 device_printf(sc->sc_dev, "%s, %dMHz, SCSI ID %d\n", 242 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 243 244 sc->sc_ntarg = (sc->sc_rev == NCR_VARIANT_FAS366) ? 16 : 8; 245 246 /* 247 * Allocate SCSI message buffers. 248 * Front-ends can override allocation to avoid alignment 249 * handling in the DMA engines. Note that that ncr53c9x_msgout() 250 * can request a 1 byte DMA transfer. 251 */ 252 if (sc->sc_omess == NULL) 253 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 254 255 if (sc->sc_imess == NULL) 256 sc->sc_imess = malloc(NCR_MAX_MSG_LEN + 1, M_DEVBUF, M_NOWAIT); 257 258 sc->sc_tinfo = malloc(sc->sc_ntarg * sizeof(sc->sc_tinfo[0]), 259 M_DEVBUF, M_NOWAIT | M_ZERO); 260 261 if (!sc->sc_omess || !sc->sc_imess || !sc->sc_tinfo) { 262 printf("out of memory\n"); 263 return (ENOMEM); 264 } 265 266 callout_init(&sc->sc_watchdog, 0); 267 268 /* 269 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100 270 * from now on. 271 */ 272 if (sc->sc_rev == NCR_VARIANT_NCR53C90_86C01) 273 sc->sc_rev = NCR_VARIANT_ESP100; 274 275 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 276 277 /* The value *must not* be == 1. Make it 2 */ 278 if (sc->sc_ccf == 1) 279 sc->sc_ccf = 2; 280 281 /* 282 * The recommended timeout is 250ms. This register is loaded 283 * with a value calculated as follows, from the docs: 284 * 285 * (timout period) x (CLK frequency) 286 * reg = ------------------------------------- 287 * 8192 x (Clock Conversion Factor) 288 * 289 * Since CCF has a linear relation to CLK, this generally computes 290 * to the constant of 153. 291 */ 292 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 293 294 /* CCF register only has 3 bits; 0 is actually 8 */ 295 sc->sc_ccf &= 7; 296 297 /* 298 * Register with CAM 299 */ 300 devq = cam_simq_alloc(sc->sc_ntarg); 301 if (devq == NULL) 302 return (ENOMEM); 303 304 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc, 305 device_get_unit(sc->sc_dev), 1, 306 NCR_TAG_DEPTH, devq); 307 if (sim == NULL) { 308 cam_simq_free(devq); 309 return (ENOMEM); 310 } 311 if (xpt_bus_register(sim, 0) != CAM_SUCCESS) { 312 cam_sim_free(sim, TRUE); 313 return (EIO); 314 } 315 316 if (xpt_create_path(&path, NULL, cam_sim_path(sim), 317 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) 318 != CAM_REQ_CMP) { 319 xpt_bus_deregister(cam_sim_path(sim)); 320 cam_sim_free(sim, TRUE); 321 return (EIO); 322 } 323 324 sc->sc_sim = sim; 325 sc->sc_path = path; 326 327 /* Reset state & bus */ 328#if 0 329 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 330#endif 331 sc->sc_state = 0; 332 ncr53c9x_init(sc, 1); 333 334 TAILQ_INIT(&sc->free_list); 335 if ((sc->ecb_array = malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH, 336 M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) { 337 device_printf(sc->sc_dev, "Cannot allocate ecb array!\n"); 338 return (ENOMEM); 339 } 340 for (i = 0; i < NCR_TAG_DEPTH; i++) { 341 ecb = &sc->ecb_array[i]; 342 ecb->sc = sc; 343 ecb->tag_id = i; 344 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links); 345 } 346 347 callout_reset(&sc->sc_watchdog, 60*hz, ncr53c9x_watch, sc); 348 349 return (0); 350} 351 352int 353ncr53c9x_detach(struct ncr53c9x_softc *sc, int flags) 354{ 355 356#if 0 /* don't allow detach for now */ 357 free(sc->sc_imess, M_DEVBUF); 358 free(sc->sc_omess, M_DEVBUF); 359#endif 360 361 return (EINVAL); 362} 363 364/* 365 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus, 366 * only this controller, but kills any on-going commands, and also stops 367 * and resets the DMA. 368 * 369 * After reset, registers are loaded with the defaults from the attach 370 * routine above. 371 */ 372void 373ncr53c9x_reset(struct ncr53c9x_softc *sc) 374{ 375 376 /* reset DMA first */ 377 NCRDMA_RESET(sc); 378 379 /* reset SCSI chip */ 380 NCRCMD(sc, NCRCMD_RSTCHIP); 381 NCRCMD(sc, NCRCMD_NOP); 382 DELAY(500); 383 384 /* do these backwards, and fall through */ 385 switch (sc->sc_rev) { 386 case NCR_VARIANT_ESP406: 387 case NCR_VARIANT_FAS408: 388 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT); 389 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4); 390 case NCR_VARIANT_AM53C974: 391 case NCR_VARIANT_FAS216: 392 case NCR_VARIANT_NCR53C94: 393 case NCR_VARIANT_NCR53C96: 394 case NCR_VARIANT_ESP200: 395 sc->sc_features |= NCR_F_HASCFG3; 396 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 397 case NCR_VARIANT_ESP100A: 398 sc->sc_features |= NCR_F_SELATN3; 399 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 400 case NCR_VARIANT_ESP100: 401 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 402 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 403 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 404 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 405 break; 406 407 case NCR_VARIANT_FAS366: 408 sc->sc_features |= 409 NCR_F_HASCFG3 | NCR_F_FASTSCSI | NCR_F_SELATN3; 410 sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO; 411 sc->sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI; 412 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 413 sc->sc_cfg2 = 0; /* NCRCFG2_HMEFE| NCRCFG2_HME32 */ 414 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 415 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 416 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 417 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 418 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 419 break; 420 421 default: 422 device_printf(sc->sc_dev, "unknown revision code, " 423 "assuming ESP100\n"); 424 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 425 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 426 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 427 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 428 } 429 430 if (sc->sc_rev == NCR_VARIANT_AM53C974) 431 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4); 432 433#if 0 434 device_printf(sc->sc_dev, "ncr53c9x_reset: revision %d\n", 435 sc->sc_rev); 436 device_printf(sc->sc_dev, "ncr53c9x_reset: cfg1 0x%x, cfg2 0x%x, " 437 "cfg3 0x%x, ccf 0x%x, timeout 0x%x\n", 438 sc->sc_cfg1, sc->sc_cfg2, sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout); 439#endif 440} 441 442/* 443 * Reset the SCSI bus, but not the chip 444 */ 445static void 446ncr53c9x_scsi_reset(struct ncr53c9x_softc *sc) 447{ 448 449 (*sc->sc_glue->gl_dma_stop)(sc); 450 451 NCR_MISC(("%s: resetting SCSI bus\n", device_get_nameunit(sc->sc_dev))); 452 NCRCMD(sc, NCRCMD_RSTSCSI); 453 DELAY(250000); /* Give the bus a fighting chance to settle */ 454} 455 456/* 457 * Initialize ncr53c9x state machine 458 */ 459void 460ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset) 461{ 462 struct ncr53c9x_ecb *ecb; 463 struct ncr53c9x_linfo *li; 464 int i, r; 465 466 NCR_MISC(("[NCR_INIT(%d) %d] ", doreset, sc->sc_state)); 467 468 if (sc->sc_state == 0) { 469 /* First time through; initialize. */ 470 471 TAILQ_INIT(&sc->ready_list); 472 sc->sc_nexus = NULL; 473 memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 474 for (r = 0; r < sc->sc_ntarg; r++) { 475 LIST_INIT(&sc->sc_tinfo[r].luns); 476 } 477 } else { 478 /* Cancel any active commands. */ 479 sc->sc_state = NCR_CLEANING; 480 sc->sc_msgify = 0; 481 if ((ecb = sc->sc_nexus) != NULL) { 482 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT; 483 ncr53c9x_done(sc, ecb); 484 } 485 /* Cancel outstanding disconnected commands on each LUN */ 486 for (r = 0; r < sc->sc_ntarg; r++) { 487 LIST_FOREACH(li, &sc->sc_tinfo[r].luns, link) { 488 if ((ecb = li->untagged) != NULL) { 489 li->untagged = NULL; 490 /* 491 * XXXXXXX 492 * 493 * Should we terminate a command 494 * that never reached the disk? 495 */ 496 li->busy = 0; 497 ecb->ccb->ccb_h.status = 498 CAM_CMD_TIMEOUT; 499 ncr53c9x_done(sc, ecb); 500 } 501 for (i = 0; i < 256; i++) 502 if ((ecb = li->queued[i])) { 503 li->queued[i] = NULL; 504 ecb->ccb->ccb_h.status = 505 CAM_CMD_TIMEOUT; 506 ncr53c9x_done(sc, ecb); 507 } 508 li->used = 0; 509 } 510 } 511 } 512 513 /* 514 * reset the chip to a known state 515 */ 516 ncr53c9x_reset(sc); 517 518 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 519 for (r = 0; r < sc->sc_ntarg; r++) { 520 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r]; 521/* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 522 523 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<((r&7)+8)))) 524 ? 0 : T_SYNCHOFF) | 525 ((sc->sc_cfflags & (1<<(r&7))) ? T_RSELECTOFF : 0); 526#ifdef DEBUG 527 if (ncr53c9x_notag) 528 ti->flags &= ~T_TAG; 529#endif 530 ti->period = sc->sc_minsync; 531 ti->offset = 0; 532 ti->cfg3 = 0; 533 } 534 535 if (doreset) { 536 sc->sc_state = NCR_SBR; 537 NCRCMD(sc, NCRCMD_RSTSCSI); 538 } else { 539 sc->sc_state = NCR_IDLE; 540 ncr53c9x_sched(sc); 541 } 542} 543 544/* 545 * Read the NCR registers, and save their contents for later use. 546 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 547 * NCR_INTR - so make sure it is the last read. 548 * 549 * I think that (from reading the docs) most bits in these registers 550 * only make sense when he DMA CSR has an interrupt showing. Call only 551 * if an interrupt is pending. 552 */ 553static __inline void 554ncr53c9x_readregs(struct ncr53c9x_softc *sc) 555{ 556 557 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 558 /* Only the stepo bits are of interest */ 559 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 560 561 if (sc->sc_rev == NCR_VARIANT_FAS366) 562 sc->sc_espstat2 = NCR_READ_REG(sc, NCR_STAT2); 563 564 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 565 566 if (sc->sc_glue->gl_clear_latched_intr != NULL) 567 (*sc->sc_glue->gl_clear_latched_intr)(sc); 568 569 /* 570 * Determine the SCSI bus phase, return either a real SCSI bus phase 571 * or some pseudo phase we use to detect certain exceptions. 572 */ 573 574 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) ? 575 /* Disconnected */ BUSFREE_PHASE : sc->sc_espstat & NCRSTAT_PHASE; 576 577 NCR_INTS(("regs[intr=%02x,stat=%02x,step=%02x,stat2=%02x] ", 578 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep, sc->sc_espstat2)); 579} 580 581/* 582 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 583 */ 584static __inline int 585ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, int period) 586{ 587 int v; 588 v = (sc->sc_freq * period) / 250; 589 if (ncr53c9x_cpb2stp(sc, v) < period) 590 /* Correct round-down error */ 591 v++; 592 return (v); 593} 594 595static __inline void 596ncr53c9x_setsync(struct ncr53c9x_softc *sc, struct ncr53c9x_tinfo *ti) 597{ 598 u_char syncoff, synctp; 599 u_char cfg3 = sc->sc_cfg3 | ti->cfg3; 600 601 if (ti->flags & T_SYNCMODE) { 602 syncoff = ti->offset; 603 synctp = ncr53c9x_stp2cpb(sc, ti->period); 604 if (sc->sc_features & NCR_F_FASTSCSI) { 605 /* 606 * If the period is 200ns or less (ti->period <= 50), 607 * put the chip in Fast SCSI mode. 608 */ 609 if (ti->period <= 50) 610 /* 611 * There are (at least) 4 variations of the 612 * configuration 3 register. The drive attach 613 * routine sets the appropriate bit to put the 614 * chip into Fast SCSI mode so that it doesn't 615 * have to be figured out here each time. 616 */ 617 cfg3 |= sc->sc_cfg3_fscsi; 618 } 619 620 /* 621 * Am53c974 requires different SYNCTP values when the 622 * FSCSI bit is off. 623 */ 624 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 625 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 626 synctp--; 627 } else { 628 syncoff = 0; 629 synctp = 0; 630 } 631 632 if (sc->sc_features & NCR_F_HASCFG3) 633 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 634 635 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 636 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 637} 638 639/* 640 * Send a command to a target, set the driver state to NCR_SELECTING 641 * and let the caller take care of the rest. 642 * 643 * Keeping this as a function allows me to say that this may be done 644 * by DMA instead of programmed I/O soon. 645 */ 646static void 647ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 648{ 649 int target = ecb->ccb->ccb_h.target_id; 650 int lun = ecb->ccb->ccb_h.target_lun; 651 struct ncr53c9x_tinfo *ti; 652 int tiflags; 653 u_char *cmd; 654 int clen; 655 int selatn3, selatns; 656 size_t dmasize; 657 658 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x,tag:%x,%x)] ", 659 target, lun, ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1])); 660 661 ti = &sc->sc_tinfo[target]; 662 tiflags = ti->flags; 663 sc->sc_state = NCR_SELECTING; 664 /* 665 * Schedule the timeout now, the first time we will go away 666 * expecting to come back due to an interrupt, because it is 667 * always possible that the interrupt may never happen. 668 */ 669 ecb->ccb->ccb_h.timeout_ch = 670 timeout(ncr53c9x_timeout, ecb, mstohz(ecb->timeout)); 671 672 /* 673 * The docs say the target register is never reset, and I 674 * can't think of a better place to set it 675 */ 676 if (sc->sc_rev == NCR_VARIANT_FAS366) { 677 NCRCMD(sc, NCRCMD_FLUSH); 678 NCR_WRITE_REG(sc, NCR_SELID, target | NCR_BUSID_HME); 679 } else { 680 NCR_WRITE_REG(sc, NCR_SELID, target); 681 } 682 ncr53c9x_setsync(sc, ti); 683 684 if ((ecb->flags & ECB_SENSE) != 0) { 685 /* 686 * For REQUEST SENSE, we should not send an IDENTIFY or 687 * otherwise mangle the target. There should be no MESSAGE IN 688 * phase. 689 */ 690 if (sc->sc_features & NCR_F_DMASELECT) { 691 /* setup DMA transfer for command */ 692 dmasize = clen = ecb->clen; 693 sc->sc_cmdlen = clen; 694 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 695 696 /* Program the SCSI counter */ 697 NCR_SET_COUNT(sc, dmasize); 698 699 if (sc->sc_rev != NCR_VARIANT_FAS366) 700 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 701 702 /* And get the targets attention */ 703 NCRCMD(sc, NCRCMD_SELNATN | NCRCMD_DMA); 704 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, 705 &dmasize); 706 NCRDMA_GO(sc); 707 } else { 708 ncr53c9x_wrfifo(sc, (u_char *)&ecb->cmd.cmd, ecb->clen); 709 NCRCMD(sc, NCRCMD_SELNATN); 710 } 711 return; 712 } 713 714 selatn3 = selatns = 0; 715 if (ecb->tag[0] != 0) { 716 if (sc->sc_features & NCR_F_SELATN3) 717 /* use SELATN3 to send tag messages */ 718 selatn3 = 1; 719 else 720 /* We don't have SELATN3; use SELATNS to send tags */ 721 selatns = 1; 722 } 723 724 if (ti->flags & T_NEGOTIATE) { 725 /* We have to use SELATNS to send sync/wide messages */ 726 selatn3 = 0; 727 selatns = 1; 728 } 729 730 cmd = (u_char *)&ecb->cmd.cmd; 731 732 if (selatn3) { 733 /* We'll use tags with SELATN3 */ 734 clen = ecb->clen + 3; 735 cmd -= 3; 736 cmd[0] = MSG_IDENTIFY(lun, 1); /* msg[0] */ 737 cmd[1] = ecb->tag[0]; /* msg[1] */ 738 cmd[2] = ecb->tag[1]; /* msg[2] */ 739 } else { 740 /* We don't have tags, or will send messages with SELATNS */ 741 clen = ecb->clen + 1; 742 cmd -= 1; 743 cmd[0] = MSG_IDENTIFY(lun, (tiflags & T_RSELECTOFF) == 0); 744 } 745 746 if ((sc->sc_features & NCR_F_DMASELECT) && !selatns) { 747 748 /* setup DMA transfer for command */ 749 dmasize = clen; 750 sc->sc_cmdlen = clen; 751 sc->sc_cmdp = cmd; 752 753 /* Program the SCSI counter */ 754 NCR_SET_COUNT(sc, dmasize); 755 756 /* load the count in */ 757 /* if (sc->sc_rev != NCR_VARIANT_FAS366) */ 758 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 759 760 /* And get the targets attention */ 761 if (selatn3) { 762 sc->sc_msgout = SEND_TAG; 763 sc->sc_flags |= NCR_ATN; 764 NCRCMD(sc, NCRCMD_SELATN3 | NCRCMD_DMA); 765 } else 766 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); 767 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); 768 NCRDMA_GO(sc); 769 return; 770 } 771 772 /* 773 * Who am I. This is where we tell the target that we are 774 * happy for it to disconnect etc. 775 */ 776 777 /* Now get the command into the FIFO */ 778 ncr53c9x_wrfifo(sc, cmd, clen); 779 780 /* And get the targets attention */ 781 if (selatns) { 782 NCR_MSGS(("SELATNS \n")); 783 /* Arbitrate, select and stop after IDENTIFY message */ 784 NCRCMD(sc, NCRCMD_SELATNS); 785 } else if (selatn3) { 786 sc->sc_msgout = SEND_TAG; 787 sc->sc_flags |= NCR_ATN; 788 NCRCMD(sc, NCRCMD_SELATN3); 789 } else 790 NCRCMD(sc, NCRCMD_SELATN); 791} 792 793static void 794ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 795{ 796 797 ecb->flags = 0; 798 TAILQ_INSERT_TAIL(&sc->free_list, ecb, free_links); 799 return; 800} 801 802static struct ncr53c9x_ecb * 803ncr53c9x_get_ecb(struct ncr53c9x_softc *sc) 804{ 805 struct ncr53c9x_ecb *ecb; 806 807 ecb = TAILQ_FIRST(&sc->free_list); 808 if (ecb) { 809 if (ecb->flags != 0) 810 panic("ecb flags not cleared\n"); 811 TAILQ_REMOVE(&sc->free_list, ecb, free_links); 812 ecb->flags = ECB_ALLOC; 813 bzero(&ecb->ccb, sizeof(struct ncr53c9x_ecb) - 814 offsetof(struct ncr53c9x_ecb, ccb)); 815 } 816 return (ecb); 817} 818 819/* 820 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 821 */ 822 823/* 824 * Start a SCSI-command 825 * This function is called by the higher level SCSI-driver to queue/run 826 * SCSI-commands. 827 */ 828 829void 830ncr53c9x_action(struct cam_sim *sim, union ccb *ccb) 831{ 832 struct ncr53c9x_softc *sc; 833 struct ncr53c9x_ecb *ecb; 834 835 NCR_TRACE(("[ncr53c9x_action %d]", ccb->ccb_h.func_code)); 836 837 sc = cam_sim_softc(sim); 838 mtx_lock(&sc->sc_lock); 839 840 switch (ccb->ccb_h.func_code) { 841 case XPT_RESET_BUS: 842 ncr53c9x_scsi_reset(sc); 843 ccb->ccb_h.status = CAM_REQ_CMP; 844 mtx_unlock(&sc->sc_lock); 845 xpt_done(ccb); 846 return; 847 case XPT_CALC_GEOMETRY: 848 mtx_unlock(&sc->sc_lock); 849 cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom); 850 xpt_done(ccb); 851 return; 852 case XPT_PATH_INQ: 853 { 854 struct ccb_pathinq *cpi = &ccb->cpi; 855 856 cpi->version_num = 1; 857 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 858 cpi->hba_inquiry |= 859 (sc->sc_rev == NCR_VARIANT_FAS366) ? PI_WIDE_16 : 0; 860 cpi->target_sprt = 0; 861 cpi->hba_misc = 0; 862 cpi->hba_eng_cnt = 0; 863 cpi->max_target = sc->sc_ntarg - 1; 864 cpi->max_lun = 8; 865 cpi->initiator_id = sc->sc_id; 866 cpi->bus_id = 0; 867 cpi->base_transfer_speed = 3300; 868 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 869 strncpy(cpi->hba_vid, "Sun", HBA_IDLEN); 870 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 871 cpi->unit_number = cam_sim_unit(sim); 872 ccb->ccb_h.status = CAM_REQ_CMP; 873 mtx_unlock(&sc->sc_lock); 874 xpt_done(ccb); 875 return; 876 } 877 case XPT_GET_TRAN_SETTINGS: 878 { 879 struct ccb_trans_settings *cts = &ccb->cts; 880 struct ncr53c9x_tinfo *ti; 881 882 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 883 884 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 885 cts->sync_period = ti->period; 886 cts->sync_offset = ti->offset; 887 cts->bus_width = ti->width; 888 if ((ti->flags & T_TAG) != 0) 889 cts->flags |= 890 (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 891 else 892 cts->flags &= 893 ~(CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 894 } else { 895 cts->sync_period = sc->sc_maxsync; 896 cts->sync_offset = sc->sc_maxoffset; 897 cts->bus_width = sc->sc_maxwidth; 898 cts->flags |= (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 899 } 900 cts->valid = CCB_TRANS_BUS_WIDTH_VALID | 901 CCB_TRANS_SYNC_RATE_VALID | 902 CCB_TRANS_SYNC_OFFSET_VALID | 903 CCB_TRANS_DISC_VALID | 904 CCB_TRANS_TQ_VALID; 905 ccb->ccb_h.status = CAM_REQ_CMP; 906 mtx_unlock(&sc->sc_lock); 907 xpt_done(ccb); 908 return; 909 } 910 case XPT_ABORT: 911 printf("XPT_ABORT called\n"); 912 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 913 mtx_unlock(&sc->sc_lock); 914 xpt_done(ccb); 915 return; 916 case XPT_TERM_IO: 917 printf("XPT_TERM_IO called\n"); 918 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 919 mtx_unlock(&sc->sc_lock); 920 xpt_done(ccb); 921 return; 922 case XPT_RESET_DEV: 923 printf("XPT_RESET_DEV called\n"); 924 case XPT_SCSI_IO: 925 { 926 struct ccb_scsiio *csio; 927 928 if (ccb->ccb_h.target_id < 0 || 929 ccb->ccb_h.target_id >= sc->sc_ntarg) { 930 ccb->ccb_h.status = CAM_PATH_INVALID; 931 mtx_unlock(&sc->sc_lock); 932 xpt_done(ccb); 933 return; 934 } 935 /* Get an ECB to use. */ 936 ecb = ncr53c9x_get_ecb(sc); 937 /* 938 * This should never happen as we track resources 939 * in the mid-layer. 940 */ 941 if (ecb == NULL) { 942 xpt_freeze_simq(sim, 1); 943 ccb->ccb_h.status = CAM_REQUEUE_REQ; 944 printf("unable to allocate ecb\n"); 945 mtx_unlock(&sc->sc_lock); 946 xpt_done(ccb); 947 return; 948 } 949 950 /* Initialize ecb */ 951 ecb->ccb = ccb; 952 ecb->timeout = ccb->ccb_h.timeout; 953 954 if (ccb->ccb_h.func_code == XPT_RESET_DEV) { 955 ecb->flags |= ECB_RESET; 956 ecb->clen = 0; 957 ecb->dleft = 0; 958 } else { 959 csio = &ccb->csio; 960 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 961 bcopy(csio->cdb_io.cdb_ptr, &ecb->cmd.cmd, 962 csio->cdb_len); 963 else 964 bcopy(csio->cdb_io.cdb_bytes, &ecb->cmd.cmd, 965 csio->cdb_len); 966 ecb->clen = csio->cdb_len; 967 ecb->daddr = csio->data_ptr; 968 ecb->dleft = csio->dxfer_len; 969 } 970 ecb->stat = 0; 971 972 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 973 ecb->flags |= ECB_READY; 974 if (sc->sc_state == NCR_IDLE) 975 ncr53c9x_sched(sc); 976 977 break; 978 } 979 980 case XPT_SET_TRAN_SETTINGS: 981 { 982 struct ncr53c9x_tinfo *ti; 983 struct ccb_trans_settings *cts = &ccb->cts; 984 int target = ccb->ccb_h.target_id; 985 986 ti = &sc->sc_tinfo[target]; 987 988 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 989 if ((sc->sc_cfflags & (1<<((target & 7) + 16))) == 0 && 990 (cts->flags & CCB_TRANS_TAG_ENB)) { 991 NCR_MISC(("%s: target %d: tagged queuing\n", 992 device_get_nameunit(sc->sc_dev), target)); 993 ti->flags |= T_TAG; 994 } else 995 ti->flags &= ~T_TAG; 996 } 997 998 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { 999 if (cts->bus_width != 0) { 1000 NCR_MISC(("%s: target %d: wide negotiation\n", 1001 device_get_nameunit(sc->sc_dev), target)); 1002 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1003 ti->flags |= T_WIDE; 1004 ti->width = 1; 1005 } 1006 } else { 1007 ti->flags &= ~T_WIDE; 1008 ti->width = 0; 1009 } 1010 ti->flags |= T_NEGOTIATE; 1011 } 1012 1013 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 1014 NCR_MISC(("%s: target %d: sync period negotiation\n", 1015 device_get_nameunit(sc->sc_dev), target)); 1016 ti->flags |= T_NEGOTIATE; 1017 ti->period = cts->sync_period; 1018 } 1019 1020 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) { 1021 NCR_MISC(("%s: target %d: sync offset negotiation\n", 1022 device_get_nameunit(sc->sc_dev), target)); 1023 ti->flags |= T_NEGOTIATE; 1024 ti->offset = cts->sync_offset; 1025 } 1026 1027 mtx_unlock(&sc->sc_lock); 1028 ccb->ccb_h.status = CAM_REQ_CMP; 1029 xpt_done(ccb); 1030 return; 1031 } 1032 1033 default: 1034 device_printf(sc->sc_dev, "Unhandled function code %d\n", 1035 ccb->ccb_h.func_code); 1036 ccb->ccb_h.status = CAM_PROVIDE_FAIL; 1037 mtx_unlock(&sc->sc_lock); 1038 xpt_done(ccb); 1039 return; 1040 } 1041 1042 mtx_unlock(&sc->sc_lock); 1043} 1044 1045/* 1046 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 1047 */ 1048static void 1049ncr53c9x_poll(struct cam_sim *sim) 1050{ 1051 struct ncr53c9x_softc *sc; 1052 1053 NCR_TRACE(("[ncr53c9x_poll] ")); 1054 sc = cam_sim_softc(sim); 1055 if (NCRDMA_ISINTR(sc)) { 1056 ncr53c9x_intr(sc); 1057 } 1058} 1059 1060/* 1061 * LOW LEVEL SCSI UTILITIES 1062 */ 1063 1064/* 1065 * Schedule a scsi operation. This has now been pulled out of the interrupt 1066 * handler so that we may call it from ncr53c9x_scsipi_request and 1067 * ncr53c9x_done. This may save us an unecessary interrupt just to get 1068 * things going. Should only be called when state == NCR_IDLE and at bio pl. 1069 */ 1070static void 1071ncr53c9x_sched(struct ncr53c9x_softc *sc) 1072{ 1073 struct ncr53c9x_ecb *ecb; 1074 struct ncr53c9x_tinfo *ti; 1075 struct ncr53c9x_linfo *li; 1076 int lun; 1077 int tag; 1078 1079 NCR_TRACE(("[ncr53c9x_sched] ")); 1080 if (sc->sc_state != NCR_IDLE) 1081 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 1082 1083 /* 1084 * Find first ecb in ready queue that is for a target/lunit 1085 * combinations that is not busy. 1086 */ 1087 for (ecb = TAILQ_FIRST(&sc->ready_list); ecb != NULL; 1088 ecb = TAILQ_NEXT(ecb, chain)) { 1089 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1090 lun = ecb->ccb->ccb_h.target_lun; 1091 1092 /* Select type of tag for this command */ 1093 if ((ti->flags & (T_RSELECTOFF)) != 0) 1094 tag = 0; 1095 else if ((ti->flags & (T_TAG)) == 0) 1096 tag = 0; 1097 else if ((ecb->flags & ECB_SENSE) != 0) 1098 tag = 0; 1099 else if ((ecb->ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0) 1100 tag = 0; 1101 else if (ecb->ccb->csio.tag_action == CAM_TAG_ACTION_NONE) 1102 tag = 0; 1103 else 1104 tag = ecb->ccb->csio.tag_action; 1105 1106 li = TINFO_LUN(ti, lun); 1107 if (li == NULL) { 1108 /* Initialize LUN info and add to list. */ 1109 if ((li = malloc(sizeof(*li), 1110 M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) { 1111 continue; 1112 } 1113 li->lun = lun; 1114 1115 LIST_INSERT_HEAD(&ti->luns, li, link); 1116 if (lun < NCR_NLUN) 1117 ti->lun[lun] = li; 1118 } 1119 li->last_used = time_second; 1120 if (tag == 0) { 1121 /* Try to issue this as an un-tagged command */ 1122 if (li->untagged == NULL) 1123 li->untagged = ecb; 1124 } 1125 if (li->untagged != NULL) { 1126 tag = 0; 1127 if ((li->busy != 1) && li->used == 0) { 1128 /* We need to issue this untagged command now */ 1129 ecb = li->untagged; 1130 } else { 1131 /* Not ready yet */ 1132 continue; 1133 } 1134 } 1135 ecb->tag[0] = tag; 1136 if (tag != 0) { 1137 li->queued[ecb->tag_id] = ecb; 1138 ecb->tag[1] = ecb->tag_id; 1139 li->used++; 1140 } 1141 if (li->untagged != NULL && (li->busy != 1)) { 1142 li->busy = 1; 1143 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1144 ecb->flags &= ~ECB_READY; 1145 sc->sc_nexus = ecb; 1146 ncr53c9x_select(sc, ecb); 1147 break; 1148 } 1149 if (li->untagged == NULL && tag != 0) { 1150 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1151 ecb->flags &= ~ECB_READY; 1152 sc->sc_nexus = ecb; 1153 ncr53c9x_select(sc, ecb); 1154 break; 1155 } else 1156 NCR_TRACE(("%d:%d busy\n", 1157 ecb->ccb->ccb_h.target_id, 1158 ecb->ccb->ccb_h.target_lun)); 1159 } 1160} 1161 1162static void 1163ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1164{ 1165 union ccb *ccb = ecb->ccb; 1166 struct ncr53c9x_tinfo *ti; 1167 struct scsi_request_sense *ss = (void *)&ecb->cmd.cmd; 1168 struct ncr53c9x_linfo *li; 1169 int lun; 1170 1171 NCR_TRACE(("requesting sense ")); 1172 1173 lun = ccb->ccb_h.target_lun; 1174 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1175 1176 /* Next, setup a request sense command block */ 1177 memset(ss, 0, sizeof(*ss)); 1178 ss->opcode = REQUEST_SENSE; 1179 ss->byte2 = ccb->ccb_h.target_lun << SCSI_CMD_LUN_SHIFT; 1180 ss->length = sizeof(struct scsi_sense_data); 1181 ecb->clen = sizeof(*ss); 1182 ecb->daddr = (char *)&ecb->ccb->csio.sense_data; 1183 ecb->dleft = sizeof(struct scsi_sense_data); 1184 ecb->flags |= ECB_SENSE; 1185 ecb->timeout = NCR_SENSE_TIMEOUT; 1186 ti->senses++; 1187 li = TINFO_LUN(ti, lun); 1188 if (li->busy) 1189 li->busy = 0; 1190 ncr53c9x_dequeue(sc, ecb); 1191 li->untagged = ecb; /* must be executed first to fix C/A */ 1192 li->busy = 2; 1193 if (ecb == sc->sc_nexus) { 1194 ncr53c9x_select(sc, ecb); 1195 } else { 1196 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1197 ecb->flags |= ECB_READY; 1198 if (sc->sc_state == NCR_IDLE) 1199 ncr53c9x_sched(sc); 1200 } 1201} 1202 1203/* 1204 * POST PROCESSING OF SCSI_CMD (usually current) 1205 */ 1206static void 1207ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1208{ 1209 union ccb *ccb = ecb->ccb; 1210 struct ncr53c9x_tinfo *ti; 1211 struct ncr53c9x_linfo *li; 1212 int lun; 1213 1214 NCR_TRACE(("[ncr53c9x_done(status:%x)] ", ccb->ccb_h.status)); 1215 1216 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1217 lun = ccb->ccb_h.target_lun; 1218 li = TINFO_LUN(ti, lun); 1219 1220 untimeout(ncr53c9x_timeout, ecb, ccb->ccb_h.timeout_ch); 1221 1222 /* 1223 * Now, if we've come here with no error code, i.e. we've kept the 1224 * initial XS_NOERROR, and the status code signals that we should 1225 * check sense, we'll need to set up a request sense cmd block and 1226 * push the command back into the ready queue *before* any other 1227 * commands for this target/lunit, else we lose the sense info. 1228 * We don't support chk sense conditions for the request sense cmd. 1229 */ 1230 if (ccb->ccb_h.status == CAM_REQ_CMP) { 1231 if ((ecb->flags & ECB_ABORT) != 0) { 1232 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1233 } else if ((ecb->flags & ECB_SENSE) != 0 && 1234 (ecb->stat != SCSI_STATUS_CHECK_COND)) { 1235 ccb->ccb_h.status = CAM_AUTOSNS_VALID; 1236 } else if (ecb->stat == SCSI_STATUS_CHECK_COND) { 1237 if ((ecb->flags & ECB_SENSE) != 0) 1238 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1239 else { 1240 /* First, save the return values */ 1241 ccb->csio.resid = ecb->dleft; 1242 ncr53c9x_sense(sc, ecb); 1243 return; 1244 } 1245 } else { 1246 ccb->csio.resid = ecb->dleft; 1247 } 1248#if 0 1249 if (xs->status == SCSI_QUEUE_FULL || xs->status == XS_BUSY) 1250 xs->error = XS_BUSY; 1251#endif 1252 } 1253 1254#ifdef NCR53C9X_DEBUG 1255 if (ncr53c9x_debug & NCR_SHOWTRAC) { 1256 if (ccb->csio.resid != 0) 1257 printf("resid=%d ", ccb->csio.resid); 1258#if 0 1259 if (xs->error == XS_SENSE) 1260 printf("sense=0x%02x\n", 1261 xs->sense.scsi_sense.error_code); 1262 else 1263 printf("error=%d\n", xs->error); 1264#endif 1265 } 1266#endif 1267 1268 /* 1269 * Remove the ECB from whatever queue it's on. 1270 */ 1271 ncr53c9x_dequeue(sc, ecb); 1272 if (ecb == sc->sc_nexus) { 1273 sc->sc_nexus = NULL; 1274 if (sc->sc_state != NCR_CLEANING) { 1275 sc->sc_state = NCR_IDLE; 1276 ncr53c9x_sched(sc); 1277 } 1278 } 1279 1280 if (ccb->ccb_h.status == CAM_SEL_TIMEOUT) { 1281 /* Selection timeout -- discard this LUN if empty */ 1282 if (li->untagged == NULL && li->used == 0) { 1283 if (lun < NCR_NLUN) 1284 ti->lun[lun] = NULL; 1285 LIST_REMOVE(li, link); 1286 free(li, M_DEVBUF); 1287 } 1288 } 1289 1290 ncr53c9x_free_ecb(sc, ecb); 1291 ti->cmds++; 1292 mtx_unlock(&sc->sc_lock); 1293 xpt_done(ccb); 1294 mtx_lock(&sc->sc_lock); 1295} 1296 1297static void 1298ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1299{ 1300 struct ncr53c9x_tinfo *ti; 1301 struct ncr53c9x_linfo *li; 1302 int64_t lun; 1303 1304 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1305 lun = ecb->ccb->ccb_h.target_lun; 1306 li = TINFO_LUN(ti, lun); 1307#ifdef DIAGNOSTIC 1308 if (li == NULL || li->lun != lun) 1309 panic("ncr53c9x_dequeue: lun %qx for ecb %p does not exist", 1310 (long long) lun, ecb); 1311#endif 1312 if (li->untagged == ecb) { 1313 li->busy = 0; 1314 li->untagged = NULL; 1315 } 1316 if (ecb->tag[0] && li->queued[ecb->tag[1]] != NULL) { 1317#ifdef DIAGNOSTIC 1318 if (li->queued[ecb->tag[1]] != NULL && 1319 (li->queued[ecb->tag[1]] != ecb)) 1320 panic("ncr53c9x_dequeue: slot %d for lun %qx has %p " 1321 "instead of ecb %p\n", ecb->tag[1], 1322 (long long) lun, 1323 li->queued[ecb->tag[1]], ecb); 1324#endif 1325 li->queued[ecb->tag[1]] = NULL; 1326 li->used--; 1327 } 1328 1329 if ((ecb->flags & ECB_READY) != 0) { 1330 ecb->flags &= ~ECB_READY; 1331 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1332 } 1333} 1334 1335/* 1336 * INTERRUPT/PROTOCOL ENGINE 1337 */ 1338 1339/* 1340 * Schedule an outgoing message by prioritizing it, and asserting 1341 * attention on the bus. We can only do this when we are the initiator 1342 * else there will be an illegal command interrupt. 1343 */ 1344#define ncr53c9x_sched_msgout(m) \ 1345 do { \ 1346 NCR_MSGS(("ncr53c9x_sched_msgout %x %d", m, __LINE__)); \ 1347 NCRCMD(sc, NCRCMD_SETATN); \ 1348 sc->sc_flags |= NCR_ATN; \ 1349 sc->sc_msgpriq |= (m); \ 1350 } while (0) 1351 1352static void 1353ncr53c9x_flushfifo(struct ncr53c9x_softc *sc) 1354{ 1355 NCR_TRACE(("[flushfifo] ")); 1356 1357 NCRCMD(sc, NCRCMD_FLUSH); 1358 1359 if (sc->sc_phase == COMMAND_PHASE || 1360 sc->sc_phase == MESSAGE_OUT_PHASE) 1361 DELAY(2); 1362} 1363 1364static int 1365ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how) 1366{ 1367 int i, n; 1368 u_char *buf; 1369 1370 switch(how) { 1371 case NCR_RDFIFO_START: 1372 buf = sc->sc_imess; 1373 sc->sc_imlen = 0; 1374 break; 1375 case NCR_RDFIFO_CONTINUE: 1376 buf = sc->sc_imess + sc->sc_imlen; 1377 break; 1378 default: 1379 panic("ncr53c9x_rdfifo: bad flag"); 1380 break; 1381 } 1382 1383 /* 1384 * XXX buffer (sc_imess) size for message 1385 */ 1386 1387 n = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 1388 1389 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1390 n *= 2; 1391 1392 for (i = 0; i < n; i++) 1393 buf[i] = NCR_READ_REG(sc, NCR_FIFO); 1394 1395 if (sc->sc_espstat2 & NCRFAS_STAT2_ISHUTTLE) { 1396 1397 NCR_WRITE_REG(sc, NCR_FIFO, 0); 1398 buf[i++] = NCR_READ_REG(sc, NCR_FIFO); 1399 1400 NCR_READ_REG(sc, NCR_FIFO); 1401 1402 ncr53c9x_flushfifo(sc); 1403 } 1404 } else { 1405 for (i = 0; i < n; i++) 1406 buf[i] = NCR_READ_REG(sc, NCR_FIFO); 1407 } 1408 1409 sc->sc_imlen += i; 1410 1411#if 0 1412#ifdef NCR53C9X_DEBUG 1413 { 1414 int j; 1415 1416 NCR_TRACE(("\n[rdfifo %s (%d):", 1417 (how == NCR_RDFIFO_START) ? "start" : "cont", 1418 (int)sc->sc_imlen)); 1419 if (ncr53c9x_debug & NCR_SHOWTRAC) { 1420 for (j = 0; j < sc->sc_imlen; j++) 1421 printf(" %02x", sc->sc_imess[j]); 1422 printf("]\n"); 1423 } 1424 } 1425#endif 1426#endif 1427 return sc->sc_imlen; 1428} 1429 1430static void 1431ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, int len) 1432{ 1433 int i; 1434 1435#ifdef NCR53C9X_DEBUG 1436 NCR_MSGS(("[wrfifo(%d):", len)); 1437 if (ncr53c9x_debug & NCR_SHOWMSGS) { 1438 for (i = 0; i < len; i++) 1439 printf(" %02x", p[i]); 1440 printf("]\n"); 1441 } 1442#endif 1443 1444 for (i = 0; i < len; i++) { 1445 NCR_WRITE_REG(sc, NCR_FIFO, p[i]); 1446 1447 if (sc->sc_rev == NCR_VARIANT_FAS366) 1448 NCR_WRITE_REG(sc, NCR_FIFO, 0); 1449 } 1450} 1451 1452static int 1453ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype, 1454 int tagid) 1455{ 1456 u_char selid, target, lun; 1457 struct ncr53c9x_ecb *ecb = NULL; 1458 struct ncr53c9x_tinfo *ti; 1459 struct ncr53c9x_linfo *li; 1460 1461 1462 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1463 target = sc->sc_selid; 1464 } else { 1465 /* 1466 * The SCSI chip made a snapshot of the data bus 1467 * while the reselection was being negotiated. 1468 * This enables us to determine which target did 1469 * the reselect. 1470 */ 1471 selid = sc->sc_selid & ~(1 << sc->sc_id); 1472 if (selid & (selid - 1)) { 1473 device_printf(sc->sc_dev, "reselect with invalid " 1474 "selid %02x; sending DEVICE RESET\n", selid); 1475 goto reset; 1476 } 1477 1478 target = ffs(selid) - 1; 1479 } 1480 lun = message & 0x07; 1481 1482 /* 1483 * Search wait queue for disconnected cmd 1484 * The list should be short, so I haven't bothered with 1485 * any more sophisticated structures than a simple 1486 * singly linked list. 1487 */ 1488 ti = &sc->sc_tinfo[target]; 1489 li = TINFO_LUN(ti, lun); 1490 1491 /* 1492 * We can get as far as the LUN with the IDENTIFY 1493 * message. Check to see if we're running an 1494 * un-tagged command. Otherwise ack the IDENTIFY 1495 * and wait for a tag message. 1496 */ 1497 if (li != NULL) { 1498 if (li->untagged != NULL && li->busy) 1499 ecb = li->untagged; 1500 else if (tagtype != MSG_SIMPLE_Q_TAG) { 1501 /* Wait for tag to come by */ 1502 sc->sc_state = NCR_IDENTIFIED; 1503 return (0); 1504 } else if (tagtype) 1505 ecb = li->queued[tagid]; 1506 } 1507 if (ecb == NULL) { 1508 device_printf(sc->sc_dev, "reselect from target %d lun %d " 1509 "tag %x:%x with no nexus; sending ABORT\n", 1510 target, lun, tagtype, tagid); 1511 goto abort; 1512 } 1513 1514 /* Make this nexus active again. */ 1515 sc->sc_state = NCR_CONNECTED; 1516 sc->sc_nexus = ecb; 1517 ncr53c9x_setsync(sc, ti); 1518 1519 if (ecb->flags & ECB_RESET) 1520 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1521 else if (ecb->flags & ECB_ABORT) 1522 ncr53c9x_sched_msgout(SEND_ABORT); 1523 1524 /* Do an implicit RESTORE POINTERS. */ 1525 sc->sc_dp = ecb->daddr; 1526 sc->sc_dleft = ecb->dleft; 1527 1528 return (0); 1529 1530reset: 1531 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1532 return (1); 1533 1534abort: 1535 ncr53c9x_sched_msgout(SEND_ABORT); 1536 return (1); 1537} 1538 1539/* From NetBSD. These should go into CAM at some point */ 1540#define MSG_ISEXTENDED(m) ((m) == MSG_EXTENDED) 1541#define MSG_IS1BYTE(m) \ 1542 ((!MSG_ISEXTENDED(m) && (m) < 0x20) || MSG_ISIDENTIFY(m)) 1543#define MSG_IS2BYTE(m) (((m) & 0xf0) == 0x20) 1544 1545static inline int 1546__verify_msg_format(u_char *p, int len) 1547{ 1548 1549 if (len == 1 && MSG_IS1BYTE(p[0])) 1550 return 1; 1551 if (len == 2 && MSG_IS2BYTE(p[0])) 1552 return 1; 1553 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1554 len == p[1] + 2) 1555 return 1; 1556 1557 return 0; 1558} 1559 1560/* 1561 * Get an incoming message as initiator. 1562 * 1563 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1564 * byte in the FIFO 1565 */ 1566static void 1567ncr53c9x_msgin(struct ncr53c9x_softc *sc) 1568{ 1569 1570 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1571 1572 if (sc->sc_imlen == 0) { 1573 device_printf(sc->sc_dev, "msgin: no msg byte available\n"); 1574 return; 1575 } 1576 1577 /* 1578 * Prepare for a new message. A message should (according 1579 * to the SCSI standard) be transmitted in one single 1580 * MESSAGE_IN_PHASE. If we have been in some other phase, 1581 * then this is a new message. 1582 */ 1583 if (sc->sc_prevphase != MESSAGE_IN_PHASE && 1584 sc->sc_state != NCR_RESELECTED) { 1585 device_printf(sc->sc_dev, "phase change, dropping message, " 1586 "prev %d, state %d\n", sc->sc_prevphase, sc->sc_state); 1587 sc->sc_flags &= ~NCR_DROP_MSGI; 1588 sc->sc_imlen = 0; 1589 } 1590 1591 /* 1592 * If we're going to reject the message, don't bother storing 1593 * the incoming bytes. But still, we need to ACK them. 1594 */ 1595 if ((sc->sc_flags & NCR_DROP_MSGI) != 0) { 1596 NCRCMD(sc, NCRCMD_MSGOK); 1597 printf("<dropping msg byte %x>", sc->sc_imess[sc->sc_imlen]); 1598 return; 1599 } 1600 1601 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1602 ncr53c9x_sched_msgout(SEND_REJECT); 1603 sc->sc_flags |= NCR_DROP_MSGI; 1604 } else { 1605 u_char *pb; 1606 int plen; 1607 1608 switch (sc->sc_state) { 1609 /* 1610 * if received message is the first of reselection 1611 * then first byte is selid, and then message 1612 */ 1613 case NCR_RESELECTED: 1614 pb = sc->sc_imess + 1; 1615 plen = sc->sc_imlen - 1; 1616 break; 1617 default: 1618 pb = sc->sc_imess; 1619 plen = sc->sc_imlen; 1620 break; 1621 } 1622 1623 if (__verify_msg_format(pb, plen)) 1624 goto gotit; 1625 } 1626 1627 /* Ack what we have so far */ 1628 NCRCMD(sc, NCRCMD_MSGOK); 1629 return; 1630 1631gotit: 1632 NCR_MSGS(("gotmsg(%x) state %d", sc->sc_imess[0], sc->sc_state)); 1633 /* we got complete message, flush the imess, */ 1634 /* XXX nobody uses imlen below */ 1635 sc->sc_imlen = 0; 1636 /* 1637 * Now we should have a complete message (1 byte, 2 byte 1638 * and moderately long extended messages). We only handle 1639 * extended messages which total length is shorter than 1640 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1641 */ 1642 switch (sc->sc_state) { 1643 struct ncr53c9x_ecb *ecb; 1644 struct ncr53c9x_tinfo *ti; 1645 struct ncr53c9x_linfo *li; 1646 int lun; 1647 1648 case NCR_CONNECTED: 1649 ecb = sc->sc_nexus; 1650 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1651 1652 switch (sc->sc_imess[0]) { 1653 case MSG_CMDCOMPLETE: 1654 NCR_MSGS(("cmdcomplete ")); 1655 if (sc->sc_dleft < 0) { 1656 xpt_print_path(ecb->ccb->ccb_h.path); 1657 printf("got %ld extra bytes\n", 1658 -(long)sc->sc_dleft); 1659 sc->sc_dleft = 0; 1660 } 1661 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) ? 1662 0 : sc->sc_dleft; 1663 if ((ecb->flags & ECB_SENSE) == 0) 1664 ecb->ccb->csio.resid = ecb->dleft; 1665 sc->sc_state = NCR_CMDCOMPLETE; 1666 break; 1667 1668 case MSG_MESSAGE_REJECT: 1669 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1670 switch (sc->sc_msgout) { 1671 case SEND_TAG: 1672 /* 1673 * Target does not like tagged queuing. 1674 * - Flush the command queue 1675 * - Disable tagged queuing for the target 1676 * - Dequeue ecb from the queued array. 1677 */ 1678 device_printf(sc->sc_dev, "tagged queuing " 1679 "rejected: target %d\n", 1680 ecb->ccb->ccb_h.target_id); 1681 1682 NCR_MSGS(("(rejected sent tag)")); 1683 NCRCMD(sc, NCRCMD_FLUSH); 1684 DELAY(1); 1685 ti->flags &= ~T_TAG; 1686 lun = ecb->ccb->ccb_h.target_lun; 1687 li = TINFO_LUN(ti, lun); 1688 if (ecb->tag[0] && 1689 li->queued[ecb->tag[1]] != NULL) { 1690 li->queued[ecb->tag[1]] = NULL; 1691 li->used--; 1692 } 1693 ecb->tag[0] = ecb->tag[1] = 0; 1694 li->untagged = ecb; 1695 li->busy = 1; 1696 break; 1697 1698 case SEND_SDTR: 1699 device_printf(sc->sc_dev, "sync transfer " 1700 "rejected: target %d\n", 1701 ecb->ccb->ccb_h.target_id); 1702 1703 sc->sc_flags &= ~NCR_SYNCHNEGO; 1704 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1705 ncr53c9x_setsync(sc, ti); 1706 break; 1707 1708 case SEND_WDTR: 1709 device_printf(sc->sc_dev, "wide transfer " 1710 "rejected: target %d\n", 1711 ecb->ccb->ccb_h.target_id); 1712 ti->flags &= ~(T_WIDE | T_WDTRSENT); 1713 ti->width = 0; 1714 break; 1715 1716 case SEND_INIT_DET_ERR: 1717 goto abort; 1718 } 1719 break; 1720 1721 case MSG_NOOP: 1722 NCR_MSGS(("noop ")); 1723 break; 1724 1725 case MSG_HEAD_OF_Q_TAG: 1726 case MSG_SIMPLE_Q_TAG: 1727 case MSG_ORDERED_Q_TAG: 1728 NCR_MSGS(("TAG %x:%x", 1729 sc->sc_imess[0], sc->sc_imess[1])); 1730 break; 1731 1732 case MSG_DISCONNECT: 1733 NCR_MSGS(("disconnect ")); 1734 ti->dconns++; 1735 sc->sc_state = NCR_DISCONNECT; 1736 1737 /* 1738 * Mark the fact that all bytes have moved. The 1739 * target may not bother to do a SAVE POINTERS 1740 * at this stage. This flag will set the residual 1741 * count to zero on MSG COMPLETE. 1742 */ 1743 if (sc->sc_dleft == 0) 1744 ecb->flags |= ECB_TENTATIVE_DONE; 1745 1746 break; 1747 1748 case MSG_SAVEDATAPOINTER: 1749 NCR_MSGS(("save datapointer ")); 1750 ecb->daddr = sc->sc_dp; 1751 ecb->dleft = sc->sc_dleft; 1752 break; 1753 1754 case MSG_RESTOREPOINTERS: 1755 NCR_MSGS(("restore datapointer ")); 1756 sc->sc_dp = ecb->daddr; 1757 sc->sc_dleft = ecb->dleft; 1758 break; 1759 1760 case MSG_EXTENDED: 1761 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1762 switch (sc->sc_imess[2]) { 1763 case MSG_EXT_SDTR: 1764 NCR_MSGS(("SDTR period %d, offset %d ", 1765 sc->sc_imess[3], sc->sc_imess[4])); 1766 if (sc->sc_imess[1] != 3) 1767 goto reject; 1768 ti->period = sc->sc_imess[3]; 1769 ti->offset = sc->sc_imess[4]; 1770 ti->flags &= ~T_NEGOTIATE; 1771 if (sc->sc_minsync == 0 || 1772 ti->offset == 0 || 1773 ti->period > 124) { 1774#if 0 1775#ifdef NCR53C9X_DEBUG 1776 xpt_print_path(ecb->ccb->ccb_h.path); 1777 printf("async mode\n"); 1778#endif 1779#endif 1780 ti->flags &= ~T_SYNCMODE; 1781 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) { 1782 /* 1783 * target initiated negotiation 1784 */ 1785 ti->offset = 0; 1786 ncr53c9x_sched_msgout( 1787 SEND_SDTR); 1788 } 1789 } else { 1790 int p; 1791 1792 p = ncr53c9x_stp2cpb(sc, ti->period); 1793 ti->period = ncr53c9x_cpb2stp(sc, p); 1794 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) { 1795 /* 1796 * target initiated negotiation 1797 */ 1798 if (ti->period < 1799 sc->sc_minsync) 1800 ti->period = 1801 sc->sc_minsync; 1802 if (ti->offset > 15) 1803 ti->offset = 15; 1804 ti->flags &= ~T_SYNCMODE; 1805 ncr53c9x_sched_msgout( 1806 SEND_SDTR); 1807 } else { 1808 /* we are sync */ 1809 ti->flags |= T_SYNCMODE; 1810 } 1811 } 1812 sc->sc_flags &= ~NCR_SYNCHNEGO; 1813 ncr53c9x_setsync(sc, ti); 1814 break; 1815 1816 case MSG_EXT_WDTR: 1817#ifdef NCR53C9X_DEBUG 1818 device_printf(sc->sc_dev, "wide mode %d\n", 1819 sc->sc_imess[3]); 1820#endif 1821 if (sc->sc_imess[3] == 1) { 1822 ti->cfg3 |= NCRFASCFG3_EWIDE; 1823 ncr53c9x_setsync(sc, ti); 1824 } else 1825 ti->width = 0; 1826 /* 1827 * Device started width negotiation. 1828 */ 1829 if (!(ti->flags & T_WDTRSENT)) 1830 ncr53c9x_sched_msgout(SEND_WDTR); 1831 ti->flags &= ~(T_WIDE | T_WDTRSENT); 1832 break; 1833 default: 1834 xpt_print_path(ecb->ccb->ccb_h.path); 1835 printf("unrecognized MESSAGE EXTENDED;" 1836 " sending REJECT\n"); 1837 goto reject; 1838 } 1839 break; 1840 1841 default: 1842 NCR_MSGS(("ident ")); 1843 xpt_print_path(ecb->ccb->ccb_h.path); 1844 printf("unrecognized MESSAGE; sending REJECT\n"); 1845 reject: 1846 ncr53c9x_sched_msgout(SEND_REJECT); 1847 break; 1848 } 1849 break; 1850 1851 case NCR_IDENTIFIED: 1852 /* 1853 * IDENTIFY message was received and queue tag is expected now 1854 */ 1855 if ((sc->sc_imess[0] != MSG_SIMPLE_Q_TAG) || 1856 (sc->sc_msgify == 0)) { 1857 device_printf(sc->sc_dev, "TAG reselect without " 1858 "IDENTIFY; MSG %x; sending DEVICE RESET\n", 1859 sc->sc_imess[0]); 1860 goto reset; 1861 } 1862 (void) ncr53c9x_reselect(sc, sc->sc_msgify, 1863 sc->sc_imess[0], sc->sc_imess[1]); 1864 break; 1865 1866 case NCR_RESELECTED: 1867 if (MSG_ISIDENTIFY(sc->sc_imess[1])) { 1868 sc->sc_msgify = sc->sc_imess[1]; 1869 } else { 1870 device_printf(sc->sc_dev, "reselect without IDENTIFY;" 1871 " MSG %x; sending DEVICE RESET\n", sc->sc_imess[1]); 1872 goto reset; 1873 } 1874 (void) ncr53c9x_reselect(sc, sc->sc_msgify, 0, 0); 1875 break; 1876 1877 default: 1878 device_printf(sc->sc_dev, "unexpected MESSAGE IN; " 1879 "sending DEVICE RESET\n"); 1880 reset: 1881 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1882 break; 1883 1884 abort: 1885 ncr53c9x_sched_msgout(SEND_ABORT); 1886 break; 1887 } 1888 1889 /* if we have more messages to send set ATN */ 1890 if (sc->sc_msgpriq) 1891 NCRCMD(sc, NCRCMD_SETATN); 1892 1893 /* Ack last message byte */ 1894 NCRCMD(sc, NCRCMD_MSGOK); 1895 1896 /* Done, reset message pointer. */ 1897 sc->sc_flags &= ~NCR_DROP_MSGI; 1898 sc->sc_imlen = 0; 1899} 1900 1901 1902/* 1903 * Send the highest priority, scheduled message 1904 */ 1905static void 1906ncr53c9x_msgout(struct ncr53c9x_softc *sc) 1907{ 1908 struct ncr53c9x_tinfo *ti; 1909 struct ncr53c9x_ecb *ecb; 1910 size_t size; 1911 1912 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1913 sc->sc_msgpriq, sc->sc_prevphase)); 1914 1915 /* 1916 * XXX - the NCR_ATN flag is not in sync with the actual ATN 1917 * condition on the SCSI bus. The 53c9x chip 1918 * automatically turns off ATN before sending the 1919 * message byte. (see also the comment below in the 1920 * default case when picking out a message to send) 1921 */ 1922 if (sc->sc_flags & NCR_ATN) { 1923 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1924 new: 1925 NCRCMD(sc, NCRCMD_FLUSH); 1926/* DELAY(1); */ 1927 sc->sc_msgoutq = 0; 1928 sc->sc_omlen = 0; 1929 } 1930 } else { 1931 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1932 ncr53c9x_sched_msgout(sc->sc_msgoutq); 1933 goto new; 1934 } else { 1935 device_printf(sc->sc_dev, "at line %d: unexpected " 1936 "MESSAGE OUT phase\n", __LINE__); 1937 } 1938 } 1939 1940 if (sc->sc_omlen == 0) { 1941 /* Pick up highest priority message */ 1942 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1943 sc->sc_msgoutq |= sc->sc_msgout; 1944 sc->sc_msgpriq &= ~sc->sc_msgout; 1945 sc->sc_omlen = 1; /* "Default" message len */ 1946 switch (sc->sc_msgout) { 1947 case SEND_SDTR: 1948 ecb = sc->sc_nexus; 1949 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1950 sc->sc_omess[0] = MSG_EXTENDED; 1951 sc->sc_omess[1] = MSG_EXT_SDTR_LEN; 1952 sc->sc_omess[2] = MSG_EXT_SDTR; 1953 sc->sc_omess[3] = ti->period; 1954 sc->sc_omess[4] = ti->offset; 1955 sc->sc_omlen = 5; 1956 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 1957 ti->flags |= T_SYNCMODE; 1958 ncr53c9x_setsync(sc, ti); 1959 } 1960 break; 1961 case SEND_WDTR: 1962 ecb = sc->sc_nexus; 1963 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1964 sc->sc_omess[0] = MSG_EXTENDED; 1965 sc->sc_omess[1] = MSG_EXT_WDTR_LEN; 1966 sc->sc_omess[2] = MSG_EXT_WDTR; 1967 sc->sc_omess[3] = ti->width; 1968 sc->sc_omlen = 4; 1969 break; 1970 case SEND_IDENTIFY: 1971 if (sc->sc_state != NCR_CONNECTED) { 1972 device_printf(sc->sc_dev, "at line %d: no " 1973 "nexus\n", __LINE__); 1974 } 1975 ecb = sc->sc_nexus; 1976 sc->sc_omess[0] = 1977 MSG_IDENTIFY(ecb->ccb->ccb_h.target_lun, 0); 1978 break; 1979 case SEND_TAG: 1980 if (sc->sc_state != NCR_CONNECTED) { 1981 device_printf(sc->sc_dev, "at line %d: no " 1982 "nexus\n", __LINE__); 1983 } 1984 ecb = sc->sc_nexus; 1985 sc->sc_omess[0] = ecb->tag[0]; 1986 sc->sc_omess[1] = ecb->tag[1]; 1987 sc->sc_omlen = 2; 1988 break; 1989 case SEND_DEV_RESET: 1990 sc->sc_flags |= NCR_ABORTING; 1991 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1992 ecb = sc->sc_nexus; 1993 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1994 ti->flags &= ~T_SYNCMODE; 1995 if ((ti->flags & T_SYNCHOFF) == 0) 1996 /* We can re-start sync negotiation */ 1997 ti->flags |= T_NEGOTIATE; 1998 break; 1999 case SEND_PARITY_ERROR: 2000 sc->sc_omess[0] = MSG_PARITY_ERROR; 2001 break; 2002 case SEND_ABORT: 2003 sc->sc_flags |= NCR_ABORTING; 2004 sc->sc_omess[0] = MSG_ABORT; 2005 break; 2006 case SEND_INIT_DET_ERR: 2007 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 2008 break; 2009 case SEND_REJECT: 2010 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 2011 break; 2012 default: 2013 /* 2014 * We normally do not get here, since the chip 2015 * automatically turns off ATN before the last 2016 * byte of a message is sent to the target. 2017 * However, if the target rejects our (multi-byte) 2018 * message early by switching to MSG IN phase 2019 * ATN remains on, so the target may return to 2020 * MSG OUT phase. If there are no scheduled messages 2021 * left we send a NO-OP. 2022 * 2023 * XXX - Note that this leaves no useful purpose for 2024 * the NCR_ATN flag. 2025 */ 2026 sc->sc_flags &= ~NCR_ATN; 2027 sc->sc_omess[0] = MSG_NOOP; 2028 break; 2029 } 2030 sc->sc_omp = sc->sc_omess; 2031 } 2032 2033#ifdef DEBUG 2034 if (ncr53c9x_debug & NCR_SHOWMSGS) { 2035 int i; 2036 2037 NCR_MSGS(("<msgout:")); 2038 for (i = 0; i < sc->sc_omlen; i++) 2039 NCR_MSGS((" %02x", sc->sc_omess[i])); 2040 NCR_MSGS(("> ")); 2041 } 2042#endif 2043 if (sc->sc_rev == NCR_VARIANT_FAS366) { 2044 /* 2045 * XXX fifo size 2046 */ 2047 ncr53c9x_flushfifo(sc); 2048 ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen); 2049 NCRCMD(sc, NCRCMD_TRANS); 2050 } else { 2051 /* (re)send the message */ 2052 size = min(sc->sc_omlen, sc->sc_maxxfer); 2053 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 2054 /* Program the SCSI counter */ 2055 NCR_SET_COUNT(sc, size); 2056 2057 /* Load the count in and start the message-out transfer */ 2058 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2059 NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA); 2060 NCRDMA_GO(sc); 2061 } 2062} 2063 2064/* 2065 * This is the most critical part of the driver, and has to know 2066 * how to deal with *all* error conditions and phases from the SCSI 2067 * bus. If there are no errors and the DMA was active, then call the 2068 * DMA pseudo-interrupt handler. If this returns 1, then that was it 2069 * and we can return from here without further processing. 2070 * 2071 * Most of this needs verifying. 2072 */ 2073void 2074ncr53c9x_intr(void *arg) 2075{ 2076 struct ncr53c9x_softc *sc = arg; 2077 struct ncr53c9x_ecb *ecb; 2078 struct ncr53c9x_tinfo *ti; 2079 size_t size; 2080 int nfifo; 2081 2082 NCR_INTS(("[ncr53c9x_intr: state %d]", sc->sc_state)); 2083 2084 if (!NCRDMA_ISINTR(sc)) 2085 return; 2086 2087 mtx_lock(&sc->sc_lock); 2088again: 2089 /* and what do the registers say... */ 2090 ncr53c9x_readregs(sc); 2091 2092 /* 2093 * At the moment, only a SCSI Bus Reset or Illegal 2094 * Command are classed as errors. A disconnect is a 2095 * valid condition, and we let the code check is the 2096 * "NCR_BUSFREE_OK" flag was set before declaring it 2097 * and error. 2098 * 2099 * Also, the status register tells us about "Gross 2100 * Errors" and "Parity errors". Only the Gross Error 2101 * is really bad, and the parity errors are dealt 2102 * with later 2103 * 2104 * TODO 2105 * If there are too many parity error, go to slow 2106 * cable mode ? 2107 */ 2108 2109 /* SCSI Reset */ 2110 if ((sc->sc_espintr & NCRINTR_SBR) != 0) { 2111 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) != 0) { 2112 NCRCMD(sc, NCRCMD_FLUSH); 2113 DELAY(1); 2114 } 2115 if (sc->sc_state != NCR_SBR) { 2116 device_printf(sc->sc_dev, "SCSI bus reset\n"); 2117 ncr53c9x_init(sc, 0); /* Restart everything */ 2118 goto out; 2119 } 2120#if 0 2121/*XXX*/ printf("<expected bus reset: " 2122 "[intr %x, stat %x, step %d]>\n", 2123 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2124#endif 2125 if (sc->sc_nexus != NULL) 2126 panic("%s: nexus in reset state", 2127 device_get_nameunit(sc->sc_dev)); 2128 goto sched; 2129 } 2130 2131 ecb = sc->sc_nexus; 2132 2133#define NCRINTR_ERR (NCRINTR_SBR|NCRINTR_ILL) 2134 if (sc->sc_espintr & NCRINTR_ERR || 2135 sc->sc_espstat & NCRSTAT_GE) { 2136 2137 if ((sc->sc_espstat & NCRSTAT_GE) != 0) { 2138 /* Gross Error; no target ? */ 2139 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2140 NCRCMD(sc, NCRCMD_FLUSH); 2141 DELAY(1); 2142 } 2143 if (sc->sc_state == NCR_CONNECTED || 2144 sc->sc_state == NCR_SELECTING) { 2145 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2146 ncr53c9x_done(sc, ecb); 2147 } 2148 goto out; 2149 } 2150 2151 if ((sc->sc_espintr & NCRINTR_ILL) != 0) { 2152 if ((sc->sc_flags & NCR_EXPECT_ILLCMD) != 0) { 2153 /* 2154 * Eat away "Illegal command" interrupt 2155 * on a ESP100 caused by a re-selection 2156 * while we were trying to select 2157 * another target. 2158 */ 2159#ifdef DEBUG 2160 device_printf(sc->sc_dev, "ESP100 work-around " 2161 "activated\n"); 2162#endif 2163 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 2164 goto out; 2165 } 2166 /* illegal command, out of sync ? */ 2167 device_printf(sc->sc_dev, "illegal command: 0x%x " 2168 "(state %d, phase %x, prevphase %x)\n", 2169 sc->sc_lastcmd, 2170 sc->sc_state, sc->sc_phase, sc->sc_prevphase); 2171 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2172 NCRCMD(sc, NCRCMD_FLUSH); 2173 DELAY(1); 2174 } 2175 ncr53c9x_init(sc, 1); /* Restart everything */ 2176 goto out; 2177 } 2178 } 2179 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 2180 2181 /* 2182 * Call if DMA is active. 2183 * 2184 * If DMA_INTR returns true, then maybe go 'round the loop 2185 * again in case there is no more DMA queued, but a phase 2186 * change is expected. 2187 */ 2188 if (NCRDMA_ISACTIVE(sc)) { 2189 int r = NCRDMA_INTR(sc); 2190 if (r == -1) { 2191 device_printf(sc->sc_dev, "DMA error; resetting\n"); 2192 ncr53c9x_init(sc, 1); 2193 goto out; 2194 } 2195 /* If DMA active here, then go back to work... */ 2196 if (NCRDMA_ISACTIVE(sc)) 2197 goto out; 2198 2199 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 2200 /* 2201 * DMA not completed. If we can not find a 2202 * acceptable explanation, print a diagnostic. 2203 */ 2204 if (sc->sc_state == NCR_SELECTING) 2205 /* 2206 * This can happen if we are reselected 2207 * while using DMA to select a target. 2208 */ 2209 /*void*/; 2210 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 2211 /* 2212 * Our (multi-byte) message (eg SDTR) was 2213 * interrupted by the target to send 2214 * a MSG REJECT. 2215 * Print diagnostic if current phase 2216 * is not MESSAGE IN. 2217 */ 2218 if (sc->sc_phase != MESSAGE_IN_PHASE) 2219 device_printf(sc->sc_dev,"!TC on MSGOUT" 2220 " [intr %x, stat %x, step %d]" 2221 " prevphase %x, resid %lx\n", 2222 sc->sc_espintr, 2223 sc->sc_espstat, 2224 sc->sc_espstep, 2225 sc->sc_prevphase, 2226 (u_long)sc->sc_omlen); 2227 } else if (sc->sc_dleft == 0) { 2228 /* 2229 * The DMA operation was started for 2230 * a DATA transfer. Print a diagnostic 2231 * if the DMA counter and TC bit 2232 * appear to be out of sync. 2233 */ 2234 device_printf(sc->sc_dev, "!TC on DATA XFER" 2235 " [intr %x, stat %x, step %d]" 2236 " prevphase %x, resid %x\n", 2237 sc->sc_espintr, 2238 sc->sc_espstat, 2239 sc->sc_espstep, 2240 sc->sc_prevphase, 2241 ecb ? ecb->dleft : -1); 2242 } 2243 } 2244 } 2245 2246 /* 2247 * Check for less serious errors. 2248 */ 2249 if ((sc->sc_espstat & NCRSTAT_PE) != 0) { 2250 device_printf(sc->sc_dev, "SCSI bus parity error\n"); 2251 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 2252 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 2253 else 2254 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 2255 } 2256 2257 if ((sc->sc_espintr & NCRINTR_DIS) != 0) { 2258 sc->sc_msgify = 0; 2259 NCR_INTS(("<DISC [intr %x, stat %x, step %d]>", 2260 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 2261 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2262 NCRCMD(sc, NCRCMD_FLUSH); 2263/* DELAY(1); */ 2264 } 2265 /* 2266 * This command must (apparently) be issued within 2267 * 250mS of a disconnect. So here you are... 2268 */ 2269 NCRCMD(sc, NCRCMD_ENSEL); 2270 2271 switch (sc->sc_state) { 2272 case NCR_RESELECTED: 2273 goto sched; 2274 2275 case NCR_SELECTING: 2276 { 2277 struct ncr53c9x_linfo *li; 2278 2279 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2280 2281 /* Selection timeout -- discard all LUNs if empty */ 2282 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2283 li = LIST_FIRST(&ti->luns); 2284 while (li != NULL) { 2285 if (li->untagged == NULL && li->used == 0) { 2286 if (li->lun < NCR_NLUN) 2287 ti->lun[li->lun] = NULL; 2288 LIST_REMOVE(li, link); 2289 free(li, M_DEVBUF); 2290 /* 2291 * Restart the search at the beginning 2292 */ 2293 li = LIST_FIRST(&ti->luns); 2294 continue; 2295 } 2296 li = LIST_NEXT(li, link); 2297 } 2298 goto finish; 2299 } 2300 case NCR_CONNECTED: 2301 if ((sc->sc_flags & NCR_SYNCHNEGO) != 0) { 2302#ifdef NCR53C9X_DEBUG 2303 if (ecb != NULL) 2304 xpt_print_path(ecb->ccb->ccb_h.path); 2305 printf("sync nego not completed!\n"); 2306#endif 2307 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2308 sc->sc_flags &= ~NCR_SYNCHNEGO; 2309 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 2310 } 2311 2312 /* it may be OK to disconnect */ 2313 if ((sc->sc_flags & NCR_ABORTING) == 0) { 2314 /* 2315 * Section 5.1.1 of the SCSI 2 spec 2316 * suggests issuing a REQUEST SENSE 2317 * following an unexpected disconnect. 2318 * Some devices go into a contingent 2319 * allegiance condition when 2320 * disconnecting, and this is necessary 2321 * to clean up their state. 2322 */ 2323 device_printf(sc->sc_dev, "unexpected " 2324 "disconnect [state %d, intr %x, stat %x, " 2325 "phase(c %x, p %x)]; ", sc->sc_state, 2326 sc->sc_espintr, sc->sc_espstat, 2327 sc->sc_phase, sc->sc_prevphase); 2328 2329 if ((ecb->flags & ECB_SENSE) != 0) { 2330 printf("resetting\n"); 2331 goto reset; 2332 } 2333 printf("sending REQUEST SENSE\n"); 2334 untimeout(ncr53c9x_timeout, ecb, 2335 ecb->ccb->ccb_h.timeout_ch); 2336 ncr53c9x_sense(sc, ecb); 2337 goto out; 2338 } 2339 2340 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT; 2341 goto finish; 2342 2343 case NCR_DISCONNECT: 2344 sc->sc_nexus = NULL; 2345 goto sched; 2346 2347 case NCR_CMDCOMPLETE: 2348 ecb->ccb->ccb_h.status = CAM_REQ_CMP; 2349 goto finish; 2350 } 2351 } 2352 2353 switch (sc->sc_state) { 2354 2355 case NCR_SBR: 2356 device_printf(sc->sc_dev, "waiting for Bus Reset to happen\n"); 2357 goto out; 2358 2359 case NCR_RESELECTED: 2360 /* 2361 * we must be continuing a message ? 2362 */ 2363 device_printf(sc->sc_dev, "unhandled reselect continuation, " 2364 "state %d, intr %02x\n", sc->sc_state, sc->sc_espintr); 2365 ncr53c9x_init(sc, 1); 2366 goto out; 2367 break; 2368 2369 case NCR_IDENTIFIED: 2370 ecb = sc->sc_nexus; 2371 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2372 int i = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 2373 /* 2374 * Things are seriously fucked up. 2375 * Pull the brakes, i.e. reset 2376 */ 2377 device_printf(sc->sc_dev, "target didn't send tag: %d " 2378 "bytes in fifo\n", i); 2379 /* Drain and display fifo */ 2380 while (i-- > 0) 2381 printf("[%d] ", NCR_READ_REG(sc, NCR_FIFO)); 2382 2383 ncr53c9x_init(sc, 1); 2384 goto out; 2385 } else 2386 goto msgin; 2387 2388 break; 2389 2390 case NCR_IDLE: 2391 case NCR_SELECTING: 2392 ecb = sc->sc_nexus; 2393 if (sc->sc_espintr & NCRINTR_RESEL) { 2394 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 2395 sc->sc_flags = 0; 2396 /* 2397 * If we're trying to select a 2398 * target ourselves, push our command 2399 * back into the ready list. 2400 */ 2401 if (sc->sc_state == NCR_SELECTING) { 2402 NCR_INTS(("backoff selector ")); 2403 untimeout(ncr53c9x_timeout, ecb, 2404 ecb->ccb->ccb_h.timeout_ch); 2405 ncr53c9x_dequeue(sc, ecb); 2406 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2407 ecb->flags |= ECB_READY; 2408 ecb = sc->sc_nexus = NULL; 2409 } 2410 sc->sc_state = NCR_RESELECTED; 2411 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2412 /* 2413 * Things are seriously fucked up. 2414 * Pull the brakes, i.e. reset 2415 */ 2416 device_printf(sc->sc_dev, "target didn't " 2417 "identify\n"); 2418 ncr53c9x_init(sc, 1); 2419 goto out; 2420 } 2421 /* 2422 * The C90 only inhibits FIFO writes until reselection 2423 * is complete, instead of waiting until the interrupt 2424 * status register has been read. So, if the reselect 2425 * happens while we were entering command bytes (for 2426 * another target) some of those bytes can appear in 2427 * the FIFO here, after the interrupt is taken. 2428 * 2429 * To remedy this situation, pull the Selection ID 2430 * and Identify message from the FIFO directly, and 2431 * ignore any extraneous fifo contents. Also, set 2432 * a flag that allows one Illegal Command Interrupt 2433 * to occur which the chip also generates as a result 2434 * of writing to the FIFO during a reselect. 2435 */ 2436 if (sc->sc_rev == NCR_VARIANT_ESP100) { 2437 nfifo = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 2438 sc->sc_imess[0] = NCR_READ_REG(sc, NCR_FIFO); 2439 sc->sc_imess[1] = NCR_READ_REG(sc, NCR_FIFO); 2440 sc->sc_imlen = 2; 2441 if (nfifo != 2) { 2442 /* Flush the rest */ 2443 NCRCMD(sc, NCRCMD_FLUSH); 2444 } 2445 sc->sc_flags |= NCR_EXPECT_ILLCMD; 2446 if (nfifo > 2) 2447 nfifo = 2; /* We fixed it.. */ 2448 } else 2449 nfifo = ncr53c9x_rdfifo(sc, NCR_RDFIFO_START); 2450 2451 if (nfifo != 2) { 2452 device_printf(sc->sc_dev, "RESELECT: %d bytes " 2453 "in FIFO! [intr %x, stat %x, step %d, " 2454 "prevphase %x]\n", 2455 nfifo, 2456 sc->sc_espintr, 2457 sc->sc_espstat, 2458 sc->sc_espstep, 2459 sc->sc_prevphase); 2460 ncr53c9x_init(sc, 1); 2461 goto out; 2462 } 2463 sc->sc_selid = sc->sc_imess[0]; 2464 NCR_INTS(("selid=%02x ", sc->sc_selid)); 2465 2466 /* Handle identify message */ 2467 ncr53c9x_msgin(sc); 2468 2469 if (sc->sc_state != NCR_CONNECTED && 2470 sc->sc_state != NCR_IDENTIFIED) { 2471 /* IDENTIFY fail?! */ 2472 device_printf(sc->sc_dev, "identify failed, " 2473 "state %d, intr %02x\n", sc->sc_state, 2474 sc->sc_espintr); 2475 ncr53c9x_init(sc, 1); 2476 goto out; 2477 } 2478 goto shortcut; /* ie. next phase expected soon */ 2479 } 2480 2481#define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS) 2482 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 2483 /* 2484 * Arbitration won; examine the `step' register 2485 * to determine how far the selection could progress. 2486 */ 2487 ecb = sc->sc_nexus; 2488 if (ecb == NULL) 2489 panic("ncr53c9x: no nexus"); 2490 2491 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2492 2493 switch (sc->sc_espstep) { 2494 case 0: 2495 /* 2496 * The target did not respond with a 2497 * message out phase - probably an old 2498 * device that doesn't recognize ATN. 2499 * Clear ATN and just continue, the 2500 * target should be in the command 2501 * phase. 2502 * XXXX check for command phase? 2503 */ 2504 NCRCMD(sc, NCRCMD_RSTATN); 2505 break; 2506 case 1: 2507 if ((ti->flags & T_NEGOTIATE) == 0 && 2508 ecb->tag[0] == 0) { 2509 device_printf(sc->sc_dev, "step 1 & " 2510 "!NEG\n"); 2511 goto reset; 2512 } 2513 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 2514 device_printf(sc->sc_dev, "!MSGOUT\n"); 2515 goto reset; 2516 } 2517 if (ti->flags & T_WIDE) { 2518 ti->flags |= T_WDTRSENT; 2519 ncr53c9x_sched_msgout(SEND_WDTR); 2520 } 2521 if (ti->flags & T_NEGOTIATE) { 2522 /* Start negotiating */ 2523 sc->sc_flags |= NCR_SYNCHNEGO; 2524 if (ecb->tag[0]) 2525 ncr53c9x_sched_msgout( 2526 SEND_TAG|SEND_SDTR); 2527 else 2528 ncr53c9x_sched_msgout( 2529 SEND_SDTR); 2530 } else { 2531 /* Could not do ATN3 so send TAG */ 2532 ncr53c9x_sched_msgout(SEND_TAG); 2533 } 2534 sc->sc_prevphase = MESSAGE_OUT_PHASE; /* XXXX */ 2535 break; 2536 case 3: 2537 /* 2538 * Grr, this is supposed to mean 2539 * "target left command phase prematurely". 2540 * It seems to happen regularly when 2541 * sync mode is on. 2542 * Look at FIFO to see if command went out. 2543 * (Timing problems?) 2544 */ 2545 if (sc->sc_features & NCR_F_DMASELECT) { 2546 if (sc->sc_cmdlen == 0) 2547 /* Hope for the best.. */ 2548 break; 2549 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 2550 & NCRFIFO_FF) == 0) { 2551 /* Hope for the best.. */ 2552 break; 2553 } 2554 printf("(%s:%d:%d): selection failed;" 2555 " %d left in FIFO " 2556 "[intr %x, stat %x, step %d]\n", 2557 device_get_nameunit(sc->sc_dev), 2558 ecb->ccb->ccb_h.target_id, 2559 ecb->ccb->ccb_h.target_lun, 2560 NCR_READ_REG(sc, NCR_FFLAG) 2561 & NCRFIFO_FF, 2562 sc->sc_espintr, sc->sc_espstat, 2563 sc->sc_espstep); 2564 NCRCMD(sc, NCRCMD_FLUSH); 2565 ncr53c9x_sched_msgout(SEND_ABORT); 2566 goto out; 2567 case 2: 2568 /* Select stuck at Command Phase */ 2569 NCRCMD(sc, NCRCMD_FLUSH); 2570 break; 2571 case 4: 2572 if (sc->sc_features & NCR_F_DMASELECT && 2573 sc->sc_cmdlen != 0) 2574 printf("(%s:%d:%d): select; " 2575 "%lu left in DMA buffer " 2576 "[intr %x, stat %x, step %d]\n", 2577 device_get_nameunit(sc->sc_dev), 2578 ecb->ccb->ccb_h.target_id, 2579 ecb->ccb->ccb_h.target_lun, 2580 (u_long)sc->sc_cmdlen, 2581 sc->sc_espintr, 2582 sc->sc_espstat, 2583 sc->sc_espstep); 2584 /* So far, everything went fine */ 2585 break; 2586 } 2587 2588 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 2589 /* Do an implicit RESTORE POINTERS. */ 2590 sc->sc_dp = ecb->daddr; 2591 sc->sc_dleft = ecb->dleft; 2592 sc->sc_state = NCR_CONNECTED; 2593 break; 2594 2595 } else { 2596 2597 device_printf(sc->sc_dev, "unexpected status after " 2598 "select: [intr %x, stat %x, step %x]\n", 2599 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2600 NCRCMD(sc, NCRCMD_FLUSH); 2601 DELAY(1); 2602 goto reset; 2603 } 2604 if (sc->sc_state == NCR_IDLE) { 2605 device_printf(sc->sc_dev, "stray interrupt\n"); 2606 mtx_unlock(&sc->sc_lock); 2607 return; 2608 } 2609 break; 2610 2611 case NCR_CONNECTED: 2612 if ((sc->sc_flags & NCR_ICCS) != 0) { 2613 /* "Initiate Command Complete Steps" in progress */ 2614 u_char msg; 2615 2616 sc->sc_flags &= ~NCR_ICCS; 2617 2618 if (!(sc->sc_espintr & NCRINTR_DONE)) { 2619 device_printf(sc->sc_dev, "ICCS: " 2620 ": [intr %x, stat %x, step %x]\n", 2621 sc->sc_espintr, sc->sc_espstat, 2622 sc->sc_espstep); 2623 } 2624 ncr53c9x_rdfifo(sc, NCR_RDFIFO_START); 2625 if (sc->sc_imlen < 2) 2626 device_printf(sc->sc_dev, "can't get status, " 2627 "only %d bytes\n", (int)sc->sc_imlen); 2628 ecb->stat = sc->sc_imess[sc->sc_imlen - 2]; 2629 msg = sc->sc_imess[sc->sc_imlen - 1]; 2630 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2631 if (msg == MSG_CMDCOMPLETE) { 2632 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) 2633 ? 0 : sc->sc_dleft; 2634 if ((ecb->flags & ECB_SENSE) == 0) 2635 ecb->ccb->csio.resid = ecb->dleft; 2636 sc->sc_state = NCR_CMDCOMPLETE; 2637 } else 2638 device_printf(sc->sc_dev, "STATUS_PHASE: " 2639 "msg %d\n", msg); 2640 sc->sc_imlen = 0; 2641 NCRCMD(sc, NCRCMD_MSGOK); 2642 goto shortcut; /* ie. wait for disconnect */ 2643 } 2644 break; 2645 2646 default: 2647 device_printf(sc->sc_dev, "invalid state: %d [intr %x, " 2648 "phase(c %x, p %x)]\n", sc->sc_state, 2649 sc->sc_espintr, sc->sc_phase, sc->sc_prevphase); 2650 goto reset; 2651 } 2652 2653 /* 2654 * Driver is now in state NCR_CONNECTED, i.e. we 2655 * have a current command working the SCSI bus. 2656 */ 2657 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 2658 panic("ncr53c9x: no nexus"); 2659 } 2660 2661 switch (sc->sc_phase) { 2662 case MESSAGE_OUT_PHASE: 2663 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 2664 ncr53c9x_msgout(sc); 2665 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2666 break; 2667 2668 case MESSAGE_IN_PHASE: 2669msgin: 2670 NCR_PHASE(("MESSAGE_IN_PHASE ")); 2671 if ((sc->sc_espintr & NCRINTR_BS) != 0) { 2672 if ((sc->sc_rev != NCR_VARIANT_FAS366) || 2673 !(sc->sc_espstat2 & NCRFAS_STAT2_EMPTY)) { 2674 NCRCMD(sc, NCRCMD_FLUSH); 2675 } 2676 sc->sc_flags |= NCR_WAITI; 2677 NCRCMD(sc, NCRCMD_TRANS); 2678 } else if ((sc->sc_espintr & NCRINTR_FC) != 0) { 2679 if ((sc->sc_flags & NCR_WAITI) == 0) { 2680 device_printf(sc->sc_dev, "MSGIN: unexpected " 2681 "FC bit: [intr %x, stat %x, step %x]\n", 2682 sc->sc_espintr, sc->sc_espstat, 2683 sc->sc_espstep); 2684 } 2685 sc->sc_flags &= ~NCR_WAITI; 2686 ncr53c9x_rdfifo(sc, 2687 (sc->sc_prevphase == sc->sc_phase) ? 2688 NCR_RDFIFO_CONTINUE : NCR_RDFIFO_START); 2689 ncr53c9x_msgin(sc); 2690 } else { 2691 device_printf(sc->sc_dev, "MSGIN: weird bits: " 2692 "[intr %x, stat %x, step %x]\n", 2693 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2694 } 2695 sc->sc_prevphase = MESSAGE_IN_PHASE; 2696 goto shortcut; /* i.e. expect data to be ready */ 2697 break; 2698 2699 case COMMAND_PHASE: 2700 /* 2701 * Send the command block. Normally we don't see this 2702 * phase because the SEL_ATN command takes care of 2703 * all this. However, we end up here if either the 2704 * target or we wanted to exchange some more messages 2705 * first (e.g. to start negotiations). 2706 */ 2707 2708 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2709 ecb->cmd.cmd.opcode, ecb->clen)); 2710 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2711 NCRCMD(sc, NCRCMD_FLUSH); 2712/* DELAY(1);*/ 2713 } 2714 if (sc->sc_features & NCR_F_DMASELECT) { 2715 /* setup DMA transfer for command */ 2716 size = ecb->clen; 2717 sc->sc_cmdlen = size; 2718 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2719 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2720 0, &size); 2721 /* Program the SCSI counter */ 2722 NCR_SET_COUNT(sc, size); 2723 2724 /* load the count in */ 2725 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2726 2727 /* start the command transfer */ 2728 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2729 NCRDMA_GO(sc); 2730 } else { 2731 ncr53c9x_wrfifo(sc, (u_char *)&ecb->cmd.cmd, ecb->clen); 2732 NCRCMD(sc, NCRCMD_TRANS); 2733 } 2734 sc->sc_prevphase = COMMAND_PHASE; 2735 break; 2736 2737 case DATA_OUT_PHASE: 2738 NCR_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 2739 NCRCMD(sc, NCRCMD_FLUSH); 2740 size = min(sc->sc_dleft, sc->sc_maxxfer); 2741 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size); 2742 sc->sc_prevphase = DATA_OUT_PHASE; 2743 goto setup_xfer; 2744 2745 case DATA_IN_PHASE: 2746 NCR_PHASE(("DATA_IN_PHASE ")); 2747 if (sc->sc_rev == NCR_VARIANT_ESP100) 2748 NCRCMD(sc, NCRCMD_FLUSH); 2749 size = min(sc->sc_dleft, sc->sc_maxxfer); 2750 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size); 2751 sc->sc_prevphase = DATA_IN_PHASE; 2752 setup_xfer: 2753 /* Target returned to data phase: wipe "done" memory */ 2754 ecb->flags &= ~ECB_TENTATIVE_DONE; 2755 2756 /* Program the SCSI counter */ 2757 NCR_SET_COUNT(sc, size); 2758 2759 /* load the count in */ 2760 NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA); 2761 2762 /* 2763 * Note that if `size' is 0, we've already transceived 2764 * all the bytes we want but we're still in DATA PHASE. 2765 * Apparently, the device needs padding. Also, a 2766 * transfer size of 0 means "maximum" to the chip 2767 * DMA logic. 2768 */ 2769 NCRCMD(sc, 2770 (size == 0 ? NCRCMD_TRPAD : NCRCMD_TRANS) | NCRCMD_DMA); 2771 NCRDMA_GO(sc); 2772 goto out; 2773 2774 case STATUS_PHASE: 2775 NCR_PHASE(("STATUS_PHASE ")); 2776 sc->sc_flags |= NCR_ICCS; 2777 NCRCMD(sc, NCRCMD_ICCS); 2778 sc->sc_prevphase = STATUS_PHASE; 2779 goto shortcut; /* i.e. expect status results soon */ 2780 break; 2781 2782 case INVALID_PHASE: 2783 break; 2784 2785 default: 2786 device_printf(sc->sc_dev, "unexpected bus phase; resetting\n"); 2787 goto reset; 2788 } 2789 2790out: 2791 mtx_unlock(&sc->sc_lock); 2792 return; 2793 2794reset: 2795 ncr53c9x_init(sc, 1); 2796 goto out; 2797 2798finish: 2799 ncr53c9x_done(sc, ecb); 2800 goto out; 2801 2802sched: 2803 sc->sc_state = NCR_IDLE; 2804 ncr53c9x_sched(sc); 2805 goto out; 2806 2807shortcut: 2808 /* 2809 * The idea is that many of the SCSI operations take very little 2810 * time, and going away and getting interrupted is too high an 2811 * overhead to pay. For example, selecting, sending a message 2812 * and command and then doing some work can be done in one "pass". 2813 * 2814 * The delay is a heuristic. It is 2 when at 20MHz, 2 at 25MHz and 1 2815 * at 40MHz. This needs testing. 2816 */ 2817 { 2818 struct timeval wait, cur; 2819 2820 microtime(&wait); 2821 wait.tv_usec += 50 / sc->sc_freq; 2822 if (wait.tv_usec > 1000000) { 2823 wait.tv_sec++; 2824 wait.tv_usec -= 1000000; 2825 } 2826 do { 2827 if (NCRDMA_ISINTR(sc)) 2828 goto again; 2829 microtime(&cur); 2830 } while (cur.tv_sec <= wait.tv_sec && 2831 cur.tv_usec <= wait.tv_usec); 2832 } 2833 goto out; 2834} 2835 2836static void 2837ncr53c9x_abort(sc, ecb) 2838 struct ncr53c9x_softc *sc; 2839 struct ncr53c9x_ecb *ecb; 2840{ 2841 2842 /* 2 secs for the abort */ 2843 ecb->timeout = NCR_ABORT_TIMEOUT; 2844 ecb->flags |= ECB_ABORT; 2845 2846 if (ecb == sc->sc_nexus) { 2847 /* 2848 * If we're still selecting, the message will be scheduled 2849 * after selection is complete. 2850 */ 2851 if (sc->sc_state == NCR_CONNECTED) 2852 ncr53c9x_sched_msgout(SEND_ABORT); 2853 2854 /* 2855 * Reschedule timeout. 2856 */ 2857 ecb->ccb->ccb_h.timeout_ch = 2858 timeout(ncr53c9x_timeout, ecb, mstohz(ecb->timeout)); 2859 } else { 2860 /* 2861 * Just leave the command where it is. 2862 * XXX - what choice do we have but to reset the SCSI 2863 * eventually? 2864 */ 2865 if (sc->sc_state == NCR_IDLE) 2866 ncr53c9x_sched(sc); 2867 } 2868} 2869 2870static void 2871ncr53c9x_timeout(void *arg) 2872{ 2873 struct ncr53c9x_ecb *ecb = arg; 2874 union ccb *ccb = ecb->ccb; 2875 struct ncr53c9x_softc *sc = ecb->sc; 2876 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 2877 2878 xpt_print_path(ccb->ccb_h.path); 2879 device_printf(sc->sc_dev, "timed out [ecb %p (flags 0x%x, dleft %x, " 2880 "stat %x)], <state %d, nexus %p, phase(l %x, c %x, p %x), " 2881 "resid %lx, msg(q %x,o %x) %s>", 2882 ecb, ecb->flags, ecb->dleft, ecb->stat, 2883 sc->sc_state, sc->sc_nexus, 2884 NCR_READ_REG(sc, NCR_STAT), 2885 sc->sc_phase, sc->sc_prevphase, 2886 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2887 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2888#if NCR53C9X_DEBUG > 1 2889 printf("TRACE: %s.", ecb->trace); 2890#endif 2891 2892 mtx_lock(&sc->sc_lock); 2893 2894 if (ecb->flags & ECB_ABORT) { 2895 /* abort timed out */ 2896 printf(" AGAIN\n"); 2897 2898 ncr53c9x_init(sc, 1); 2899 } else { 2900 /* abort the operation that has timed out */ 2901 printf("\n"); 2902 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 2903 ncr53c9x_abort(sc, ecb); 2904 2905 /* Disable sync mode if stuck in a data phase */ 2906 if (ecb == sc->sc_nexus && 2907 (ti->flags & T_SYNCMODE) != 0 && 2908 (sc->sc_phase & (MSGI|CDI)) == 0) { 2909 /* XXX ASYNC CALLBACK! */ 2910 xpt_print_path(ccb->ccb_h.path); 2911 printf("sync negotiation disabled\n"); 2912 sc->sc_cfflags |= 2913 (1 << ((ccb->ccb_h.target_id & 7) + 8)); 2914 } 2915 } 2916 2917 mtx_unlock(&sc->sc_lock); 2918} 2919 2920static void 2921ncr53c9x_watch(void *arg) 2922{ 2923 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 2924 struct ncr53c9x_tinfo *ti; 2925 struct ncr53c9x_linfo *li; 2926 int t; 2927 /* Delete any structures that have not been used in 10min. */ 2928 time_t old = time_second - (10 * 60); 2929 2930 mtx_lock(&sc->sc_lock); 2931 for (t = 0; t < sc->sc_ntarg; t++) { 2932 ti = &sc->sc_tinfo[t]; 2933 li = LIST_FIRST(&ti->luns); 2934 while (li) { 2935 if (li->last_used < old && 2936 li->untagged == NULL && 2937 li->used == 0) { 2938 if (li->lun < NCR_NLUN) 2939 ti->lun[li->lun] = NULL; 2940 LIST_REMOVE(li, link); 2941 free(li, M_DEVBUF); 2942 /* Restart the search at the beginning */ 2943 li = LIST_FIRST(&ti->luns); 2944 continue; 2945 } 2946 li = LIST_NEXT(li, link); 2947 } 2948 } 2949 mtx_unlock(&sc->sc_lock); 2950 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc); 2951} 2952 2953