if_edvar.h revision 142202
1178354Ssam/*-
2186904Ssam * Copyright (c) 1995, David Greenman
3178354Ssam * All rights reserved.
4178354Ssam *
5178354Ssam * Redistribution and use in source and binary forms, with or without
6178354Ssam * modification, are permitted provided that the following conditions
7178354Ssam * are met:
8178354Ssam * 1. Redistributions of source code must retain the above copyright
9178354Ssam *    notice unmodified, this list of conditions, and the following
10178354Ssam *    disclaimer.
11178354Ssam * 2. Redistributions in binary form must reproduce the above copyright
12178354Ssam *    notice, this list of conditions and the following disclaimer in the
13178354Ssam *    documentation and/or other materials provided with the distribution.
14178354Ssam *
15178354Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16178354Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17178354Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18178354Ssam * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19178354Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20178354Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21178354Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22178354Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23178354Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24178354Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25178354Ssam * SUCH DAMAGE.
26178354Ssam *
27178354Ssam * $FreeBSD: head/sys/dev/ed/if_edvar.h 142202 2005-02-22 05:12:25Z imp $
28178354Ssam */
29178354Ssam
30189106Sbz#ifndef SYS_DEV_ED_IF_EDVAR_H
31178354Ssam#define SYS_DEV_ED_IF_EDVAR_H
32178354Ssam/*
33178354Ssam * ed_softc: per line info and status
34178354Ssam */
35178354Ssamstruct ed_softc {
36178354Ssam	struct arpcom arpcom;	/* ethernet common */
37178354Ssam
38178354Ssam	char   *type_str;	/* pointer to type string */
39178354Ssam	u_char  vendor;		/* interface vendor */
40178354Ssam	u_char  type;		/* interface type code */
41182144Sjulian	u_char	chip_type;	/* the type of chip (one of ED_CHIP_TYPE_*) */
42178354Ssam	u_char	gone;		/* HW missing, presumed having a good time */
43178354Ssam	u_char  isa16bit;	/* width of access to card 0=8 or 1=16 */
44178354Ssam	u_char  mem_shared;	/* NIC memory is shared with host */
45178354Ssam	u_char  xmit_busy;	/* transmitter is busy */
46178354Ssam
47178354Ssam	int	port_rid;	/* resource id for port range */
48189106Sbz	int	port_used;	/* nonzero if ports used */
49185571Sbz	struct resource* port_res; /* resource for port range */
50178354Ssam	bus_space_tag_t port_bst;
51178354Ssam	bus_space_handle_t port_bsh;
52191551Ssam	int	mem_rid;	/* resource id for memory range */
53191551Ssam	int	mem_used;	/* nonzero if memory used */
54191551Ssam	struct resource* mem_res; /* resource for memory range */
55178354Ssam	bus_space_tag_t mem_bst;
56178354Ssam	bus_space_handle_t mem_bsh;
57183355Sthompsa	int	irq_rid;	/* resource id for irq */
58178354Ssam	struct resource* irq_res; /* resource for irq */
59191551Ssam	void*	irq_handle;	/* handle for irq handler */
60191551Ssam	device_t miibus;	/* MII bus for cards with MII. */
61183355Sthompsa	void	(*mii_writebits)(struct ed_softc *, u_int, int);
62191551Ssam	u_int	(*mii_readbits)(struct ed_softc *, int);
63191551Ssam	struct callout_handle tick_ch; /* Callout handle for ed_tick */
64183355Sthompsa
65178354Ssam	int	nic_offset;	/* NIC (DS8390) I/O bus address offset */
66178354Ssam	int	asic_offset;	/* ASIC I/O bus address offset */
67178354Ssam
68178354Ssam/*
69178354Ssam * The following 'proto' variable is part of a work-around for 8013EBT asics
70188182Ssam *	being write-only. It's sort of a prototype/shadow of the real thing.
71188182Ssam */
72178354Ssam	u_char  wd_laar_proto;
73178354Ssam	u_char	cr_proto;
74178354Ssam
75178354Ssam/*
76178354Ssam * HP PC LAN PLUS card support.
77178354Ssam */
78178354Ssam
79178354Ssam	u_short	hpp_options;	/* flags controlling behaviour of the HP card */
80178354Ssam	u_short hpp_id;		/* software revision and other fields */
81178354Ssam	caddr_t hpp_mem_start;	/* Memory-mapped IO register address */
82178354Ssam
83178354Ssam	caddr_t mem_start;	/* NIC memory start address */
84178354Ssam	caddr_t mem_end;		/* NIC memory end address */
85178354Ssam	uint32_t mem_size;	/* total NIC memory size */
86178354Ssam	caddr_t mem_ring;	/* start of RX ring-buffer (in NIC mem) */
87178354Ssam
88178354Ssam	u_char  txb_cnt;	/* number of transmit buffers */
89178354Ssam	u_char  txb_inuse;	/* number of TX buffers currently in-use */
90178354Ssam
91188182Ssam	u_char  txb_new;	/* pointer to where new buffer will be added */
92188182Ssam	u_char  txb_next_tx;	/* pointer to next buffer ready to xmit */
93188182Ssam	u_short txb_len[8];	/* buffered xmit buffer lengths */
94188182Ssam	u_char  tx_page_start;	/* first page of TX buffer area */
95188182Ssam	u_char  rec_page_start;	/* first page of RX ring-buffer */
96188182Ssam	u_char  rec_page_stop;	/* last page of RX ring-buffer */
97188182Ssam	u_char  next_packet;	/* pointer to next unread RX packet */
98188182Ssam	struct	ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
99188182Ssam};
100178354Ssam
101178354Ssam#define	ed_nic_inb(sc, port) \
102178354Ssam	bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
103178354Ssam
104178354Ssam#define	ed_nic_outb(sc, port, value) \
105178354Ssam	bus_space_write_1(sc->port_bst, sc->port_bsh, \
106178354Ssam	    (sc)->nic_offset + (port), (value))
107178354Ssam
108178354Ssam#define	ed_nic_inw(sc, port) \
109178354Ssam	bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
110178354Ssam
111178354Ssam#define	ed_nic_outw(sc, port, value) \
112178354Ssam	bus_space_write_2(sc->port_bst, sc->port_bsh, \
113178354Ssam	    (sc)->nic_offset + (port), (value))
114178354Ssam
115178354Ssam#define	ed_nic_insb(sc, port, addr, count) \
116178354Ssam	bus_space_read_multi_1(sc->port_bst,  sc->port_bsh, \
117178354Ssam		(sc)->nic_offset + (port), (addr), (count))
118178354Ssam
119178354Ssam#define	ed_nic_outsb(sc, port, addr, count) \
120178354Ssam	bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
121178354Ssam		(sc)->nic_offset + (port), (addr), (count))
122178354Ssam
123178354Ssam#define	ed_nic_insw(sc, port, addr, count) \
124178354Ssam	bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
125178354Ssam		(sc)->nic_offset + (port), (uint16_t *)(addr), (count))
126178354Ssam
127178354Ssam#define	ed_nic_outsw(sc, port, addr, count) \
128178354Ssam	bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
129178354Ssam		(sc)->nic_offset + (port), (uint16_t *)(addr), (count))
130178354Ssam
131178354Ssam#define	ed_nic_insl(sc, port, addr, count) \
132178354Ssam	bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
133178354Ssam		(sc)->nic_offset + (port), (uint32_t *)(addr), (count))
134178354Ssam
135178354Ssam#define	ed_nic_outsl(sc, port, addr, count) \
136178354Ssam	bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
137178354Ssam		(sc)->nic_offset + (port), (uint32_t *)(addr), (count))
138178354Ssam
139178354Ssam#define	ed_asic_inb(sc, port) \
140178354Ssam	bus_space_read_1(sc->port_bst, sc->port_bsh, \
141178354Ssam	    (sc)->asic_offset + (port))
142178354Ssam
143178354Ssam#define	ed_asic_outb(sc, port, value) \
144178354Ssam	bus_space_write_1(sc->port_bst, sc->port_bsh, \
145178354Ssam	    (sc)->asic_offset + (port), (value))
146178354Ssam
147178354Ssam#define	ed_asic_inw(sc, port) \
148178354Ssam	bus_space_read_2(sc->port_bst, sc->port_bsh, \
149178354Ssam	    (sc)->asic_offset + (port))
150178354Ssam
151183550Szec#define	ed_asic_outw(sc, port, value) \
152178354Ssam	bus_space_write_2(sc->port_bst, sc->port_bsh, \
153178354Ssam	    (sc)->asic_offset + (port), (value))
154178354Ssam
155178354Ssam#define	ed_asic_insb(sc, port, addr, count) \
156178354Ssam	bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
157178354Ssam		(sc)->asic_offset + (port), (addr), (count))
158178354Ssam
159178354Ssam#define	ed_asic_outsb(sc, port, addr, count) \
160178354Ssam	bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
161178354Ssam		(sc)->asic_offset + (port), (addr), (count))
162183550Szec
163183550Szec#define	ed_asic_insw(sc, port, addr, count) \
164183550Szec	bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
165183550Szec		(sc)->asic_offset + (port), (uint16_t *)(addr), (count))
166183550Szec
167178354Ssam#define	ed_asic_outsw(sc, port, addr, count) \
168183550Szec	bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
169183550Szec		(sc)->asic_offset + (port), (uint16_t *)(addr), (count))
170183550Szec
171183550Szec#define	ed_asic_insl(sc, port, addr, count) \
172183550Szec	bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
173183550Szec		(sc)->asic_offset + (port), (uint32_t *)(addr), (count))
174183550Szec
175183550Szec#define	ed_asic_outsl(sc, port, addr, count) \
176183550Szec	bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
177183550Szec		(sc)->asic_offset + (port), (uint32_t *)(addr), (count))
178183550Szec
179183550Szecvoid	ed_release_resources(device_t);
180183550Szecint	ed_alloc_port(device_t, int, int);
181178354Ssamint	ed_alloc_memory(device_t, int, int);
182178354Ssamint	ed_alloc_irq(device_t, int, int);
183178354Ssam
184178354Ssamint	ed_probe_generic8390(struct ed_softc *);
185178354Ssamint	ed_probe_WD80x3(device_t, int, int);
186191551Ssamint	ed_probe_WD80x3_generic(device_t, int, uint16_t *[]);
187191551Ssam#ifdef ED_3C503
188191551Ssamint	ed_probe_3Com(device_t, int, int);
189191551Ssam#endif
190191551Ssam#ifdef ED_SIC
191191551Ssamint	ed_probe_SIC(device_t, int, int);
192191551Ssam#endif
193191551Ssamint	ed_probe_Novell(device_t, int, int);
194191551Ssamvoid	ed_Novell_read_mac(struct ed_softc *);
195191551Ssam#ifdef ED_HPP
196178354Ssamint	ed_probe_HP_pclanp(device_t, int, int);
197178354Ssam#endif
198178354Ssam
199178354Ssamint	ed_attach(device_t);
200178354Ssamint	ed_detach(device_t);
201191551Ssamint	ed_clear_memory(device_t);
202191551Ssamint	ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */
203178354Ssamvoid	ed_stop(struct ed_softc *);
204178354Ssamvoid	ed_pio_readmem(struct ed_softc *, long, uint8_t *, uint16_t);
205178354Ssamvoid	ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t);
206178354Ssam#ifndef ED_NO_MIIBUS
207178354Ssamint	ed_miibus_readreg(device_t, int, int);
208191551Ssamvoid	ed_miibus_writereg(device_t, int, int, int);
209191551Ssamint	ed_ifmedia_upd(struct ifnet *);
210191551Ssamvoid	ed_ifmedia_sts(struct ifnet *, struct ifmediareq *);
211191551Ssamvoid	ed_child_detached(device_t, device_t);
212191551Ssam#endif
213191551Ssam
214191551Ssam/* The following is unsatisfying XXX */
215178354Ssam#ifdef ED_HPP
216178354Ssamvoid	ed_hpp_set_physical_link(struct ed_softc *);
217178354Ssamvoid	ed_hpp_readmem(struct ed_softc *, long, uint8_t *, uint16_t);
218178354Ssamu_short	ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int);
219178354Ssam#endif
220178354Ssam
221178354Ssamvoid	ed_disable_16bit_access(struct ed_softc *);
222178354Ssamvoid	ed_enable_16bit_access(struct ed_softc *);
223178354Ssam
224178354Ssamdriver_intr_t	edintr;
225178354Ssam
226178354Ssamextern devclass_t ed_devclass;
227178354Ssam
228178354Ssam
229178354Ssam/*
230178354Ssam * Vendor types
231178354Ssam */
232178354Ssam#define ED_VENDOR_WD_SMC	0x00		/* Western Digital/SMC */
233178354Ssam#define ED_VENDOR_3COM		0x01		/* 3Com */
234178354Ssam#define ED_VENDOR_NOVELL	0x02		/* Novell */
235178354Ssam#define ED_VENDOR_HP		0x03		/* Hewlett Packard */
236178354Ssam#define ED_VENDOR_SIC		0x04		/* Allied-Telesis SIC */
237178354Ssam
238178354Ssam/*
239178354Ssam * Compile-time config flags
240178354Ssam */
241178354Ssam/*
242178354Ssam * this sets the default for enabling/disabling the transceiver
243178354Ssam */
244178354Ssam#define ED_FLAGS_DISABLE_TRANCEIVER	0x0001
245178354Ssam
246178354Ssam/*
247178354Ssam * This forces the board to be used in 8/16bit mode even if it
248188170Ssam *	autoconfigs differently
249178354Ssam */
250178354Ssam#define ED_FLAGS_FORCE_8BIT_MODE	0x0002
251178354Ssam#define ED_FLAGS_FORCE_16BIT_MODE	0x0004
252178354Ssam
253178354Ssam/*
254178354Ssam * This disables the use of double transmit buffers.
255178354Ssam */
256178354Ssam#define ED_FLAGS_NO_MULTI_BUFFERING	0x0008
257178354Ssam
258178354Ssam/*
259178354Ssam * This forces all operations with the NIC memory to use Programmed
260178354Ssam *	I/O (i.e. not via shared memory)
261178354Ssam */
262178354Ssam#define ED_FLAGS_FORCE_PIO		0x0010
263178354Ssam
264178354Ssam/*
265178354Ssam * These are flags describing the chip type.
266182821Ssam */
267182821Ssam#define ED_FLAGS_TOSH_ETHER		0x10000
268178354Ssam#define ED_FLAGS_GWETHER		0x20000
269178354Ssam#define ED_FLAGS_AX88190		0x30000
270178354Ssam#define ED_FLAGS_LINKSYS		0x80000
271178354Ssam
272178354Ssam#define ED_FLAGS_GETTYPE(flg)		((flg) & 0xff0000)
273178354Ssam
274191551Ssam#endif /* SYS_DEV_ED_IF_EDVAR_H */
275191551Ssam