1205869Sjfv/****************************************************************************** 2205869Sjfv 3235527Sjfv Copyright (c) 2001-2011, Intel Corporation 4205869Sjfv All rights reserved. 5205869Sjfv 6205869Sjfv Redistribution and use in source and binary forms, with or without 7205869Sjfv modification, are permitted provided that the following conditions are met: 8205869Sjfv 9205869Sjfv 1. Redistributions of source code must retain the above copyright notice, 10205869Sjfv this list of conditions and the following disclaimer. 11205869Sjfv 12205869Sjfv 2. Redistributions in binary form must reproduce the above copyright 13205869Sjfv notice, this list of conditions and the following disclaimer in the 14205869Sjfv documentation and/or other materials provided with the distribution. 15205869Sjfv 16205869Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17205869Sjfv contributors may be used to endorse or promote products derived from 18205869Sjfv this software without specific prior written permission. 19205869Sjfv 20205869Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21205869Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22205869Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23205869Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24205869Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25205869Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26205869Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27205869Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28205869Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29205869Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30205869Sjfv POSSIBILITY OF SUCH DAMAGE. 31205869Sjfv 32205869Sjfv******************************************************************************/ 33205869Sjfv/*$FreeBSD$*/ 34205869Sjfv 35205869Sjfv 36205869Sjfv#ifndef _LEM_H_DEFINED_ 37205869Sjfv#define _LEM_H_DEFINED_ 38205869Sjfv 39205869Sjfv 40205869Sjfv/* Tunables */ 41205869Sjfv 42205869Sjfv/* 43205869Sjfv * EM_TXD: Maximum number of Transmit Descriptors 44205869Sjfv * Valid Range: 80-256 for 82542 and 82543-based adapters 45205869Sjfv * 80-4096 for others 46205869Sjfv * Default Value: 256 47205869Sjfv * This value is the number of transmit descriptors allocated by the driver. 48205869Sjfv * Increasing this value allows the driver to queue more transmits. Each 49205869Sjfv * descriptor is 16 bytes. 50205869Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 51205869Sjfv * desscriptors should meet the following condition. 52205869Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53205869Sjfv */ 54205869Sjfv#define EM_MIN_TXD 80 55205869Sjfv#define EM_MAX_TXD_82543 256 56205869Sjfv#define EM_MAX_TXD 4096 57205869Sjfv#define EM_DEFAULT_TXD EM_MAX_TXD_82543 58205869Sjfv 59205869Sjfv/* 60205869Sjfv * EM_RXD - Maximum number of receive Descriptors 61205869Sjfv * Valid Range: 80-256 for 82542 and 82543-based adapters 62205869Sjfv * 80-4096 for others 63205869Sjfv * Default Value: 256 64205869Sjfv * This value is the number of receive descriptors allocated by the driver. 65205869Sjfv * Increasing this value allows the driver to buffer more incoming packets. 66205869Sjfv * Each descriptor is 16 bytes. A receive buffer is also allocated for each 67205869Sjfv * descriptor. The maximum MTU size is 16110. 68205869Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 69205869Sjfv * desscriptors should meet the following condition. 70205869Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 71205869Sjfv */ 72205869Sjfv#define EM_MIN_RXD 80 73205869Sjfv#define EM_MAX_RXD_82543 256 74205869Sjfv#define EM_MAX_RXD 4096 75205869Sjfv#define EM_DEFAULT_RXD EM_MAX_RXD_82543 76205869Sjfv 77205869Sjfv/* 78205869Sjfv * EM_TIDV - Transmit Interrupt Delay Value 79205869Sjfv * Valid Range: 0-65535 (0=off) 80205869Sjfv * Default Value: 64 81205869Sjfv * This value delays the generation of transmit interrupts in units of 82205869Sjfv * 1.024 microseconds. Transmit interrupt reduction can improve CPU 83205869Sjfv * efficiency if properly tuned for specific network traffic. If the 84205869Sjfv * system is reporting dropped transmits, this value may be set too high 85205869Sjfv * causing the driver to run out of available transmit descriptors. 86205869Sjfv */ 87205869Sjfv#define EM_TIDV 64 88205869Sjfv 89205869Sjfv/* 90205869Sjfv * EM_TADV - Transmit Absolute Interrupt Delay Value 91205869Sjfv * (Not valid for 82542/82543/82544) 92205869Sjfv * Valid Range: 0-65535 (0=off) 93205869Sjfv * Default Value: 64 94205869Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 95205869Sjfv * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 96205869Sjfv * this value ensures that an interrupt is generated after the initial 97205869Sjfv * packet is sent on the wire within the set amount of time. Proper tuning, 98205869Sjfv * along with EM_TIDV, may improve traffic throughput in specific 99205869Sjfv * network conditions. 100205869Sjfv */ 101205869Sjfv#define EM_TADV 64 102205869Sjfv 103205869Sjfv/* 104205869Sjfv * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 105205869Sjfv * Valid Range: 0-65535 (0=off) 106205869Sjfv * Default Value: 0 107205869Sjfv * This value delays the generation of receive interrupts in units of 1.024 108205869Sjfv * microseconds. Receive interrupt reduction can improve CPU efficiency if 109205869Sjfv * properly tuned for specific network traffic. Increasing this value adds 110205869Sjfv * extra latency to frame reception and can end up decreasing the throughput 111205869Sjfv * of TCP traffic. If the system is reporting dropped receives, this value 112205869Sjfv * may be set too high, causing the driver to run out of available receive 113205869Sjfv * descriptors. 114205869Sjfv * 115205869Sjfv * CAUTION: When setting EM_RDTR to a value other than 0, adapters 116205869Sjfv * may hang (stop transmitting) under certain network conditions. 117205869Sjfv * If this occurs a WATCHDOG message is logged in the system 118205869Sjfv * event log. In addition, the controller is automatically reset, 119205869Sjfv * restoring the network connection. To eliminate the potential 120205869Sjfv * for the hang ensure that EM_RDTR is set to 0. 121205869Sjfv */ 122205869Sjfv#define EM_RDTR 0 123205869Sjfv 124205869Sjfv/* 125205869Sjfv * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 126205869Sjfv * Valid Range: 0-65535 (0=off) 127205869Sjfv * Default Value: 64 128205869Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 129205869Sjfv * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 130205869Sjfv * this value ensures that an interrupt is generated after the initial 131205869Sjfv * packet is received within the set amount of time. Proper tuning, 132205869Sjfv * along with EM_RDTR, may improve traffic throughput in specific network 133205869Sjfv * conditions. 134205869Sjfv */ 135205869Sjfv#define EM_RADV 64 136205869Sjfv 137205869Sjfv/* 138205869Sjfv * This parameter controls the max duration of transmit watchdog. 139205869Sjfv */ 140205869Sjfv#define EM_WATCHDOG (10 * hz) 141205869Sjfv 142205869Sjfv/* 143205869Sjfv * This parameter controls when the driver calls the routine to reclaim 144205869Sjfv * transmit descriptors. 145205869Sjfv */ 146205869Sjfv#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 147205869Sjfv#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 148205869Sjfv 149205869Sjfv/* 150205869Sjfv * This parameter controls whether or not autonegotation is enabled. 151205869Sjfv * 0 - Disable autonegotiation 152205869Sjfv * 1 - Enable autonegotiation 153205869Sjfv */ 154205869Sjfv#define DO_AUTO_NEG 1 155205869Sjfv 156205869Sjfv/* 157205869Sjfv * This parameter control whether or not the driver will wait for 158205869Sjfv * autonegotiation to complete. 159205869Sjfv * 1 - Wait for autonegotiation to complete 160205869Sjfv * 0 - Don't wait for autonegotiation to complete 161205869Sjfv */ 162205869Sjfv#define WAIT_FOR_AUTO_NEG_DEFAULT 0 163205869Sjfv 164205869Sjfv/* Tunables -- End */ 165205869Sjfv 166205869Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 167205869Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 168205869Sjfv ADVERTISE_1000_FULL) 169205869Sjfv 170205869Sjfv#define AUTO_ALL_MODES 0 171205869Sjfv 172205869Sjfv/* PHY master/slave setting */ 173205869Sjfv#define EM_MASTER_SLAVE e1000_ms_hw_default 174205869Sjfv 175205869Sjfv/* 176205869Sjfv * Micellaneous constants 177205869Sjfv */ 178205869Sjfv#define EM_VENDOR_ID 0x8086 179205869Sjfv#define EM_FLASH 0x0014 180205869Sjfv 181205869Sjfv#define EM_JUMBO_PBA 0x00000028 182205869Sjfv#define EM_DEFAULT_PBA 0x00000030 183205869Sjfv#define EM_SMARTSPEED_DOWNSHIFT 3 184205869Sjfv#define EM_SMARTSPEED_MAX 15 185205869Sjfv#define EM_MAX_LOOP 10 186205869Sjfv 187205869Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 188205869Sjfv#define PCI_ANY_ID (~0U) 189205869Sjfv#define ETHER_ALIGN 2 190205869Sjfv#define EM_FC_PAUSE_TIME 0x0680 191205869Sjfv#define EM_EEPROM_APME 0x400; 192205869Sjfv#define EM_82544_APME 0x0004; 193205869Sjfv 194205869Sjfv/* Code compatilbility between 6 and 7 */ 195205869Sjfv#ifndef ETHER_BPF_MTAP 196205869Sjfv#define ETHER_BPF_MTAP BPF_MTAP 197205869Sjfv#endif 198205869Sjfv 199205869Sjfv/* 200205869Sjfv * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201205869Sjfv * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202205869Sjfv * also optimize cache line size effect. H/W supports up to cache line size 128. 203205869Sjfv */ 204205869Sjfv#define EM_DBA_ALIGN 128 205205869Sjfv 206205869Sjfv#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207205869Sjfv 208205869Sjfv/* PCI Config defines */ 209205869Sjfv#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 210205869Sjfv#define EM_BAR_TYPE_MASK 0x00000001 211205869Sjfv#define EM_BAR_TYPE_MMEM 0x00000000 212205869Sjfv#define EM_BAR_TYPE_IO 0x00000001 213205869Sjfv#define EM_BAR_TYPE_FLASH 0x0014 214205869Sjfv#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 215205869Sjfv#define EM_BAR_MEM_TYPE_MASK 0x00000006 216205869Sjfv#define EM_BAR_MEM_TYPE_32BIT 0x00000000 217205869Sjfv#define EM_BAR_MEM_TYPE_64BIT 0x00000004 218205869Sjfv#define EM_MSIX_BAR 3 /* On 82575 */ 219205869Sjfv 220235527Sjfv#if __FreeBSD_version < 900000 221219753Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 222219753Sjfv#endif 223219753Sjfv 224205869Sjfv/* Defines for printing debug information */ 225205869Sjfv#define DEBUG_INIT 0 226205869Sjfv#define DEBUG_IOCTL 0 227205869Sjfv#define DEBUG_HW 0 228205869Sjfv 229205869Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 230205869Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 231205869Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 232205869Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 233205869Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 234205869Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 235205869Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 236205869Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 237205869Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 238205869Sjfv 239205869Sjfv#define EM_MAX_SCATTER 64 240205869Sjfv#define EM_VFTA_SIZE 128 241205869Sjfv#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 242205869Sjfv#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 243205869Sjfv#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 244205869Sjfv#define ETH_ZLEN 60 245205869Sjfv#define ETH_ADDR_LEN 6 246205869Sjfv#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 247205869Sjfv 248205869Sjfv/* 249205869Sjfv * 82574 has a nonstandard address for EIAC 250205869Sjfv * and since its only used in MSIX, and in 251205869Sjfv * the em driver only 82574 uses MSIX we can 252205869Sjfv * solve it just using this define. 253205869Sjfv */ 254205869Sjfv#define EM_EIAC 0x000DC 255205869Sjfv 256205869Sjfv/* Used in for 82547 10Mb Half workaround */ 257205869Sjfv#define EM_PBA_BYTES_SHIFT 0xA 258205869Sjfv#define EM_TX_HEAD_ADDR_SHIFT 7 259205869Sjfv#define EM_PBA_TX_MASK 0xFFFF0000 260205869Sjfv#define EM_FIFO_HDR 0x10 261205869Sjfv#define EM_82547_PKT_THRESH 0x3e0 262205869Sjfv 263205869Sjfv/* Precision Time Sync (IEEE 1588) defines */ 264205869Sjfv#define ETHERTYPE_IEEE1588 0x88F7 265205869Sjfv#define PICOSECS_PER_TICK 20833 266205869Sjfv#define TSYNC_PORT 319 /* UDP port for the protocol */ 267205869Sjfv 268205869Sjfv/* 269205869Sjfv * Bus dma allocation structure used by 270205869Sjfv * e1000_dma_malloc and e1000_dma_free. 271205869Sjfv */ 272205869Sjfvstruct em_dma_alloc { 273205869Sjfv bus_addr_t dma_paddr; 274205869Sjfv caddr_t dma_vaddr; 275205869Sjfv bus_dma_tag_t dma_tag; 276205869Sjfv bus_dmamap_t dma_map; 277205869Sjfv bus_dma_segment_t dma_seg; 278205869Sjfv int dma_nseg; 279205869Sjfv}; 280205869Sjfv 281205869Sjfvstruct adapter; 282205869Sjfv 283205869Sjfvstruct em_int_delay_info { 284205869Sjfv struct adapter *adapter; /* Back-pointer to the adapter struct */ 285205869Sjfv int offset; /* Register offset to read/write */ 286205869Sjfv int value; /* Current value in usecs */ 287205869Sjfv}; 288205869Sjfv 289205869Sjfv/* Our adapter structure */ 290205869Sjfvstruct adapter { 291205869Sjfv struct ifnet *ifp; 292205869Sjfv#if __FreeBSD_version >= 800000 293205869Sjfv struct buf_ring *br; 294205869Sjfv#endif 295205869Sjfv struct e1000_hw hw; 296205869Sjfv 297205869Sjfv /* FreeBSD operating-system-specific structures. */ 298205869Sjfv struct e1000_osdep osdep; 299205869Sjfv struct device *dev; 300206001Smarius struct cdev *led_dev; 301205869Sjfv 302205869Sjfv struct resource *memory; 303205869Sjfv struct resource *flash; 304205869Sjfv struct resource *msix; 305205869Sjfv 306205869Sjfv struct resource *ioport; 307205869Sjfv int io_rid; 308205869Sjfv 309205869Sjfv /* 82574 may use 3 int vectors */ 310205869Sjfv struct resource *res[3]; 311205869Sjfv void *tag[3]; 312205869Sjfv int rid[3]; 313205869Sjfv 314205869Sjfv struct ifmedia media; 315205869Sjfv struct callout timer; 316205869Sjfv struct callout tx_fifo_timer; 317205869Sjfv bool watchdog_check; 318205869Sjfv int watchdog_time; 319205869Sjfv int msi; 320205869Sjfv int if_flags; 321205869Sjfv int max_frame_size; 322205869Sjfv int min_frame_size; 323205869Sjfv struct mtx core_mtx; 324205869Sjfv struct mtx tx_mtx; 325205869Sjfv struct mtx rx_mtx; 326205869Sjfv int em_insert_vlan_header; 327205869Sjfv 328205869Sjfv /* Task for FAST handling */ 329205869Sjfv struct task link_task; 330205869Sjfv struct task rxtx_task; 331205869Sjfv struct task rx_task; 332205869Sjfv struct task tx_task; 333205869Sjfv struct taskqueue *tq; /* private task queue */ 334205869Sjfv 335205869Sjfv eventhandler_tag vlan_attach; 336205869Sjfv eventhandler_tag vlan_detach; 337205869Sjfv u32 num_vlans; 338205869Sjfv 339205869Sjfv /* Management and WOL features */ 340205869Sjfv u32 wol; 341205869Sjfv bool has_manage; 342205869Sjfv bool has_amt; 343205869Sjfv 344211913Syongari /* Multicast array memory */ 345211913Syongari u8 *mta; 346214646Sjfv 347214646Sjfv /* 348214646Sjfv ** Shadow VFTA table, this is needed because 349214646Sjfv ** the real vlan filter table gets cleared during 350214646Sjfv ** a soft reset and the driver needs to be able 351214646Sjfv ** to repopulate it. 352214646Sjfv */ 353214646Sjfv u32 shadow_vfta[EM_VFTA_SIZE]; 354214646Sjfv 355214646Sjfv /* Info about the interface */ 356205869Sjfv uint8_t link_active; 357205869Sjfv uint16_t link_speed; 358205869Sjfv uint16_t link_duplex; 359205869Sjfv uint32_t smartspeed; 360214646Sjfv uint32_t fc_setting; 361214646Sjfv 362205869Sjfv struct em_int_delay_info tx_int_delay; 363205869Sjfv struct em_int_delay_info tx_abs_int_delay; 364205869Sjfv struct em_int_delay_info rx_int_delay; 365205869Sjfv struct em_int_delay_info rx_abs_int_delay; 366250458Sluigi struct em_int_delay_info tx_itr; 367205869Sjfv 368205869Sjfv /* 369205869Sjfv * Transmit definitions 370205869Sjfv * 371205869Sjfv * We have an array of num_tx_desc descriptors (handled 372205869Sjfv * by the controller) paired with an array of tx_buffers 373205869Sjfv * (at tx_buffer_area). 374205869Sjfv * The index of the next available descriptor is next_avail_tx_desc. 375205869Sjfv * The number of remaining tx_desc is num_tx_desc_avail. 376205869Sjfv */ 377205869Sjfv struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 378205869Sjfv struct e1000_tx_desc *tx_desc_base; 379205869Sjfv uint32_t next_avail_tx_desc; 380205869Sjfv uint32_t next_tx_to_clean; 381205869Sjfv volatile uint16_t num_tx_desc_avail; 382205869Sjfv uint16_t num_tx_desc; 383205869Sjfv uint16_t last_hw_offload; 384205869Sjfv uint32_t txd_cmd; 385205869Sjfv struct em_buffer *tx_buffer_area; 386205869Sjfv bus_dma_tag_t txtag; /* dma tag for tx */ 387205869Sjfv uint32_t tx_tso; /* last tx was tso */ 388205869Sjfv 389205869Sjfv /* 390205869Sjfv * Receive definitions 391205869Sjfv * 392205869Sjfv * we have an array of num_rx_desc rx_desc (handled by the 393205869Sjfv * controller), and paired with an array of rx_buffers 394205869Sjfv * (at rx_buffer_area). 395205869Sjfv * The next pair to check on receive is at offset next_rx_desc_to_check 396205869Sjfv */ 397205869Sjfv struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 398205869Sjfv struct e1000_rx_desc *rx_desc_base; 399205869Sjfv uint32_t next_rx_desc_to_check; 400205869Sjfv uint32_t rx_buffer_len; 401205869Sjfv uint16_t num_rx_desc; 402205869Sjfv int rx_process_limit; 403205869Sjfv struct em_buffer *rx_buffer_area; 404205869Sjfv bus_dma_tag_t rxtag; 405205869Sjfv bus_dmamap_t rx_sparemap; 406205869Sjfv 407205869Sjfv /* 408205869Sjfv * First/last mbuf pointers, for 409205869Sjfv * collecting multisegment RX packets. 410205869Sjfv */ 411205869Sjfv struct mbuf *fmp; 412205869Sjfv struct mbuf *lmp; 413205869Sjfv 414205869Sjfv /* Misc stats maintained by the driver */ 415205869Sjfv unsigned long dropped_pkts; 416205869Sjfv unsigned long mbuf_alloc_failed; 417205869Sjfv unsigned long mbuf_cluster_failed; 418205869Sjfv unsigned long no_tx_desc_avail1; 419205869Sjfv unsigned long no_tx_desc_avail2; 420205869Sjfv unsigned long no_tx_map_avail; 421205869Sjfv unsigned long no_tx_dma_setup; 422205869Sjfv unsigned long watchdog_events; 423205869Sjfv unsigned long rx_overruns; 424214646Sjfv unsigned long rx_irq; 425214646Sjfv unsigned long tx_irq; 426214646Sjfv unsigned long link_irq; 427205869Sjfv 428205869Sjfv /* 82547 workaround */ 429205869Sjfv uint32_t tx_fifo_size; 430205869Sjfv uint32_t tx_fifo_head; 431205869Sjfv uint32_t tx_fifo_head_addr; 432205869Sjfv uint64_t tx_fifo_reset_cnt; 433205869Sjfv uint64_t tx_fifo_wrk_cnt; 434205869Sjfv uint32_t tx_head_addr; 435205869Sjfv 436205869Sjfv /* For 82544 PCIX Workaround */ 437205869Sjfv boolean_t pcix_82544; 438205869Sjfv boolean_t in_detach; 439205869Sjfv 440205869Sjfv 441205869Sjfv struct e1000_hw_stats stats; 442205869Sjfv}; 443205869Sjfv 444205869Sjfv/* ****************************************************************************** 445205869Sjfv * vendor_info_array 446205869Sjfv * 447205869Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 448205869Sjfv * should load. 449205869Sjfv * 450205869Sjfv * ******************************************************************************/ 451205869Sjfvtypedef struct _em_vendor_info_t { 452205869Sjfv unsigned int vendor_id; 453205869Sjfv unsigned int device_id; 454205869Sjfv unsigned int subvendor_id; 455205869Sjfv unsigned int subdevice_id; 456205869Sjfv unsigned int index; 457205869Sjfv} em_vendor_info_t; 458205869Sjfv 459205869Sjfvstruct em_buffer { 460205869Sjfv int next_eop; /* Index of the desc to watch */ 461205869Sjfv struct mbuf *m_head; 462205869Sjfv bus_dmamap_t map; /* bus_dma map for packet */ 463205869Sjfv}; 464205869Sjfv 465205869Sjfv/* For 82544 PCIX Workaround */ 466205869Sjfvtypedef struct _ADDRESS_LENGTH_PAIR 467205869Sjfv{ 468205869Sjfv uint64_t address; 469205869Sjfv uint32_t length; 470205869Sjfv} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 471205869Sjfv 472205869Sjfvtypedef struct _DESCRIPTOR_PAIR 473205869Sjfv{ 474205869Sjfv ADDRESS_LENGTH_PAIR descriptor[4]; 475205869Sjfv uint32_t elements; 476205869Sjfv} DESC_ARRAY, *PDESC_ARRAY; 477205869Sjfv 478205869Sjfv#define EM_CORE_LOCK_INIT(_sc, _name) \ 479205869Sjfv mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 480205869Sjfv#define EM_TX_LOCK_INIT(_sc, _name) \ 481205869Sjfv mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 482205869Sjfv#define EM_RX_LOCK_INIT(_sc, _name) \ 483205869Sjfv mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 484205869Sjfv#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 485205869Sjfv#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 486205869Sjfv#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 487205869Sjfv#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 488205869Sjfv#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 489205869Sjfv#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 490205869Sjfv#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 491205869Sjfv#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 492205869Sjfv#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 493205869Sjfv#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 494205869Sjfv#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 495205869Sjfv#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 496205869Sjfv 497205869Sjfv#endif /* _LEM_H_DEFINED_ */ 498