if_igb.h revision 218530
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 218530 2011-02-11 01:00:26Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 256 51#define IGB_DEFAULT_TXD 1024 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Transmit Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 256 66#define IGB_DEFAULT_RXD 1024 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_WATCHDOG (10 * hz) 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 138#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 139 140/* 141 * This parameter controls whether or not autonegotation is enabled. 142 * 0 - Disable autonegotiation 143 * 1 - Enable autonegotiation 144 */ 145#define DO_AUTO_NEG 1 146 147/* 148 * This parameter control whether or not the driver will wait for 149 * autonegotiation to complete. 150 * 1 - Wait for autonegotiation to complete 151 * 0 - Don't wait for autonegotiation to complete 152 */ 153#define WAIT_FOR_AUTO_NEG_DEFAULT 0 154 155/* Tunables -- End */ 156 157#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 159 ADVERTISE_1000_FULL) 160 161#define AUTO_ALL_MODES 0 162 163/* PHY master/slave setting */ 164#define IGB_MASTER_SLAVE e1000_ms_hw_default 165 166/* 167 * Micellaneous constants 168 */ 169#define IGB_VENDOR_ID 0x8086 170 171#define IGB_JUMBO_PBA 0x00000028 172#define IGB_DEFAULT_PBA 0x00000030 173#define IGB_SMARTSPEED_DOWNSHIFT 3 174#define IGB_SMARTSPEED_MAX 15 175#define IGB_MAX_LOOP 10 176 177#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 178#define IGB_RX_HTHRESH 8 179#define IGB_RX_WTHRESH 1 180 181#define IGB_TX_PTHRESH 8 182#define IGB_TX_HTHRESH 1 183#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 184 adapter->msix_mem) ? 1 : 16) 185 186#define MAX_NUM_MULTICAST_ADDRESSES 128 187#define PCI_ANY_ID (~0U) 188#define ETHER_ALIGN 2 189#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 190#define IGB_FC_PAUSE_TIME 0x0680 191#define IGB_EEPROM_APME 0x400; 192#define IGB_QUEUE_IDLE 0 193#define IGB_QUEUE_WORKING 1 194#define IGB_QUEUE_HUNG 2 195 196/* 197 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 198 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 199 * also optimize cache line size effect. H/W supports up to cache line size 128. 200 */ 201#define IGB_DBA_ALIGN 128 202 203#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 204 205/* PCI Config defines */ 206#define IGB_MSIX_BAR 3 207 208/* Defines for printing debug information */ 209#define DEBUG_INIT 0 210#define DEBUG_IOCTL 0 211#define DEBUG_HW 0 212 213#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 214#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 215#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 216#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 217#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 218#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 219#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 220#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 221#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 222 223#define IGB_MAX_SCATTER 64 224#define IGB_VFTA_SIZE 128 225#define IGB_BR_SIZE 4096 /* ring buf size */ 226#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 227#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 228#define IGB_HDR_BUF 128 229#define IGB_PKTTYPE_MASK 0x0000FFF0 230#define ETH_ZLEN 60 231#define ETH_ADDR_LEN 6 232 233/* Offload bits in mbuf flag */ 234#if __FreeBSD_version >= 800000 235#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 236#else 237#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 238#endif 239 240/* Define the starting Interrupt rate per Queue */ 241#define IGB_INTS_PER_SEC 8000 242#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 243 244#define IGB_LINK_ITR 2000 245 246/* Precision Time Sync (IEEE 1588) defines */ 247#define ETHERTYPE_IEEE1588 0x88F7 248#define PICOSECS_PER_TICK 20833 249#define TSYNC_PORT 319 /* UDP port for the protocol */ 250 251/* 252 * Bus dma allocation structure used by 253 * e1000_dma_malloc and e1000_dma_free. 254 */ 255struct igb_dma_alloc { 256 bus_addr_t dma_paddr; 257 caddr_t dma_vaddr; 258 bus_dma_tag_t dma_tag; 259 bus_dmamap_t dma_map; 260 bus_dma_segment_t dma_seg; 261 int dma_nseg; 262}; 263 264 265/* 266** Driver queue struct: this is the interrupt container 267** for the associated tx and rx ring. 268*/ 269struct igb_queue { 270 struct adapter *adapter; 271 u32 msix; /* This queue's MSIX vector */ 272 u32 eims; /* This queue's EIMS bit */ 273 u32 eitr_setting; 274 struct resource *res; 275 void *tag; 276 struct tx_ring *txr; 277 struct rx_ring *rxr; 278 struct task que_task; 279 struct taskqueue *tq; 280 u64 irqs; 281}; 282 283/* 284 * Transmit ring: one per queue 285 */ 286struct tx_ring { 287 struct adapter *adapter; 288 u32 me; 289 struct mtx tx_mtx; 290 char mtx_name[16]; 291 struct igb_dma_alloc txdma; 292 struct e1000_tx_desc *tx_base; 293 u32 next_avail_desc; 294 u32 next_to_clean; 295 volatile u16 tx_avail; 296 struct igb_tx_buffer *tx_buffers; 297#if __FreeBSD_version >= 800000 298 struct buf_ring *br; 299#endif 300 bus_dma_tag_t txtag; 301 302 u32 bytes; 303 u32 packets; 304 305 int queue_status; 306 int watchdog_time; 307 int tdt; 308 int tdh; 309 u64 no_desc_avail; 310 u64 tx_packets; 311}; 312 313/* 314 * Receive ring: one per queue 315 */ 316struct rx_ring { 317 struct adapter *adapter; 318 u32 me; 319 struct igb_dma_alloc rxdma; 320 union e1000_adv_rx_desc *rx_base; 321 struct lro_ctrl lro; 322 bool lro_enabled; 323 bool hdr_split; 324 bool discard; 325 bool needs_refresh; 326 struct mtx rx_mtx; 327 char mtx_name[16]; 328 u32 next_to_refresh; 329 u32 next_to_check; 330 struct igb_rx_buf *rx_buffers; 331 bus_dma_tag_t htag; /* dma tag for rx head */ 332 bus_dma_tag_t ptag; /* dma tag for rx packet */ 333 /* 334 * First/last mbuf pointers, for 335 * collecting multisegment RX packets. 336 */ 337 struct mbuf *fmp; 338 struct mbuf *lmp; 339 340 u32 bytes; 341 u32 packets; 342 int rdt; 343 int rdh; 344 345 /* Soft stats */ 346 u64 rx_split_packets; 347 u64 rx_discarded; 348 u64 rx_packets; 349 u64 rx_bytes; 350}; 351 352struct adapter { 353 struct ifnet *ifp; 354 struct e1000_hw hw; 355 356 struct e1000_osdep osdep; 357 struct device *dev; 358 struct cdev *led_dev; 359 360 struct resource *pci_mem; 361 struct resource *msix_mem; 362 struct resource *res; 363 void *tag; 364 u32 que_mask; 365 366 int linkvec; 367 int link_mask; 368 struct task link_task; 369 int link_irq; 370 371 struct ifmedia media; 372 struct callout timer; 373 int msix; /* total vectors allocated */ 374 int if_flags; 375 int max_frame_size; 376 int min_frame_size; 377 int pause_frames; 378 struct mtx core_mtx; 379 int igb_insert_vlan_header; 380 u16 num_queues; 381 u16 vf_ifp; /* a VF interface */ 382 383 eventhandler_tag vlan_attach; 384 eventhandler_tag vlan_detach; 385 u32 num_vlans; 386 387 /* Management and WOL features */ 388 int wol; 389 int has_manage; 390 391 /* 392 ** Shadow VFTA table, this is needed because 393 ** the real vlan filter table gets cleared during 394 ** a soft reset and the driver needs to be able 395 ** to repopulate it. 396 */ 397 u32 shadow_vfta[IGB_VFTA_SIZE]; 398 399 /* Info about the interface */ 400 u8 link_active; 401 u16 link_speed; 402 u16 link_duplex; 403 u32 smartspeed; 404 405 /* Interface queues */ 406 struct igb_queue *queues; 407 408 /* 409 * Transmit rings 410 */ 411 struct tx_ring *tx_rings; 412 u16 num_tx_desc; 413 414 /* Multicast array pointer */ 415 u8 *mta; 416 417 /* 418 * Receive rings 419 */ 420 struct rx_ring *rx_rings; 421 bool rx_hdr_split; 422 u16 num_rx_desc; 423 int rx_process_limit; 424 u32 rx_mbuf_sz; 425 u32 rx_mask; 426 427 /* Misc stats maintained by the driver */ 428 unsigned long dropped_pkts; 429 unsigned long mbuf_defrag_failed; 430 unsigned long mbuf_header_failed; 431 unsigned long mbuf_packet_failed; 432 unsigned long no_tx_map_avail; 433 unsigned long no_tx_dma_setup; 434 unsigned long watchdog_events; 435 unsigned long rx_overruns; 436 unsigned long device_control; 437 unsigned long rx_control; 438 unsigned long int_mask; 439 unsigned long eint_mask; 440 unsigned long packet_buf_alloc_rx; 441 unsigned long packet_buf_alloc_tx; 442 443 boolean_t in_detach; 444 445#ifdef IGB_IEEE1588 446 /* IEEE 1588 precision time support */ 447 struct cyclecounter cycles; 448 struct nettimer clock; 449 struct nettime_compare compare; 450 struct hwtstamp_ctrl hwtstamp; 451#endif 452 453 void *stats; 454}; 455 456/* ****************************************************************************** 457 * vendor_info_array 458 * 459 * This array contains the list of Subvendor/Subdevice IDs on which the driver 460 * should load. 461 * 462 * ******************************************************************************/ 463typedef struct _igb_vendor_info_t { 464 unsigned int vendor_id; 465 unsigned int device_id; 466 unsigned int subvendor_id; 467 unsigned int subdevice_id; 468 unsigned int index; 469} igb_vendor_info_t; 470 471 472struct igb_tx_buffer { 473 int next_eop; /* Index of the desc to watch */ 474 struct mbuf *m_head; 475 bus_dmamap_t map; /* bus_dma map for packet */ 476}; 477 478struct igb_rx_buf { 479 struct mbuf *m_head; 480 struct mbuf *m_pack; 481 bus_dmamap_t hmap; /* bus_dma map for header */ 482 bus_dmamap_t pmap; /* bus_dma map for packet */ 483}; 484 485#define IGB_CORE_LOCK_INIT(_sc, _name) \ 486 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 487#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 488#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 489#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 490#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 491 492#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 493#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 494#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 495#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 496#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 497 498#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 499#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 500#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 501#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 502 503#define UPDATE_VF_REG(reg, last, cur) \ 504{ \ 505 u32 new = E1000_READ_REG(hw, reg); \ 506 if (new < last) \ 507 cur += 0x100000000LL; \ 508 last = new; \ 509 cur &= 0xFFFFFFFF00000000LL; \ 510 cur |= new; \ 511} 512 513#if __FreeBSD_version < 800504 514static __inline int 515drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 516{ 517#ifdef ALTQ 518 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 519 return (1); 520#endif 521 return (!buf_ring_empty(br)); 522} 523#endif 524 525#endif /* _IGB_H_DEFINED_ */ 526 527 528