if_igb.h revision 190872
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 190872 2009-04-10 00:05:46Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 80 51#define IGB_DEFAULT_TXD 256 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Transmit Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 80 66#define IGB_DEFAULT_RXD 256 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_TX_TIMEOUT 5 /* set to 5 seconds */ 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 138#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 139 140/* 141 * This parameter controls whether or not autonegotation is enabled. 142 * 0 - Disable autonegotiation 143 * 1 - Enable autonegotiation 144 */ 145#define DO_AUTO_NEG 1 146 147/* 148 * This parameter control whether or not the driver will wait for 149 * autonegotiation to complete. 150 * 1 - Wait for autonegotiation to complete 151 * 0 - Don't wait for autonegotiation to complete 152 */ 153#define WAIT_FOR_AUTO_NEG_DEFAULT 0 154 155/* Tunables -- End */ 156 157#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 159 ADVERTISE_1000_FULL) 160 161#define AUTO_ALL_MODES 0 162 163/* PHY master/slave setting */ 164#define IGB_MASTER_SLAVE e1000_ms_hw_default 165 166/* 167 * Micellaneous constants 168 */ 169#define IGB_VENDOR_ID 0x8086 170 171#define IGB_JUMBO_PBA 0x00000028 172#define IGB_DEFAULT_PBA 0x00000030 173#define IGB_SMARTSPEED_DOWNSHIFT 3 174#define IGB_SMARTSPEED_MAX 15 175#define IGB_MAX_LOOP 10 176#define IGB_RX_PTHRESH 16 177#define IGB_RX_HTHRESH 8 178#define IGB_RX_WTHRESH 1 179 180#define MAX_NUM_MULTICAST_ADDRESSES 128 181#define PCI_ANY_ID (~0U) 182#define ETHER_ALIGN 2 183#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 184#define IGB_FC_PAUSE_TIME 0x0680 185#define IGB_EEPROM_APME 0x400; 186 187/* Code compatilbility between 6 and 7 */ 188#ifndef ETHER_BPF_MTAP 189#define ETHER_BPF_MTAP BPF_MTAP 190#endif 191 192#if __FreeBSD_version < 700000 193#define CSUM_TSO 0 194#define IFCAP_TSO4 0 195#define FILTER_STRAY 196#define FILTER_HANDLED 197#endif 198 199/* 200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202 * also optimize cache line size effect. H/W supports up to cache line size 128. 203 */ 204#define IGB_DBA_ALIGN 128 205 206#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207 208/* PCI Config defines */ 209#define IGB_MSIX_BAR 3 210 211/* 212** This is the total number of MSIX vectors you wish 213** to use, it also controls the size of resources. 214** The 82575 has a total of 10, 82576 has 25. Set this 215** to the real amount you need to streamline data storage. 216*/ 217#define IGB_MSIX_VEC 6 /* MSIX vectors configured */ 218 219/* Defines for printing debug information */ 220#define DEBUG_INIT 0 221#define DEBUG_IOCTL 0 222#define DEBUG_HW 0 223 224#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 225#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 226#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 227#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 228#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 229#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 230#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 231#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 232#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 233 234#define IGB_MAX_SCATTER 64 235#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 236#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 237#define IGB_HDR_BUF 128 238#define ETH_ZLEN 60 239#define ETH_ADDR_LEN 6 240 241/* Offload bits in mbuf flag */ 242#if __FreeBSD_version >= 800000 243#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 244#else 245#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 246#endif 247 248/* Header split codes for get_buf */ 249#define IGB_CLEAN_HEADER 1 250#define IGB_CLEAN_PAYLOAD 2 251#define IGB_CLEAN_BOTH 3 252 253/* 254 * Interrupt Moderation parameters 255 */ 256#define IGB_LOW_LATENCY 128 257#define IGB_AVE_LATENCY 450 258#define IGB_BULK_LATENCY 1200 259#define IGB_LINK_ITR 2000 260 261#ifdef IGB_TIMESYNC 262/* Precision Time Sync (IEEE 1588) defines */ 263#define ETHERTYPE_IEEE1588 0x88F7 264#define PICOSECS_PER_TICK 20833 265#define TSYNC_PORT 319 /* UDP port for the protocol */ 266 267/* TIMESYNC IOCTL defines */ 268#define IGB_TIMESYNC_READTS _IOWR('i', 127, struct igb_tsync_read) 269#define IGB_TIMESTAMP 5 /* A unique return value */ 270 271/* Used in the READTS IOCTL */ 272struct igb_tsync_read { 273 int read_current_time; 274 struct timespec system_time; 275 u64 network_time; 276 u64 rx_stamp; 277 u64 tx_stamp; 278 u16 seqid; 279 unsigned char srcid[6]; 280 int rx_valid; 281 int tx_valid; 282}; 283 284#endif /* IGB_TIMESYNC */ 285 286struct adapter; /* forward reference */ 287 288struct igb_int_delay_info { 289 struct adapter *adapter; /* Back-pointer to the adapter struct */ 290 int offset; /* Register offset to read/write */ 291 int value; /* Current value in usecs */ 292}; 293 294/* 295 * Bus dma allocation structure used by 296 * e1000_dma_malloc and e1000_dma_free. 297 */ 298struct igb_dma_alloc { 299 bus_addr_t dma_paddr; 300 caddr_t dma_vaddr; 301 bus_dma_tag_t dma_tag; 302 bus_dmamap_t dma_map; 303 bus_dma_segment_t dma_seg; 304 int dma_nseg; 305}; 306 307 308/* 309 * Transmit ring: one per tx queue 310 */ 311struct tx_ring { 312 struct adapter *adapter; 313 u32 me; 314 u32 msix; /* This ring's MSIX vector */ 315 u32 eims; /* This ring's EIMS bit */ 316 struct mtx tx_mtx; 317 char mtx_name[16]; 318 struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */ 319 struct e1000_tx_desc *tx_base; 320 struct task tx_task; /* cleanup tasklet */ 321 u32 next_avail_desc; 322 u32 next_to_clean; 323 volatile u16 tx_avail; 324 struct igb_tx_buffer *tx_buffers; 325 bus_dma_tag_t txtag; /* dma tag for tx */ 326 u32 watchdog_timer; 327 u64 no_desc_avail; 328 u64 tx_irq; 329 u64 tx_packets; 330}; 331 332/* 333 * Receive ring: one per rx queue 334 */ 335struct rx_ring { 336 struct adapter *adapter; 337 u32 me; 338 u32 msix; /* This ring's MSIX vector */ 339 u32 eims; /* This ring's EIMS bit */ 340 struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */ 341 union e1000_adv_rx_desc *rx_base; 342 struct lro_ctrl lro; 343 struct task rx_task; /* cleanup tasklet */ 344 struct mtx rx_mtx; 345 char mtx_name[16]; 346 u32 last_cleaned; 347 u32 next_to_check; 348 struct igb_rx_buffer *rx_buffers; 349 bus_dma_tag_t rxtag; /* dma tag for tx */ 350 bus_dmamap_t rx_spare_map; 351 /* 352 * First/last mbuf pointers, for 353 * collecting multisegment RX packets. 354 */ 355 struct mbuf *fmp; 356 struct mbuf *lmp; 357 358 u32 bytes; 359 u32 eitr_setting; 360 361 /* Soft stats */ 362 u64 rx_irq; 363 u64 rx_split_packets; 364 u64 rx_packets; 365 u64 rx_bytes; 366}; 367 368struct adapter { 369 struct ifnet *ifp; 370 struct e1000_hw hw; 371 372 /* FreeBSD operating-system-specific structures. */ 373 struct e1000_osdep osdep; 374 struct device *dev; 375 376 struct resource *pci_mem; 377 struct resource *msix_mem; 378 struct resource *res[IGB_MSIX_VEC]; 379 void *tag[IGB_MSIX_VEC]; 380 int rid[IGB_MSIX_VEC]; 381 u32 eims_mask; 382 383 int linkvec; 384 int link_mask; 385 int link_irq; 386 387 struct ifmedia media; 388 struct callout timer; 389 int msix; /* total vectors allocated */ 390 int if_flags; 391 int max_frame_size; 392 int min_frame_size; 393 struct mtx core_mtx; 394 int igb_insert_vlan_header; 395 struct task link_task; 396 struct task rxtx_task; 397 struct taskqueue *tq; /* private task queue */ 398 eventhandler_tag vlan_attach; 399 eventhandler_tag vlan_detach; 400 401 /* Management and WOL features */ 402 int wol; 403 int has_manage; 404 405 /* Info about the board itself */ 406 u8 link_active; 407 u16 link_speed; 408 u16 link_duplex; 409 u32 smartspeed; 410 411 /* 412 * Transmit rings 413 */ 414 struct tx_ring *tx_rings; 415 u16 num_tx_desc; 416 u16 num_tx_queues; 417 u32 txd_cmd; 418 419 /* 420 * Receive rings 421 */ 422 struct rx_ring *rx_rings; 423 bool rx_hdr_split; 424 u16 num_rx_desc; 425 u16 num_rx_queues; 426 int rx_process_limit; 427 u32 rx_mbuf_sz; 428 u32 rx_mask; 429 430 /* Misc stats maintained by the driver */ 431 unsigned long dropped_pkts; 432 unsigned long mbuf_defrag_failed; 433 unsigned long mbuf_header_failed; 434 unsigned long mbuf_packet_failed; 435 unsigned long no_tx_map_avail; 436 unsigned long no_tx_dma_setup; 437 unsigned long watchdog_events; 438 unsigned long rx_overruns; 439 440 boolean_t in_detach; 441 442#ifdef IGB_TIMESYNC 443 u64 last_stamp; 444 u64 last_sec; 445 u32 last_ns; 446#endif 447 448 struct e1000_hw_stats stats; 449}; 450 451/* ****************************************************************************** 452 * vendor_info_array 453 * 454 * This array contains the list of Subvendor/Subdevice IDs on which the driver 455 * should load. 456 * 457 * ******************************************************************************/ 458typedef struct _igb_vendor_info_t { 459 unsigned int vendor_id; 460 unsigned int device_id; 461 unsigned int subvendor_id; 462 unsigned int subdevice_id; 463 unsigned int index; 464} igb_vendor_info_t; 465 466 467struct igb_tx_buffer { 468 int next_eop; /* Index of the desc to watch */ 469 struct mbuf *m_head; 470 bus_dmamap_t map; /* bus_dma map for packet */ 471}; 472 473struct igb_rx_buffer { 474 struct mbuf *m_head; 475 struct mbuf *m_pack; 476 bus_dmamap_t map; /* bus_dma map for packet */ 477}; 478 479#define IGB_CORE_LOCK_INIT(_sc, _name) \ 480 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 481#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 482#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 483#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 484#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 485#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 486#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 487#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 488#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 489#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 490#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 491#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 492 493#endif /* _IGB_H_DEFINED_ */ 494 495 496