if_igb.h revision 183714
11573Srgrimes/****************************************************************************** 21573Srgrimes 31573Srgrimes Copyright (c) 2001-2008, Intel Corporation 41573Srgrimes All rights reserved. 51573Srgrimes 61573Srgrimes Redistribution and use in source and binary forms, with or without 71573Srgrimes modification, are permitted provided that the following conditions are met: 81573Srgrimes 91573Srgrimes 1. Redistributions of source code must retain the above copyright notice, 101573Srgrimes this list of conditions and the following disclaimer. 111573Srgrimes 121573Srgrimes 2. Redistributions in binary form must reproduce the above copyright 131573Srgrimes notice, this list of conditions and the following disclaimer in the 141573Srgrimes documentation and/or other materials provided with the distribution. 151573Srgrimes 16249808Semaste 3. Neither the name of the Intel Corporation nor the names of its 171573Srgrimes contributors may be used to endorse or promote products derived from 181573Srgrimes this software without specific prior written permission. 191573Srgrimes 201573Srgrimes THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 211573Srgrimes AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221573Srgrimes IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231573Srgrimes ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 241573Srgrimes LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251573Srgrimes CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261573Srgrimes SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271573Srgrimes INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281573Srgrimes CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291573Srgrimes ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 301573Srgrimes POSSIBILITY OF SUCH DAMAGE. 311573Srgrimes 321573Srgrimes******************************************************************************/ 331573Srgrimes/*$FreeBSD: head/sys/dev/e1000/if_igb.h 183714 2008-10-09 02:25:18Z peter $*/ 341573Srgrimes 351573Srgrimes#ifndef _IGB_H_DEFINED_ 3692986Sobrien#define _IGB_H_DEFINED_ 3792986Sobrien 381573Srgrimes/* Tunables */ 391573Srgrimes 4037487Speter/* 411573Srgrimes * IGB_TXD: Maximum number of Transmit Descriptors 421573Srgrimes * 431573Srgrimes * This value is the number of transmit descriptors allocated by the driver. 441573Srgrimes * Increasing this value allows the driver to queue more transmits. Each 451573Srgrimes * descriptor is 16 bytes. 461573Srgrimes * Since TDLEN should be multiple of 128bytes, the number of transmit 471573Srgrimes * desscriptors should meet the following condition. 481573Srgrimes * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 491573Srgrimes */ 501573Srgrimes#define IGB_MIN_TXD 80 5116586Sjraynard#define IGB_DEFAULT_TXD 256 52249810Semaste#define IGB_MAX_TXD 4096 531573Srgrimes 5492889Sobrien/* 5592889Sobrien * IGB_RXD: Maximum number of Transmit Descriptors 5692889Sobrien * 5792889Sobrien * This value is the number of receive descriptors allocated by the driver. 581573Srgrimes * Increasing this value allows the driver to buffer more incoming packets. 5982838Sache * Each descriptor is 16 bytes. A receive buffer is also allocated for each 601573Srgrimes * descriptor. The maximum MTU size is 16110. 61199781Swollman * Since TDLEN should be multiple of 128bytes, the number of transmit 621573Srgrimes * desscriptors should meet the following condition. 631573Srgrimes * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64130232Sdas */ 651573Srgrimes#define IGB_MIN_RXD 80 661573Srgrimes#define IGB_DEFAULT_RXD 256 671573Srgrimes#define IGB_MAX_RXD 4096 681573Srgrimes 691573Srgrimes/* 701573Srgrimes * IGB_TIDV - Transmit Interrupt Delay Value 711573Srgrimes * Valid Range: 0-65535 (0=off) 721573Srgrimes * Default Value: 64 731573Srgrimes * This value delays the generation of transmit interrupts in units of 741573Srgrimes * 1.024 microseconds. Transmit interrupt reduction can improve CPU 751573Srgrimes * efficiency if properly tuned for specific network traffic. If the 761573Srgrimes * system is reporting dropped transmits, this value may be set too high 771573Srgrimes * causing the driver to run out of available transmit descriptors. 781573Srgrimes */ 791573Srgrimes#define IGB_TIDV 64 801573Srgrimes 811573Srgrimes/* 821573Srgrimes * IGB_TADV - Transmit Absolute Interrupt Delay Value 831573Srgrimes * Valid Range: 0-65535 (0=off) 841573Srgrimes * Default Value: 64 851573Srgrimes * This value, in units of 1.024 microseconds, limits the delay in which a 861573Srgrimes * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 8782838Sache * this value ensures that an interrupt is generated after the initial 881573Srgrimes * packet is sent on the wire within the set amount of time. Proper tuning, 891573Srgrimes * along with IGB_TIDV, may improve traffic throughput in specific 901573Srgrimes * network conditions. 911573Srgrimes */ 921573Srgrimes#define IGB_TADV 64 931573Srgrimes 941573Srgrimes/* 951573Srgrimes * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 961573Srgrimes * Valid Range: 0-65535 (0=off) 971573Srgrimes * Default Value: 0 981573Srgrimes * This value delays the generation of receive interrupts in units of 1.024 991573Srgrimes * microseconds. Receive interrupt reduction can improve CPU efficiency if 10031981Sache * properly tuned for specific network traffic. Increasing this value adds 10131981Sache * extra latency to frame reception and can end up decreasing the throughput 10231981Sache * of TCP traffic. If the system is reporting dropped receives, this value 10331981Sache * may be set too high, causing the driver to run out of available receive 1041573Srgrimes * descriptors. 1051573Srgrimes * 1061573Srgrimes * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 10737487Speter * may hang (stop transmitting) under certain network conditions. 10837487Speter * If this occurs a WATCHDOG message is logged in the system 10937487Speter * event log. In addition, the controller is automatically reset, 11037487Speter * restoring the network connection. To eliminate the potential 11137487Speter * for the hang ensure that IGB_RDTR is set to 0. 11237487Speter */ 11337487Speter#define IGB_RDTR 0 11437487Speter 11537487Speter/* 11637487Speter * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 11737487Speter * Valid Range: 0-65535 (0=off) 11839327Simp * Default Value: 64 11937487Speter * This value, in units of 1.024 microseconds, limits the delay in which a 12037487Speter * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 12137487Speter * this value ensures that an interrupt is generated after the initial 12237487Speter * packet is received within the set amount of time. Proper tuning, 1231573Srgrimes * along with IGB_RDTR, may improve traffic throughput in specific network 1241573Srgrimes * conditions. 1251573Srgrimes */ 1261573Srgrimes#define IGB_RADV 64 12731981Sache 12831981Sache/* 12931981Sache * This parameter controls the duration of transmit watchdog timer. 13031981Sache */ 13131981Sache#define IGB_TX_TIMEOUT 5 /* set to 5 seconds */ 1321573Srgrimes 1331573Srgrimes/* 1341573Srgrimes * This parameter controls when the driver calls the routine to reclaim 1351573Srgrimes * transmit descriptors. 1361573Srgrimes */ 1371573Srgrimes#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 13871579Sdeischen#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 1391573Srgrimes 1401573Srgrimes/* 1411573Srgrimes * This parameter controls whether or not autonegotation is enabled. 14282838Sache * 0 - Disable autonegotiation 1431573Srgrimes * 1 - Enable autonegotiation 1441573Srgrimes */ 1451573Srgrimes#define DO_AUTO_NEG 1 1461573Srgrimes 1471573Srgrimes/* 1481573Srgrimes * This parameter control whether or not the driver will wait for 1491573Srgrimes * autonegotiation to complete. 1501573Srgrimes * 1 - Wait for autonegotiation to complete 1511573Srgrimes * 0 - Don't wait for autonegotiation to complete 1521573Srgrimes */ 1531573Srgrimes#define WAIT_FOR_AUTO_NEG_DEFAULT 0 1541573Srgrimes 1551573Srgrimes/* Tunables -- End */ 1561573Srgrimes 1571573Srgrimes#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 1581573Srgrimes ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 1591573Srgrimes ADVERTISE_1000_FULL) 1601573Srgrimes 1611573Srgrimes#define AUTO_ALL_MODES 0 1621573Srgrimes 1631573Srgrimes/* PHY master/slave setting */ 1641573Srgrimes#define IGB_MASTER_SLAVE e1000_ms_hw_default 1651573Srgrimes 1661573Srgrimes/* 1671573Srgrimes * Micellaneous constants 1681573Srgrimes */ 1691573Srgrimes#define IGB_VENDOR_ID 0x8086 1701573Srgrimes 1711573Srgrimes#define IGB_JUMBO_PBA 0x00000028 1721573Srgrimes#define IGB_DEFAULT_PBA 0x00000030 1731573Srgrimes#define IGB_SMARTSPEED_DOWNSHIFT 3 1741573Srgrimes#define IGB_SMARTSPEED_MAX 15 1751573Srgrimes#define IGB_MAX_INTR 10 1761573Srgrimes#define IGB_RX_PTHRESH 16 1771573Srgrimes#define IGB_RX_HTHRESH 8 17871579Sdeischen#define IGB_RX_WTHRESH 1 1791573Srgrimes 1801573Srgrimes#define MAX_NUM_MULTICAST_ADDRESSES 128 18182838Sache#define PCI_ANY_ID (~0U) 1821573Srgrimes#define ETHER_ALIGN 2 1831573Srgrimes#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 1841573Srgrimes#define IGB_FC_PAUSE_TIME 0x0680 1851573Srgrimes#define IGB_EEPROM_APME 0x400; 1861573Srgrimes 1871573Srgrimes#define MAX_INTS_PER_SEC 8000 1881573Srgrimes#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 1891573Srgrimes 1901573Srgrimes/* Code compatilbility between 6 and 7 */ 1911573Srgrimes#ifndef ETHER_BPF_MTAP 19271579Sdeischen#define ETHER_BPF_MTAP BPF_MTAP 1931573Srgrimes#endif 1941573Srgrimes 1951573Srgrimes/* 1961573Srgrimes * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 1971573Srgrimes * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 1981573Srgrimes * also optimize cache line size effect. H/W supports up to cache line size 128. 1991573Srgrimes */ 2001573Srgrimes#define IGB_DBA_ALIGN 128 2011573Srgrimes 2021573Srgrimes#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 2031573Srgrimes 2041573Srgrimes/* PCI Config defines */ 2051573Srgrimes#define IGB_MSIX_BAR 3 206 207/* 208** This is the total number of MSIX vectors you wish 209** to use, it also controls the size of resources. 210** The 82575 has a total of 10, 82576 has 25. Set this 211** to the real amount you need to streamline data storage. 212*/ 213#define IGB_MSIX_VEC 6 /* MSIX vectors configured */ 214 215/* Defines for printing debug information */ 216#define DEBUG_INIT 0 217#define DEBUG_IOCTL 0 218#define DEBUG_HW 0 219 220#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 221#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 222#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 223#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 224#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 225#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 226#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 227#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 228#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 229 230#define IGB_MAX_SCATTER 64 231#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 232#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 233#define ETH_ZLEN 60 234#define ETH_ADDR_LEN 6 235#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 236 237/* 238 * Interrupt Moderation parameters 239 */ 240#define IGB_LOW_LATENCY 128 241#define IGB_AVE_LATENCY 450 242#define IGB_BULK_LATENCY 1200 243#define IGB_LINK_ITR 2000 244 245#ifdef IGB_TIMESYNC 246/* Precision Time Sync (IEEE 1588) defines */ 247#define ETHERTYPE_IEEE1588 0x88F7 248#define PICOSECS_PER_TICK 20833 249#define TSYNC_PORT 319 /* UDP port for the protocol */ 250 251/* TIMESYNC IOCTL defines */ 252#define IGB_TIMESYNC_READTS _IOWR('i', 127, struct igb_tsync_read) 253#define IGB_TIMESTAMP 5 /* A unique return value */ 254 255/* Used in the READTS IOCTL */ 256struct igb_tsync_read { 257 int read_current_time; 258 struct timespec system_time; 259 u64 network_time; 260 u64 rx_stamp; 261 u64 tx_stamp; 262 u16 seqid; 263 unsigned char srcid[6]; 264 int rx_valid; 265 int tx_valid; 266}; 267 268#endif /* IGB_TIMESYNC */ 269 270struct adapter; /* forward reference */ 271 272struct igb_int_delay_info { 273 struct adapter *adapter; /* Back-pointer to the adapter struct */ 274 int offset; /* Register offset to read/write */ 275 int value; /* Current value in usecs */ 276}; 277 278/* 279 * Bus dma allocation structure used by 280 * e1000_dma_malloc and e1000_dma_free. 281 */ 282struct igb_dma_alloc { 283 bus_addr_t dma_paddr; 284 caddr_t dma_vaddr; 285 bus_dma_tag_t dma_tag; 286 bus_dmamap_t dma_map; 287 bus_dma_segment_t dma_seg; 288 int dma_nseg; 289}; 290 291 292/* 293 * Transmit ring: one per tx queue 294 */ 295struct tx_ring { 296 struct adapter *adapter; 297 u32 me; 298 u32 msix; /* This ring's MSIX vector */ 299 u32 eims; /* This ring's EIMS bit */ 300 struct mtx tx_mtx; 301 char mtx_name[16]; 302 struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */ 303 struct e1000_tx_desc *tx_base; 304 struct task tx_task; /* cleanup tasklet */ 305 u32 next_avail_desc; 306 u32 next_to_clean; 307 volatile u16 tx_avail; 308 struct igb_buffer *tx_buffers; 309 bus_dma_tag_t txtag; /* dma tag for tx */ 310 u32 watchdog_timer; 311 u64 no_desc_avail; 312 u64 tx_irq; 313 u64 tx_packets; 314}; 315 316/* 317 * Receive ring: one per rx queue 318 */ 319struct rx_ring { 320 struct adapter *adapter; 321 u32 me; 322 u32 msix; /* This ring's MSIX vector */ 323 u32 eims; /* This ring's EIMS bit */ 324 struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */ 325 union e1000_adv_rx_desc *rx_base; 326 struct lro_ctrl lro; 327 struct task rx_task; /* cleanup tasklet */ 328 struct mtx rx_mtx; 329 char mtx_name[16]; 330 u32 last_cleaned; 331 u32 next_to_check; 332 struct igb_buffer *rx_buffers; 333 bus_dma_tag_t rxtag; /* dma tag for tx */ 334 bus_dmamap_t rx_spare_map; 335 /* 336 * First/last mbuf pointers, for 337 * collecting multisegment RX packets. 338 */ 339 struct mbuf *fmp; 340 struct mbuf *lmp; 341 342 u32 bytes; 343 u32 eitr_setting; 344 345 /* Soft stats */ 346 u64 rx_irq; 347 u64 rx_packets; 348 u64 rx_bytes; 349}; 350 351struct adapter { 352 struct ifnet *ifp; 353 struct e1000_hw hw; 354 355 /* FreeBSD operating-system-specific structures. */ 356 struct e1000_osdep osdep; 357 struct device *dev; 358 359 struct resource *pci_mem; 360 struct resource *msix_mem; 361 struct resource *res[IGB_MSIX_VEC]; 362 void *tag[IGB_MSIX_VEC]; 363 int rid[IGB_MSIX_VEC]; 364 u32 eims_mask; 365 366 int linkvec; 367 int link_mask; 368 int link_irq; 369 370 struct ifmedia media; 371 struct callout timer; 372 int msix; /* total vectors allocated */ 373 int if_flags; 374 int max_frame_size; 375 int min_frame_size; 376 struct mtx core_mtx; 377 int igb_insert_vlan_header; 378 struct task link_task; 379 struct task rxtx_task; 380 struct taskqueue *tq; /* private task queue */ 381 eventhandler_tag vlan_attach; 382 eventhandler_tag vlan_detach; 383 /* Management and WOL features */ 384 int wol; 385 int has_manage; 386 387 /* Info about the board itself */ 388 u8 link_active; 389 u16 link_speed; 390 u16 link_duplex; 391 u32 smartspeed; 392 393 /* 394 * Transmit rings 395 */ 396 struct tx_ring *tx_rings; 397 u16 num_tx_desc; 398 u16 num_tx_queues; 399 u32 txd_cmd; 400 401 /* 402 * Receive rings 403 */ 404 struct rx_ring *rx_rings; 405 u16 num_rx_desc; 406 u16 num_rx_queues; 407 int rx_process_limit; 408 u32 rx_buffer_len; 409 410 /* Misc stats maintained by the driver */ 411 unsigned long dropped_pkts; 412 unsigned long mbuf_alloc_failed; 413 unsigned long mbuf_cluster_failed; 414 unsigned long no_tx_map_avail; 415 unsigned long no_tx_dma_setup; 416 unsigned long watchdog_events; 417 unsigned long rx_overruns; 418 419 boolean_t in_detach; 420 421#ifdef IGB_TIMESYNC 422 u64 last_stamp; 423 u64 last_sec; 424 u32 last_ns; 425#endif 426 427 struct e1000_hw_stats stats; 428}; 429 430/* ****************************************************************************** 431 * vendor_info_array 432 * 433 * This array contains the list of Subvendor/Subdevice IDs on which the driver 434 * should load. 435 * 436 * ******************************************************************************/ 437typedef struct _igb_vendor_info_t { 438 unsigned int vendor_id; 439 unsigned int device_id; 440 unsigned int subvendor_id; 441 unsigned int subdevice_id; 442 unsigned int index; 443} igb_vendor_info_t; 444 445 446struct igb_buffer { 447 int next_eop; /* Index of the desc to watch */ 448 struct mbuf *m_head; 449 bus_dmamap_t map; /* bus_dma map for packet */ 450}; 451 452#define IGB_CORE_LOCK_INIT(_sc, _name) \ 453 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 454#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 455#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 456#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 457#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 458#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 459#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 460#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 461#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 462#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 463#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 464#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 465 466#endif /* _IGB_H_DEFINED_ */ 467 468 469