if_igb.h revision 178523
1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/igb/if_igb.h 178523 2008-04-25 21:19:41Z jfv $*/ 34 35#ifndef _IGB_H_DEFINED_ 36#define _IGB_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50#define IGB_MIN_TXD 80 51#define IGB_DEFAULT_TXD 256 52#define IGB_MAX_TXD 4096 53 54/* 55 * IGB_RXD: Maximum number of Transmit Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65#define IGB_MIN_RXD 80 66#define IGB_DEFAULT_RXD 256 67#define IGB_MAX_RXD 4096 68 69/* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79#define IGB_TIDV 64 80 81/* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92#define IGB_TADV 64 93 94/* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113#define IGB_RDTR 0 114 115/* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126#define IGB_RADV 64 127 128/* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131#define IGB_TX_TIMEOUT 5 /* set to 5 seconds */ 132 133/* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. 136 */ 137#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 138#define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 139 140/* 141 * This parameter controls whether or not autonegotation is enabled. 142 * 0 - Disable autonegotiation 143 * 1 - Enable autonegotiation 144 */ 145#define DO_AUTO_NEG 1 146 147/* 148 * This parameter control whether or not the driver will wait for 149 * autonegotiation to complete. 150 * 1 - Wait for autonegotiation to complete 151 * 0 - Don't wait for autonegotiation to complete 152 */ 153#define WAIT_FOR_AUTO_NEG_DEFAULT 0 154 155/* Tunables -- End */ 156 157#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 159 ADVERTISE_1000_FULL) 160 161#define AUTO_ALL_MODES 0 162 163/* PHY master/slave setting */ 164#define IGB_MASTER_SLAVE e1000_ms_hw_default 165 166/* 167 * Micellaneous constants 168 */ 169#define IGB_VENDOR_ID 0x8086 170 171#define IGB_JUMBO_PBA 0x00000028 172#define IGB_DEFAULT_PBA 0x00000030 173#define IGB_SMARTSPEED_DOWNSHIFT 3 174#define IGB_SMARTSPEED_MAX 15 175#define IGB_MAX_INTR 10 176#define IGB_RX_PTHRESH 16 177#define IGB_RX_HTHRESH 8 178#define IGB_RX_WTHRESH 1 179 180#define MAX_NUM_MULTICAST_ADDRESSES 128 181#define PCI_ANY_ID (~0U) 182#define ETHER_ALIGN 2 183#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 184#define IGB_FC_PAUSE_TIME 0x0680 185#define IGB_EEPROM_APME 0x400; 186 187#define MAX_INTS_PER_SEC 8000 188#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 189 190/* Code compatilbility between 6 and 7 */ 191#ifndef ETHER_BPF_MTAP 192#define ETHER_BPF_MTAP BPF_MTAP 193#endif 194 195/* 196 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 197 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 198 * also optimize cache line size effect. H/W supports up to cache line size 128. 199 */ 200#define IGB_DBA_ALIGN 128 201 202#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 203 204/* PCI Config defines */ 205#define IGB_MSIX_BAR 3 206 207/* 208** This is the total number of MSIX vectors you wish 209** to use, it also controls the size of resources. 210** The 82575 has a total of 10, 82576 has 25. Set this 211** to the real amount you need to streamline data storage. 212*/ 213#define IGB_MSIX_VEC 5 /* MSIX vectors configured */ 214 215/* Defines for printing debug information */ 216#define DEBUG_INIT 0 217#define DEBUG_IOCTL 0 218#define DEBUG_HW 0 219 220#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 221#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 222#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 223#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 224#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 225#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 226#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 227#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 228#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 229 230#define IGB_MAX_SCATTER 64 231#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 232#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 233#define ETH_ZLEN 60 234#define ETH_ADDR_LEN 6 235#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 236 237 238struct adapter; /* forward reference */ 239 240struct igb_int_delay_info { 241 struct adapter *adapter; /* Back-pointer to the adapter struct */ 242 int offset; /* Register offset to read/write */ 243 int value; /* Current value in usecs */ 244}; 245 246/* 247 * Bus dma allocation structure used by 248 * e1000_dma_malloc and e1000_dma_free. 249 */ 250struct igb_dma_alloc { 251 bus_addr_t dma_paddr; 252 caddr_t dma_vaddr; 253 bus_dma_tag_t dma_tag; 254 bus_dmamap_t dma_map; 255 bus_dma_segment_t dma_seg; 256 int dma_nseg; 257}; 258 259 260/* 261 * Transmit ring: one per tx queue 262 */ 263struct tx_ring { 264 struct adapter *adapter; 265 u32 me; 266 u32 msix; /* This ring's MSIX vector */ 267 u32 eims; /* This ring's EIMS bit */ 268 struct mtx tx_mtx; 269 struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */ 270 struct e1000_tx_desc *tx_base; 271 struct task tx_task; /* cleanup tasklet */ 272 u32 next_avail_desc; 273 u32 next_to_clean; 274 volatile u16 tx_avail; 275 struct igb_buffer *tx_buffers; 276 bus_dma_tag_t txtag; /* dma tag for tx */ 277 u32 watchdog_timer; 278 u64 no_desc_avail; 279 u64 tx_irq; 280 u64 tx_packets; 281}; 282 283/* 284 * Receive ring: one per rx queue 285 */ 286struct rx_ring { 287 struct adapter *adapter; 288 u32 me; 289 u32 msix; /* This ring's MSIX vector */ 290 u32 eims; /* This ring's EIMS bit */ 291 struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */ 292 union e1000_adv_rx_desc *rx_base; 293 struct task rx_task; /* cleanup tasklet */ 294 struct mtx rx_mtx; 295 u32 last_cleaned; 296 u32 next_to_check; 297 struct igb_buffer *rx_buffers; 298 bus_dma_tag_t rxtag; /* dma tag for tx */ 299 bus_dmamap_t rx_spare_map; 300 /* 301 * First/last mbuf pointers, for 302 * collecting multisegment RX packets. 303 */ 304 struct mbuf *fmp; 305 struct mbuf *lmp; 306 /* Soft stats */ 307 u64 rx_irq; 308 u64 rx_packets; 309 u64 rx_bytes; 310}; 311 312struct adapter { 313 struct ifnet *ifp; 314 struct e1000_hw hw; 315 316 /* FreeBSD operating-system-specific structures. */ 317 struct e1000_osdep osdep; 318 struct device *dev; 319 320 struct resource *pci_mem; 321 struct resource *msix_mem; 322 struct resource *res[IGB_MSIX_VEC]; 323 void *tag[IGB_MSIX_VEC]; 324 int rid[IGB_MSIX_VEC]; 325 u32 eims_mask; 326 327 int linkvec; 328 int link_mask; 329 int link_irq; 330 331 struct ifmedia media; 332 struct callout timer; 333 int msix; /* total vectors allocated */ 334 int if_flags; 335 int max_frame_size; 336 int min_frame_size; 337 struct mtx core_mtx; 338 int igb_insert_vlan_header; 339 struct task link_task; 340 struct task rxtx_task; 341 struct taskqueue *tq; /* private task queue */ 342 343 /* Management and WOL features */ 344 int wol; 345 int has_manage; 346 347 /* Info about the board itself */ 348 u8 link_active; 349 u16 link_speed; 350 u16 link_duplex; 351 u32 smartspeed; 352 struct igb_int_delay_info tx_int_delay; 353 struct igb_int_delay_info tx_abs_int_delay; 354 struct igb_int_delay_info rx_int_delay; 355 struct igb_int_delay_info rx_abs_int_delay; 356 357 /* 358 * Transmit rings 359 */ 360 struct tx_ring *tx_rings; 361 u16 num_tx_desc; 362 u16 num_tx_queues; 363 u32 txd_cmd; 364 365 /* 366 * Receive rings 367 */ 368 struct rx_ring *rx_rings; 369 u16 num_rx_desc; 370 u16 num_rx_queues; 371 int rx_process_limit; 372 u32 rx_buffer_len; 373 374 /* Misc stats maintained by the driver */ 375 unsigned long dropped_pkts; 376 unsigned long mbuf_alloc_failed; 377 unsigned long mbuf_cluster_failed; 378 unsigned long no_tx_map_avail; 379 unsigned long no_tx_dma_setup; 380 unsigned long watchdog_events; 381 unsigned long rx_overruns; 382 383 boolean_t in_detach; 384 385 386 struct e1000_hw_stats stats; 387}; 388 389/* ****************************************************************************** 390 * vendor_info_array 391 * 392 * This array contains the list of Subvendor/Subdevice IDs on which the driver 393 * should load. 394 * 395 * ******************************************************************************/ 396typedef struct _igb_vendor_info_t { 397 unsigned int vendor_id; 398 unsigned int device_id; 399 unsigned int subvendor_id; 400 unsigned int subdevice_id; 401 unsigned int index; 402} igb_vendor_info_t; 403 404 405struct igb_buffer { 406 int next_eop; /* Index of the desc to watch */ 407 struct mbuf *m_head; 408 bus_dmamap_t map; /* bus_dma map for packet */ 409}; 410 411#define IGB_CORE_LOCK_INIT(_sc, _name) \ 412 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 413#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 414#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 415#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 416#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 417#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 418#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 419#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 420#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 421#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 422#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 423#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 424 425#endif /* _IGB_H_DEFINED_ */ 426 427 428