if_em.h revision 203049
1187767Sluigi/****************************************************************************** 2204591Sluigi 3187767Sluigi Copyright (c) 2001-2010, Intel Corporation 4187767Sluigi All rights reserved. 5187767Sluigi 6187767Sluigi Redistribution and use in source and binary forms, with or without 7187767Sluigi modification, are permitted provided that the following conditions are met: 8187767Sluigi 9187767Sluigi 1. Redistributions of source code must retain the above copyright notice, 10187767Sluigi this list of conditions and the following disclaimer. 11187767Sluigi 12187767Sluigi 2. Redistributions in binary form must reproduce the above copyright 13187767Sluigi notice, this list of conditions and the following disclaimer in the 14187767Sluigi documentation and/or other materials provided with the distribution. 15187767Sluigi 16187767Sluigi 3. Neither the name of the Intel Corporation nor the names of its 17187767Sluigi contributors may be used to endorse or promote products derived from 18187767Sluigi this software without specific prior written permission. 19187767Sluigi 20187767Sluigi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21187767Sluigi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22187767Sluigi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23187767Sluigi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24187767Sluigi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25187767Sluigi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26187767Sluigi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27187767Sluigi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28187767Sluigi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29187767Sluigi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30187767Sluigi POSSIBILITY OF SUCH DAMAGE. 31187767Sluigi 32187767Sluigi******************************************************************************/ 33187767Sluigi/*$FreeBSD: head/sys/dev/e1000/if_em.h 203049 2010-01-26 22:32:22Z jfv $*/ 34187767Sluigi 35187767Sluigi 36187767Sluigi#ifndef _EM_H_DEFINED_ 37187767Sluigi#define _EM_H_DEFINED_ 38187767Sluigi 39187767Sluigi 40187767Sluigi/* Tunables */ 41187767Sluigi 42187767Sluigi/* 43187767Sluigi * EM_TXD: Maximum number of Transmit Descriptors 44187767Sluigi * Valid Range: 80-256 for 82542 and 82543-based adapters 45187767Sluigi * 80-4096 for others 46187767Sluigi * Default Value: 256 47187767Sluigi * This value is the number of transmit descriptors allocated by the driver. 48187767Sluigi * Increasing this value allows the driver to queue more transmits. Each 49187767Sluigi * descriptor is 16 bytes. 50187767Sluigi * Since TDLEN should be multiple of 128bytes, the number of transmit 51187767Sluigi * desscriptors should meet the following condition. 52187767Sluigi * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53187767Sluigi */ 54187767Sluigi#define EM_MIN_TXD 80 55187767Sluigi#define EM_MAX_TXD_82543 256 56187767Sluigi#define EM_MAX_TXD 4096 57190633Spiso#define EM_DEFAULT_TXD 1024 58187767Sluigi 59187767Sluigi/* 60187767Sluigi * EM_RXD - Maximum number of receive Descriptors 61187767Sluigi * Valid Range: 80-256 for 82542 and 82543-based adapters 62187767Sluigi * 80-4096 for others 63187767Sluigi * Default Value: 256 64187767Sluigi * This value is the number of receive descriptors allocated by the driver. 65187767Sluigi * Increasing this value allows the driver to buffer more incoming packets. 66187767Sluigi * Each descriptor is 16 bytes. A receive buffer is also allocated for each 67187767Sluigi * descriptor. The maximum MTU size is 16110. 68187767Sluigi * Since TDLEN should be multiple of 128bytes, the number of transmit 69187767Sluigi * desscriptors should meet the following condition. 70187767Sluigi * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 71187767Sluigi */ 72187767Sluigi#define EM_MIN_RXD 80 73187767Sluigi#define EM_MAX_RXD_82543 256 74187767Sluigi#define EM_MAX_RXD 4096 75187767Sluigi#define EM_DEFAULT_RXD 1024 76187767Sluigi 77187767Sluigi/* 78187767Sluigi * EM_TIDV - Transmit Interrupt Delay Value 79187767Sluigi * Valid Range: 0-65535 (0=off) 80187767Sluigi * Default Value: 64 81187767Sluigi * This value delays the generation of transmit interrupts in units of 82187767Sluigi * 1.024 microseconds. Transmit interrupt reduction can improve CPU 83187767Sluigi * efficiency if properly tuned for specific network traffic. If the 84187767Sluigi * system is reporting dropped transmits, this value may be set too high 85187767Sluigi * causing the driver to run out of available transmit descriptors. 86204591Sluigi */ 87204591Sluigi#define EM_TIDV 64 88204591Sluigi 89204591Sluigi/* 90204591Sluigi * EM_TADV - Transmit Absolute Interrupt Delay Value 91204591Sluigi * (Not valid for 82542/82543/82544) 92204591Sluigi * Valid Range: 0-65535 (0=off) 93187767Sluigi * Default Value: 64 94187767Sluigi * This value, in units of 1.024 microseconds, limits the delay in which a 95187767Sluigi * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 96187767Sluigi * this value ensures that an interrupt is generated after the initial 97204591Sluigi * packet is sent on the wire within the set amount of time. Proper tuning, 98187767Sluigi * along with EM_TIDV, may improve traffic throughput in specific 99187767Sluigi * network conditions. 100187767Sluigi */ 101189396Sluigi#define EM_TADV 64 102204591Sluigi 103204591Sluigi/* 104187767Sluigi * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 105187767Sluigi * Valid Range: 0-65535 (0=off) 106187767Sluigi * Default Value: 0 107187767Sluigi * This value delays the generation of receive interrupts in units of 1.024 108187767Sluigi * microseconds. Receive interrupt reduction can improve CPU efficiency if 109187767Sluigi * properly tuned for specific network traffic. Increasing this value adds 110187767Sluigi * extra latency to frame reception and can end up decreasing the throughput 111204591Sluigi * of TCP traffic. If the system is reporting dropped receives, this value 112204591Sluigi * may be set too high, causing the driver to run out of available receive 113204591Sluigi * descriptors. 114187767Sluigi * 115187767Sluigi * CAUTION: When setting EM_RDTR to a value other than 0, adapters 116187767Sluigi * may hang (stop transmitting) under certain network conditions. 117187767Sluigi * If this occurs a WATCHDOG message is logged in the system 118187767Sluigi * event log. In addition, the controller is automatically reset, 119187767Sluigi * restoring the network connection. To eliminate the potential 120187767Sluigi * for the hang ensure that EM_RDTR is set to 0. 121187767Sluigi */ 122187767Sluigi#define EM_RDTR 0 123187767Sluigi 124187767Sluigi/* 125187767Sluigi * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 126187767Sluigi * Valid Range: 0-65535 (0=off) 127187767Sluigi * Default Value: 64 128187767Sluigi * This value, in units of 1.024 microseconds, limits the delay in which a 129187767Sluigi * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 130187767Sluigi * this value ensures that an interrupt is generated after the initial 131187767Sluigi * packet is received within the set amount of time. Proper tuning, 132187767Sluigi * along with EM_RDTR, may improve traffic throughput in specific network 133187767Sluigi * conditions. 134187767Sluigi */ 135187767Sluigi#define EM_RADV 64 136187767Sluigi 137187767Sluigi/* 138187767Sluigi * This parameter controls the duration of transmit watchdog. 139187767Sluigi */ 140187767Sluigi#define EM_WATCHDOG (10 * hz) 141187767Sluigi 142187767Sluigi/* 143187767Sluigi * This parameter controls when the driver calls the routine to reclaim 144187767Sluigi * transmit descriptors. 145187767Sluigi */ 146187767Sluigi#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 147187767Sluigi#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 148204591Sluigi 149204591Sluigi/* 150204591Sluigi * This parameter controls whether or not autonegotation is enabled. 151204591Sluigi * 0 - Disable autonegotiation 152204591Sluigi * 1 - Enable autonegotiation 153187767Sluigi */ 154204591Sluigi#define DO_AUTO_NEG 1 155204591Sluigi 156204591Sluigi/* 157187767Sluigi * This parameter control whether or not the driver will wait for 158187767Sluigi * autonegotiation to complete. 159204591Sluigi * 1 - Wait for autonegotiation to complete 160204591Sluigi * 0 - Don't wait for autonegotiation to complete 161187767Sluigi */ 162187767Sluigi#define WAIT_FOR_AUTO_NEG_DEFAULT 0 163204591Sluigi 164204591Sluigi/* Tunables -- End */ 165187767Sluigi 166187767Sluigi#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 167187767Sluigi ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 168204591Sluigi ADVERTISE_1000_FULL) 169204591Sluigi 170204591Sluigi#define AUTO_ALL_MODES 0 171204591Sluigi 172187767Sluigi/* PHY master/slave setting */ 173187767Sluigi#define EM_MASTER_SLAVE e1000_ms_hw_default 174187767Sluigi 175204591Sluigi/* 176187767Sluigi * Micellaneous constants 177187767Sluigi */ 178187767Sluigi#define EM_VENDOR_ID 0x8086 179187767Sluigi#define EM_FLASH 0x0014 180204591Sluigi 181187767Sluigi#define EM_JUMBO_PBA 0x00000028 182204591Sluigi#define EM_DEFAULT_PBA 0x00000030 183204591Sluigi#define EM_SMARTSPEED_DOWNSHIFT 3 184204591Sluigi#define EM_SMARTSPEED_MAX 15 185204591Sluigi#define EM_MAX_INTR 10 186204591Sluigi 187204591Sluigi#define MAX_NUM_MULTICAST_ADDRESSES 128 188204591Sluigi#define PCI_ANY_ID (~0U) 189204591Sluigi#define ETHER_ALIGN 2 190204591Sluigi#define EM_FC_PAUSE_TIME 0x0680 191204591Sluigi#define EM_EEPROM_APME 0x400; 192204591Sluigi#define EM_82544_APME 0x0004; 193204591Sluigi 194204591Sluigi/* Code compatilbility between 6 and 7 */ 195204591Sluigi#ifndef ETHER_BPF_MTAP 196204591Sluigi#define ETHER_BPF_MTAP BPF_MTAP 197204591Sluigi#endif 198204591Sluigi 199204591Sluigi/* 200204591Sluigi * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201187767Sluigi * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202187767Sluigi * also optimize cache line size effect. H/W supports up to cache line size 128. 203187767Sluigi */ 204187767Sluigi#define EM_DBA_ALIGN 128 205187767Sluigi 206187767Sluigi#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207187767Sluigi 208204591Sluigi/* PCI Config defines */ 209187767Sluigi#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 210204591Sluigi#define EM_BAR_TYPE_MASK 0x00000001 211204591Sluigi#define EM_BAR_TYPE_MMEM 0x00000000 212187767Sluigi#define EM_BAR_TYPE_IO 0x00000001 213204591Sluigi#define EM_BAR_TYPE_FLASH 0x0014 214187767Sluigi#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 215187767Sluigi#define EM_BAR_MEM_TYPE_MASK 0x00000006 216187767Sluigi#define EM_BAR_MEM_TYPE_32BIT 0x00000000 217187767Sluigi#define EM_BAR_MEM_TYPE_64BIT 0x00000004 218187767Sluigi#define EM_MSIX_BAR 3 /* On 82575 */ 219187767Sluigi 220187767Sluigi/* Defines for printing debug information */ 221204591Sluigi#define DEBUG_INIT 0 222204591Sluigi#define DEBUG_IOCTL 0 223204591Sluigi#define DEBUG_HW 0 224204591Sluigi 225204591Sluigi#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 226204591Sluigi#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 227204591Sluigi#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 228187767Sluigi#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 229187767Sluigi#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 230187767Sluigi#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 231187767Sluigi#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 232204591Sluigi#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 233204591Sluigi#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 234204591Sluigi 235204591Sluigi#define EM_MAX_SCATTER 64 236204591Sluigi#define EM_VFTA_SIZE 128 237204591Sluigi#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 238204591Sluigi#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 239204591Sluigi#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 240204591Sluigi#define ETH_ZLEN 60 241204591Sluigi#define ETH_ADDR_LEN 6 242204591Sluigi#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 243204591Sluigi#define M_TSO_LEN 66 244204591Sluigi 245204591Sluigi/* 246204591Sluigi * 82574 has a nonstandard address for EIAC 247204591Sluigi * and since its only used in MSIX, and in 248204591Sluigi * the em driver only 82574 uses MSIX we can 249204591Sluigi * solve it just using this define. 250204591Sluigi */ 251204591Sluigi#define EM_EIAC 0x000DC 252204591Sluigi 253204591Sluigi/* Used in for 82547 10Mb Half workaround */ 254204591Sluigi#define EM_PBA_BYTES_SHIFT 0xA 255204591Sluigi#define EM_TX_HEAD_ADDR_SHIFT 7 256204591Sluigi#define EM_PBA_TX_MASK 0xFFFF0000 257204591Sluigi#define EM_FIFO_HDR 0x10 258204591Sluigi#define EM_82547_PKT_THRESH 0x3e0 259204591Sluigi 260204591Sluigi/* Precision Time Sync (IEEE 1588) defines */ 261187767Sluigi#define ETHERTYPE_IEEE1588 0x88F7 262187767Sluigi#define PICOSECS_PER_TICK 20833 263187767Sluigi#define TSYNC_PORT 319 /* UDP port for the protocol */ 264187767Sluigi 265187767Sluigi/* 266187767Sluigi * Bus dma allocation structure used by 267187767Sluigi * e1000_dma_malloc and e1000_dma_free. 268187767Sluigi */ 269187767Sluigistruct em_dma_alloc { 270187767Sluigi bus_addr_t dma_paddr; 271187767Sluigi caddr_t dma_vaddr; 272187767Sluigi bus_dma_tag_t dma_tag; 273187767Sluigi bus_dmamap_t dma_map; 274187767Sluigi bus_dma_segment_t dma_seg; 275187767Sluigi int dma_nseg; 276187767Sluigi}; 277187767Sluigi 278187767Sluigistruct adapter; 279187767Sluigi 280187767Sluigistruct em_int_delay_info { 281187767Sluigi struct adapter *adapter; /* Back-pointer to the adapter struct */ 282187767Sluigi int offset; /* Register offset to read/write */ 283187767Sluigi int value; /* Current value in usecs */ 284187767Sluigi}; 285187767Sluigi 286187767Sluigi/* 287187767Sluigi** Driver queue struct: this is the interrupt container 288187767Sluigi** for the associated tx and rx ring. 289187767Sluigi*/ 290187767Sluigistruct em_queue { 291187767Sluigi struct adapter *adapter; 292187767Sluigi u32 msix; /* This queue's MSIX vector */ 293204591Sluigi u32 eims; /* This queue's EIMS bit */ 294187767Sluigi u32 eitr_setting; 295187767Sluigi struct resource *res; 296187767Sluigi void *tag; 297187767Sluigi struct tx_ring *txr; 298187767Sluigi struct rx_ring *rxr; 299187767Sluigi struct task que_task; 300187767Sluigi struct taskqueue *tq; 301187767Sluigi u64 irqs; 302187767Sluigi}; 303187767Sluigi 304187767Sluigi/* 305187767Sluigi * Transmit ring: one per queue 306187767Sluigi */ 307187767Sluigistruct tx_ring { 308187767Sluigi struct adapter *adapter; 309187767Sluigi u32 me; 310187767Sluigi struct mtx tx_mtx; 311187767Sluigi char mtx_name[16]; 312187767Sluigi struct em_dma_alloc txdma; 313187767Sluigi struct e1000_tx_desc *tx_base; 314187767Sluigi u32 next_avail_desc; 315187767Sluigi u32 next_to_clean; 316187767Sluigi volatile u16 tx_avail; 317187767Sluigi struct em_tx_buffer *tx_buffers; 318187767Sluigi#if __FreeBSD_version >= 800000 319187767Sluigi struct buf_ring *br; 320187767Sluigi#endif 321187767Sluigi bus_dma_tag_t txtag; 322187767Sluigi 323187767Sluigi u32 bytes; 324187767Sluigi u32 packets; 325187767Sluigi 326187767Sluigi bool watchdog_check; 327187767Sluigi int watchdog_time; 328187767Sluigi u64 no_desc_avail; 329187767Sluigi u64 tx_packets; 330187767Sluigi}; 331187767Sluigi 332187767Sluigi/* 333187767Sluigi * Receive ring: one per queue 334204591Sluigi */ 335187767Sluigistruct rx_ring { 336187767Sluigi struct adapter *adapter; 337187767Sluigi u32 me; 338187767Sluigi struct em_dma_alloc rxdma; 339187767Sluigi union e1000_adv_rx_desc *rx_base; 340187767Sluigi struct lro_ctrl lro; 341187767Sluigi bool lro_enabled; 342187767Sluigi bool hdr_split; 343187767Sluigi bool discard; 344187767Sluigi struct mtx rx_mtx; 345187767Sluigi char mtx_name[16]; 346187767Sluigi u32 last_cleaned; 347187767Sluigi u32 next_to_check; 348187767Sluigi struct em_rx_buf *rx_buffers; 349187767Sluigi bus_dma_tag_t rx_htag; /* dma tag for rx head */ 350187767Sluigi bus_dmamap_t rx_hspare_map; 351187767Sluigi bus_dma_tag_t rx_ptag; /* dma tag for rx packet */ 352187767Sluigi bus_dmamap_t rx_pspare_map; 353187767Sluigi /* 354187767Sluigi * First/last mbuf pointers, for 355187767Sluigi * collecting multisegment RX packets. 356187767Sluigi */ 357187767Sluigi struct mbuf *fmp; 358187767Sluigi struct mbuf *lmp; 359222745Sae 360187767Sluigi /* Temporary stats used by AIM */ 361220802Sglebius u32 bytes; 362187767Sluigi u32 packets; 363187767Sluigi 364187767Sluigi /* Soft stats */ 365187767Sluigi u64 rx_split_packets; 366204591Sluigi u64 rx_discarded; 367204591Sluigi u64 rx_packets; 368204591Sluigi u64 rx_bytes; 369204591Sluigi}; 370187767Sluigi 371187767Sluigistruct adapter { 372187767Sluigi struct ifnet *ifp; 373187767Sluigi struct e1000_hw hw; 374187767Sluigi 375187767Sluigi struct e1000_osdep osdep; 376187767Sluigi struct device *dev; 377187767Sluigi 378187767Sluigi struct resource *pci_mem; 379187767Sluigi struct resource *msix_mem; 380187767Sluigi struct resource *res; 381187767Sluigi void *tag; 382187767Sluigi u32 eims_mask; 383187767Sluigi 384187767Sluigi int linkvec; 385187767Sluigi int link_mask; 386187767Sluigi int link_irq; 387187767Sluigi 388187767Sluigi struct ifmedia media; 389187767Sluigi struct callout timer; 390187767Sluigi int msix; /* total vectors allocated */ 391187767Sluigi int if_flags; 392187767Sluigi int max_frame_size; 393187767Sluigi int min_frame_size; 394187767Sluigi struct mtx core_mtx; 395187767Sluigi int em_insert_vlan_header; 396187767Sluigi struct task rxtx_task; 397187767Sluigi struct taskqueue *tq; /* private task queue */ 398187767Sluigi u16 num_queues; 399187767Sluigi 400187767Sluigi eventhandler_tag vlan_attach; 401204591Sluigi eventhandler_tag vlan_detach; 402187767Sluigi u32 num_vlans; 403187767Sluigi 404187767Sluigi /* Management and WOL features */ 405187767Sluigi int wol; 406187767Sluigi int has_manage; 407187767Sluigi 408187767Sluigi /* Info about the board itself */ 409204591Sluigi u8 link_active; 410187767Sluigi u16 link_speed; 411187767Sluigi u16 link_duplex; 412187767Sluigi u32 smartspeed; 413204591Sluigi 414187767Sluigi /* Interface queues */ 415204591Sluigi struct em_queue *queues; 416187767Sluigi 417187767Sluigi /* 418187767Sluigi * Transmit rings 419187767Sluigi */ 420187767Sluigi struct tx_ring *tx_rings; 421187767Sluigi u16 num_tx_desc; 422204591Sluigi 423187767Sluigi /* 424187767Sluigi * Receive rings 425187767Sluigi */ 426187767Sluigi struct rx_ring *rx_rings; 427187767Sluigi bool rx_hdr_split; 428187767Sluigi u16 num_rx_desc; 429187767Sluigi int rx_process_limit; 430220802Sglebius u32 rx_mbuf_sz; 431187767Sluigi u32 rx_mask; 432187767Sluigi 433187767Sluigi /* Misc stats maintained by the driver */ 434187767Sluigi unsigned long dropped_pkts; 435187767Sluigi unsigned long mbuf_defrag_failed; 436187767Sluigi unsigned long mbuf_header_failed; 437187767Sluigi unsigned long mbuf_packet_failed; 438187767Sluigi unsigned long no_tx_map_avail; 439204591Sluigi unsigned long no_tx_dma_setup; 440187767Sluigi unsigned long watchdog_events; 441187767Sluigi unsigned long rx_overruns; 442187767Sluigi 443187767Sluigi /* 82547 workaround */ 444187767Sluigi uint32_t tx_fifo_size; 445187767Sluigi uint32_t tx_fifo_head; 446187767Sluigi uint32_t tx_fifo_head_addr; 447187767Sluigi uint64_t tx_fifo_reset_cnt; 448222744Sae uint64_t tx_fifo_wrk_cnt; 449187767Sluigi uint32_t tx_head_addr; 450187767Sluigi 451187767Sluigi /* For 82544 PCIX Workaround */ 452187767Sluigi boolean_t pcix_82544; 453187767Sluigi boolean_t in_detach; 454187767Sluigi 455187767Sluigi struct e1000_hw_stats stats; 456187767Sluigi}; 457187767Sluigi 458187767Sluigi/* ****************************************************************************** 459187767Sluigi * vendor_info_array 460187767Sluigi * 461187767Sluigi * This array contains the list of Subvendor/Subdevice IDs on which the driver 462187767Sluigi * should load. 463187767Sluigi * 464187767Sluigi * ******************************************************************************/ 465187767Sluigitypedef struct _em_vendor_info_t { 466187767Sluigi unsigned int vendor_id; 467187767Sluigi unsigned int device_id; 468187767Sluigi unsigned int subvendor_id; 469187767Sluigi unsigned int subdevice_id; 470187767Sluigi unsigned int index; 471187767Sluigi} em_vendor_info_t; 472187767Sluigi 473187767Sluigistruct em_buffer { 474187767Sluigi int next_eop; /* Index of the desc to watch */ 475187767Sluigi struct mbuf *m_head; 476187767Sluigi bus_dmamap_t map; /* bus_dma map for packet */ 477187767Sluigi}; 478187767Sluigi 479187767Sluigi/* For 82544 PCIX Workaround */ 480187767Sluigitypedef struct _ADDRESS_LENGTH_PAIR 481187767Sluigi{ 482187767Sluigi uint64_t address; 483187767Sluigi uint32_t length; 484187767Sluigi} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 485187767Sluigi 486187767Sluigitypedef struct _DESCRIPTOR_PAIR 487187767Sluigi{ 488187767Sluigi ADDRESS_LENGTH_PAIR descriptor[4]; 489187767Sluigi uint32_t elements; 490187767Sluigi} DESC_ARRAY, *PDESC_ARRAY; 491187767Sluigi 492187767Sluigi#define EM_CORE_LOCK_INIT(_sc, _name) \ 493187767Sluigi mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 494187767Sluigi#define EM_TX_LOCK_INIT(_sc, _name) \ 495187767Sluigi mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 496187767Sluigi#define EM_RX_LOCK_INIT(_sc, _name) \ 497187767Sluigi mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 498187767Sluigi#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 499187767Sluigi#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 500187767Sluigi#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 501187767Sluigi#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 502187767Sluigi#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 503187767Sluigi#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 504187767Sluigi#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 505187767Sluigi#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 506187767Sluigi#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 507187767Sluigi#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 508187767Sluigi#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 509187767Sluigi#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 510187767Sluigi 511187767Sluigi#endif /* _EM_H_DEFINED_ */ 512187767Sluigi