if_em.h revision 176671
1/************************************************************************** 2 3Copyright (c) 2001-2008, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/if_em.h 176671 2008-02-29 22:38:12Z jfv $ */ 34 35#ifndef _EM_H_DEFINED_ 36#define _EM_H_DEFINED_ 37 38/* Tunables */ 39 40/* Set FAST Interrupt handling as default */ 41#define EM_FAST_IRQ 42 43/* 44 * EM_TXD: Maximum number of Transmit Descriptors 45 * Valid Range: 80-256 for 82542 and 82543-based adapters 46 * 80-4096 for others 47 * Default Value: 256 48 * This value is the number of transmit descriptors allocated by the driver. 49 * Increasing this value allows the driver to queue more transmits. Each 50 * descriptor is 16 bytes. 51 * Since TDLEN should be multiple of 128bytes, the number of transmit 52 * desscriptors should meet the following condition. 53 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 54 */ 55#define EM_MIN_TXD 80 56#define EM_MAX_TXD_82543 256 57#define EM_MAX_TXD 4096 58#define EM_DEFAULT_TXD EM_MAX_TXD_82543 59 60/* 61 * EM_RXD - Maximum number of receive Descriptors 62 * Valid Range: 80-256 for 82542 and 82543-based adapters 63 * 80-4096 for others 64 * Default Value: 256 65 * This value is the number of receive descriptors allocated by the driver. 66 * Increasing this value allows the driver to buffer more incoming packets. 67 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 68 * descriptor. The maximum MTU size is 16110. 69 * Since TDLEN should be multiple of 128bytes, the number of transmit 70 * desscriptors should meet the following condition. 71 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 72 */ 73#define EM_MIN_RXD 80 74#define EM_MAX_RXD_82543 256 75#define EM_MAX_RXD 4096 76#define EM_DEFAULT_RXD EM_MAX_RXD_82543 77 78/* 79 * EM_TIDV - Transmit Interrupt Delay Value 80 * Valid Range: 0-65535 (0=off) 81 * Default Value: 64 82 * This value delays the generation of transmit interrupts in units of 83 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 84 * efficiency if properly tuned for specific network traffic. If the 85 * system is reporting dropped transmits, this value may be set too high 86 * causing the driver to run out of available transmit descriptors. 87 */ 88#define EM_TIDV 64 89 90/* 91 * EM_TADV - Transmit Absolute Interrupt Delay Value 92 * (Not valid for 82542/82543/82544) 93 * Valid Range: 0-65535 (0=off) 94 * Default Value: 64 95 * This value, in units of 1.024 microseconds, limits the delay in which a 96 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 97 * this value ensures that an interrupt is generated after the initial 98 * packet is sent on the wire within the set amount of time. Proper tuning, 99 * along with EM_TIDV, may improve traffic throughput in specific 100 * network conditions. 101 */ 102#define EM_TADV 64 103 104/* 105 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 106 * Valid Range: 0-65535 (0=off) 107 * Default Value: 0 108 * This value delays the generation of receive interrupts in units of 1.024 109 * microseconds. Receive interrupt reduction can improve CPU efficiency if 110 * properly tuned for specific network traffic. Increasing this value adds 111 * extra latency to frame reception and can end up decreasing the throughput 112 * of TCP traffic. If the system is reporting dropped receives, this value 113 * may be set too high, causing the driver to run out of available receive 114 * descriptors. 115 * 116 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 117 * may hang (stop transmitting) under certain network conditions. 118 * If this occurs a WATCHDOG message is logged in the system 119 * event log. In addition, the controller is automatically reset, 120 * restoring the network connection. To eliminate the potential 121 * for the hang ensure that EM_RDTR is set to 0. 122 */ 123#define EM_RDTR 0 124 125/* 126 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 127 * Valid Range: 0-65535 (0=off) 128 * Default Value: 64 129 * This value, in units of 1.024 microseconds, limits the delay in which a 130 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 131 * this value ensures that an interrupt is generated after the initial 132 * packet is received within the set amount of time. Proper tuning, 133 * along with EM_RDTR, may improve traffic throughput in specific network 134 * conditions. 135 */ 136#define EM_RADV 64 137 138/* 139 * This parameter controls the duration of transmit watchdog timer. 140 */ 141#define EM_TX_TIMEOUT 5 142 143/* 144 * This parameter controls when the driver calls the routine to reclaim 145 * transmit descriptors. 146 */ 147#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149 150/* 151 * This parameter controls whether or not autonegotation is enabled. 152 * 0 - Disable autonegotiation 153 * 1 - Enable autonegotiation 154 */ 155#define DO_AUTO_NEG 1 156 157/* 158 * This parameter control whether or not the driver will wait for 159 * autonegotiation to complete. 160 * 1 - Wait for autonegotiation to complete 161 * 0 - Don't wait for autonegotiation to complete 162 */ 163#define WAIT_FOR_AUTO_NEG_DEFAULT 0 164 165/* Tunables -- End */ 166 167#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 168 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 169 ADVERTISE_1000_FULL) 170 171#define AUTO_ALL_MODES 0 172 173/* PHY master/slave setting */ 174#define EM_MASTER_SLAVE e1000_ms_hw_default 175 176/* 177 * Micellaneous constants 178 */ 179#define EM_VENDOR_ID 0x8086 180#define EM_FLASH 0x0014 181 182#define EM_JUMBO_PBA 0x00000028 183#define EM_DEFAULT_PBA 0x00000030 184#define EM_SMARTSPEED_DOWNSHIFT 3 185#define EM_SMARTSPEED_MAX 15 186#define EM_MAX_INTR 10 187 188#define MAX_NUM_MULTICAST_ADDRESSES 128 189#define PCI_ANY_ID (~0U) 190#define ETHER_ALIGN 2 191#define EM_FC_PAUSE_TIME 0x0680 192#define EM_EEPROM_APME 0x400; 193 194/* Code compatilbility between 6 and 7 */ 195#ifndef ETHER_BPF_MTAP 196#define ETHER_BPF_MTAP BPF_MTAP 197#endif 198 199/* 200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202 * also optimize cache line size effect. H/W supports up to cache line size 128. 203 */ 204#define EM_DBA_ALIGN 128 205 206#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207 208/* PCI Config defines */ 209#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 210#define EM_BAR_TYPE_MASK 0x00000001 211#define EM_BAR_TYPE_MMEM 0x00000000 212#define EM_BAR_TYPE_IO 0x00000001 213#define EM_BAR_TYPE_FLASH 0x0014 214#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 215#define EM_BAR_MEM_TYPE_MASK 0x00000006 216#define EM_BAR_MEM_TYPE_32BIT 0x00000000 217#define EM_BAR_MEM_TYPE_64BIT 0x00000004 218#define EM_MSIX_BAR 3 /* On 82575 */ 219 220/* Defines for printing debug information */ 221#define DEBUG_INIT 0 222#define DEBUG_IOCTL 0 223#define DEBUG_HW 0 224 225#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 226#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 227#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 228#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 229#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 230#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 231#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 232#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 233#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 234 235#define EM_MAX_SCATTER 64 236#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 237#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 238#define ETH_ZLEN 60 239#define ETH_ADDR_LEN 6 240#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 241 242/* Used in for 82547 10Mb Half workaround */ 243#define EM_PBA_BYTES_SHIFT 0xA 244#define EM_TX_HEAD_ADDR_SHIFT 7 245#define EM_PBA_TX_MASK 0xFFFF0000 246#define EM_FIFO_HDR 0x10 247#define EM_82547_PKT_THRESH 0x3e0 248 249 250struct adapter; 251 252struct em_int_delay_info { 253 struct adapter *adapter; /* Back-pointer to the adapter struct */ 254 int offset; /* Register offset to read/write */ 255 int value; /* Current value in usecs */ 256}; 257 258/* 259 * Bus dma allocation structure used by 260 * e1000_dma_malloc and e1000_dma_free. 261 */ 262struct em_dma_alloc { 263 bus_addr_t dma_paddr; 264 caddr_t dma_vaddr; 265 bus_dma_tag_t dma_tag; 266 bus_dmamap_t dma_map; 267 bus_dma_segment_t dma_seg; 268 int dma_nseg; 269}; 270 271/* Our adapter structure */ 272struct adapter { 273 struct ifnet *ifp; 274 struct e1000_hw hw; 275 276 /* FreeBSD operating-system-specific structures. */ 277 struct e1000_osdep osdep; 278 struct device *dev; 279 280 struct resource *memory; 281 struct resource *flash; 282 struct resource *msix; 283 284 struct resource *ioport; 285 int io_rid; 286 287 /* 82574 uses 3 int vectors */ 288 struct resource *res[3]; 289 void *tag[3]; 290 int rid[3]; 291 292 struct ifmedia media; 293 struct callout timer; 294 struct callout tx_fifo_timer; 295 int watchdog_timer; 296 int msi; 297 int if_flags; 298 int max_frame_size; 299 int min_frame_size; 300 struct mtx core_mtx; 301 struct mtx tx_mtx; 302 int em_insert_vlan_header; 303 304 /* Task for FAST handling */ 305 struct task link_task; 306 struct task rxtx_task; 307 struct task rx_task; 308 struct task tx_task; 309 struct taskqueue *tq; /* private task queue */ 310 311 /* Management and WOL features */ 312 int wol; 313 int has_manage; 314 315 /* Info about the board itself */ 316 uint8_t link_active; 317 uint16_t link_speed; 318 uint16_t link_duplex; 319 uint32_t smartspeed; 320 struct em_int_delay_info tx_int_delay; 321 struct em_int_delay_info tx_abs_int_delay; 322 struct em_int_delay_info rx_int_delay; 323 struct em_int_delay_info rx_abs_int_delay; 324 325 /* 326 * Transmit definitions 327 * 328 * We have an array of num_tx_desc descriptors (handled 329 * by the controller) paired with an array of tx_buffers 330 * (at tx_buffer_area). 331 * The index of the next available descriptor is next_avail_tx_desc. 332 * The number of remaining tx_desc is num_tx_desc_avail. 333 */ 334 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 335 struct e1000_tx_desc *tx_desc_base; 336 uint32_t next_avail_tx_desc; 337 uint32_t next_tx_to_clean; 338 volatile uint16_t num_tx_desc_avail; 339 uint16_t num_tx_desc; 340 uint32_t txd_cmd; 341 struct em_buffer *tx_buffer_area; 342 bus_dma_tag_t txtag; /* dma tag for tx */ 343 uint32_t tx_tso; /* last tx was tso */ 344 345 /* 346 * Receive definitions 347 * 348 * we have an array of num_rx_desc rx_desc (handled by the 349 * controller), and paired with an array of rx_buffers 350 * (at rx_buffer_area). 351 * The next pair to check on receive is at offset next_rx_desc_to_check 352 */ 353 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 354 struct e1000_rx_desc *rx_desc_base; 355 uint32_t next_rx_desc_to_check; 356 uint32_t rx_buffer_len; 357 uint16_t num_rx_desc; 358 int rx_process_limit; 359 struct em_buffer *rx_buffer_area; 360 bus_dma_tag_t rxtag; 361 bus_dmamap_t rx_sparemap; 362 363 /* 364 * First/last mbuf pointers, for 365 * collecting multisegment RX packets. 366 */ 367 struct mbuf *fmp; 368 struct mbuf *lmp; 369 370 /* Misc stats maintained by the driver */ 371 unsigned long dropped_pkts; 372 unsigned long mbuf_alloc_failed; 373 unsigned long mbuf_cluster_failed; 374 unsigned long no_tx_desc_avail1; 375 unsigned long no_tx_desc_avail2; 376 unsigned long no_tx_map_avail; 377 unsigned long no_tx_dma_setup; 378 unsigned long watchdog_events; 379 unsigned long rx_overruns; 380 unsigned long rx_irq; 381 unsigned long tx_irq; 382 383 /* 82547 workaround */ 384 uint32_t tx_fifo_size; 385 uint32_t tx_fifo_head; 386 uint32_t tx_fifo_head_addr; 387 uint64_t tx_fifo_reset_cnt; 388 uint64_t tx_fifo_wrk_cnt; 389 uint32_t tx_head_addr; 390 391 /* For 82544 PCIX Workaround */ 392 boolean_t pcix_82544; 393 boolean_t in_detach; 394 395 396 struct e1000_hw_stats stats; 397}; 398 399/* ****************************************************************************** 400 * vendor_info_array 401 * 402 * This array contains the list of Subvendor/Subdevice IDs on which the driver 403 * should load. 404 * 405 * ******************************************************************************/ 406typedef struct _em_vendor_info_t { 407 unsigned int vendor_id; 408 unsigned int device_id; 409 unsigned int subvendor_id; 410 unsigned int subdevice_id; 411 unsigned int index; 412} em_vendor_info_t; 413 414 415struct em_buffer { 416 int next_eop; /* Index of the desc to watch */ 417 struct mbuf *m_head; 418 bus_dmamap_t map; /* bus_dma map for packet */ 419}; 420 421/* For 82544 PCIX Workaround */ 422typedef struct _ADDRESS_LENGTH_PAIR 423{ 424 uint64_t address; 425 uint32_t length; 426} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 427 428typedef struct _DESCRIPTOR_PAIR 429{ 430 ADDRESS_LENGTH_PAIR descriptor[4]; 431 uint32_t elements; 432} DESC_ARRAY, *PDESC_ARRAY; 433 434#define EM_CORE_LOCK_INIT(_sc, _name) \ 435 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 436#define EM_TX_LOCK_INIT(_sc, _name) \ 437 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 438#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 439#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 440#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 441#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 442#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 443#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 444#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 445#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 446 447#endif /* _EM_H_DEFINED_ */ 448