if_em.h revision 176667
1/************************************************************************** 2 3Copyright (c) 2001-2008, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33/* $FreeBSD: head/sys/dev/em/if_em.h 176667 2008-02-29 21:50:11Z jfv $ */ 34 35#ifndef _EM_H_DEFINED_ 36#define _EM_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * EM_TXD: Maximum number of Transmit Descriptors 42 * Valid Range: 80-256 for 82542 and 82543-based adapters 43 * 80-4096 for others 44 * Default Value: 256 45 * This value is the number of transmit descriptors allocated by the driver. 46 * Increasing this value allows the driver to queue more transmits. Each 47 * descriptor is 16 bytes. 48 * Since TDLEN should be multiple of 128bytes, the number of transmit 49 * desscriptors should meet the following condition. 50 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 51 */ 52#define EM_MIN_TXD 80 53#define EM_MAX_TXD_82543 256 54#define EM_MAX_TXD 4096 55#define EM_DEFAULT_TXD EM_MAX_TXD_82543 56 57/* 58 * EM_RXD - Maximum number of receive Descriptors 59 * Valid Range: 80-256 for 82542 and 82543-based adapters 60 * 80-4096 for others 61 * Default Value: 256 62 * This value is the number of receive descriptors allocated by the driver. 63 * Increasing this value allows the driver to buffer more incoming packets. 64 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 65 * descriptor. The maximum MTU size is 16110. 66 * Since TDLEN should be multiple of 128bytes, the number of transmit 67 * desscriptors should meet the following condition. 68 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 69 */ 70#define EM_MIN_RXD 80 71#define EM_MAX_RXD_82543 256 72#define EM_MAX_RXD 4096 73#define EM_DEFAULT_RXD EM_MAX_RXD_82543 74 75/* 76 * EM_TIDV - Transmit Interrupt Delay Value 77 * Valid Range: 0-65535 (0=off) 78 * Default Value: 64 79 * This value delays the generation of transmit interrupts in units of 80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 81 * efficiency if properly tuned for specific network traffic. If the 82 * system is reporting dropped transmits, this value may be set too high 83 * causing the driver to run out of available transmit descriptors. 84 */ 85#define EM_TIDV 64 86 87/* 88 * EM_TADV - Transmit Absolute Interrupt Delay Value 89 * (Not valid for 82542/82543/82544) 90 * Valid Range: 0-65535 (0=off) 91 * Default Value: 64 92 * This value, in units of 1.024 microseconds, limits the delay in which a 93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94 * this value ensures that an interrupt is generated after the initial 95 * packet is sent on the wire within the set amount of time. Proper tuning, 96 * along with EM_TIDV, may improve traffic throughput in specific 97 * network conditions. 98 */ 99#define EM_TADV 64 100 101/* 102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103 * Valid Range: 0-65535 (0=off) 104 * Default Value: 0 105 * This value delays the generation of receive interrupts in units of 1.024 106 * microseconds. Receive interrupt reduction can improve CPU efficiency if 107 * properly tuned for specific network traffic. Increasing this value adds 108 * extra latency to frame reception and can end up decreasing the throughput 109 * of TCP traffic. If the system is reporting dropped receives, this value 110 * may be set too high, causing the driver to run out of available receive 111 * descriptors. 112 * 113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114 * may hang (stop transmitting) under certain network conditions. 115 * If this occurs a WATCHDOG message is logged in the system 116 * event log. In addition, the controller is automatically reset, 117 * restoring the network connection. To eliminate the potential 118 * for the hang ensure that EM_RDTR is set to 0. 119 */ 120#define EM_RDTR 0 121 122/* 123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124 * Valid Range: 0-65535 (0=off) 125 * Default Value: 64 126 * This value, in units of 1.024 microseconds, limits the delay in which a 127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128 * this value ensures that an interrupt is generated after the initial 129 * packet is received within the set amount of time. Proper tuning, 130 * along with EM_RDTR, may improve traffic throughput in specific network 131 * conditions. 132 */ 133#define EM_RADV 64 134 135/* 136 * This parameter controls the duration of transmit watchdog timer. 137 */ 138#define EM_TX_TIMEOUT 5 139 140/* 141 * This parameter controls when the driver calls the routine to reclaim 142 * transmit descriptors. 143 */ 144#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 145#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 146 147/* 148 * This parameter controls whether or not autonegotation is enabled. 149 * 0 - Disable autonegotiation 150 * 1 - Enable autonegotiation 151 */ 152#define DO_AUTO_NEG 1 153 154/* 155 * This parameter control whether or not the driver will wait for 156 * autonegotiation to complete. 157 * 1 - Wait for autonegotiation to complete 158 * 0 - Don't wait for autonegotiation to complete 159 */ 160#define WAIT_FOR_AUTO_NEG_DEFAULT 0 161 162/* Tunables -- End */ 163 164#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 165 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 166 ADVERTISE_1000_FULL) 167 168#define AUTO_ALL_MODES 0 169 170/* PHY master/slave setting */ 171#define EM_MASTER_SLAVE e1000_ms_hw_default 172 173/* 174 * Micellaneous constants 175 */ 176#define EM_VENDOR_ID 0x8086 177#define EM_FLASH 0x0014 178 179#define EM_JUMBO_PBA 0x00000028 180#define EM_DEFAULT_PBA 0x00000030 181#define EM_SMARTSPEED_DOWNSHIFT 3 182#define EM_SMARTSPEED_MAX 15 183#define EM_MAX_INTR 10 184 185#define MAX_NUM_MULTICAST_ADDRESSES 128 186#define PCI_ANY_ID (~0U) 187#define ETHER_ALIGN 2 188#define EM_FC_PAUSE_TIME 0x0680 189#define EM_EEPROM_APME 0x400; 190 191/* Code compatilbility between 6 and 7 */ 192#ifndef ETHER_BPF_MTAP 193#define ETHER_BPF_MTAP BPF_MTAP 194#endif 195 196/* 197 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 198 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 199 * also optimize cache line size effect. H/W supports up to cache line size 128. 200 */ 201#define EM_DBA_ALIGN 128 202 203#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 204 205/* PCI Config defines */ 206#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 207#define EM_BAR_TYPE_MASK 0x00000001 208#define EM_BAR_TYPE_MMEM 0x00000000 209#define EM_BAR_TYPE_IO 0x00000001 210#define EM_BAR_TYPE_FLASH 0x0014 211#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 212#define EM_BAR_MEM_TYPE_MASK 0x00000006 213#define EM_BAR_MEM_TYPE_32BIT 0x00000000 214#define EM_BAR_MEM_TYPE_64BIT 0x00000004 215#define EM_MSIX_BAR 3 /* On 82575 */ 216 217/* Defines for printing debug information */ 218#define DEBUG_INIT 0 219#define DEBUG_IOCTL 0 220#define DEBUG_HW 0 221 222#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 223#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 224#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 225#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 226#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 227#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 228#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 229#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 230#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 231 232#define EM_MAX_SCATTER 64 233#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 234#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 235#define ETH_ZLEN 60 236#define ETH_ADDR_LEN 6 237#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 238 239/* Used in for 82547 10Mb Half workaround */ 240#define EM_PBA_BYTES_SHIFT 0xA 241#define EM_TX_HEAD_ADDR_SHIFT 7 242#define EM_PBA_TX_MASK 0xFFFF0000 243#define EM_FIFO_HDR 0x10 244#define EM_82547_PKT_THRESH 0x3e0 245 246 247struct adapter; 248 249struct em_int_delay_info { 250 struct adapter *adapter; /* Back-pointer to the adapter struct */ 251 int offset; /* Register offset to read/write */ 252 int value; /* Current value in usecs */ 253}; 254 255/* 256 * Bus dma allocation structure used by 257 * e1000_dma_malloc and e1000_dma_free. 258 */ 259struct em_dma_alloc { 260 bus_addr_t dma_paddr; 261 caddr_t dma_vaddr; 262 bus_dma_tag_t dma_tag; 263 bus_dmamap_t dma_map; 264 bus_dma_segment_t dma_seg; 265 int dma_nseg; 266}; 267 268/* Our adapter structure */ 269struct adapter { 270 struct ifnet *ifp; 271 struct e1000_hw hw; 272 273 /* FreeBSD operating-system-specific structures. */ 274 struct e1000_osdep osdep; 275 struct device *dev; 276 277 struct resource *memory; 278 struct resource *flash; 279 struct resource *msix; 280 281 struct resource *ioport; 282 int io_rid; 283 284 /* 82574 uses 3 int vectors */ 285 struct resource *res[3]; 286 void *tag[3]; 287 int rid[3]; 288 289 struct ifmedia media; 290 struct callout timer; 291 struct callout tx_fifo_timer; 292 int watchdog_timer; 293 int msi; 294 int if_flags; 295 int max_frame_size; 296 int min_frame_size; 297 struct mtx core_mtx; 298 struct mtx tx_mtx; 299 int em_insert_vlan_header; 300 301 /* Task for FAST handling */ 302 struct task link_task; 303 struct task rxtx_task; 304 struct task rx_task; 305 struct task tx_task; 306 struct taskqueue *tq; /* private task queue */ 307 308 /* Management and WOL features */ 309 int wol; 310 int has_manage; 311 312 /* Info about the board itself */ 313 uint8_t link_active; 314 uint16_t link_speed; 315 uint16_t link_duplex; 316 uint32_t smartspeed; 317 struct em_int_delay_info tx_int_delay; 318 struct em_int_delay_info tx_abs_int_delay; 319 struct em_int_delay_info rx_int_delay; 320 struct em_int_delay_info rx_abs_int_delay; 321 322 /* 323 * Transmit definitions 324 * 325 * We have an array of num_tx_desc descriptors (handled 326 * by the controller) paired with an array of tx_buffers 327 * (at tx_buffer_area). 328 * The index of the next available descriptor is next_avail_tx_desc. 329 * The number of remaining tx_desc is num_tx_desc_avail. 330 */ 331 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 332 struct e1000_tx_desc *tx_desc_base; 333 uint32_t next_avail_tx_desc; 334 uint32_t next_tx_to_clean; 335 volatile uint16_t num_tx_desc_avail; 336 uint16_t num_tx_desc; 337 uint32_t txd_cmd; 338 struct em_buffer *tx_buffer_area; 339 bus_dma_tag_t txtag; /* dma tag for tx */ 340 uint32_t tx_tso; /* last tx was tso */ 341 342 /* 343 * Receive definitions 344 * 345 * we have an array of num_rx_desc rx_desc (handled by the 346 * controller), and paired with an array of rx_buffers 347 * (at rx_buffer_area). 348 * The next pair to check on receive is at offset next_rx_desc_to_check 349 */ 350 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 351 struct e1000_rx_desc *rx_desc_base; 352 uint32_t next_rx_desc_to_check; 353 uint32_t rx_buffer_len; 354 uint16_t num_rx_desc; 355 int rx_process_limit; 356 struct em_buffer *rx_buffer_area; 357 bus_dma_tag_t rxtag; 358 bus_dmamap_t rx_sparemap; 359 360 /* 361 * First/last mbuf pointers, for 362 * collecting multisegment RX packets. 363 */ 364 struct mbuf *fmp; 365 struct mbuf *lmp; 366 367 /* Misc stats maintained by the driver */ 368 unsigned long dropped_pkts; 369 unsigned long mbuf_alloc_failed; 370 unsigned long mbuf_cluster_failed; 371 unsigned long no_tx_desc_avail1; 372 unsigned long no_tx_desc_avail2; 373 unsigned long no_tx_map_avail; 374 unsigned long no_tx_dma_setup; 375 unsigned long watchdog_events; 376 unsigned long rx_overruns; 377 unsigned long rx_irq; 378 unsigned long tx_irq; 379 380 /* 82547 workaround */ 381 uint32_t tx_fifo_size; 382 uint32_t tx_fifo_head; 383 uint32_t tx_fifo_head_addr; 384 uint64_t tx_fifo_reset_cnt; 385 uint64_t tx_fifo_wrk_cnt; 386 uint32_t tx_head_addr; 387 388 /* For 82544 PCIX Workaround */ 389 boolean_t pcix_82544; 390 boolean_t in_detach; 391 392 393 struct e1000_hw_stats stats; 394}; 395 396/* ****************************************************************************** 397 * vendor_info_array 398 * 399 * This array contains the list of Subvendor/Subdevice IDs on which the driver 400 * should load. 401 * 402 * ******************************************************************************/ 403typedef struct _em_vendor_info_t { 404 unsigned int vendor_id; 405 unsigned int device_id; 406 unsigned int subvendor_id; 407 unsigned int subdevice_id; 408 unsigned int index; 409} em_vendor_info_t; 410 411 412struct em_buffer { 413 int next_eop; /* Index of the desc to watch */ 414 struct mbuf *m_head; 415 bus_dmamap_t map; /* bus_dma map for packet */ 416}; 417 418/* For 82544 PCIX Workaround */ 419typedef struct _ADDRESS_LENGTH_PAIR 420{ 421 uint64_t address; 422 uint32_t length; 423} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 424 425typedef struct _DESCRIPTOR_PAIR 426{ 427 ADDRESS_LENGTH_PAIR descriptor[4]; 428 uint32_t elements; 429} DESC_ARRAY, *PDESC_ARRAY; 430 431#define EM_CORE_LOCK_INIT(_sc, _name) \ 432 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 433#define EM_TX_LOCK_INIT(_sc, _name) \ 434 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 435#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 436#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 437#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 438#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 439#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 440#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 441#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 442#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 443 444#endif /* _EM_H_DEFINED_ */ 445