if_em.h revision 173789
1163976Sdougb/************************************************************************** 2135446Strhodes 3135446StrhodesCopyright (c) 2001-2007, Intel Corporation 4135446StrhodesAll rights reserved. 5135446Strhodes 6135446StrhodesRedistribution and use in source and binary forms, with or without 7135446Strhodesmodification, are permitted provided that the following conditions are met: 8135446Strhodes 9135446Strhodes 1. Redistributions of source code must retain the above copyright notice, 10135446Strhodes this list of conditions and the following disclaimer. 11135446Strhodes 12135446Strhodes 2. Redistributions in binary form must reproduce the above copyright 13135446Strhodes notice, this list of conditions and the following disclaimer in the 14135446Strhodes documentation and/or other materials provided with the distribution. 15135446Strhodes 16135446Strhodes 3. Neither the name of the Intel Corporation nor the names of its 17135446Strhodes contributors may be used to endorse or promote products derived from 18135446Strhodes this software without specific prior written permission. 19135446Strhodes 20135446StrhodesTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21163976SdougbAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22135446StrhodesIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23135446StrhodesARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24135446StrhodesLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25135446StrhodesCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26135446StrhodesSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27135446StrhodesINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28135446StrhodesCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29135446StrhodesARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30135446StrhodesPOSSIBILITY OF SUCH DAMAGE. 31135446Strhodes 32135446Strhodes***************************************************************************/ 33135446Strhodes/*$FreeBSD: head/sys/dev/em/if_em.h 173789 2007-11-20 22:06:01Z jfv $ */ 34135446Strhodes 35135446Strhodes#ifndef _EM_H_DEFINED_ 36135446Strhodes#define _EM_H_DEFINED_ 37135446Strhodes 38135446Strhodes/* Tunables */ 39135446Strhodes 40135446Strhodes/* Set FAST handling on by default */ 41135446Strhodes#if __FreeBSD_version > 700000 42135446Strhodes#define EM_FAST_IRQ 43135446Strhodes#endif 44135446Strhodes 45135446Strhodes/* 46135446Strhodes * EM_TXD: Maximum number of Transmit Descriptors 47135446Strhodes * Valid Range: 80-256 for 82542 and 82543-based adapters 48135446Strhodes * 80-4096 for others 49135446Strhodes * Default Value: 256 50135446Strhodes * This value is the number of transmit descriptors allocated by the driver. 51135446Strhodes * Increasing this value allows the driver to queue more transmits. Each 52135446Strhodes * descriptor is 16 bytes. 53135446Strhodes * Since TDLEN should be multiple of 128bytes, the number of transmit 54135446Strhodes * desscriptors should meet the following condition. 55135446Strhodes * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 56135446Strhodes */ 57135446Strhodes#define EM_MIN_TXD 80 58135446Strhodes#define EM_MAX_TXD_82543 256 59135446Strhodes#define EM_MAX_TXD 4096 60135446Strhodes#define EM_DEFAULT_TXD EM_MAX_TXD_82543 61135446Strhodes 62135446Strhodes/* 63135446Strhodes * EM_RXD - Maximum number of receive Descriptors 64135446Strhodes * Valid Range: 80-256 for 82542 and 82543-based adapters 65135446Strhodes * 80-4096 for others 66135446Strhodes * Default Value: 256 67135446Strhodes * This value is the number of receive descriptors allocated by the driver. 68135446Strhodes * Increasing this value allows the driver to buffer more incoming packets. 69135446Strhodes * Each descriptor is 16 bytes. A receive buffer is also allocated for each 70135446Strhodes * descriptor. The maximum MTU size is 16110. 71135446Strhodes * Since TDLEN should be multiple of 128bytes, the number of transmit 72135446Strhodes * desscriptors should meet the following condition. 73135446Strhodes * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 74135446Strhodes */ 75135446Strhodes#define EM_MIN_RXD 80 76135446Strhodes#define EM_MAX_RXD_82543 256 77135446Strhodes#define EM_MAX_RXD 4096 78135446Strhodes#define EM_DEFAULT_RXD EM_MAX_RXD_82543 79135446Strhodes 80135446Strhodes/* 81135446Strhodes * EM_TIDV - Transmit Interrupt Delay Value 82135446Strhodes * Valid Range: 0-65535 (0=off) 83135446Strhodes * Default Value: 64 84135446Strhodes * This value delays the generation of transmit interrupts in units of 85135446Strhodes * 1.024 microseconds. Transmit interrupt reduction can improve CPU 86135446Strhodes * efficiency if properly tuned for specific network traffic. If the 87135446Strhodes * system is reporting dropped transmits, this value may be set too high 88135446Strhodes * causing the driver to run out of available transmit descriptors. 89135446Strhodes */ 90135446Strhodes#define EM_TIDV 64 91135446Strhodes 92135446Strhodes/* 93135446Strhodes * EM_TADV - Transmit Absolute Interrupt Delay Value 94135446Strhodes * (Not valid for 82542/82543/82544) 95135446Strhodes * Valid Range: 0-65535 (0=off) 96135446Strhodes * Default Value: 64 97135446Strhodes * This value, in units of 1.024 microseconds, limits the delay in which a 98135446Strhodes * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 99135446Strhodes * this value ensures that an interrupt is generated after the initial 100135446Strhodes * packet is sent on the wire within the set amount of time. Proper tuning, 101135446Strhodes * along with EM_TIDV, may improve traffic throughput in specific 102135446Strhodes * network conditions. 103135446Strhodes */ 104135446Strhodes#define EM_TADV 64 105135446Strhodes 106135446Strhodes/* 107135446Strhodes * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 108135446Strhodes * Valid Range: 0-65535 (0=off) 109135446Strhodes * Default Value: 0 110135446Strhodes * This value delays the generation of receive interrupts in units of 1.024 111135446Strhodes * microseconds. Receive interrupt reduction can improve CPU efficiency if 112135446Strhodes * properly tuned for specific network traffic. Increasing this value adds 113135446Strhodes * extra latency to frame reception and can end up decreasing the throughput 114135446Strhodes * of TCP traffic. If the system is reporting dropped receives, this value 115135446Strhodes * may be set too high, causing the driver to run out of available receive 116135446Strhodes * descriptors. 117135446Strhodes * 118135446Strhodes * CAUTION: When setting EM_RDTR to a value other than 0, adapters 119135446Strhodes * may hang (stop transmitting) under certain network conditions. 120135446Strhodes * If this occurs a WATCHDOG message is logged in the system 121135446Strhodes * event log. In addition, the controller is automatically reset, 122135446Strhodes * restoring the network connection. To eliminate the potential 123135446Strhodes * for the hang ensure that EM_RDTR is set to 0. 124135446Strhodes */ 125135446Strhodes#define EM_RDTR 0 126135446Strhodes 127135446Strhodes/* 128135446Strhodes * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 129135446Strhodes * Valid Range: 0-65535 (0=off) 130135446Strhodes * Default Value: 64 131135446Strhodes * This value, in units of 1.024 microseconds, limits the delay in which a 132135446Strhodes * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 133135446Strhodes * this value ensures that an interrupt is generated after the initial 134135446Strhodes * packet is received within the set amount of time. Proper tuning, 135135446Strhodes * along with EM_RDTR, may improve traffic throughput in specific network 136135446Strhodes * conditions. 137135446Strhodes */ 138135446Strhodes#define EM_RADV 64 139135446Strhodes 140135446Strhodes/* 141135446Strhodes * This parameter controls the duration of transmit watchdog timer. 142135446Strhodes */ 143135446Strhodes#define EM_TX_TIMEOUT 5 144135446Strhodes 145135446Strhodes/* 146135446Strhodes * This parameter controls when the driver calls the routine to reclaim 147135446Strhodes * transmit descriptors. 148135446Strhodes */ 149135446Strhodes#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 150135446Strhodes#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 151135446Strhodes 152135446Strhodes/* 153135446Strhodes * This parameter controls whether or not autonegotation is enabled. 154135446Strhodes * 0 - Disable autonegotiation 155135446Strhodes * 1 - Enable autonegotiation 156135446Strhodes */ 157135446Strhodes#define DO_AUTO_NEG 1 158135446Strhodes 159135446Strhodes/* 160135446Strhodes * This parameter control whether or not the driver will wait for 161135446Strhodes * autonegotiation to complete. 162135446Strhodes * 1 - Wait for autonegotiation to complete 163135446Strhodes * 0 - Don't wait for autonegotiation to complete 164135446Strhodes */ 165135446Strhodes#define WAIT_FOR_AUTO_NEG_DEFAULT 0 166135446Strhodes 167135446Strhodes/* Tunables -- End */ 168135446Strhodes 169135446Strhodes#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 170135446Strhodes ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 171135446Strhodes ADVERTISE_1000_FULL) 172135446Strhodes 173135446Strhodes#define AUTO_ALL_MODES 0 174135446Strhodes 175135446Strhodes/* PHY master/slave setting */ 176135446Strhodes#define EM_MASTER_SLAVE e1000_ms_hw_default 177135446Strhodes 178135446Strhodes/* 179135446Strhodes * Micellaneous constants 180135446Strhodes */ 181135446Strhodes#define EM_VENDOR_ID 0x8086 182135446Strhodes#define EM_FLASH 0x0014 183135446Strhodes 184135446Strhodes#define EM_JUMBO_PBA 0x00000028 185135446Strhodes#define EM_DEFAULT_PBA 0x00000030 186135446Strhodes#define EM_SMARTSPEED_DOWNSHIFT 3 187135446Strhodes#define EM_SMARTSPEED_MAX 15 188135446Strhodes#define EM_MAX_INTR 10 189135446Strhodes 190135446Strhodes#define MAX_NUM_MULTICAST_ADDRESSES 128 191135446Strhodes#define PCI_ANY_ID (~0U) 192135446Strhodes#define ETHER_ALIGN 2 193135446Strhodes#define EM_FC_PAUSE_TIME 0x0680 194135446Strhodes#define EM_EEPROM_APME 0x400; 195135446Strhodes 196135446Strhodes/* Code compatilbility between 6 and 7 */ 197135446Strhodes#ifndef ETHER_BPF_MTAP 198135446Strhodes#define ETHER_BPF_MTAP BPF_MTAP 199135446Strhodes#endif 200135446Strhodes 201135446Strhodes/* 202135446Strhodes * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 203135446Strhodes * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 204135446Strhodes * also optimize cache line size effect. H/W supports up to cache line size 128. 205135446Strhodes */ 206135446Strhodes#define EM_DBA_ALIGN 128 207135446Strhodes 208135446Strhodes#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 209135446Strhodes 210135446Strhodes/* PCI Config defines */ 211135446Strhodes#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 212135446Strhodes#define EM_BAR_TYPE_MASK 0x00000001 213135446Strhodes#define EM_BAR_TYPE_MMEM 0x00000000 214135446Strhodes#define EM_BAR_TYPE_IO 0x00000001 215135446Strhodes#define EM_BAR_TYPE_FLASH 0x0014 216135446Strhodes#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 217135446Strhodes#define EM_BAR_MEM_TYPE_MASK 0x00000006 218135446Strhodes#define EM_BAR_MEM_TYPE_32BIT 0x00000000 219135446Strhodes#define EM_BAR_MEM_TYPE_64BIT 0x00000004 220135446Strhodes#define EM_MSIX_BAR 3 /* On 82575 */ 221135446Strhodes 222135446Strhodes/* Defines for printing debug information */ 223135446Strhodes#define DEBUG_INIT 0 224135446Strhodes#define DEBUG_IOCTL 0 225135446Strhodes#define DEBUG_HW 0 226135446Strhodes 227135446Strhodes#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 228135446Strhodes#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 229135446Strhodes#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 230135446Strhodes#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 231135446Strhodes#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 232135446Strhodes#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 233135446Strhodes#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 234135446Strhodes#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 235135446Strhodes#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 236135446Strhodes 237135446Strhodes#define EM_MAX_SCATTER 64 238135446Strhodes#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 239135446Strhodes#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 240135446Strhodes#define ETH_ZLEN 60 241135446Strhodes#define ETH_ADDR_LEN 6 242135446Strhodes#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 243135446Strhodes 244135446Strhodesstruct adapter; 245135446Strhodes 246135446Strhodesstruct em_int_delay_info { 247135446Strhodes struct adapter *adapter; /* Back-pointer to the adapter struct */ 248135446Strhodes int offset; /* Register offset to read/write */ 249135446Strhodes int value; /* Current value in usecs */ 250135446Strhodes}; 251135446Strhodes 252135446Strhodes/* 253135446Strhodes * Bus dma allocation structure used by 254135446Strhodes * e1000_dma_malloc and e1000_dma_free. 255135446Strhodes */ 256135446Strhodesstruct em_dma_alloc { 257135446Strhodes bus_addr_t dma_paddr; 258135446Strhodes caddr_t dma_vaddr; 259135446Strhodes bus_dma_tag_t dma_tag; 260135446Strhodes bus_dmamap_t dma_map; 261135446Strhodes bus_dma_segment_t dma_seg; 262135446Strhodes int dma_nseg; 263135446Strhodes}; 264153816Sdougb 265143731Sdougb/* Our adapter structure */ 266143731Sdougbstruct adapter { 267143731Sdougb struct ifnet *ifp; 268143731Sdougb struct e1000_hw hw; 269143731Sdougb 270143731Sdougb /* FreeBSD operating-system-specific structures. */ 271143731Sdougb struct e1000_osdep osdep; 272143731Sdougb struct device *dev; 273143731Sdougb struct resource *res_memory; 274143731Sdougb struct resource *flash_mem; 275143731Sdougb struct resource *msix_mem; 276143731Sdougb struct resource *res_ioport; 277143731Sdougb struct resource *res_interrupt; 278143731Sdougb void *int_handler_tag; 279143731Sdougb struct ifmedia media; 280143731Sdougb struct callout timer; 281143731Sdougb struct callout tx_fifo_timer; 282135446Strhodes int watchdog_timer; 283135446Strhodes int io_rid; 284135446Strhodes int msi; 285135446Strhodes int if_flags; 286135446Strhodes int max_frame_size; 287135446Strhodes int min_frame_size; 288135446Strhodes struct mtx core_mtx; 289135446Strhodes struct mtx tx_mtx; 290135446Strhodes int em_insert_vlan_header; 291135446Strhodes struct task link_task; 292135446Strhodes struct task rxtx_task; 293135446Strhodes struct taskqueue *tq; /* private task queue */ 294135446Strhodes /* Management and WOL features */ 295135446Strhodes int wol; 296135446Strhodes int has_manage; 297135446Strhodes 298135446Strhodes /* Info about the board itself */ 299135446Strhodes uint8_t link_active; 300135446Strhodes uint16_t link_speed; 301135446Strhodes uint16_t link_duplex; 302135446Strhodes uint32_t smartspeed; 303135446Strhodes struct em_int_delay_info tx_int_delay; 304135446Strhodes struct em_int_delay_info tx_abs_int_delay; 305135446Strhodes struct em_int_delay_info rx_int_delay; 306135446Strhodes struct em_int_delay_info rx_abs_int_delay; 307135446Strhodes 308135446Strhodes /* 309135446Strhodes * Transmit definitions 310135446Strhodes * 311135446Strhodes * We have an array of num_tx_desc descriptors (handled 312135446Strhodes * by the controller) paired with an array of tx_buffers 313135446Strhodes * (at tx_buffer_area). 314135446Strhodes * The index of the next available descriptor is next_avail_tx_desc. 315135446Strhodes * The number of remaining tx_desc is num_tx_desc_avail. 316135446Strhodes */ 317135446Strhodes struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 318135446Strhodes struct e1000_tx_desc *tx_desc_base; 319135446Strhodes uint32_t next_avail_tx_desc; 320135446Strhodes uint32_t next_tx_to_clean; 321135446Strhodes volatile uint16_t num_tx_desc_avail; 322135446Strhodes uint16_t num_tx_desc; 323135446Strhodes uint32_t txd_cmd; 324135446Strhodes struct em_buffer *tx_buffer_area; 325135446Strhodes bus_dma_tag_t txtag; /* dma tag for tx */ 326135446Strhodes uint32_t tx_tso; /* last tx was tso */ 327135446Strhodes 328135446Strhodes /* 329135446Strhodes * Transmit function pointer: 330135446Strhodes * legacy or advanced (82575 and later) 331135446Strhodes */ 332135446Strhodes int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp); 333135446Strhodes 334135446Strhodes /* 335135446Strhodes * Receive definitions 336135446Strhodes * 337135446Strhodes * we have an array of num_rx_desc rx_desc (handled by the 338135446Strhodes * controller), and paired with an array of rx_buffers 339135446Strhodes * (at rx_buffer_area). 340135446Strhodes * The next pair to check on receive is at offset next_rx_desc_to_check 341135446Strhodes */ 342135446Strhodes struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 343135446Strhodes struct e1000_rx_desc *rx_desc_base; 344135446Strhodes uint32_t next_rx_desc_to_check; 345135446Strhodes uint32_t rx_buffer_len; 346135446Strhodes uint16_t num_rx_desc; 347135446Strhodes int rx_process_limit; 348135446Strhodes struct em_buffer *rx_buffer_area; 349135446Strhodes bus_dma_tag_t rxtag; 350135446Strhodes bus_dmamap_t rx_sparemap; 351135446Strhodes 352135446Strhodes /* 353135446Strhodes * First/last mbuf pointers, for 354135446Strhodes * collecting multisegment RX packets. 355135446Strhodes */ 356135446Strhodes struct mbuf *fmp; 357135446Strhodes struct mbuf *lmp; 358135446Strhodes 359135446Strhodes /* Misc stats maintained by the driver */ 360163976Sdougb unsigned long dropped_pkts; 361135446Strhodes unsigned long mbuf_alloc_failed; 362135446Strhodes unsigned long mbuf_cluster_failed; 363135446Strhodes unsigned long no_tx_desc_avail1; 364135446Strhodes unsigned long no_tx_desc_avail2; 365135446Strhodes unsigned long no_tx_map_avail; 366135446Strhodes unsigned long no_tx_dma_setup; 367143731Sdougb unsigned long watchdog_events; 368143731Sdougb unsigned long rx_overruns; 369143731Sdougb 370143731Sdougb /* Used in for 82547 10Mb Half workaround */ 371143731Sdougb #define EM_PBA_BYTES_SHIFT 0xA 372143731Sdougb #define EM_TX_HEAD_ADDR_SHIFT 7 373143731Sdougb #define EM_PBA_TX_MASK 0xFFFF0000 374143731Sdougb #define EM_FIFO_HDR 0x10 375143731Sdougb 376143731Sdougb #define EM_82547_PKT_THRESH 0x3e0 377143731Sdougb 378143731Sdougb uint32_t tx_fifo_size; 379135446Strhodes uint32_t tx_fifo_head; 380135446Strhodes uint32_t tx_fifo_head_addr; 381135446Strhodes uint64_t tx_fifo_reset_cnt; 382135446Strhodes uint64_t tx_fifo_wrk_cnt; 383135446Strhodes uint32_t tx_head_addr; 384135446Strhodes 385143731Sdougb /* For 82544 PCIX Workaround */ 386143731Sdougb boolean_t pcix_82544; 387143731Sdougb boolean_t in_detach; 388143731Sdougb 389143731Sdougb struct e1000_hw_stats stats; 390135446Strhodes}; 391143731Sdougb 392135446Strhodes/* ****************************************************************************** 393135446Strhodes * vendor_info_array 394135446Strhodes * 395135446Strhodes * This array contains the list of Subvendor/Subdevice IDs on which the driver 396135446Strhodes * should load. 397135446Strhodes * 398135446Strhodes * ******************************************************************************/ 399135446Strhodestypedef struct _em_vendor_info_t { 400135446Strhodes unsigned int vendor_id; 401135446Strhodes unsigned int device_id; 402135446Strhodes unsigned int subvendor_id; 403135446Strhodes unsigned int subdevice_id; 404135446Strhodes unsigned int index; 405135446Strhodes} em_vendor_info_t; 406135446Strhodes 407135446Strhodes 408135446Strhodesstruct em_buffer { 409135446Strhodes int next_eop; /* Index of the desc to watch */ 410135446Strhodes struct mbuf *m_head; 411135446Strhodes bus_dmamap_t map; /* bus_dma map for packet */ 412135446Strhodes}; 413135446Strhodes 414135446Strhodes/* For 82544 PCIX Workaround */ 415135446Strhodestypedef struct _ADDRESS_LENGTH_PAIR 416135446Strhodes{ 417135446Strhodes uint64_t address; 418135446Strhodes uint32_t length; 419135446Strhodes} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 420135446Strhodes 421135446Strhodestypedef struct _DESCRIPTOR_PAIR 422135446Strhodes{ 423135446Strhodes ADDRESS_LENGTH_PAIR descriptor[4]; 424135446Strhodes uint32_t elements; 425135446Strhodes} DESC_ARRAY, *PDESC_ARRAY; 426135446Strhodes 427135446Strhodes#define EM_CORE_LOCK_INIT(_sc, _name) \ 428135446Strhodes mtx_init(&(_sc)->core_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 429135446Strhodes#define EM_TX_LOCK_INIT(_sc, _name) \ 430135446Strhodes mtx_init(&(_sc)->tx_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 431135446Strhodes#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 432135446Strhodes#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 433135446Strhodes#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 434135446Strhodes#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 435135446Strhodes#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 436135446Strhodes#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 437135446Strhodes#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 438135446Strhodes#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 439135446Strhodes 440135446Strhodes#endif /* _EM_H_DEFINED_ */ 441135446Strhodes