if_em.h revision 169248
11556Srgrimes/************************************************************************** 21556Srgrimes 31556SrgrimesCopyright (c) 2001-2007, Intel Corporation 41556SrgrimesAll rights reserved. 51556Srgrimes 61556SrgrimesRedistribution and use in source and binary forms, with or without 71556Srgrimesmodification, are permitted provided that the following conditions are met: 81556Srgrimes 91556Srgrimes 1. Redistributions of source code must retain the above copyright notice, 101556Srgrimes this list of conditions and the following disclaimer. 111556Srgrimes 121556Srgrimes 2. Redistributions in binary form must reproduce the above copyright 131556Srgrimes notice, this list of conditions and the following disclaimer in the 141556Srgrimes documentation and/or other materials provided with the distribution. 151556Srgrimes 161556Srgrimes 3. Neither the name of the Intel Corporation nor the names of its 171556Srgrimes contributors may be used to endorse or promote products derived from 181556Srgrimes this software without specific prior written permission. 191556Srgrimes 201556SrgrimesTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 211556SrgrimesAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221556SrgrimesIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231556SrgrimesARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 241556SrgrimesLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251556SrgrimesCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261556SrgrimesSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271556SrgrimesINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281556SrgrimesCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291556SrgrimesARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 301556SrgrimesPOSSIBILITY OF SUCH DAMAGE. 311556Srgrimes 321556Srgrimes***************************************************************************/ 331556Srgrimes 341556Srgrimes/* 351556Srgrimes * $FreeBSD: head/sys/dev/em/if_em.h 169248 2007-05-04 13:30:44Z rwatson $ 361556Srgrimes */ 371556Srgrimes 3836150Scharnier#ifndef _EM_H_DEFINED_ 3936150Scharnier#define _EM_H_DEFINED_ 4036150Scharnier 4136150Scharnier/* Tunables */ 4246684Skris 431556Srgrimes/* 441556Srgrimes * EM_TXD: Maximum number of Transmit Descriptors 4517987Speter * Valid Range: 80-256 for 82542 and 82543-based adapters 4617987Speter * 80-4096 for others 4717987Speter * Default Value: 256 4817987Speter * This value is the number of transmit descriptors allocated by the driver. 491556Srgrimes * Increasing this value allows the driver to queue more transmits. Each 501556Srgrimes * descriptor is 16 bytes. 511556Srgrimes * Since TDLEN should be multiple of 128bytes, the number of transmit 521556Srgrimes * desscriptors should meet the following condition. 531556Srgrimes * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 5417987Speter */ 551556Srgrimes#define EM_MIN_TXD 80 561556Srgrimes#define EM_MAX_TXD_82543 256 571556Srgrimes#define EM_MAX_TXD 4096 581556Srgrimes#define EM_DEFAULT_TXD EM_MAX_TXD_82543 591556Srgrimes 601556Srgrimes/* 611556Srgrimes * EM_RXD - Maximum number of receive Descriptors 621556Srgrimes * Valid Range: 80-256 for 82542 and 82543-based adapters 631556Srgrimes * 80-4096 for others 641556Srgrimes * Default Value: 256 651556Srgrimes * This value is the number of receive descriptors allocated by the driver. 661556Srgrimes * Increasing this value allows the driver to buffer more incoming packets. 671556Srgrimes * Each descriptor is 16 bytes. A receive buffer is also allocated for each 681556Srgrimes * descriptor. The maximum MTU size is 16110. 691556Srgrimes * Since TDLEN should be multiple of 128bytes, the number of transmit 701556Srgrimes * desscriptors should meet the following condition. 711556Srgrimes * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 721556Srgrimes */ 7346684Skris#define EM_MIN_RXD 80 741556Srgrimes#define EM_MAX_RXD_82543 256 751556Srgrimes#define EM_MAX_RXD 4096 761556Srgrimes#define EM_DEFAULT_RXD EM_MAX_RXD_82543 7717987Speter 7838521Scracauer/* 7938536Scracauer * EM_TIDV - Transmit Interrupt Delay Value 8038950Scracauer * Valid Range: 0-65535 (0=off) 8138521Scracauer * Default Value: 64 8238521Scracauer * This value delays the generation of transmit interrupts in units of 8320902Ssteve * 1.024 microseconds. Transmit interrupt reduction can improve CPU 841556Srgrimes * efficiency if properly tuned for specific network traffic. If the 8517987Speter * system is reporting dropped transmits, this value may be set too high 8617987Speter * causing the driver to run out of available transmit descriptors. 8720902Ssteve */ 881556Srgrimes#define EM_TIDV 64 8920902Ssteve 9020902Ssteve/* 9120902Ssteve * EM_TADV - Transmit Absolute Interrupt Delay Value 9220902Ssteve * (Not valid for 82542/82543/82544) 9320902Ssteve * Valid Range: 0-65535 (0=off) 9420902Ssteve * Default Value: 64 9520902Ssteve * This value, in units of 1.024 microseconds, limits the delay in which a 9620902Ssteve * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 9720902Ssteve * this value ensures that an interrupt is generated after the initial 9820902Ssteve * packet is sent on the wire within the set amount of time. Proper tuning, 9920902Ssteve * along with EM_TIDV, may improve traffic throughput in specific 10020902Ssteve * network conditions. 10120902Ssteve */ 10220902Ssteve#define EM_TADV 64 10320902Ssteve 10420902Ssteve/* 10520902Ssteve * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 10620902Ssteve * Valid Range: 0-65535 (0=off) 10720902Ssteve * Default Value: 0 10820902Ssteve * This value delays the generation of receive interrupts in units of 1.024 10920902Ssteve * microseconds. Receive interrupt reduction can improve CPU efficiency if 11020902Ssteve * properly tuned for specific network traffic. Increasing this value adds 11120902Ssteve * extra latency to frame reception and can end up decreasing the throughput 11220902Ssteve * of TCP traffic. If the system is reporting dropped receives, this value 11320902Ssteve * may be set too high, causing the driver to run out of available receive 11420902Ssteve * descriptors. 11520902Ssteve * 11620902Ssteve * CAUTION: When setting EM_RDTR to a value other than 0, adapters 11720902Ssteve * may hang (stop transmitting) under certain network conditions. 11820902Ssteve * If this occurs a WATCHDOG message is logged in the system 11920902Ssteve * event log. In addition, the controller is automatically reset, 12020902Ssteve * restoring the network connection. To eliminate the potential 12120902Ssteve * for the hang ensure that EM_RDTR is set to 0. 12220902Ssteve */ 12320902Ssteve#define EM_RDTR 0 12420902Ssteve 12520902Ssteve/* 12620902Ssteve * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 12720902Ssteve * Valid Range: 0-65535 (0=off) 12820902Ssteve * Default Value: 64 12920902Ssteve * This value, in units of 1.024 microseconds, limits the delay in which a 13020902Ssteve * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 13120902Ssteve * this value ensures that an interrupt is generated after the initial 13220902Ssteve * packet is received within the set amount of time. Proper tuning, 13320902Ssteve * along with EM_RDTR, may improve traffic throughput in specific network 13420902Ssteve * conditions. 1351556Srgrimes */ 1361556Srgrimes#define EM_RADV 64 13717987Speter 13817987Speter/* 13917987Speter * Inform the stack about transmit checksum offload capabilities. 14020425Ssteve */ 14117987Speter#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 1421556Srgrimes 1431556Srgrimes/* 1441556Srgrimes * Inform the stack about transmit segmentation offload capabilities. 1451556Srgrimes */ 14620902Ssteve#define EM_TCPSEG_FEATURES CSUM_TSO 1471556Srgrimes 14820902Ssteve/* 14920902Ssteve * This parameter controls the duration of transmit watchdog timer. 1501556Srgrimes */ 1511556Srgrimes#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 1521556Srgrimes 15320902Ssteve/* 15420902Ssteve * This parameter controls when the driver calls the routine to reclaim 15520902Ssteve * transmit descriptors. 15620902Ssteve */ 15720902Ssteve#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 15820902Ssteve#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 15920902Ssteve 16020902Ssteve/* 16120902Ssteve * This parameter controls whether or not autonegotation is enabled. 16220902Ssteve * 0 - Disable autonegotiation 16320902Ssteve * 1 - Enable autonegotiation 16420902Ssteve */ 16520902Ssteve#define DO_AUTO_NEG 1 16620902Ssteve 16720902Ssteve/* 16820902Ssteve * This parameter control whether or not the driver will wait for 16920902Ssteve * autonegotiation to complete. 17020902Ssteve * 1 - Wait for autonegotiation to complete 17120902Ssteve * 0 - Don't wait for autonegotiation to complete 1721556Srgrimes */ 1731556Srgrimes#define WAIT_FOR_AUTO_NEG_DEFAULT 0 1741556Srgrimes 1751556Srgrimes/* Tunables -- End */ 1761556Srgrimes 1771556Srgrimes#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 1781556Srgrimes ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 1791556Srgrimes ADVERTISE_1000_FULL) 1801556Srgrimes 18120902Ssteve#define AUTO_ALL_MODES 0 1821556Srgrimes 1831556Srgrimes/* PHY master/slave setting */ 1841556Srgrimes#define EM_MASTER_SLAVE e1000_ms_hw_default 1851556Srgrimes 1861556Srgrimes/* 1871556Srgrimes * Micellaneous constants 1881556Srgrimes */ 1891556Srgrimes#define EM_VENDOR_ID 0x8086 1901556Srgrimes#define EM_FLASH 0x0014 19120902Ssteve 19220902Ssteve#define EM_JUMBO_PBA 0x00000028 19338950Scracauer#define EM_DEFAULT_PBA 0x00000030 1941556Srgrimes#define EM_SMARTSPEED_DOWNSHIFT 3 19520902Ssteve#define EM_SMARTSPEED_MAX 15 1961556Srgrimes#define EM_MAX_INTR 10 1971556Srgrimes#define EM_TSO_SEG_SIZE 4096 /* Max dma seg size */ 1981556Srgrimes 1991556Srgrimes#define MAX_NUM_MULTICAST_ADDRESSES 128 2001556Srgrimes#define PCI_ANY_ID (~0U) 2011556Srgrimes#define ETHER_ALIGN 2 2021556Srgrimes#define EM_TX_BUFFER_SIZE ((uint32_t) 1514) 2031556Srgrimes#define EM_FC_PAUSE_TIME 0x0680 2041556Srgrimes#define EM_EEPROM_APME 0x400; 2051556Srgrimes 2061556Srgrimes/* 2071556Srgrimes * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 2081556Srgrimes * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 2091556Srgrimes * also optimize cache line size effect. H/W supports up to cache line size 128. 2101556Srgrimes */ 2111556Srgrimes#define EM_DBA_ALIGN 128 21231098Sbde 21320425Ssteve#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 21417987Speter 21517987Speter/* PCI Config defines */ 2161556Srgrimes#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 21731098Sbde#define EM_BAR_TYPE_MASK 0x00000001 2181556Srgrimes#define EM_BAR_TYPE_MMEM 0x00000000 2191556Srgrimes#define EM_BAR_TYPE_IO 0x00000001 2201556Srgrimes#define EM_BAR_TYPE_FLASH 0x0014 2211556Srgrimes#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 2221556Srgrimes#define EM_BAR_MEM_TYPE_MASK 0x00000006 2231556Srgrimes#define EM_BAR_MEM_TYPE_32BIT 0x00000000 2241556Srgrimes#define EM_BAR_MEM_TYPE_64BIT 0x00000004 2251556Srgrimes 22638521Scracauer/* Defines for printing debug information */ 2271556Srgrimes#define DEBUG_INIT 0 2281556Srgrimes#define DEBUG_IOCTL 0 22938521Scracauer#define DEBUG_HW 0 2301556Srgrimes 2311556Srgrimes#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 2321556Srgrimes#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 2331556Srgrimes#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 2341556Srgrimes#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 2351556Srgrimes#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 2361556Srgrimes#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 2371556Srgrimes#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 2381556Srgrimes#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 2391556Srgrimes#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 24038535Scracauer 24138521Scracauer#define EM_MAX_SCATTER 64 2421556Srgrimes#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */ 24338521Scracauer#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 2441556Srgrimes#define ETH_ZLEN 60 2451556Srgrimes#define ETH_ADDR_LEN 6 2461556Srgrimes 2471556Srgrimesstruct adapter; 2481556Srgrimes 24938521Scracauerstruct em_int_delay_info { 2501556Srgrimes struct adapter *adapter; /* Back-pointer to the adapter struct */ 2511556Srgrimes int offset; /* Register offset to read/write */ 2521556Srgrimes int value; /* Current value in usecs */ 2531556Srgrimes}; 2541556Srgrimes 25517987Speter/* 25620902Ssteve * Bus dma allocation structure used by 2578855Srgrimes * e1000_dma_malloc and e1000_dma_free. 2588855Srgrimes */ 2598855Srgrimesstruct em_dma_alloc { 2601556Srgrimes bus_addr_t dma_paddr; 26117987Speter caddr_t dma_vaddr; 26217987Speter bus_dma_tag_t dma_tag; 26317987Speter bus_dmamap_t dma_map; 26417987Speter bus_dma_segment_t dma_seg; 26517987Speter int dma_nseg; 26617987Speter}; 26731098Sbde 26817987Speter/* Our adapter structure */ 2691556Srgrimesstruct adapter { 2708855Srgrimes struct ifnet *ifp; 2711556Srgrimes struct e1000_hw hw; 2721556Srgrimes 2731556Srgrimes /* FreeBSD operating-system-specific structures. */ 2741556Srgrimes struct e1000_osdep osdep; 2751556Srgrimes struct device *dev; 2761556Srgrimes struct resource *res_memory; 2771556Srgrimes struct resource *flash_mem; 2781556Srgrimes struct resource *res_ioport; 2791556Srgrimes struct resource *res_interrupt; 28031098Sbde void *int_handler_tag; 2811556Srgrimes struct ifmedia media; 2821556Srgrimes struct callout timer; 2831556Srgrimes struct callout tx_fifo_timer; 2841556Srgrimes int watchdog_timer; 2851556Srgrimes int io_rid; 2861556Srgrimes int msi; 28731098Sbde int if_flags; 28830969Sache struct mtx mtx; 28931098Sbde int em_insert_vlan_header; 29031098Sbde struct task link_task; 29130969Sache struct task rxtx_task; 2921556Srgrimes struct taskqueue *tq; /* private task queue */ 2931556Srgrimes /* Management and WOL features */ 29420902Ssteve int wol; 2951556Srgrimes int has_manage; 2961556Srgrimes 2971556Srgrimes /* Info about the board itself */ 29817987Speter uint32_t part_num; 29920425Ssteve uint8_t link_active; 30017987Speter uint16_t link_speed; 30117987Speter uint16_t link_duplex; 30217987Speter uint32_t smartspeed; 3031556Srgrimes struct em_int_delay_info tx_int_delay; 3041556Srgrimes struct em_int_delay_info tx_abs_int_delay; 3051556Srgrimes struct em_int_delay_info rx_int_delay; 30617987Speter struct em_int_delay_info rx_abs_int_delay; 30717987Speter 30817987Speter /* 3091556Srgrimes * Transmit definitions 3101556Srgrimes * 31120902Ssteve * We have an array of num_tx_desc descriptors (handled 3121556Srgrimes * by the controller) paired with an array of tx_buffers 3131556Srgrimes * (at tx_buffer_area). 3141556Srgrimes * The index of the next available descriptor is next_avail_tx_desc. 3151556Srgrimes * The number of remaining tx_desc is num_tx_desc_avail. 31620425Ssteve */ 31717987Speter struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 31817987Speter struct e1000_tx_desc *tx_desc_base; 31920902Ssteve uint32_t next_avail_tx_desc; 32020902Ssteve uint32_t next_tx_to_clean; 3211556Srgrimes volatile uint16_t num_tx_desc_avail; 3221556Srgrimes uint16_t num_tx_desc; 32320902Ssteve uint32_t txd_cmd; 3241556Srgrimes struct em_buffer *tx_buffer_area; 3251556Srgrimes bus_dma_tag_t txtag; /* dma tag for tx */ 3261556Srgrimes uint32_t tx_tso; /* last tx was tso */ 3271556Srgrimes 32817987Speter /* 3291556Srgrimes * Transmit function pointer: 3301556Srgrimes * legacy or advanced (82575 and later) 3311556Srgrimes */ 3321556Srgrimes int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp); 3331556Srgrimes 3341556Srgrimes /* 33517987Speter * Receive definitions 3361556Srgrimes * 3371556Srgrimes * we have an array of num_rx_desc rx_desc (handled by the 3381556Srgrimes * controller), and paired with an array of rx_buffers 3391556Srgrimes * (at rx_buffer_area). 3401556Srgrimes * The next pair to check on receive is at offset next_rx_desc_to_check 3411556Srgrimes */ 3421556Srgrimes struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 3431556Srgrimes struct e1000_rx_desc *rx_desc_base; 3441556Srgrimes uint32_t next_rx_desc_to_check; 3451556Srgrimes uint32_t rx_buffer_len; 3461556Srgrimes uint16_t num_rx_desc; 34720425Ssteve int rx_process_limit; 34817987Speter struct em_buffer *rx_buffer_area; 34917987Speter bus_dma_tag_t rxtag; 35031098Sbde bus_dmamap_t rx_sparemap; 35130969Sache 3521556Srgrimes /* 35330969Sache * First/last mbuf pointers, for 3541556Srgrimes * collecting multisegment RX packets. 3551556Srgrimes */ 3561556Srgrimes struct mbuf *fmp; 3571556Srgrimes struct mbuf *lmp; 35838950Scracauer 35920902Ssteve /* Misc stats maintained by the driver */ 36020902Ssteve unsigned long dropped_pkts; 3611556Srgrimes unsigned long mbuf_alloc_failed; 36238950Scracauer unsigned long mbuf_cluster_failed; 36338950Scracauer unsigned long no_tx_desc_avail1; 36438950Scracauer unsigned long no_tx_desc_avail2; 36538521Scracauer unsigned long no_tx_map_avail; 36638950Scracauer unsigned long no_tx_dma_setup; 36739056Scracauer unsigned long watchdog_events; 36839056Scracauer unsigned long rx_overruns; 36938950Scracauer 37045221Scracauer /* Used in for 82547 10Mb Half workaround */ 37145221Scracauer #define EM_PBA_BYTES_SHIFT 0xA 37239056Scracauer #define EM_TX_HEAD_ADDR_SHIFT 7 37339049Scracauer #define EM_PBA_TX_MASK 0xFFFF0000 37439049Scracauer #define EM_FIFO_HDR 0x10 3751556Srgrimes 3761556Srgrimes #define EM_82547_PKT_THRESH 0x3e0 3771556Srgrimes 3781556Srgrimes uint32_t tx_fifo_size; 3791556Srgrimes uint32_t tx_fifo_head; 3801556Srgrimes uint32_t tx_fifo_head_addr; 3811556Srgrimes uint64_t tx_fifo_reset_cnt; 3821556Srgrimes uint64_t tx_fifo_wrk_cnt; 38320902Ssteve uint32_t tx_head_addr; 38420902Ssteve 3851556Srgrimes /* For 82544 PCIX Workaround */ 3861556Srgrimes boolean_t pcix_82544; 3871556Srgrimes boolean_t in_detach; 38838521Scracauer 3891556Srgrimes struct e1000_hw_stats stats; 39020902Ssteve}; 39120902Ssteve 39220902Ssteve/* ****************************************************************************** 39320902Ssteve * vendor_info_array 39420902Ssteve * 39520902Ssteve * This array contains the list of Subvendor/Subdevice IDs on which the driver 39620902Ssteve * should load. 39720902Ssteve * 39820902Ssteve * ******************************************************************************/ 39920902Sstevetypedef struct _em_vendor_info_t { 40020902Ssteve unsigned int vendor_id; 40120902Ssteve unsigned int device_id; 40220902Ssteve unsigned int subvendor_id; 40320902Ssteve unsigned int subdevice_id; 40420902Ssteve unsigned int index; 40520902Ssteve} em_vendor_info_t; 4061556Srgrimes 40720902Ssteve 4081556Srgrimesstruct em_buffer { 40920902Ssteve int next_eop; /* Index of the desc to watch */ 41020902Ssteve struct mbuf *m_head; 4111556Srgrimes bus_dmamap_t map; /* bus_dma map for packet */ 41238521Scracauer}; 4131556Srgrimes 4141556Srgrimes/* For 82544 PCIX Workaround */ 4151556Srgrimestypedef struct _ADDRESS_LENGTH_PAIR 4161556Srgrimes{ 4171556Srgrimes uint64_t address; 4181556Srgrimes uint32_t length; 4191556Srgrimes} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 4201556Srgrimes 42117987Spetertypedef struct _DESCRIPTOR_PAIR 42217987Speter{ 42317987Speter ADDRESS_LENGTH_PAIR descriptor[4]; 42438521Scracauer uint32_t elements; 4251556Srgrimes} DESC_ARRAY, *PDESC_ARRAY; 4261556Srgrimes 4271556Srgrimes#define EM_LOCK_INIT(_sc, _name) \ 4281556Srgrimes mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 4291556Srgrimes#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 4301556Srgrimes#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx) 4311556Srgrimes#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 4321556Srgrimes#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 4331556Srgrimes 4341556Srgrimes#endif /* _EM_H_DEFINED_ */ 4351556Srgrimes