if_em.h revision 169240
1/************************************************************************** 2 3Copyright (c) 2001-2007, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33$FreeBSD: head/sys/dev/em/if_em.h 169240 2007-05-04 00:00:12Z jfv $ 34 35#ifndef _EM_H_DEFINED_ 36#define _EM_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * EM_TXD: Maximum number of Transmit Descriptors 42 * Valid Range: 80-256 for 82542 and 82543-based adapters 43 * 80-4096 for others 44 * Default Value: 256 45 * This value is the number of transmit descriptors allocated by the driver. 46 * Increasing this value allows the driver to queue more transmits. Each 47 * descriptor is 16 bytes. 48 * Since TDLEN should be multiple of 128bytes, the number of transmit 49 * desscriptors should meet the following condition. 50 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 51 */ 52#define EM_MIN_TXD 80 53#define EM_MAX_TXD_82543 256 54#define EM_MAX_TXD 4096 55#define EM_DEFAULT_TXD EM_MAX_TXD_82543 56 57/* 58 * EM_RXD - Maximum number of receive Descriptors 59 * Valid Range: 80-256 for 82542 and 82543-based adapters 60 * 80-4096 for others 61 * Default Value: 256 62 * This value is the number of receive descriptors allocated by the driver. 63 * Increasing this value allows the driver to buffer more incoming packets. 64 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 65 * descriptor. The maximum MTU size is 16110. 66 * Since TDLEN should be multiple of 128bytes, the number of transmit 67 * desscriptors should meet the following condition. 68 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 69 */ 70#define EM_MIN_RXD 80 71#define EM_MAX_RXD_82543 256 72#define EM_MAX_RXD 4096 73#define EM_DEFAULT_RXD EM_MAX_RXD_82543 74 75/* 76 * EM_TIDV - Transmit Interrupt Delay Value 77 * Valid Range: 0-65535 (0=off) 78 * Default Value: 64 79 * This value delays the generation of transmit interrupts in units of 80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 81 * efficiency if properly tuned for specific network traffic. If the 82 * system is reporting dropped transmits, this value may be set too high 83 * causing the driver to run out of available transmit descriptors. 84 */ 85#define EM_TIDV 64 86 87/* 88 * EM_TADV - Transmit Absolute Interrupt Delay Value 89 * (Not valid for 82542/82543/82544) 90 * Valid Range: 0-65535 (0=off) 91 * Default Value: 64 92 * This value, in units of 1.024 microseconds, limits the delay in which a 93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94 * this value ensures that an interrupt is generated after the initial 95 * packet is sent on the wire within the set amount of time. Proper tuning, 96 * along with EM_TIDV, may improve traffic throughput in specific 97 * network conditions. 98 */ 99#define EM_TADV 64 100 101/* 102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103 * Valid Range: 0-65535 (0=off) 104 * Default Value: 0 105 * This value delays the generation of receive interrupts in units of 1.024 106 * microseconds. Receive interrupt reduction can improve CPU efficiency if 107 * properly tuned for specific network traffic. Increasing this value adds 108 * extra latency to frame reception and can end up decreasing the throughput 109 * of TCP traffic. If the system is reporting dropped receives, this value 110 * may be set too high, causing the driver to run out of available receive 111 * descriptors. 112 * 113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114 * may hang (stop transmitting) under certain network conditions. 115 * If this occurs a WATCHDOG message is logged in the system 116 * event log. In addition, the controller is automatically reset, 117 * restoring the network connection. To eliminate the potential 118 * for the hang ensure that EM_RDTR is set to 0. 119 */ 120#define EM_RDTR 0 121 122/* 123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124 * Valid Range: 0-65535 (0=off) 125 * Default Value: 64 126 * This value, in units of 1.024 microseconds, limits the delay in which a 127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128 * this value ensures that an interrupt is generated after the initial 129 * packet is received within the set amount of time. Proper tuning, 130 * along with EM_RDTR, may improve traffic throughput in specific network 131 * conditions. 132 */ 133#define EM_RADV 64 134 135/* 136 * Inform the stack about transmit checksum offload capabilities. 137 */ 138#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 139 140/* 141 * Inform the stack about transmit segmentation offload capabilities. 142 */ 143#define EM_TCPSEG_FEATURES CSUM_TSO 144 145/* 146 * This parameter controls the duration of transmit watchdog timer. 147 */ 148#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 149 150/* 151 * This parameter controls when the driver calls the routine to reclaim 152 * transmit descriptors. 153 */ 154#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 155#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 156 157/* 158 * This parameter controls whether or not autonegotation is enabled. 159 * 0 - Disable autonegotiation 160 * 1 - Enable autonegotiation 161 */ 162#define DO_AUTO_NEG 1 163 164/* 165 * This parameter control whether or not the driver will wait for 166 * autonegotiation to complete. 167 * 1 - Wait for autonegotiation to complete 168 * 0 - Don't wait for autonegotiation to complete 169 */ 170#define WAIT_FOR_AUTO_NEG_DEFAULT 0 171 172/* Tunables -- End */ 173 174#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 175 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 176 ADVERTISE_1000_FULL) 177 178#define AUTO_ALL_MODES 0 179 180/* PHY master/slave setting */ 181#define EM_MASTER_SLAVE e1000_ms_hw_default 182 183/* 184 * Micellaneous constants 185 */ 186#define EM_VENDOR_ID 0x8086 187#define EM_FLASH 0x0014 188 189#define EM_JUMBO_PBA 0x00000028 190#define EM_DEFAULT_PBA 0x00000030 191#define EM_SMARTSPEED_DOWNSHIFT 3 192#define EM_SMARTSPEED_MAX 15 193#define EM_MAX_INTR 10 194#define EM_TSO_SEG_SIZE 4096 /* Max dma seg size */ 195 196#define MAX_NUM_MULTICAST_ADDRESSES 128 197#define PCI_ANY_ID (~0U) 198#define ETHER_ALIGN 2 199#define EM_TX_BUFFER_SIZE ((uint32_t) 1514) 200#define EM_FC_PAUSE_TIME 0x0680 201#define EM_EEPROM_APME 0x400; 202 203/* 204 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 205 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 206 * also optimize cache line size effect. H/W supports up to cache line size 128. 207 */ 208#define EM_DBA_ALIGN 128 209 210#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 211 212/* PCI Config defines */ 213#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 214#define EM_BAR_TYPE_MASK 0x00000001 215#define EM_BAR_TYPE_MMEM 0x00000000 216#define EM_BAR_TYPE_IO 0x00000001 217#define EM_BAR_TYPE_FLASH 0x0014 218#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 219#define EM_BAR_MEM_TYPE_MASK 0x00000006 220#define EM_BAR_MEM_TYPE_32BIT 0x00000000 221#define EM_BAR_MEM_TYPE_64BIT 0x00000004 222 223/* Defines for printing debug information */ 224#define DEBUG_INIT 0 225#define DEBUG_IOCTL 0 226#define DEBUG_HW 0 227 228#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 229#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 230#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 231#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 232#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 233#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 234#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 235#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 236#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 237 238#define EM_MAX_SCATTER 64 239#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */ 240#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 241#define ETH_ZLEN 60 242#define ETH_ADDR_LEN 6 243 244struct adapter; 245 246struct em_int_delay_info { 247 struct adapter *adapter; /* Back-pointer to the adapter struct */ 248 int offset; /* Register offset to read/write */ 249 int value; /* Current value in usecs */ 250}; 251 252/* 253 * Bus dma allocation structure used by 254 * e1000_dma_malloc and e1000_dma_free. 255 */ 256struct em_dma_alloc { 257 bus_addr_t dma_paddr; 258 caddr_t dma_vaddr; 259 bus_dma_tag_t dma_tag; 260 bus_dmamap_t dma_map; 261 bus_dma_segment_t dma_seg; 262 int dma_nseg; 263}; 264 265/* Our adapter structure */ 266struct adapter { 267 struct ifnet *ifp; 268 struct e1000_hw hw; 269 270 /* FreeBSD operating-system-specific structures. */ 271 struct e1000_osdep osdep; 272 struct device *dev; 273 struct resource *res_memory; 274 struct resource *flash_mem; 275 struct resource *res_ioport; 276 struct resource *res_interrupt; 277 void *int_handler_tag; 278 struct ifmedia media; 279 struct callout timer; 280 struct callout tx_fifo_timer; 281 int watchdog_timer; 282 int io_rid; 283 int msi; 284 int if_flags; 285 struct mtx mtx; 286 int em_insert_vlan_header; 287 struct task link_task; 288 struct task rxtx_task; 289 struct taskqueue *tq; /* private task queue */ 290 /* Management and WOL features */ 291 int wol; 292 int has_manage; 293 294 /* Info about the board itself */ 295 uint32_t part_num; 296 uint8_t link_active; 297 uint16_t link_speed; 298 uint16_t link_duplex; 299 uint32_t smartspeed; 300 struct em_int_delay_info tx_int_delay; 301 struct em_int_delay_info tx_abs_int_delay; 302 struct em_int_delay_info rx_int_delay; 303 struct em_int_delay_info rx_abs_int_delay; 304 305 /* 306 * Transmit definitions 307 * 308 * We have an array of num_tx_desc descriptors (handled 309 * by the controller) paired with an array of tx_buffers 310 * (at tx_buffer_area). 311 * The index of the next available descriptor is next_avail_tx_desc. 312 * The number of remaining tx_desc is num_tx_desc_avail. 313 */ 314 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 315 struct e1000_tx_desc *tx_desc_base; 316 uint32_t next_avail_tx_desc; 317 uint32_t next_tx_to_clean; 318 volatile uint16_t num_tx_desc_avail; 319 uint16_t num_tx_desc; 320 uint32_t txd_cmd; 321 struct em_buffer *tx_buffer_area; 322 bus_dma_tag_t txtag; /* dma tag for tx */ 323 uint32_t tx_tso; /* last tx was tso */ 324 325 /* 326 * Transmit function pointer: 327 * legacy or advanced (82575 and later) 328 */ 329 int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp); 330 331 /* 332 * Receive definitions 333 * 334 * we have an array of num_rx_desc rx_desc (handled by the 335 * controller), and paired with an array of rx_buffers 336 * (at rx_buffer_area). 337 * The next pair to check on receive is at offset next_rx_desc_to_check 338 */ 339 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 340 struct e1000_rx_desc *rx_desc_base; 341 uint32_t next_rx_desc_to_check; 342 uint32_t rx_buffer_len; 343 uint16_t num_rx_desc; 344 int rx_process_limit; 345 struct em_buffer *rx_buffer_area; 346 bus_dma_tag_t rxtag; 347 bus_dmamap_t rx_sparemap; 348 349 /* 350 * First/last mbuf pointers, for 351 * collecting multisegment RX packets. 352 */ 353 struct mbuf *fmp; 354 struct mbuf *lmp; 355 356 /* Misc stats maintained by the driver */ 357 unsigned long dropped_pkts; 358 unsigned long mbuf_alloc_failed; 359 unsigned long mbuf_cluster_failed; 360 unsigned long no_tx_desc_avail1; 361 unsigned long no_tx_desc_avail2; 362 unsigned long no_tx_map_avail; 363 unsigned long no_tx_dma_setup; 364 unsigned long watchdog_events; 365 unsigned long rx_overruns; 366 367 /* Used in for 82547 10Mb Half workaround */ 368 #define EM_PBA_BYTES_SHIFT 0xA 369 #define EM_TX_HEAD_ADDR_SHIFT 7 370 #define EM_PBA_TX_MASK 0xFFFF0000 371 #define EM_FIFO_HDR 0x10 372 373 #define EM_82547_PKT_THRESH 0x3e0 374 375 uint32_t tx_fifo_size; 376 uint32_t tx_fifo_head; 377 uint32_t tx_fifo_head_addr; 378 uint64_t tx_fifo_reset_cnt; 379 uint64_t tx_fifo_wrk_cnt; 380 uint32_t tx_head_addr; 381 382 /* For 82544 PCIX Workaround */ 383 boolean_t pcix_82544; 384 boolean_t in_detach; 385 386 struct e1000_hw_stats stats; 387}; 388 389/* ****************************************************************************** 390 * vendor_info_array 391 * 392 * This array contains the list of Subvendor/Subdevice IDs on which the driver 393 * should load. 394 * 395 * ******************************************************************************/ 396typedef struct _em_vendor_info_t { 397 unsigned int vendor_id; 398 unsigned int device_id; 399 unsigned int subvendor_id; 400 unsigned int subdevice_id; 401 unsigned int index; 402} em_vendor_info_t; 403 404 405struct em_buffer { 406 int next_eop; /* Index of the desc to watch */ 407 struct mbuf *m_head; 408 bus_dmamap_t map; /* bus_dma map for packet */ 409}; 410 411/* For 82544 PCIX Workaround */ 412typedef struct _ADDRESS_LENGTH_PAIR 413{ 414 uint64_t address; 415 uint32_t length; 416} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 417 418typedef struct _DESCRIPTOR_PAIR 419{ 420 ADDRESS_LENGTH_PAIR descriptor[4]; 421 uint32_t elements; 422} DESC_ARRAY, *PDESC_ARRAY; 423 424#define EM_LOCK_INIT(_sc, _name) \ 425 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 426#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 427#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx) 428#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 429#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 430 431#endif /* _EM_H_DEFINED_ */ 432