if_em.h revision 163730
1/************************************************************************** 2 3Copyright (c) 2001-2006, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/*$FreeBSD: head/sys/dev/em/if_em.h 163730 2006-10-28 08:11:07Z jfv $*/ 35 36#ifndef _EM_H_DEFINED_ 37#define _EM_H_DEFINED_ 38 39/* Tunables */ 40 41/* 42 * EM_TXD: Maximum number of Transmit Descriptors 43 * Valid Range: 80-256 for 82542 and 82543-based adapters 44 * 80-4096 for others 45 * Default Value: 256 46 * This value is the number of transmit descriptors allocated by the driver. 47 * Increasing this value allows the driver to queue more transmits. Each 48 * descriptor is 16 bytes. 49 * Since TDLEN should be multiple of 128bytes, the number of transmit 50 * desscriptors should meet the following condition. 51 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 52 */ 53#define EM_MIN_TXD 80 54#define EM_MAX_TXD_82543 256 55#define EM_MAX_TXD 4096 56#define EM_DEFAULT_TXD EM_MAX_TXD_82543 57 58/* 59 * EM_RXD - Maximum number of receive Descriptors 60 * Valid Range: 80-256 for 82542 and 82543-based adapters 61 * 80-4096 for others 62 * Default Value: 256 63 * This value is the number of receive descriptors allocated by the driver. 64 * Increasing this value allows the driver to buffer more incoming packets. 65 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 66 * descriptor. The maximum MTU size is 16110. 67 * Since TDLEN should be multiple of 128bytes, the number of transmit 68 * desscriptors should meet the following condition. 69 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 70 */ 71#define EM_MIN_RXD 80 72#define EM_MAX_RXD_82543 256 73#define EM_MAX_RXD 4096 74#define EM_DEFAULT_RXD EM_MAX_RXD_82543 75 76/* 77 * EM_TIDV - Transmit Interrupt Delay Value 78 * Valid Range: 0-65535 (0=off) 79 * Default Value: 64 80 * This value delays the generation of transmit interrupts in units of 81 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 82 * efficiency if properly tuned for specific network traffic. If the 83 * system is reporting dropped transmits, this value may be set too high 84 * causing the driver to run out of available transmit descriptors. 85 */ 86#define EM_TIDV 64 87 88/* 89 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544) 90 * Valid Range: 0-65535 (0=off) 91 * Default Value: 64 92 * This value, in units of 1.024 microseconds, limits the delay in which a 93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94 * this value ensures that an interrupt is generated after the initial 95 * packet is sent on the wire within the set amount of time. Proper tuning, 96 * along with EM_TIDV, may improve traffic throughput in specific 97 * network conditions. 98 */ 99#define EM_TADV 64 100 101/* 102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103 * Valid Range: 0-65535 (0=off) 104 * Default Value: 0 105 * This value delays the generation of receive interrupts in units of 1.024 106 * microseconds. Receive interrupt reduction can improve CPU efficiency if 107 * properly tuned for specific network traffic. Increasing this value adds 108 * extra latency to frame reception and can end up decreasing the throughput 109 * of TCP traffic. If the system is reporting dropped receives, this value 110 * may be set too high, causing the driver to run out of available receive 111 * descriptors. 112 * 113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114 * may hang (stop transmitting) under certain network conditions. 115 * If this occurs a WATCHDOG message is logged in the system event log. 116 * In addition, the controller is automatically reset, restoring the 117 * network connection. To eliminate the potential for the hang 118 * ensure that EM_RDTR is set to 0. 119 */ 120#define EM_RDTR 0 121 122/* 123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124 * Valid Range: 0-65535 (0=off) 125 * Default Value: 64 126 * This value, in units of 1.024 microseconds, limits the delay in which a 127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128 * this value ensures that an interrupt is generated after the initial 129 * packet is received within the set amount of time. Proper tuning, 130 * along with EM_RDTR, may improve traffic throughput in specific network 131 * conditions. 132 */ 133#define EM_RADV 64 134 135/* 136 * Inform the stack about transmit checksum offload capabilities. 137 */ 138#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 139 140/* 141 * Inform the stack about transmit segmentation offload capabilities. 142 */ 143#define EM_TCPSEG_FEATURES CSUM_TSO 144 145/* 146 * This parameter controls the duration of transmit watchdog timer. 147 */ 148#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 149 150/* 151 * This parameter controls when the driver calls the routine to reclaim 152 * transmit descriptors. 153 */ 154#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 155 156/* 157 * This parameter controls whether or not autonegotation is enabled. 158 * 0 - Disable autonegotiation 159 * 1 - Enable autonegotiation 160 */ 161#define DO_AUTO_NEG 1 162 163/* 164 * This parameter control whether or not the driver will wait for 165 * autonegotiation to complete. 166 * 1 - Wait for autonegotiation to complete 167 * 0 - Don't wait for autonegotiation to complete 168 */ 169#define WAIT_FOR_AUTO_NEG_DEFAULT 0 170 171/* 172 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue 173 * with 82541/82547 devices and some switches. See the "Known Limitations" section of 174 * the README file for a complete description and a list of affected switches. 175 * 176 * 0 = Hardware default 177 * 1 = Master mode 178 * 2 = Slave mode 179 * 3 = Auto master/slave 180 */ 181/* #define EM_MASTER_SLAVE 2 */ 182 183/* Tunables -- End */ 184 185#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 186 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 187 ADVERTISE_1000_FULL) 188 189#define EM_VENDOR_ID 0x8086 190#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 191 192#define EM_JUMBO_PBA 0x00000028 193#define EM_DEFAULT_PBA 0x00000030 194#define EM_SMARTSPEED_DOWNSHIFT 3 195#define EM_SMARTSPEED_MAX 15 196 197#define MAX_NUM_MULTICAST_ADDRESSES 128 198#define PCI_ANY_ID (~0U) 199#define ETHER_ALIGN 2 200 201/* 202 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 203 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 204 * also optimize cache line size effect. H/W supports up to cache line size 128. 205 */ 206#define EM_DBA_ALIGN 128 207 208#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 209 210/* Defines for printing debug information */ 211#define DEBUG_INIT 0 212#define DEBUG_IOCTL 0 213#define DEBUG_HW 0 214 215#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 216#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 217#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 218#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 219#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 220#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 221#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 222#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 223#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 224 225 226/* Supported RX Buffer Sizes */ 227#define EM_RXBUFFER_2048 2048 228#define EM_RXBUFFER_4096 4096 229#define EM_RXBUFFER_8192 8192 230#define EM_RXBUFFER_16384 16384 231 232#define EM_MAX_SCATTER 64 233#define EM_TSO_SIZE 65535 234 235typedef enum _XSUM_CONTEXT_T { 236 OFFLOAD_NONE, 237 OFFLOAD_TCP_IP, 238 OFFLOAD_UDP_IP 239} XSUM_CONTEXT_T; 240 241struct adapter; 242 243struct em_int_delay_info { 244 struct adapter *adapter; /* Back-pointer to the adapter struct */ 245 int offset; /* Register offset to read/write */ 246 int value; /* Current value in usecs */ 247}; 248 249/* 250 * Bus dma allocation structure used by 251 * em_dma_malloc() and em_dma_free(). 252 */ 253struct em_dma_alloc { 254 bus_addr_t dma_paddr; 255 caddr_t dma_vaddr; 256 bus_dma_tag_t dma_tag; 257 bus_dmamap_t dma_map; 258 bus_dma_segment_t dma_seg; 259 int dma_nseg; 260}; 261 262/* Driver softc. */ 263struct adapter { 264 struct ifnet *ifp; 265 struct em_hw hw; 266 267 /* FreeBSD operating-system-specific structures. */ 268 struct em_osdep osdep; 269 struct device *dev; 270 struct resource *res_memory; 271 struct resource *flash_mem; 272 struct resource *res_ioport; 273 struct resource *res_interrupt; 274 void *int_handler_tag; 275 struct ifmedia media; 276 struct callout timer; 277 struct callout tx_fifo_timer; 278 int io_rid; 279 int if_flags; 280 struct mtx mtx; 281 int em_insert_vlan_header; 282 struct task link_task; 283 struct task rxtx_task; 284 struct taskqueue *tq; /* private task queue */ 285 286 /* Info about the board itself */ 287 uint32_t part_num; 288 uint8_t link_active; 289 uint16_t link_speed; 290 uint16_t link_duplex; 291 uint32_t smartspeed; 292 struct em_int_delay_info tx_int_delay; 293 struct em_int_delay_info tx_abs_int_delay; 294 struct em_int_delay_info rx_int_delay; 295 struct em_int_delay_info rx_abs_int_delay; 296 297 XSUM_CONTEXT_T active_checksum_context; 298 299 /* 300 * Transmit definitions 301 * 302 * We have an array of num_tx_desc descriptors (handled 303 * by the controller) paired with an array of tx_buffers 304 * (at tx_buffer_area). 305 * The index of the next available descriptor is next_avail_tx_desc. 306 * The number of remaining tx_desc is num_tx_desc_avail. 307 */ 308 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 309 struct em_tx_desc *tx_desc_base; 310 uint32_t next_avail_tx_desc; 311 uint32_t oldest_used_tx_desc; 312 volatile uint16_t num_tx_desc_avail; 313 uint16_t num_tx_desc; 314 uint32_t txd_cmd; 315 struct em_buffer *tx_buffer_area; 316 bus_dma_tag_t txtag; /* dma tag for tx */ 317 uint32_t tx_tso; /* last tx was tso */ 318 319 /* 320 * Receive definitions 321 * 322 * we have an array of num_rx_desc rx_desc (handled by the 323 * controller), and paired with an array of rx_buffers 324 * (at rx_buffer_area). 325 * The next pair to check on receive is at offset next_rx_desc_to_check 326 */ 327 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 328 struct em_rx_desc *rx_desc_base; 329 uint32_t next_rx_desc_to_check; 330 uint32_t rx_buffer_len; 331 uint16_t num_rx_desc; 332 int rx_process_limit; 333 struct em_buffer *rx_buffer_area; 334 bus_dma_tag_t rxtag; 335 bus_dmamap_t rx_sparemap; 336 337 /* First/last mbuf pointers, for collecting multisegment RX packets. */ 338 struct mbuf *fmp; 339 struct mbuf *lmp; 340 341 /* Misc stats maintained by the driver */ 342 unsigned long mbuf_alloc_failed; 343 unsigned long mbuf_cluster_failed; 344 unsigned long no_tx_desc_avail1; 345 unsigned long no_tx_desc_avail2; 346 unsigned long no_tx_map_avail; 347 unsigned long no_tx_dma_setup; 348 unsigned long watchdog_events; 349 unsigned long rx_overruns; 350 351 /* Used in for 82547 10Mb Half workaround */ 352 #define EM_PBA_BYTES_SHIFT 0xA 353 #define EM_TX_HEAD_ADDR_SHIFT 7 354 #define EM_PBA_TX_MASK 0xFFFF0000 355 #define EM_FIFO_HDR 0x10 356 357 #define EM_82547_PKT_THRESH 0x3e0 358 359 uint32_t tx_fifo_size; 360 uint32_t tx_fifo_head; 361 uint32_t tx_fifo_head_addr; 362 uint64_t tx_fifo_reset_cnt; 363 uint64_t tx_fifo_wrk_cnt; 364 uint32_t tx_head_addr; 365 366 /* For 82544 PCIX Workaround */ 367 boolean_t pcix_82544; 368 boolean_t in_detach; 369 370 struct em_hw_stats stats; 371}; 372 373/* ****************************************************************************** 374 * vendor_info_array 375 * 376 * This array contains the list of Subvendor/Subdevice IDs on which the driver 377 * should load. 378 * 379 * ******************************************************************************/ 380typedef struct _em_vendor_info_t { 381 unsigned int vendor_id; 382 unsigned int device_id; 383 unsigned int subvendor_id; 384 unsigned int subdevice_id; 385 unsigned int index; 386} em_vendor_info_t; 387 388 389struct em_buffer { 390 struct mbuf *m_head; 391 bus_dmamap_t map; /* bus_dma map for packet */ 392}; 393 394/* For 82544 PCIX Workaround */ 395typedef struct _ADDRESS_LENGTH_PAIR 396{ 397 u_int64_t address; 398 u_int32_t length; 399} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 400 401typedef struct _DESCRIPTOR_PAIR 402{ 403 ADDRESS_LENGTH_PAIR descriptor[4]; 404 u_int32_t elements; 405} DESC_ARRAY, *PDESC_ARRAY; 406 407#define EM_LOCK_INIT(_sc, _name) \ 408 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 409#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 410#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx) 411#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 412#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 413 414#endif /* _EM_H_DEFINED_ */ 415