if_em.h revision 163724
1/************************************************************************** 2 3Copyright (c) 2001-2006, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/if_em.h 163724 2006-10-28 00:47:55Z jfv $*/ 34 35#ifndef _EM_H_DEFINED_ 36#define _EM_H_DEFINED_ 37 38/* Tunables */ 39 40/* 41 * EM_TXD: Maximum number of Transmit Descriptors 42 * Valid Range: 80-256 for 82542 and 82543-based adapters 43 * 80-4096 for others 44 * Default Value: 256 45 * This value is the number of transmit descriptors allocated by the driver. 46 * Increasing this value allows the driver to queue more transmits. Each 47 * descriptor is 16 bytes. 48 * Since TDLEN should be multiple of 128bytes, the number of transmit 49 * desscriptors should meet the following condition. 50 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 51 */ 52#define EM_MIN_TXD 80 53#define EM_MAX_TXD_82543 256 54#define EM_MAX_TXD 4096 55#define EM_DEFAULT_TXD EM_MAX_TXD_82543 56 57/* 58 * EM_RXD - Maximum number of receive Descriptors 59 * Valid Range: 80-256 for 82542 and 82543-based adapters 60 * 80-4096 for others 61 * Default Value: 256 62 * This value is the number of receive descriptors allocated by the driver. 63 * Increasing this value allows the driver to buffer more incoming packets. 64 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 65 * descriptor. The maximum MTU size is 16110. 66 * Since TDLEN should be multiple of 128bytes, the number of transmit 67 * desscriptors should meet the following condition. 68 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 69 */ 70#define EM_MIN_RXD 80 71#define EM_MAX_RXD_82543 256 72#define EM_MAX_RXD 4096 73#define EM_DEFAULT_RXD EM_MAX_RXD_82543 74 75/* 76 * EM_TIDV - Transmit Interrupt Delay Value 77 * Valid Range: 0-65535 (0=off) 78 * Default Value: 64 79 * This value delays the generation of transmit interrupts in units of 80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 81 * efficiency if properly tuned for specific network traffic. If the 82 * system is reporting dropped transmits, this value may be set too high 83 * causing the driver to run out of available transmit descriptors. 84 */ 85#define EM_TIDV 64 86 87/* 88 * EM_TADV - Transmit Absolute Interrupt Delay Value 89 * (Not valid for 82542/82543/82544) 90 * Valid Range: 0-65535 (0=off) 91 * Default Value: 64 92 * This value, in units of 1.024 microseconds, limits the delay in which a 93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94 * this value ensures that an interrupt is generated after the initial 95 * packet is sent on the wire within the set amount of time. Proper tuning, 96 * along with EM_TIDV, may improve traffic throughput in specific 97 * network conditions. 98 */ 99#define EM_TADV 64 100 101/* 102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103 * Valid Range: 0-65535 (0=off) 104 * Default Value: 0 105 * This value delays the generation of receive interrupts in units of 1.024 106 * microseconds. Receive interrupt reduction can improve CPU efficiency if 107 * properly tuned for specific network traffic. Increasing this value adds 108 * extra latency to frame reception and can end up decreasing the throughput 109 * of TCP traffic. If the system is reporting dropped receives, this value 110 * may be set too high, causing the driver to run out of available receive 111 * descriptors. 112 * 113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114 * may hang (stop transmitting) under certain network conditions. 115 * If this occurs a WATCHDOG message is logged in the system 116 * event log. In addition, the controller is automatically reset, 117 * restoring the network connection. To eliminate the potential 118 * for the hang ensure that EM_RDTR is set to 0. 119 */ 120#define EM_RDTR 0 121 122/* 123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124 * Valid Range: 0-65535 (0=off) 125 * Default Value: 64 126 * This value, in units of 1.024 microseconds, limits the delay in which a 127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128 * this value ensures that an interrupt is generated after the initial 129 * packet is received within the set amount of time. Proper tuning, 130 * along with EM_RDTR, may improve traffic throughput in specific network 131 * conditions. 132 */ 133#define EM_RADV 64 134 135/* 136 * Inform the stack about transmit checksum offload capabilities. 137 */ 138#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 139 140#ifdef EM_TSO 141/* 142 * Inform the stack about transmit segmentation offload capabilities. 143 */ 144#define EM_TCPSEG_FEATURES CSUM_TSO 145#endif 146 147/* 148 * This parameter controls the duration of transmit watchdog timer. 149 */ 150#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 151 152/* 153 * This parameter controls when the driver calls the routine to reclaim 154 * transmit descriptors. 155 */ 156#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 157 158/* 159 * This parameter controls whether or not autonegotation is enabled. 160 * 0 - Disable autonegotiation 161 * 1 - Enable autonegotiation 162 */ 163#define DO_AUTO_NEG 1 164 165/* 166 * This parameter control whether or not the driver will wait for 167 * autonegotiation to complete. 168 * 1 - Wait for autonegotiation to complete 169 * 0 - Don't wait for autonegotiation to complete 170 */ 171#define WAIT_FOR_AUTO_NEG_DEFAULT 0 172 173/* 174 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 175 * compatibility issue with 82541/82547 devices and some switches. 176 * See the "Known Limitations" section of the README file for a complete 177 * description and a list of affected switches. 178 * 179 * 0 = Hardware default 180 * 1 = Master mode 181 * 2 = Slave mode 182 * 3 = Auto master/slave 183 */ 184/* #define EM_MASTER_SLAVE 2 */ 185 186/* Tunables -- End */ 187 188#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 189 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 190 ADVERTISE_1000_FULL) 191 192#define EM_VENDOR_ID 0x8086 193#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 194 195#define EM_JUMBO_PBA 0x00000028 196#define EM_DEFAULT_PBA 0x00000030 197#define EM_SMARTSPEED_DOWNSHIFT 3 198#define EM_SMARTSPEED_MAX 15 199 200#define MAX_NUM_MULTICAST_ADDRESSES 128 201#define PCI_ANY_ID (~0U) 202#define ETHER_ALIGN 2 203 204/* 205 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 206 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 207 * also optimize cache line size effect. H/W supports up to cache line size 128. 208 */ 209#define EM_DBA_ALIGN 128 210 211#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 212 213/* PCI Config defines */ 214#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 215#define EM_BAR_TYPE_MASK 0x00000001 216#define EM_BAR_TYPE_MMEM 0x00000000 217#define EM_BAR_TYPE_IO 0x00000001 218#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 219#define EM_BAR_MEM_TYPE_MASK 0x00000006 220#define EM_BAR_MEM_TYPE_32BIT 0x00000000 221#define EM_BAR_MEM_TYPE_64BIT 0x00000004 222/* 223 * Backward compatibility hack 224 */ 225#if !defined(PCIR_CIS) 226#define PCIR_CIS PCIR_CARDBUSCIS 227#endif 228 229/* Defines for printing debug information */ 230#define DEBUG_INIT 0 231#define DEBUG_IOCTL 0 232#define DEBUG_HW 0 233 234#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 235#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 236#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 237#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 238#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 239#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 240#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 241#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 242#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 243 244 245/* Supported RX Buffer Sizes */ 246#define EM_RXBUFFER_2048 2048 247#define EM_RXBUFFER_4096 4096 248#define EM_RXBUFFER_8192 8192 249#define EM_RXBUFFER_16384 16384 250 251#define EM_MAX_SCATTER 64 252#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */ 253 254/* ****************************************************************************** 255 * vendor_info_array 256 * 257 * This array contains the list of Subvendor/Subdevice IDs on which the driver 258 * should load. 259 * 260 * ******************************************************************************/ 261typedef struct _em_vendor_info_t { 262 unsigned int vendor_id; 263 unsigned int device_id; 264 unsigned int subvendor_id; 265 unsigned int subdevice_id; 266 unsigned int index; 267} em_vendor_info_t; 268 269 270struct em_buffer { 271 int next_eop; /* Index of the desc to watch */ 272 struct mbuf *m_head; 273 bus_dmamap_t map; /* bus_dma map for packet */ 274}; 275 276/* 277 * Bus dma allocation structure used by 278 * em_dma_malloc and em_dma_free. 279 */ 280struct em_dma_alloc { 281 bus_addr_t dma_paddr; 282 caddr_t dma_vaddr; 283 bus_dma_tag_t dma_tag; 284 bus_dmamap_t dma_map; 285 bus_dma_segment_t dma_seg; 286 int dma_nseg; 287}; 288 289typedef enum _XSUM_CONTEXT_T { 290 OFFLOAD_NONE, 291 OFFLOAD_TCP_IP, 292 OFFLOAD_UDP_IP 293} XSUM_CONTEXT_T; 294 295struct adapter adapter; /* XXX: ugly forward declaration */ 296struct em_int_delay_info { 297 struct adapter *adapter; /* Back-pointer to the adapter struct */ 298 int offset; /* Register offset to read/write */ 299 int value; /* Current value in usecs */ 300}; 301 302/* For 82544 PCIX Workaround */ 303typedef struct _ADDRESS_LENGTH_PAIR 304{ 305 uint64_t address; 306 uint32_t length; 307} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 308 309typedef struct _DESCRIPTOR_PAIR 310{ 311 ADDRESS_LENGTH_PAIR descriptor[4]; 312 uint32_t elements; 313} DESC_ARRAY, *PDESC_ARRAY; 314 315/* Our adapter structure */ 316struct adapter { 317 struct ifnet *ifp; 318 struct em_hw hw; 319 320 /* FreeBSD operating-system-specific structures. */ 321 struct em_osdep osdep; 322 struct device *dev; 323 struct resource *res_memory; 324 struct resource *flash_mem; 325 struct resource *res_ioport; 326 struct resource *res_interrupt; 327 void *int_handler_tag; 328 struct ifmedia media; 329 struct callout timer; 330 struct callout tx_fifo_timer; 331 int io_rid; 332 int if_flags; 333 struct mtx mtx; 334 int em_insert_vlan_header; 335 /* Info about the board itself */ 336 uint32_t part_num; 337 uint8_t link_active; 338 uint16_t link_speed; 339 uint16_t link_duplex; 340 uint32_t smartspeed; 341 struct em_int_delay_info tx_int_delay; 342 struct em_int_delay_info tx_abs_int_delay; 343 struct em_int_delay_info rx_int_delay; 344 struct em_int_delay_info rx_abs_int_delay; 345 346 XSUM_CONTEXT_T active_checksum_context; 347 348 /* 349 * Transmit definitions 350 * 351 * We have an array of num_tx_desc descriptors (handled 352 * by the controller) paired with an array of tx_buffers 353 * (at tx_buffer_area). 354 * The index of the next available descriptor is next_avail_tx_desc. 355 * The number of remaining tx_desc is num_tx_desc_avail. 356 */ 357 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 358 struct em_tx_desc *tx_desc_base; 359 uint32_t next_avail_tx_desc; 360 uint32_t next_tx_to_clean; 361 volatile uint16_t num_tx_desc_avail; 362 uint16_t num_tx_desc; 363 uint32_t txd_cmd; 364 struct em_buffer *tx_buffer_area; 365 bus_dma_tag_t txtag; /* dma tag for tx */ 366 uint32_t tx_tso; /* last tx was tso */ 367 368 /* 369 * Receive definitions 370 * 371 * we have an array of num_rx_desc rx_desc (handled by the 372 * controller), and paired with an array of rx_buffers 373 * (at rx_buffer_area). 374 * The next pair to check on receive is at offset next_rx_desc_to_check 375 */ 376 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 377 struct em_rx_desc *rx_desc_base; 378 uint32_t next_rx_desc_to_check; 379 uint32_t rx_buffer_len; 380 uint16_t num_rx_desc; 381 int rx_process_limit; 382 struct em_buffer *rx_buffer_area; 383 bus_dma_tag_t rxtag; 384 385 /* 386 * First/last mbuf pointers, for 387 * collecting multisegment RX packets. 388 */ 389 struct mbuf *fmp; 390 struct mbuf *lmp; 391 392 /* Misc stats maintained by the driver */ 393 unsigned long dropped_pkts; 394 unsigned long mbuf_alloc_failed; 395 unsigned long mbuf_cluster_failed; 396 unsigned long no_tx_desc_avail1; 397 unsigned long no_tx_desc_avail2; 398 unsigned long no_tx_map_avail; 399 unsigned long no_tx_dma_setup; 400 unsigned long watchdog_events; 401 unsigned long rx_overruns; 402 403 /* Used in for 82547 10Mb Half workaround */ 404 #define EM_PBA_BYTES_SHIFT 0xA 405 #define EM_TX_HEAD_ADDR_SHIFT 7 406 #define EM_PBA_TX_MASK 0xFFFF0000 407 #define EM_FIFO_HDR 0x10 408 409 #define EM_82547_PKT_THRESH 0x3e0 410 411 uint32_t tx_fifo_size; 412 uint32_t tx_fifo_head; 413 uint32_t tx_fifo_head_addr; 414 uint64_t tx_fifo_reset_cnt; 415 uint64_t tx_fifo_wrk_cnt; 416 uint32_t tx_head_addr; 417 418 /* For 82544 PCIX Workaround */ 419 boolean_t pcix_82544; 420 boolean_t in_detach; 421 422 struct em_hw_stats stats; 423}; 424 425#define EM_LOCK_INIT(_sc, _name) \ 426 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 427#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 428#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx) 429#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 430#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 431 432#endif /* _EM_H_DEFINED_ */ 433