if_em.h revision 160956
1139776Simp/************************************************************************** 21541Srgrimes 31541SrgrimesCopyright (c) 2001-2006, Intel Corporation 41541SrgrimesAll rights reserved. 51541Srgrimes 61541SrgrimesRedistribution and use in source and binary forms, with or without 71541Srgrimesmodification, are permitted provided that the following conditions are met: 81541Srgrimes 91541Srgrimes 1. Redistributions of source code must retain the above copyright notice, 101541Srgrimes this list of conditions and the following disclaimer. 111541Srgrimes 121541Srgrimes 2. Redistributions in binary form must reproduce the above copyright 131541Srgrimes notice, this list of conditions and the following disclaimer in the 141541Srgrimes documentation and/or other materials provided with the distribution. 151541Srgrimes 161541Srgrimes 3. Neither the name of the Intel Corporation nor the names of its 171541Srgrimes contributors may be used to endorse or promote products derived from 181541Srgrimes this software without specific prior written permission. 191541Srgrimes 201541SrgrimesTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 211541SrgrimesAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221541SrgrimesIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231541SrgrimesARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 241541SrgrimesLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251541SrgrimesCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261541SrgrimesSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271541SrgrimesINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281541SrgrimesCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291541SrgrimesARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 301541SrgrimesPOSSIBILITY OF SUCH DAMAGE. 311541Srgrimes 321541Srgrimes***************************************************************************/ 3322521Sdyson 3490717Sbde/*$FreeBSD: head/sys/dev/em/if_em.h 160956 2006-08-03 19:05:04Z pdeuskar $*/ 3590717Sbde 36128019Simp#ifndef _EM_H_DEFINED_ 3750477Speter#define _EM_H_DEFINED_ 381541Srgrimes 391541Srgrimes/* Tunables */ 401541Srgrimes 411541Srgrimes/* 4276166Smarkm * EM_TXD: Maximum number of Transmit Descriptors 4376166Smarkm * Valid Range: 80-256 for 82542 and 82543-based adapters 441541Srgrimes * 80-4096 for others 457090Sbde * Default Value: 256 4687321Sdes * This value is the number of transmit descriptors allocated by the driver. 477090Sbde * Increasing this value allows the driver to queue more transmits. Each 4874927Sjhb * descriptor is 16 bytes. 4987321Sdes * Since TDLEN should be multiple of 128bytes, the number of transmit 5076166Smarkm * desscriptors should meet the following condition. 5187321Sdes * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 5277031Sru */ 537090Sbde#define EM_MIN_TXD 80 5422579Smpp#define EM_MAX_TXD_82543 256 5522579Smpp#define EM_MAX_TXD 4096 561541Srgrimes#define EM_DEFAULT_TXD EM_MAX_TXD_82543 571541Srgrimes 581541Srgrimes/* 591541Srgrimes * EM_RXD - Maximum number of receive Descriptors 601541Srgrimes * Valid Range: 80-256 for 82542 and 82543-based adapters 6199072Sjulian * 80-4096 for others 621541Srgrimes * Default Value: 256 631541Srgrimes * This value is the number of receive descriptors allocated by the driver. 641541Srgrimes * Increasing this value allows the driver to buffer more incoming packets. 651541Srgrimes * Each descriptor is 16 bytes. A receive buffer is also allocated for each 661541Srgrimes * descriptor. The maximum MTU size is 16110. 671541Srgrimes * Since TDLEN should be multiple of 128bytes, the number of transmit 681541Srgrimes * desscriptors should meet the following condition. 691541Srgrimes * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 701541Srgrimes */ 7187321Sdes#define EM_MIN_RXD 80 7287321Sdes#define EM_MAX_RXD_82543 256 7387321Sdes#define EM_MAX_RXD 4096 7487321Sdes#define EM_DEFAULT_RXD EM_MAX_RXD_82543 7587321Sdes 7687321Sdes/* 771541Srgrimes * EM_TIDV - Transmit Interrupt Delay Value 781541Srgrimes * Valid Range: 0-65535 (0=off) 791541Srgrimes * Default Value: 64 801541Srgrimes * This value delays the generation of transmit interrupts in units of 811541Srgrimes * 1.024 microseconds. Transmit interrupt reduction can improve CPU 821541Srgrimes * efficiency if properly tuned for specific network traffic. If the 831541Srgrimes * system is reporting dropped transmits, this value may be set too high 841541Srgrimes * causing the driver to run out of available transmit descriptors. 851541Srgrimes */ 8687321Sdes#define EM_TIDV 64 871541Srgrimes 881541Srgrimes/* 891541Srgrimes * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544) 901541Srgrimes * Valid Range: 0-65535 (0=off) 911541Srgrimes * Default Value: 64 921541Srgrimes * This value, in units of 1.024 microseconds, limits the delay in which a 931541Srgrimes * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 941541Srgrimes * this value ensures that an interrupt is generated after the initial 951541Srgrimes * packet is sent on the wire within the set amount of time. Proper tuning, 961541Srgrimes * along with EM_TIDV, may improve traffic throughput in specific 971541Srgrimes * network conditions. 981541Srgrimes */ 991541Srgrimes#define EM_TADV 64 1001541Srgrimes 1011541Srgrimes/* 1021541Srgrimes * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 1031541Srgrimes * Valid Range: 0-65535 (0=off) 1041541Srgrimes * Default Value: 0 1051541Srgrimes * This value delays the generation of receive interrupts in units of 1.024 1061541Srgrimes * microseconds. Receive interrupt reduction can improve CPU efficiency if 10794624Sjhb * properly tuned for specific network traffic. Increasing this value adds 10812595Sbde * extra latency to frame reception and can end up decreasing the throughput 1091541Srgrimes * of TCP traffic. If the system is reporting dropped receives, this value 11094624Sjhb * may be set too high, causing the driver to run out of available receive 1111541Srgrimes * descriptors. 11274927Sjhb * 113207847Skib * CAUTION: When setting EM_RDTR to a value other than 0, adapters 1141541Srgrimes * may hang (stop transmitting) under certain network conditions. 1151541Srgrimes * If this occurs a WATCHDOG message is logged in the system event log. 1161541Srgrimes * In addition, the controller is automatically reset, restoring the 1171541Srgrimes * network connection. To eliminate the potential for the hang 1181541Srgrimes * ensure that EM_RDTR is set to 0. 1191541Srgrimes */ 12074927Sjhb#define EM_RDTR 0 12173918Sjhb 12296886Sjhb/* 12394624Sjhb * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 12473918Sjhb * Valid Range: 0-65535 (0=off) 12574927Sjhb * Default Value: 64 12674927Sjhb * This value, in units of 1.024 microseconds, limits the delay in which a 12773918Sjhb * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 1281541Srgrimes * this value ensures that an interrupt is generated after the initial 12974996Sjhb * packet is received within the set amount of time. Proper tuning, 13094624Sjhb * along with EM_RDTR, may improve traffic throughput in specific network 13174927Sjhb * conditions. 13274927Sjhb */ 13373918Sjhb#define EM_RADV 64 1341541Srgrimes 1351541Srgrimes/* 1361541Srgrimes * Inform the stack about transmit checksum offload capabilities. 1371541Srgrimes */ 1381541Srgrimes#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 1391541Srgrimes 1401541Srgrimes/* 1411541Srgrimes * This parameter controls the duration of transmit watchdog timer. 1421541Srgrimes */ 1431541Srgrimes#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 1446569Sdg 1451541Srgrimes/* 14694624Sjhb * This parameter controls when the driver calls the routine to reclaim 1471541Srgrimes * transmit descriptors. 14894624Sjhb */ 1491541Srgrimes#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 15073918Sjhb 15174996Sjhb/* 15273918Sjhb * This parameter controls whether or not autonegotation is enabled. 15374927Sjhb * 0 - Disable autonegotiation 15474996Sjhb * 1 - Enable autonegotiation 1551541Srgrimes */ 1561541Srgrimes#define DO_AUTO_NEG 1 1571541Srgrimes 15894624Sjhb/* 15994624Sjhb * This parameter control whether or not the driver will wait for 16094624Sjhb * autonegotiation to complete. 16194624Sjhb * 1 - Wait for autonegotiation to complete 16294624Sjhb * 0 - Don't wait for autonegotiation to complete 16394624Sjhb */ 16494624Sjhb#define WAIT_FOR_AUTO_NEG_DEFAULT 0 16596886Sjhb 16694624Sjhb/* 16794624Sjhb * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue 16894624Sjhb * with 82541/82547 devices and some switches. See the "Known Limitations" section of 16994624Sjhb * the README file for a complete description and a list of affected switches. 17094624Sjhb * 17194624Sjhb * 0 = Hardware default 1721541Srgrimes * 1 = Master mode 1731541Srgrimes * 2 = Slave mode 1741541Srgrimes * 3 = Auto master/slave 1751541Srgrimes */ 1761541Srgrimes/* #define EM_MASTER_SLAVE 2 */ 1771541Srgrimes 1781541Srgrimes/* Tunables -- End */ 1791541Srgrimes 1801541Srgrimes#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 1811541Srgrimes ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 18294624Sjhb ADVERTISE_1000_FULL) 18373918Sjhb 1841541Srgrimes#define EM_VENDOR_ID 0x8086 18569507Sjhb#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 1861541Srgrimes 1871541Srgrimes#define EM_JUMBO_PBA 0x00000028 18813608Speter#define EM_DEFAULT_PBA 0x00000030 18913608Speter#define EM_SMARTSPEED_DOWNSHIFT 3 1901541Srgrimes#define EM_SMARTSPEED_MAX 15 1911541Srgrimes 1921541Srgrimes#define MAX_NUM_MULTICAST_ADDRESSES 128 193177091Sjeff#define PCI_ANY_ID (~0U) 19413608Speter#define ETHER_ALIGN 2 1951541Srgrimes 1961541Srgrimes/* 1971541Srgrimes * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 1981541Srgrimes * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 1991541Srgrimes * also optimize cache line size effect. H/W supports up to cache line size 128. 2001541Srgrimes */ 2011541Srgrimes#define EM_DBA_ALIGN 128 2021541Srgrimes 2031541Srgrimes#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 2041541Srgrimes 2051541Srgrimes/* Defines for printing debug information */ 2061541Srgrimes#define DEBUG_INIT 0 2071541Srgrimes#define DEBUG_IOCTL 0 2081541Srgrimes#define DEBUG_HW 0 2091541Srgrimes 21073918Sjhb#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 21173918Sjhb#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 2121541Srgrimes#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 21373918Sjhb#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 2141541Srgrimes#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 2151541Srgrimes#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 216207847Skib#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 2171541Srgrimes#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 2185312Sache#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 219151316Sdavidxu 220207847Skib 221207847Skib/* Supported RX Buffer Sizes */ 22273918Sjhb#define EM_RXBUFFER_2048 2048 2235312Sache#define EM_RXBUFFER_4096 4096 2241541Srgrimes#define EM_RXBUFFER_8192 8192 22574927Sjhb#define EM_RXBUFFER_16384 16384 2261541Srgrimes 2271541Srgrimes#define EM_MAX_SCATTER 64 2281541Srgrimes 2291541Srgrimestypedef enum _XSUM_CONTEXT_T { 23073918Sjhb OFFLOAD_NONE, 23191140Stanimura OFFLOAD_TCP_IP, 23291140Stanimura OFFLOAD_UDP_IP 2331541Srgrimes} XSUM_CONTEXT_T; 23491140Stanimura 23573918Sjhbstruct adapter adapter; /* XXX: ugly forward declaration */ 23673918Sjhbstruct em_int_delay_info { 23773918Sjhb struct adapter *adapter; /* XXX: ugly pointer */ 23873918Sjhb int offset; /* Register offset to read/write */ 23974927Sjhb int value; /* Current value in usecs */ 2401541Srgrimes}; 241111738Sdes 2421541Srgrimes/* 2431541Srgrimes * Bus dma allocation structure used by 2441541Srgrimes * em_dma_malloc() and em_dma_free(). 2451541Srgrimes */ 2461541Srgrimesstruct em_dma_alloc { 247123247Sdes bus_addr_t dma_paddr; 2481541Srgrimes caddr_t dma_vaddr; 2491541Srgrimes bus_dma_tag_t dma_tag; 250177091Sjeff bus_dmamap_t dma_map; 251207848Skib bus_dma_segment_t dma_seg; 252207848Skib int dma_nseg; 25322521Sdyson}; 254207848Skib 2551541Srgrimes/* Driver softc. */ 2561541Srgrimesstruct adapter { 2571541Srgrimes struct ifnet *ifp; 2581541Srgrimes struct em_hw hw; 2591541Srgrimes 2601541Srgrimes /* FreeBSD operating-system-specific structures. */ 2611541Srgrimes struct em_osdep osdep; 262113619Sjhb struct device *dev; 2631541Srgrimes struct resource *res_memory; 2641541Srgrimes struct resource *flash_mem; 2651541Srgrimes struct resource *res_ioport; 2661541Srgrimes struct resource *res_interrupt; 2671541Srgrimes void *int_handler_tag; 2681541Srgrimes struct ifmedia media; 2691541Srgrimes struct callout timer; 2701541Srgrimes struct callout tx_fifo_timer; 2711541Srgrimes int io_rid; 2721541Srgrimes int if_flags; 27399072Sjulian struct mtx mtx; 2741541Srgrimes int em_insert_vlan_header; 27594624Sjhb struct task link_task; 276111738Sdes struct task rxtx_task; 2771541Srgrimes struct taskqueue *tq; /* private task queue */ 27894624Sjhb 2791541Srgrimes /* Info about the board itself */ 28099072Sjulian uint32_t part_num; 28199072Sjulian uint8_t link_active; 282111738Sdes uint16_t link_speed; 2831541Srgrimes uint16_t link_duplex; 28499072Sjulian uint32_t smartspeed; 28594624Sjhb struct em_int_delay_info tx_int_delay; 2861541Srgrimes struct em_int_delay_info tx_abs_int_delay; 2871541Srgrimes struct em_int_delay_info rx_int_delay; 2881541Srgrimes struct em_int_delay_info rx_abs_int_delay; 2891541Srgrimes 2901541Srgrimes XSUM_CONTEXT_T active_checksum_context; 291170307Sjeff 29299072Sjulian /* 293170307Sjeff * Transmit definitions 294207848Skib * 2951541Srgrimes * We have an array of num_tx_desc descriptors (handled 2961541Srgrimes * by the controller) paired with an array of tx_buffers 2971541Srgrimes * (at tx_buffer_area). 29887321Sdes * The index of the next available descriptor is next_avail_tx_desc. 29987321Sdes * The number of remaining tx_desc is num_tx_desc_avail. 30087321Sdes */ 30187321Sdes struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 30287321Sdes struct em_tx_desc *tx_desc_base; 30387321Sdes uint32_t next_avail_tx_desc; 30487321Sdes uint32_t oldest_used_tx_desc; 30587321Sdes volatile uint16_t num_tx_desc_avail; 30687321Sdes uint16_t num_tx_desc; 30787321Sdes uint32_t txd_cmd; 30887321Sdes struct em_buffer *tx_buffer_area; 3091541Srgrimes bus_dma_tag_t txtag; /* dma tag for tx */ 31087321Sdes 3111541Srgrimes /* 3121541Srgrimes * Receive definitions 31387321Sdes * 3141541Srgrimes * we have an array of num_rx_desc rx_desc (handled by the 31587321Sdes * controller), and paired with an array of rx_buffers 3161541Srgrimes * (at rx_buffer_area). 3171541Srgrimes * The next pair to check on receive is at offset next_rx_desc_to_check 3181541Srgrimes */ 3191541Srgrimes struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 3201541Srgrimes struct em_rx_desc *rx_desc_base; 3211541Srgrimes uint32_t next_rx_desc_to_check; 3221541Srgrimes uint32_t rx_buffer_len; 3231541Srgrimes uint16_t num_rx_desc; 3241541Srgrimes int rx_process_limit; 3251541Srgrimes struct em_buffer *rx_buffer_area; 3261541Srgrimes bus_dma_tag_t rxtag; 3271541Srgrimes 3281541Srgrimes /* First/last mbuf pointers, for collecting multisegment RX packets. */ 32987321Sdes struct mbuf *fmp; 33087321Sdes struct mbuf *lmp; 33187321Sdes 3321541Srgrimes /* Misc stats maintained by the driver */ 33387321Sdes unsigned long dropped_pkts; 33494624Sjhb unsigned long mbuf_alloc_failed; 3351541Srgrimes unsigned long mbuf_cluster_failed; 33687321Sdes unsigned long no_tx_desc_avail1; 3371541Srgrimes unsigned long no_tx_desc_avail2; 33887321Sdes unsigned long no_tx_map_avail; 33973918Sjhb unsigned long no_tx_dma_setup; 34090361Sjulian unsigned long watchdog_events; 34187321Sdes unsigned long rx_overruns; 3421541Srgrimes 34313608Speter /* Used in for 82547 10Mb Half workaround */ 34490717Sbde #define EM_PBA_BYTES_SHIFT 0xA 34513608Speter #define EM_TX_HEAD_ADDR_SHIFT 7 346102950Sdavidxu #define EM_PBA_TX_MASK 0xFFFF0000 347170307Sjeff #define EM_FIFO_HDR 0x10 348103216Sjulian 349170307Sjeff #define EM_82547_PKT_THRESH 0x3e0 35094624Sjhb 3511541Srgrimes uint32_t tx_fifo_size; 35273918Sjhb uint32_t tx_fifo_head; 3531541Srgrimes uint32_t tx_fifo_head_addr; 3541541Srgrimes uint64_t tx_fifo_reset_cnt; 3551541Srgrimes uint64_t tx_fifo_wrk_cnt; 3561541Srgrimes uint32_t tx_head_addr; 3571541Srgrimes 3581541Srgrimes /* For 82544 PCIX Workaround */ 359 boolean_t pcix_82544; 360 boolean_t in_detach; 361 362 struct em_hw_stats stats; 363}; 364 365/* ****************************************************************************** 366 * vendor_info_array 367 * 368 * This array contains the list of Subvendor/Subdevice IDs on which the driver 369 * should load. 370 * 371 * ******************************************************************************/ 372typedef struct _em_vendor_info_t { 373 unsigned int vendor_id; 374 unsigned int device_id; 375 unsigned int subvendor_id; 376 unsigned int subdevice_id; 377 unsigned int index; 378} em_vendor_info_t; 379 380 381struct em_buffer { 382 struct mbuf *m_head; 383 bus_dmamap_t map; /* bus_dma map for packet */ 384}; 385 386/* For 82544 PCIX Workaround */ 387typedef struct _ADDRESS_LENGTH_PAIR 388{ 389 u_int64_t address; 390 u_int32_t length; 391} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 392 393typedef struct _DESCRIPTOR_PAIR 394{ 395 ADDRESS_LENGTH_PAIR descriptor[4]; 396 u_int32_t elements; 397} DESC_ARRAY, *PDESC_ARRAY; 398 399#define EM_LOCK_INIT(_sc, _name) \ 400 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 401#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 402#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx) 403#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 404#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 405 406#endif /* _EM_H_DEFINED_ */ 407