if_em.h revision 154204 
1/**************************************************************************
2
3Copyright (c) 2001-2005, Intel Corporation
4All rights reserved.
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7modification, are permitted provided that the following conditions are met:
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10    this list of conditions and the following disclaimer.
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12 2. Redistributions in binary form must reproduce the above copyright
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14    documentation and/or other materials provided with the distribution.
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16 3. Neither the name of the Intel Corporation nor the names of its
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19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34/*$FreeBSD: head/sys/dev/em/if_em.h 154204 2006-01-11 00:30:25Z scottl $*/
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/endian.h>
44#include <sys/kernel.h>
45#include <sys/mbuf.h>
46#include <sys/malloc.h>
47#include <sys/module.h>
48#include <sys/socket.h>
49#include <sys/sockio.h>
50#include <sys/sysctl.h>
51#include <sys/taskqueue.h>
52#include <sys/kthread.h>
53#include <sys/proc.h>
54#include <sys/sched.h>
55
56#include <machine/bus.h>
57#include <sys/rman.h>
58#include <machine/resource.h>
59
60#include <net/bpf.h>
61#include <net/ethernet.h>
62#include <net/if.h>
63#include <net/if_arp.h>
64#include <net/if_dl.h>
65#include <net/if_media.h>
66
67#include <net/if_types.h>
68#include <net/if_vlan_var.h>
69
70#include <netinet/in_systm.h>
71#include <netinet/in.h>
72#include <netinet/ip.h>
73#include <netinet/tcp.h>
74#include <netinet/udp.h>
75
76#include <dev/pci/pcivar.h>
77#include <dev/pci/pcireg.h>
78
79#include <dev/em/if_em_hw.h>
80
81/* Tunables */
82
83/*
84 * EM_TXD: Maximum number of Transmit Descriptors
85 * Valid Range: 80-256 for 82542 and 82543-based adapters
86 *              80-4096 for others
87 * Default Value: 256
88 *   This value is the number of transmit descriptors allocated by the driver.
89 *   Increasing this value allows the driver to queue more transmits. Each
90 *   descriptor is 16 bytes.
91 *   Since TDLEN should be multiple of 128bytes, the number of transmit
92 *   desscriptors should meet the following condition.
93 *      (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0
94 */
95#define EM_MIN_TXD		80
96#define EM_MAX_TXD_82543	256
97#define EM_MAX_TXD		4096
98#define EM_DEFAULT_TXD		EM_MAX_TXD_82543
99
100/*
101 * EM_RXD - Maximum number of receive Descriptors
102 * Valid Range: 80-256 for 82542 and 82543-based adapters
103 *              80-4096 for others
104 * Default Value: 256
105 *   This value is the number of receive descriptors allocated by the driver.
106 *   Increasing this value allows the driver to buffer more incoming packets.
107 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
108 *   descriptor. The maximum MTU size is 16110.
109 *   Since TDLEN should be multiple of 128bytes, the number of transmit
110 *   desscriptors should meet the following condition.
111 *      (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0
112 */
113#define EM_MIN_RXD		80
114#define EM_MAX_RXD_82543	256
115#define EM_MAX_RXD		4096
116#define EM_DEFAULT_RXD		EM_MAX_RXD_82543
117
118/*
119 * EM_TIDV - Transmit Interrupt Delay Value
120 * Valid Range: 0-65535 (0=off)
121 * Default Value: 64
122 *   This value delays the generation of transmit interrupts in units of
123 *   1.024 microseconds. Transmit interrupt reduction can improve CPU
124 *   efficiency if properly tuned for specific network traffic. If the
125 *   system is reporting dropped transmits, this value may be set too high
126 *   causing the driver to run out of available transmit descriptors.
127 */
128#define EM_TIDV                         64
129
130/*
131 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544)
132 * Valid Range: 0-65535 (0=off)
133 * Default Value: 64
134 *   This value, in units of 1.024 microseconds, limits the delay in which a
135 *   transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
136 *   this value ensures that an interrupt is generated after the initial
137 *   packet is sent on the wire within the set amount of time.  Proper tuning,
138 *   along with EM_TIDV, may improve traffic throughput in specific
139 *   network conditions.
140 */
141#define EM_TADV                         64
142
143/*
144 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
145 * Valid Range: 0-65535 (0=off)
146 * Default Value: 0
147 *   This value delays the generation of receive interrupts in units of 1.024
148 *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
149 *   properly tuned for specific network traffic. Increasing this value adds
150 *   extra latency to frame reception and can end up decreasing the throughput
151 *   of TCP traffic. If the system is reporting dropped receives, this value
152 *   may be set too high, causing the driver to run out of available receive
153 *   descriptors.
154 *
155 *   CAUTION: When setting EM_RDTR to a value other than 0, adapters
156 *            may hang (stop transmitting) under certain network conditions.
157 *            If this occurs a WATCHDOG message is logged in the system event log.
158 *            In addition, the controller is automatically reset, restoring the
159 *            network connection. To eliminate the potential for the hang
160 *            ensure that EM_RDTR is set to 0.
161 */
162#define EM_RDTR                         0
163
164/*
165 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
166 * Valid Range: 0-65535 (0=off)
167 * Default Value: 64
168 *   This value, in units of 1.024 microseconds, limits the delay in which a
169 *   receive interrupt is generated. Useful only if EM_RDTR is non-zero,
170 *   this value ensures that an interrupt is generated after the initial
171 *   packet is received within the set amount of time.  Proper tuning,
172 *   along with EM_RDTR, may improve traffic throughput in specific network
173 *   conditions.
174 */
175#define EM_RADV                         64
176
177/*
178 * Inform the stack about transmit checksum offload capabilities.
179 */
180#define EM_CHECKSUM_FEATURES            (CSUM_TCP | CSUM_UDP)
181
182/*
183 * This parameter controls the duration of transmit watchdog timer.
184 */
185#define EM_TX_TIMEOUT                   5    /* set to 5 seconds */
186
187/*
188 * This parameter controls when the driver calls the routine to reclaim
189 * transmit descriptors.
190 */
191#define EM_TX_CLEANUP_THRESHOLD		(adapter->num_tx_desc / 8)
192
193/*
194 * This parameter controls whether or not autonegotation is enabled.
195 *              0 - Disable autonegotiation
196 *              1 - Enable  autonegotiation
197 */
198#define DO_AUTO_NEG                     1
199
200/*
201 * This parameter control whether or not the driver will wait for
202 * autonegotiation to complete.
203 *              1 - Wait for autonegotiation to complete
204 *              0 - Don't wait for autonegotiation to complete
205 */
206#define WAIT_FOR_AUTO_NEG_DEFAULT       0
207
208/*
209 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue
210 * with 82541/82547 devices and some switches.  See the "Known Limitations" section of
211 * the README file for a complete description and a list of affected switches.
212 *
213 *              0 = Hardware default
214 *              1 = Master mode
215 *              2 = Slave mode
216 *              3 = Auto master/slave
217 */
218/* #define EM_MASTER_SLAVE      2 */
219
220/* Tunables -- End */
221
222#define AUTONEG_ADV_DEFAULT             (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
223                                         ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
224                                         ADVERTISE_1000_FULL)
225
226#define EM_VENDOR_ID                    0x8086
227
228#define EM_JUMBO_PBA                    0x00000028
229#define EM_DEFAULT_PBA                  0x00000030
230#define EM_SMARTSPEED_DOWNSHIFT         3
231#define EM_SMARTSPEED_MAX               15
232
233
234#define MAX_NUM_MULTICAST_ADDRESSES     128
235#define PCI_ANY_ID                      (~0U)
236#define ETHER_ALIGN                     2
237
238/* Defines for printing debug information */
239#define DEBUG_INIT  0
240#define DEBUG_IOCTL 0
241#define DEBUG_HW    0
242
243#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
244#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
245#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
246#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
247#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
248#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
249#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
250#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
251#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
252
253
254/* Supported RX Buffer Sizes */
255#define EM_RXBUFFER_2048        2048
256#define EM_RXBUFFER_4096        4096
257#define EM_RXBUFFER_8192        8192
258#define EM_RXBUFFER_16384      16384
259
260#define EM_MAX_SCATTER            64
261
262/* ******************************************************************************
263 * vendor_info_array
264 *
265 * This array contains the list of Subvendor/Subdevice IDs on which the driver
266 * should load.
267 *
268 * ******************************************************************************/
269typedef struct _em_vendor_info_t {
270	unsigned int vendor_id;
271	unsigned int device_id;
272	unsigned int subvendor_id;
273	unsigned int subdevice_id;
274	unsigned int index;
275} em_vendor_info_t;
276
277
278struct em_buffer {
279        struct mbuf    *m_head;
280        bus_dmamap_t    map;         /* bus_dma map for packet */
281};
282
283/*
284 * Bus dma allocation structure used by
285 * em_dma_malloc and em_dma_free.
286 */
287struct em_dma_alloc {
288        bus_addr_t              dma_paddr;
289        caddr_t                 dma_vaddr;
290        bus_dma_tag_t           dma_tag;
291        bus_dmamap_t            dma_map;
292        bus_dma_segment_t       dma_seg;
293        int                     dma_nseg;
294};
295
296typedef enum _XSUM_CONTEXT_T {
297	OFFLOAD_NONE,
298	OFFLOAD_TCP_IP,
299	OFFLOAD_UDP_IP
300} XSUM_CONTEXT_T;
301
302struct adapter;
303struct em_int_delay_info {
304	struct adapter *adapter;	/* Back-pointer to the adapter struct */
305	int offset;			/* Register offset to read/write */
306	int value;			/* Current value in usecs */
307};
308
309/* For 82544 PCIX  Workaround */
310typedef struct _ADDRESS_LENGTH_PAIR
311{
312    u_int64_t   address;
313    u_int32_t   length;
314} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
315
316typedef struct _DESCRIPTOR_PAIR
317{
318    ADDRESS_LENGTH_PAIR descriptor[4];
319    u_int32_t   elements;
320} DESC_ARRAY, *PDESC_ARRAY;
321
322/* Our adapter structure */
323struct adapter {
324	struct ifnet   *ifp;
325	struct em_hw    hw;
326
327	/* FreeBSD operating-system-specific structures */
328	struct em_osdep osdep;
329	struct device   *dev;
330	struct resource *res_memory;
331	struct resource *res_ioport;
332	struct resource *res_interrupt;
333	void            *int_handler_tag;
334	struct ifmedia  media;
335	struct callout	timer;
336	struct callout	tx_fifo_timer;
337	int             io_rid;
338	u_int8_t        unit;
339	struct mtx	mtx;
340	int		em_insert_vlan_header;
341	struct task	link_task;
342	struct task	rxtx_task;
343	struct taskqueue *tq;		/* private task queue */
344	struct proc	*tqproc;	/* thread handling sc_tq */
345
346	/* Info about the board itself */
347	u_int32_t       part_num;
348	u_int8_t        link_active;
349	u_int16_t       link_speed;
350	u_int16_t       link_duplex;
351	u_int32_t       smartspeed;
352	struct em_int_delay_info tx_int_delay;
353	struct em_int_delay_info tx_abs_int_delay;
354	struct em_int_delay_info rx_int_delay;
355	struct em_int_delay_info rx_abs_int_delay;
356
357	XSUM_CONTEXT_T  active_checksum_context;
358
359	/*
360         * Transmit definitions
361         *
362         * We have an array of num_tx_desc descriptors (handled
363         * by the controller) paired with an array of tx_buffers
364         * (at tx_buffer_area).
365         * The index of the next available descriptor is next_avail_tx_desc.
366         * The number of remaining tx_desc is num_tx_desc_avail.
367         */
368	struct em_dma_alloc txdma;              /* bus_dma glue for tx desc */
369        struct em_tx_desc *tx_desc_base;
370        u_int32_t          next_avail_tx_desc;
371	u_int32_t          oldest_used_tx_desc;
372        volatile u_int16_t num_tx_desc_avail;
373        u_int16_t          num_tx_desc;
374        u_int32_t          txd_cmd;
375        struct em_buffer   *tx_buffer_area;
376	bus_dma_tag_t      txtag;               /* dma tag for tx */
377
378	/*
379	 * Receive definitions
380         *
381         * we have an array of num_rx_desc rx_desc (handled by the
382         * controller), and paired with an array of rx_buffers
383         * (at rx_buffer_area).
384         * The next pair to check on receive is at offset next_rx_desc_to_check
385         */
386	struct em_dma_alloc rxdma;              /* bus_dma glue for rx desc */
387        struct em_rx_desc *rx_desc_base;
388        u_int32_t          next_rx_desc_to_check;
389        u_int32_t          rx_buffer_len;
390        u_int16_t          num_rx_desc;
391        int                rx_process_limit;
392        struct em_buffer   *rx_buffer_area;
393	bus_dma_tag_t      rxtag;
394
395	/* Jumbo frame */
396	struct mbuf        *fmp;
397	struct mbuf        *lmp;
398
399	/* Misc stats maintained by the driver */
400	unsigned long   dropped_pkts;
401	unsigned long   mbuf_alloc_failed;
402	unsigned long   mbuf_cluster_failed;
403	unsigned long   no_tx_desc_avail1;
404	unsigned long   no_tx_desc_avail2;
405	unsigned long   no_tx_map_avail;
406        unsigned long   no_tx_dma_setup;
407	unsigned long	watchdog_events;
408	unsigned long	rx_overruns;
409
410	/* Used in for 82547 10Mb Half workaround */
411	#define EM_PBA_BYTES_SHIFT	0xA
412	#define EM_TX_HEAD_ADDR_SHIFT	7
413	#define EM_PBA_TX_MASK		0xFFFF0000
414	#define EM_FIFO_HDR              0x10
415
416	#define EM_82547_PKT_THRESH      0x3e0
417
418	u_int32_t       tx_fifo_size;
419	u_int32_t       tx_fifo_head;
420	u_int32_t       tx_fifo_head_addr;
421	u_int64_t       tx_fifo_reset_cnt;
422	u_int64_t       tx_fifo_wrk_cnt;
423	u_int32_t       tx_head_addr;
424
425        /* For 82544 PCIX Workaround */
426        boolean_t       pcix_82544;
427	boolean_t       in_detach;
428
429	struct em_hw_stats stats;
430};
431
432#define	EM_LOCK_INIT(_sc, _name) \
433	mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
434#define	EM_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->mtx)
435#define	EM_LOCK(_sc)		mtx_lock(&(_sc)->mtx)
436#define	EM_UNLOCK(_sc)		mtx_unlock(&(_sc)->mtx)
437#define	EM_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->mtx, MA_OWNED)
438
439#endif                                                  /* _EM_H_DEFINED_ */
440